N-MOSFET Gates

Home , Logical NOR, NMOS logic, NOR gate

Islamic University of Gaza Digital Electronics Lab (EELE 3121) Faculty of Engineering Eng. Mohammed S. Jouda Electrical Engineering department Eng. Amani S. abu reyala

Experiment 9 N-MOSFET Gates

Objectives

 To be familiar with the operation of N-MOSFET.  Be familiar with logic gates using resistors and N-MOSFET Transistor.  Studying the internal connection of AND, OR, NAND, and NOR.  To determine the VTC of these gates.

Equipments Resistors – N-MOSFET (IRF830) – Voltmeter – Power supply – Orcad software program.

Theoretical Background

The previous Experiment described NMOS logic families and their implantation in inverter form. In the present Experiment is dedicate to describing the design of Multi-input NMOS logic gates such as NANDs, NORs, AND, OR inverters.

I. NMOS NOR GATE: The general NMOS inverter can be augmented to perform the logical NOR function by placing additional out put NMOS transistors in parallel with the output N-Channel MOSFET. Figure 9.1 shows a two input NMOS NOR gate with a generic load. Both NMOS transistors have their drain-to-source channels

connected from the output to ground. VDD= 5V

50k VO

VA VB IRF830 IRF830

0 Figure 9.1 a two input NMOS NOR gate  Output High Voltage VoH:

If both input to the NMOS gate of Figure 9.1 are low, both output transistor ( NA & NB ) will be cutoff . Vout = VoH = VDD

 Output Low Voltage VoL:

If any input is high , results in an output low voltage. The parallel output NMOS structure is referred to as a parallel pull-down , since it is construction of several possible pull-down paths from the output to ground.

푉퐷퐷 VoL = 퐾푅퐿 푉퐷퐷−푉푇 + 1

 Input Low and High Voltage ViL & ViH:

The input low and high voltage for NMOS logic family NOR Gates are the same as those for corresponding inverter.

1 ViL = 푉푇 + 퐾푅퐿

II. NMOS NAND GATE: NAND gates can also be easily constructed using NMOS circuitry Figure 9.2, shows a two input NMOS NOR gate with a generic load. VDD= 5V

50k

IRF830

Figure 9.2 a two input NMOS NAND gate  Output High Voltage VoH: An output high voltage is obtain from the NMOS NAND gates of Figure 9.2 for either input being low.

 Output Low Voltage VoL: An output low voltage is obtain from the NMOS NAND gates of Figure 9.2 for both inputs being high.

 Input Low and High Voltage ViL & ViH:

The input low and high voltage for NMOS logic family inverter are all dependent on Ko and increase in VoL can also be used to show change in ViL and ViH for each of the logic family.

III. NMOS OR & AND GATES:

OR and AND gates are obtained using NMOS logic families by simply connecting inverters to the outputs of NOR and AND gates, respectively. Figure 9.3 and Figure 9.4, show NMOS OR and AND gates with generic load.

VDD= 5V

50k

VO 50k

IRF830 VDD= 5V VDD= 5V

VA VB 0

IRF830 IRF830 50k 50k

VO 0

VA IRF830

IRF830 Figure 9.3 a two input NMOS OR gate 0

IRF830

0 Figure 9.4 a two input NMOS AND gate

Procedure:

Part 1:

1. Construct the circuit shown in Figure 9.1, VDD = 5V, RL =50K 2. Find the truth table filling the following

VA VB VOUT 0 0 0 5 5 0 5 5

3. Filling the following table and Draw the VTC of this gate :

Vin 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Vout

4. Determine VOH,VOL,VIH,VIL 5. Draw the VTC of this gate by using the Orcad.

Part 2:

1. Construct the circuit shown in Figure 9.2, VDD = 5V, RL =50K 2. Find the truth table filling the following

VA VB VOUT 0 0 0 5 5 0 5 5

3. Filling the following table and Draw the VTC of this gate :

Vin 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Vout

4. Determine VOH,VOL,VIH,VIL 5. Draw the VTC of this gate by using the Orcad.

Part 3:

Draw the circuits shown in Figure 9.3 && Figure 9.4 by using the Orcad and show the results.