8. Combinational MOS Logic Circuits

Institute of Microelectronic Systems

Introduction • Combinational logic circuits, or gates, witch perform Boolean operations on multiple input variables and determine the output as Boolean functions of the inputs, are the basic building blocks of all digital systems. • We will examine the static and dynamic characteristics of various combinational MOS logic circuits. It will be seen that many of the basic principles used in the design and analysis of MOS inverters can be directly applied to the combinational logic circuit as well. • In its most general form, a combinational logic circuit, or gate, performing a Boolean function can be represented as a multiple-input single-output system.

General combinational logic circuit (gate) Institute of 8: Combinational MOS Microelectronic 2 Logic Circuits Systems MOS Logic Circuits with Depletion nMOS Loads Two-Input NOR Gate

A two-input depletion-load NOR gate, its logic symbol, and the corresponding truth table

Calculation of VOH

When both input voltages VA and VB are lower than the corresponding driver threshold voltage, the driver transistor are turned off and conduct no drain current. Consequently, the load device, which operates in the linear region, also has zero drain current. In particular, its linear region current equation becomes kn, load 2 ID, load = ⎡2VT , load(VOH )(VDD − VOH ) − (VDD − VOH ) ⎤ = 0 2 ⎣⎢ ⎦⎥

The solution of this equation gives VOH=VDD Institute of 8: Combinational MOS Microelectronic 3 Logic Circuits Systems

Calculation of VOL

To calculate the output voltage VOL, we must consider three different cases, i.e., three different input voltage combinations, which produce a conduction path from the output node to the ground. These cases are

(i) VA=VOH VB=VOL (ii) VA=VOL VB=VOH (iii) VA=VOH VB=VOH

For first two cases the NOR circuit reduces to a simple nMOS depletion-load inverter. Assuming that the threshold voltages of the two enhancement-type driver transistors are identical (VT0,A=VT0,B=VT0), the driver-to-load ratio of the corresponding inverter can be found as follows. (i) ⎛W ⎞ k′n, driver ⎜ ⎟ kdriver , A ⎝ L ⎠A kR = = kload ⎛W ⎞ k′n, load ⎜ ⎟ ⎝ L ⎠load

Institute of 8: Combinational MOS Microelectronic 4 Logic Circuits Systems (ii) ⎛W ⎞ k′n, driver ⎜ ⎟B kdriver , B ⎝ L ⎠ kR = = kload ⎛W ⎞ k′n, load ⎜ ⎟ ⎝ L ⎠load

The output low voltage level VOL in both cases is found as follows: 2 ⎛ kload ⎞ 2 VOL = VOH − VT 0 − (VOH − VT 0 ) − ⎜ ⎟VT , load(VOL ) ⎝ kdriver ⎠

The output low voltage (VOL) values calculated for case (i) and (ii) will be identical. In case (iii), where both driver transistors are turned on, the saturated load current is the sum of the two linear-mode driver currents. ID, load = ID, driverA + ID, driverB kload 2 kdriver , A ⎡ 2 ⎤ VT , load(VOL ) = 2(VA − VT 0 )VOL − V OL 2 2 ⎣⎢ ⎦⎥ kdriver , B 2 + ⎡2(VB − VT 0 )VOL − V OL⎤ 2 ⎣⎢ ⎦⎥

Institute of 8: Combinational MOS Microelectronic 5 Logic Circuits Systems

Since the gate voltages of both driver transistors are equal (VA=VB=VOH), we can devise an equivalent driver-to-load ratio for the NOR structure: ⎡⎛W ⎞ ⎛W ⎞ ⎤ k′n, driver ⎢⎜ ⎟ +⎜ ⎟B⎥ kdriver , A + kdriver , B ⎣⎝ L ⎠ ⎝ L ⎠ ⎦ kR = = A kload ⎛W ⎞ k′n, load⎜ ⎟ ⎝ L ⎠load Thus, the NOR gate with both of its inputs tied to a logic-high voltage is replaced with an nMOS depletion-load circuit with the driver-to-load ratio given by the above equation. The output voltage level in this case is: 2 ⎛ kload ⎞ 2 VOL = VOH − VT 0 − (VOH − VT 0 ) − ⎜ ⎟VT , load(VOL ) ⎝ kdriver , A + kdriver , B ⎠

The VOL is lower than the VOL values calculated for case (i) and for case (ii), when only one input is logic-high. This also suggests a simple design strategy for NOR gates. Usually, we have to achieve a certain maximum VOL for the worst case, i.e., when only one input is high. Thus, we assume that one input (either VA or VB) is logic-high and determine the driver-to-load ratio of the resulting inverter. Then set kdriver , A = kdriver , B = kRkload This design choice yields two identical driver transistors, which guarantee the required value of VOL in the worst case. When both inputs are logic-high, the output voltage is even lower than the required maximum VOL, thus the design constraint is satisfied. Institute of 8: Combinational MOS Microelectronic 6 Logic Circuits Systems Generalized NOR Structure with Multiple Inputs

Generalized n-input NOR gate

The combined pull-down current can than be expressed as follows: ⎧ µnCox ⎛W ⎞ 2 ⎡2(VGS, k − VT 0 )Vout − V out ⎤ linear ⎪ ∑ ⎜ ⎟ ⎢ ⎥ ⎪k( on ) 2 ⎝ L ⎠k ⎣ ⎦ ID = ∑ ID, k =⎨ k( on ) ⎪ µnCox ⎛W ⎞ 2 ∑ ⎜ ⎟ (VGS, k − VT 0 ) saturation ⎩⎪k( on ) 2 ⎝ L ⎠k Assuming that the input voltages of all driver transistors are identical, VGS, k = VGS for k = 1,2,...,n

Institute of 8: Combinational MOS Microelectronic 7 Logic Circuits Systems

The pull-down current expression can be rewritten as ⎧µnCox ⎛W ⎞ 2 ⎡2(VGS − VT 0 )Vout − V ⎤ linear ⎪ ∑ ⎜ ⎟ )⎢ out ⎥ ⎪ 2 ( k( on ) ⎝ L ⎠k ⎣ ⎦ ID = ⎨ ⎪µnCox ⎛W ⎞ 2 ∑ ⎜ ⎟ )(VGS − VT 0 ) saturation ⎩⎪ 2 ( k( on ) ⎝ L ⎠k

Equivalent inverter circuit corresponding to the n-input NOR gate The (W/L) ratio of the driver transistor here is: ⎛W ⎞ ⎛W ⎞ ⎜ ⎟ = ∑ ⎜ ⎟ ⎝ L ⎠equivalent k( on ) ⎝ L ⎠k

Institute of 8: Combinational MOS Microelectronic 8 Logic Circuits Systems Transient analysis of NOR Gate

Parasitic device capacitances in the NOR2 gate and the lumped equivalent load capacitance. The gate-to-source capacitances of the driver transistors are included in the load of the previous stages driving the inputs A and B.

The value of the combined load capacitance can be found:

Cload = Cgd , A + Cgd , B + Cgd , load + Cdb, A + Cdb, B + Csb, load + Cwire

Institute of 8: Combinational MOS Microelectronic 9 Logic Circuits Systems

Two-input NAND Gate

A two-input depletion-load NAND gate, its logic symbol, and the corresponding truth table.

It can easily be seen that the drain currents of all transistors in the circuit are equal to each other.

ID, load = ID, driverA = ID, driverB

Institute of 8: Combinational MOS Microelectronic 10 Logic Circuits Systems kload 2 kdriver , A ⎡ 2 ⎤ VT , load(VOL ) = 2(VGS, A − VT , A )VDS, A − V DS, A 2 2 ⎣⎢ ⎦⎥ kdriver , B ⎡ 2 ⎤ = 2(VGS, B − VT , B )VDS, B − V DS, B 2 ⎣⎢ ⎦⎥ The gate-to-source voltages of both driver transistors can be assumed to be V approximately equal to VOH. ( V GS , A = V OH − V DS , B ≈ V OH , since DS low in NSAT) The drain-to-source voltages of both transistors can be solved: 2 ⎛ kload ⎞ 2 VDS, A = VOH − VT 0 − (VOH − VT 0 ) − ⎜ ⎟VT , load(VOL ) ⎝ kdriver , A ⎠ 2 ⎛ kload ⎞ 2 VDS, B = VOH − VT 0 − (VOH − VT 0 ) − ⎜ ⎟VT , load(VOL ) ⎝ kdriver , B ⎠

Let the two driver transistors be identical, i.e., kdriver,A=kdriver,B=kdriver. Noting that the output voltage VOL is equal to the sum of the drain-to-source voltages of both drivers, we obtain:

⎛ ⎛ ⎞ ⎞ ⎜ 2 ⎜ kload ⎟ 2 ⎟ VOL ≈ 2⎜VOH − VT 0 − (VOH − VT 0 ) − VT , load(VOL ) ⎟ ⎜ ⎜ ⎟ ⎟ ⎝ ⎝ kdriver ⎠ ⎠

Institute of 8: Combinational MOS Microelectronic 11 Logic Circuits Systems

The following analysis gives a better and more accurate view of the operation of two series-connected driver transistors.Consider the two identical enhancement- type nMOS transistors with their gate terminals connected. At this point, the only

simplifying assumption will be VT,A=VT,B=VT0. When both driver transistors are in the linear region, the drain currents can be written as: kdriver ⎡ 2 ⎤ ID, A = 2(VGS, A − VT 0 )VDS, A − V DS, A 2 ⎣⎢ ⎦⎥ kdriver ⎡ 2 ⎤ ID, B = 2(VGS, B − VT 0 )VDS, B − V DS, B 2 ⎣⎢ ⎦⎥ Since ID,A=ID,B, this current can also be expressed as ID, A + ID, B ID = ID, A = ID, B = 2 Using VGS,A=VGS,B-VDS,B yields kdriver 2 ID = ⎡2(VGS, B − VT 0 )(VDS, A + VDS, B ) − (VDS, A + VDS, B ) ⎤ 4 ⎣⎢ ⎦⎥

Now let VGS=VGS,B and VDS=VDS,A+VDS,B. The drain-current expression can be written as follows. kdriver 2 ID = ⎡2(VGS − VT 0 )VDS − VDS ⎤ 4 ⎢⎣ ⎦⎥

Institute of 8: Combinational MOS Microelectronic 12 Logic Circuits Systems Generalized NAND Structure with Multiple Inputs

The generalized NAND2 structure and its inverter equivalent Neglecting the substrate-bias effect, and assuming that the threshold voltages of

all transistors equal to VT0, the driver current ID in the linear region can be derived: ⎛ ⎞ ⎜ ⎟ ⎜ ⎟⎧ 2 ⎡2(Vin − VT 0 )Vout − V ⎤ linear µnCox ⎜ 1 ⎟⎪⎢ out ⎥ ID ⎣ ⎦ = ⎜ ⎟⎨ 2 1 2 ⎜ ∑ ⎟⎪(Vin − VT 0 ) saturation ⎛W ⎞ ⎩ ⎜ k( on ) ⎜ ⎟ ⎟ ⎝ ⎝ L ⎠k ⎠ Institute of 8: Combinational MOS Microelectronic 13 Logic Circuits Systems

Hence, the (W/L) ratio of the equivalent driver transistor is ⎛W ⎞ 1 = ⎜ ⎟ 1 ⎝ L ⎠equivalent ∑ ⎛W ⎞ k( on ) ⎜ ⎟ ⎝ L ⎠k

If the series-connected transistors are identical, i.e., (W/L)1= (W/L)2=...= (W/L), the width-to-length ratio of the equivalent transistor becomes ⎛W ⎞ 1 ⎛W ⎞ ⎜ ⎟ = ⎜ ⎟ ⎝ L ⎠equivalent n ⎝ L ⎠

Institute of 8: Combinational MOS Microelectronic 14 Logic Circuits Systems Transient Analysis of NAND Gate

Parasitic device capacitances in the NAND2 gate

Institute of 8: Combinational MOS Microelectronic 15 Logic Circuits Systems

As in the inverter case, we can combine the capacitances into one capacitance, connected between the output and node and the ground. The value of the lumped

capacitance Cload depends on the input voltage conditions.

For example, the input VA is equal to VOH and the other input VB is switching from VOH to VOL. In this case, both the output voltage Vout and the internal node voltage Vx will rise, resulting in: Cload = Cgd , load + Cgd , A + Cgd , B + Cgs, A + Cdb, A + Cdb, B + Csb, A + Csb, load + Cwire Note that this value is quite conservative and fully reflects the internal node

capacitances into the lumped output capacitance Cload. In reality, only a fraction of the internal node capacitances is reflected into Cload.

Institute of 8: Combinational MOS Microelectronic 16 Logic Circuits Systems