MIPS64® I6500 Multiprocessing System Programmer’s Guide
Revision 1.00 March 29, 2017 Public Public. This publication contains proprietary information which is subject to change without notice and is supplied ‘as is’, without any warranty of any kind.
Document Number: MD01179
MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
1 3 43 ...... 25 ...... 42 ...... 13 ...... 19 ...... 27 ...... 26 ...... 13 ...... 16 ...... 18 ...... 23 ...... 28 ...... 25 ...... 11 ...... 18 ...... 26 ...... 30 ...... 19 ...... 12 ...... 14 ...... 35 ...... 14 ...... 36 ...... 24 ...... 35 ...... 15 ...... 37 ...... 36 ...... 18 ...... 22 ...... 25 ...... 17 ...... 18 ...... 21 ...... 31 ...... 18 ...... 36 ...... 40 ...... 41 ...... 11 ...... 33 ...... 13 ...... 42 ...... 17 ...... 21 1) ...... 4 ...... egister 16, Select 0) ...... T Support...... s ...... ation...... 3.4.1.1:Config Register(CP0 r 3.4.1.2:Config1 Register (CP0register 16, Select 3.4.1.3:CacheErr Register(CP0 register Select27, 0)...... 43 1.5.8: Developer Resources...... 1.2.1: MIPS64® Release 6 Architecture ...... 1.1.2: Multi-Cluster Configuration...... 1.2.2: SIMD MIPS® Architecture ...... 1.2.3: Virtualization MIPS® ...... 1.2.4: System-level Features ...... 1.2.5: Features...... Core-level 1.5.2: MIPS Android...... 1.5.3: Codescape MIPS SDK...... 1.5.4: Codescape Debugger ...... 1.5.5: Compilers...... 1.5.6: Boot Loader...... 1.5.7:MIPS RTOS and Io 3.1.1: L1 Instruction Cache ...... 3.1.2: L1 Data Cache ...... 3.1.3: L2 Cache...... 3.1.4: Cache Instructions ...... 3.4.1:L1 Instruction Cache Control Registers ...... 1.1.1:Single-Cluster Configuration ...... 1.5.1: MIPS Linux 2.1.1: TLB Types...... 2.1.2: TLB Instructions ...... 2.1.3: Shared FTLB Translations ...... 2.1.4: Global TLB Invalidate...... 2.2.6: Programming a TLB Entry...... 2.2.7:Entries.Hardwiring VTLB 2.2.8:FTLB HashingScheme and theTLBWI Instruction ...... 31 2.2.2:Determining the VTLB Size...... 2.2.3: FTLB Page Size Configuration...... 2.2.4: VTLB and FTLB Initialization...... 2.2.5:Indexing the VTLB FTLB...... and 2.2.1: Assembly Language Conventions...... 1.2: I6500 Features ...... 1.3: I6500 Core Block Diagram ...... 16 1.4:CP0 Register Assemblerto Mapping ...... 1.5:SoftwareMIPS Tool 3.2: Cache Coherency...... 3.3: Self-modified Code ...... 3.4: Register Interface ...... 3.1: Cache Subsystem Overview ...... 2.1: Overview...... 1.1: Product Overview ...... 2.3: TLB Exception Handler...... 2.4:Additional Inform 2.2: MMU Programming ...... MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 Chapter 3: Caches3: Chapter ...... Chapter 2: Memory Management Unit2: Memory Management Chapter ...... 21 Chapter 1: Architecture Overview...... 1: Architecture Chapter 9
4 4 44 .57 .. 46 ... 45 ...... 45 ...... 47 ...... 51 ...... 61 ...... 62 ...... 64 ...... 48 ...... 44 ...... 49 ...... 61 ...... 50 ...... 48 ...... 54 ...... 59 ...... 59 ...... 60 ...... 52 ...... 60 ...... 48 ...... 66 ...... 60 ...... 49 ...... 50 ...... 56 ...... 47 ...... 50 ...... em Programmer’s Guide, Revision 1.00 ...... 47 ess...... Address...... gister 28, Select 0)...... 43 register28, Select 1) ...... 43 ...... 46 )...... 46 register29, Select 1)...... 43 er Select29, 3)...... 45 er 28, Select2)...... 44 ster 28, Select 3) ...... 45 ...... e GINVI Instruction...... 50 ytesof the Physical Address ...... 63 1) ...... 4 es of the PhysicalAddress ...... 63 ...... ResetException Vectors...... MIPS64® MIPS64® I6500Multiprocessing Syst Cache Coherency Routine ...... egister 16, Select 0) ...... ess per Exception Type...... 6 NF RegisterNF (Offset 0x0008)...... ion Cache ...... the Lower 512 MBytesof the Physical the Lower GBytes4 of the Physical Addr ines ...... rdware Cache Initializationrdware . 3.4.2.1:Config Register(CP0 r 3.4.1.5:L1 Instruction Register Cache DataLo (CP0 3.4.2.2:Config1 Register (CP0register 16, Select 3.4.1.4:InstructionL1 TagLo RegisterCache (CP0 re 3.4.1.6:L1 Instruction Register Cache DataHi (CP0 3.4.3.3: L2_RAM_Config Register (Offset 0x0240) ...... 46 3.4.3.4:L2_PFT_Control Register (Offset0x0300) ...... 46 3.4.3.5:L2_PFT_Control_B Register (Offset 0x0308 3.4.3.6: L2_TAG_ADDR Register (Offset 0x0600)...... 46 3.4.3.7: L2_TAG_STATE Register (Offset 0x0608) ...... 46 3.4.3.8: L2_DATA Register (Offset 0x0610)...... 3.4.3.9:L2_DATA_ECC Register(Offset 0x0618) .... 3.4.3.10: L2SM_COPRegister (Offset 0x0620) ...... 46 3.4.3.11: L2SM_TAG_ADDR_COP Register (Offset0x0628)...... 47 3.4.3.12: CPC_CL_STAT_CO 3.4.3.1: GCR_ERR_CONTROL (Offset 0x0038)...... 45 3.4.3.2: L2_Config Register (Offset 0x0130) ...... 3.4.2.3:CacheErr Register(CP0 register Select27, 0)...... 44 3.4.2.4: DataL1 (CP0 regist RegisterCacheTagLo 3.4.2.6:L1 Data CacheDataHi Register(CP0 regist 3.4.2.5:L1 Data CacheDataLo Register(CP0 regi 3.7.1.1:L1 Instruction Invalidation Cache th Using 3.7.1.2:L1 Cache Initialization 3.4.2: L1 Data CacheControl Registers ...... 4.1.1: Exception Types...... 4.1.2: Detecting an Exception ...... 4.1.3: Exception Conditions ...... 3.4.3: L2 Cache CM GCR Control Registers ...... 4.2.1: Mapping the BEV to BEV Mapping the 4.2.1: 3.5.1:Automatic Ha 3.6.1: L2 Cache Flush...... 3.6.2: L2 Cache Burst Operations...... 3.6.3: Abort Operations...... 3.7.1:Initializing Instructthe 4.2.2: Mapping the BEV to BEV Mapping the 4.2.2: 3.5.2: Manual Hardware Cache Initialization...... 3.5.3: Software Cache Initialization...... 3.7.2: Initializing the Data Cache ...... 3.7.3:Initializing Level 2 the Cache ...... 4.2.3:Lower512 MB to the Mapping the Reset Vector 4.2.4:Lower4 GByt to the Mapping the Reset Vector SelectingBetween4.2.5: the and BEV 4.2.6:Exception VectorBase Addr 4.1: Overview of Exception Processing ...... 4.2:Exception Defining the Vector Locations... 3.5: L2 Cache Initialization Options ...... 3.7:Cache InitializationRout 3.6: L2 Cache Flush, Burst, and Abort ...... 3.8:Flushing the Data CacheL1 ...... Setting the 3.9: KSEG0 SpaceMemory 4.3:Core-Level Exception Priorities ...... 2 Chapter 4: Exceptions...... 4: Chapter
3 81 .95 109 .. 94 .... 86 ...... 101 ...... 88 ...... 112 ..... 107 ...... 111 ...... 81 ...... 111 ...... 73 ...... 104 ...... 79 ...... 100 ...... 84 ...... 108 ...... 76 ...... 105 ...... 108 ...... 101 ...... 90 ...... 78 ...... 87 ...... 98 ...... 110 ...... 76 ...... 101 ...... 91 ...... 85 ...... 109 ...... 72 ...... 85 ...... 104 ...... 107 ...... 108 ...... 100 ...... 71 ...... 99 ...... 100 ...... 102 ...... 106 ...... 104 ...... 81 ...... 107 Core ...... 92 the Same Core ...... 91 ID’s...... SystemComponents ...... 96 ...... esponding Anotherto Core-Other GlobalRegisters Interrupt in the Controller...... 99 gister Address Map ...... Register Usage...... rol Blocks ...... de ...... sions ...... Addresses in Memory ...... 5.7.1: Prefetch Enable...... 5.7.2: Select Ports for L2 Prefetching ...... 5.7.3: Enabling Code Prefetch ...... 6.2.1:Cluster Controller Re Power 6.2.2:CPC Base Address ...... 6.2.3: Global Control Block Register Map...... 6.2.4:Local and Core-OtherCont 4.7.2: Interrupt Vectored Mode ...... 5.5.1:Programming Another Processor(VP) Virtual in 5.5.2:Programming Local GCR’s Corr 5.5.3: Accessing the CPC Local Registers via the CM ...... 5.5.4:Powering Up the Debug (DBU) via theCMUnit ...... 5.5.5:Setting the RatiosClock I6500 the Between 5.5.6: Cluster to Cluster Access...... 5.5.7:Accessing Core-Local and the 4.7.1:Interrupt CompatibilityMo 5.12.1: GPRCM Register Interface ...... 5.12.2: MMIO Region Control ...... 6.1.1: Power Domains...... 6.1.2: Clock Domains...... 6.1.3: Core and IOCU Selection...... 6.1.4: Overview of Power States...... 5.1.1: CM Interface — Register and DeviceRing Bus 5.1.2: CM GCR Register Map ...... 5.1.3: Core-Local GCRs...... 5.1.4: Core-Other GCRs ...... 5.1.5:Core-Local Core-Otherand 6.2.5:Requestor Accessto CPC Registers ...... 4.7.3: External Interrupt Controller Mode...... 5.1.6: Cluster to Cluster Accesses...... 86 5.8:CM Uncached ManagementSemaphore ...... 5.9:Custom GCR Implementation 5.6: Coherency Enable ...... 5.7: L2 Cache Prefetch...... 5.10: Processing...... Error 5.11: IOCU Interface...... 5.12: MMIOAddress Regions ...... 5.13: Auxiliary Interfaces ...... 6.1: Overview...... 5.4:CM Register AccessPermis 5.5:CM Programming Examples...... 6.2: CPC Register Programming ...... 4.5: General Exception Processing ...... 4.6:Exception and Handling FlowchartsServicing ...... 5.1: CM Overview ...... 5.3:Programming the Base 4.4:Hypervisor Exception Priorities...... 5.2:Verifying Overall System Configuration..... 4.7: Interrupt Code Mode Examples...... MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 Chapter 6: Power Management6: Power Chapter ...... Chapter 5: Coherence Manager...... Coherence 5: Chapter
132 . 119 . 119 .... 118 .... 119 ..... 129 ..... 130 ..... 130 ...... 114 ...... 137 ..... 123 ...... 135 ...... 136 ...... 136 ...... 143 ...... 146 ...... 125 ...... 137 ...... 116 ...... 146 ...... 146 ...... 116 ...... 123 ...... 140 ...... 112 ...... 128 ...... 121 ...... 147 ...... 123 ...... 140 ...... 124 ...... 120 ...... 113 ...... 124 ...... 138 ...... 117 ...... 124 ...... 128 ...... 116 ...... 123 ...... 131 ...... 126 ...... 147 ...... 123 em Programmer’s Guide, Revision 1.00 ramming Sequence...... ramming 114 Delay ...... 118 ...... 139 r Domain...... 119 ...... in the System...... 127 ...... Delays...... ample — RegisterProg or Interrupt Disabled State ...... 136 y Count ...... MIPS64® MIPS64® I6500Multiprocessing Syst Group...... rrupts ...... urces ...... lay...... se Address and Address se the GIC...... Enabling 127 ...... Powerup ...... g ...... sor Interrupts...... 6.2.14.1: GlobalSequence Dela 6.2.14.2: DelayRail ...... 6.2.14.3: Reset Delay ...... 6.2.12.1: RAM Deep Sleep Mode...... 6.2.12.2: RAMShut ModeDown ...... 6.2.8.2: Clock DeChange 6.2.8.1: Clock ExDomain Change 7.1.2.1: Non-EIC Mode...... 7.1.2.2: EIC Mode...... 7.2.8.1: GIC Interval Timer ...... 7.2.8.2: GIC Watchdog Timer...... 7.2.9.1:Interrupt Local Routing ...... 7.2.9.2:Interrupt Local Masking ...... 7.2.6.1:Enabling External Inte 7.2.6.2: External Disabling Interrupts ...... 7.2.6.3: Determining the Enabled 7.2.6.4:Polling for Activean Interrupt ...... 7.2.4.1:Trigger RegisterType 7.2.6.5: Example Programming ...... 7.2.7.1:WEDGE RegisterProgramming Example .... 7.2.5.1:Mapping an Interrupt toSource a VP ...... 7.2.5.2: Mapping an InterruptSource to a Specific Processor Pin ...... 133 7.2.4.2: Edge Type Register Group...... 7.2.4.3:Polarity TypeRegister Group ...... 6.2.10: Reset Detection...... 6.2.11: Run/Suspend...... VP 6.2.12:and Wakeup / Sleep Shutdown RAM Deep Local 6.2.13: the CPC RegistersAccessing Anotherin Powe 6.2.14:and External Tuning Internal Fine Signal 6.2.9: StandaloneCM 7.2.9:Local Interrupt Routing and Masking ...... 6.2.7: Master Clock Prescaler...... 6.2.8:Individual ClockDevice Ratio Modification 6.2.6: Enabling Coherent Mode ...... 7.1.1: GIC Virtualization ...... 7.1.2: GIC Operating Modes ...... 7.1.3: GIC Register Types...... 7.1.4: GIC Register Distribution ...... 7.1.5: GIC Address Configuration...... Space 7.2.1:Setting the GICBa 7.2.2: Determining the Number ofInterrupts External 7.2.3: EIC Mode Setting...... 7.2.4:Configuring Interrupt So 7.2.8: Local Timer Configuration...... 7.3.1: Enabling Virtualization Mode...... 7.2.6:Enabling, and Polling Disabling, Interrupts 7.2.5:Interrupt Routin 7.2.7: Inter-proces 7.1: Overview...... 7.3:Virtualization Support ... 7.2: GIC Programming...... 4 Chapter 7: Global Interrupt Controller...... 7: Global Chapter
5 0 149 167 .... 147 .... 174 .... 162 ...... 171 ..... 151 ...... 154 ...... 173 ...... 163 ...... 169 ...... 166 ...... 172 ...... 161 ...... 157 ...... 160 ...... 171 ...... 163 ...... 173 ...... 155 ...... 155 ...... 157 ...... 151 ...... 151 ...... 165 ...... 162 ...... 150 ...... 162 ...... 152 ...... 153 ...... 152 ...... 156 ...... 159 ...... 169 ...... 159 ...... 165 ...... 174 ...... 154 ...... 163 ...... 171 ...... 151 sters ...... 158 ...... 15 ...... d RootInterrupts Aand non-MSA Functions...... 167 Timer Interrupts...... nt RegisterUsage for and -msimd-abi=msa-mmsa ...... 167 Point Registersto MSAVector Regi estSoftware Access to GIC registers...... 148 ction...... int FCSR Register...... s...... itecture ...... ns...... 9.4.1.1: ABI Requirements ...... 9.4.1.2: Command Line Optionsand Function Attributes...... 166 9.4.1.3:Vector and Floating-Poi 9.4.1.4:Between Inter-calling MS 9.4.1.5:MSA GNU Optionsand Directives...... 9.4.3: Examples ...... 7.3.5:an (WD) Timer Guest Watchdog 9.4.2:MSA VectorElement Sele 7.3.2: Routing of Guest External Source Interrupts ...... 7.3.3:Qualification of or Root Gu 7.3.4:Guest Mode Count-Compare 10.1.1: Root and Guest Operating Modes ...... 9.3.3:MSACSR Cause RegisterField Update Pseudocode...... 164 10.1.2: Introductionto the Hypervisor ...... 10.1.3: GuestEnabling Mode Translations...... 8.1.1: IEEE 754 Standard ...... 8.1.2: Floating Point Register 9.3.1: MSA Exception Types...... 9.3.2: MSA Non-Trapping Exceptions...... 9.4.1: MSA ABI...... 10.1.4: MMU Consideratio 10.1.5: Guest ID...... 10.1.6: Structurein Rootand GuestMode...... CP0 9.1.1: MSA Instruction Formats...... 9.1.2: SIMD Instructions...... 9.1.3: MSA Vector Registers...... 9.1.4: Layout of MSA Registers ...... 9.1.5:Mapping of Scalar Floating- 9.2.1: Enabling MSA ...... 9.2.2: Setting a MSA Exception ...... 9.2.3: Setting the Rounding Mode...... 9.2.4: Operation of the FS Bit...... 9.2.5: Operation of the NX Bit ...... 9.2.6: Programming the MSA CSR Register...... 8.4: Setting the ModeRounding ...... 8.5: Operation of the FS Bit ...... 8.6:Programming the Floating Po 8.3:a Setting Point Exception...... Floating 7.4: GIC User-Mode Visible Section...... 10.1: Overview...... 9.4:MSA GNU Support...... Compiler 9.1:Overview of the Arch SIMD 8.1: Overview...... 8.2:Enabling theFloating-Point Unit ...... 9.2: Programming MSA ...... 9.3: Exceptions MSA ...... MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 Chapter 10: Virtualization Chapter ...... Chapter 9: MIPS® SIMD Architecture (MSA)Architecture 9: MIPS® SIMD Chapter ...... 155 Chapter 8: Floating-Point Unit (FPU)8: Floating-Point Chapter ......
4 . 182 .. 182 ... 181 ... 203 .... 189 ..... 192 ...... 206 ...... 210 ...... 210 ...... 182 ...... 182 ...... 180 ...... 184 ...... 196 ...... 193 ...... 203 ...... 204 ...... 198 ...... 183 ...... 207 ...... 189 ...... 200 ...... 177 ...... 177 ...... 178 ...... 175 ...... 176 ...... 203 ...... 209 ...... 211 ...... 205 ...... 176 ...... 198 ...... 185 ...... 178 ...... 192 ...... 197 6)...... 177 ...... 212 ...... 182 ...... 203 ...... 209 ...... 190 er 9, Selecter 6) Select 7) ...... em Programmer’s Guide, Revision 1.00 Register 9, SelectRegister er 9, Select er 7) ...... g...... 205 ...... 181 ...... (CP0 Register (CP0 Select27, 0)...... 205 Register Index Register — SAARI (CP0 Regist —Register SAAR (CP0 9, Register s ExceptionsHypervisor ...... 189 gisters— Error Reportin MIPS64® MIPS64® I6500Multiprocessing Syst quence...... Exception...... de ...... ures ...... Access the Shared TLB to ErrCtl(CP0 Register26, Select 0) ...... 205 ...... r Exceptions from Guest Mode...... 18 ...... ation...... er Access...... Initializationer Control...... and er Allocation...... Locations...... dressAccess Index Register — SAARI (CP0 dressAccess —Register SAAR (CP0 Regist ...... upts...... Interface ...... RegisterManagement...... 10.5.1.4: CP0 Regist 10.5.1.5: CP0 Regist 10.5.1.1: Root and Guest 10.5.1.2: Wired 10.5.1.3: CP0 Regist 11.1.1.1: SpecialAd 11.1.1.2: SpecialAd 11.1.2.1: ErrorControl — 11.1.2.2: CacheError — CacheErr 12.1.1.1: SpecialAccess Address 12.1.1.2: SpecialAccess Address 10.7.1.1: Non-EICInterrupt Handling ...... 10.7.1.2: EICInterrupt Handling ...... 10.5.1: and Root Guest TLB Shared Operation...... 10.6.4: ExceptionPriority .... 10.6.5: ExceptionVector 10.6.6: Synchronousand Synchronou 10.6.7: GuestException Code in Root Context .. 11.1.2: toChanges ExistingCP0 Re 12.1.2: Control RegisterITU ...... 10.6.1: Exceptions in GuestMo 10.6.2: Address Faulting fo 10.3.1: Root Mode Operation..... 10.6.3: GuestRootInitiated TLB 10.7.1: Interr External 10.1.8: New CP0 Instructions...... 10.3.2: GuestMode Oper 10.1.7: New CP0 Registers...... 11.1.1: New CP0 Registers...... 12.1.1: New CP0 Registers...... 10.3.3: Debug Mode...... 10.7.2: Derivation ofGuest.CauseIP/RIPL...... 10.7.3: Timer Interrupts...... 10.7.4: CounterPerformance Interrupts...... 11.3.2: Programming Constraints ...... 11.3.1: RegisterProgramming Se 10.6: Exceptions ...... 10.2: SoftwareDetection of Virtualization...... 10.3: OfModes Operation ...... 10.4: AddressTranslation Pseudocode...... 10.5: Handling Exception in Root and Guest Mode...... 10.7: Interrupts ...... 11.2: DSPRAM Software 12.1: Overview...... 11.1: Overview...... 12.2: CellITU Structure ...... 10.8: WatchpointDebug Support ...... 10.9: Feat Guest and Debug Mode 11.3: the DSPRAM...... Accessing ...... 206 6 Chapter 12: Inter-Thread Communication Unit...... Communication 12: Inter-Thread Chapter 209 Chapter 11: Data Scratch Pad RAM11: Data Scratch Chapter ......
7 0 7 230 .. 230 .... 225 .... 225 .... 230 .... 230 ...... 220 ...... 229 ...... 221 ...... 229 ...... 229 ...... 230 ...... 223 ...... 229 ...... 229 ...... 229 ...... 216 ...... 227 ...... 230 ...... 229 ...... 225 ...... 215 ...... 227 ...... 229 ...... 229 ...... 229 ...... 222 ...... 219 ...... 212 ...... 221 ...... 224 ...... 229 ...... 213 ...... 222 ...... 219 ...... 221 ...... 215 ...... 230 ...... 223 ...... 224 s ...... 218 ...... n ...... r) (v3) ...... No ShiftIndex and No Invalid Cells...... 216 Index2-Bit Shift No Invalid Cells...... and 217 4-Bit Index4-Bit Shift Invalid and Cell ConfigurationRegisters) ...... 230 ontroller) ...... quence...... (DVP) Instruction ...... iguration Registers) ...... 23 ...... urces...... l Interruptl Controller) ...... sters ...... Interface...... porting ...... 12.2.5.1: Example 1:32 Cellswith 12.2.5.2: Example 2:32 Cellswith 12.2.5.3: Example 20 2:Cells with 14.1.1.1: APBSlave Port...... 14.1.1.2: JTAG TAP ...... 14.1.5.2: CPC(Cluster C Power 14.1.5.3: GCR(Global Conf 14.1.5.1: GIC(Globa 14.1.1.3: Debug Monitor ...... 14.1.1.4: RAM...... 14.1.5.4: CGCR- (Custom Global 14.1.5.5: CM- Manage (Coherence 14.1.5.6: IOCU(I/O Coherence Unit) ...... 14.1.4.1: BreakpointController. 14.1.4.2: Dseg ...... 14.1.4.3: Dmseg ...... 14.1.4.4: Drseg ...... 14.1.4.5: CP0 Regi 12.5.1: AXI Bus Error ...... 12.5.2: Parity Error...... 12.5.3: ExecutionError ...... 12.2.5: Examples...... Cell Indexing 12.4.1: RegisterProgramming Se 12.4.2: Programming Constraints ...... 12.2.2: Cell Views ...... 12.2.3: Cell State...... 12.2.4: Cell ITU Addressing ...... 12.2.1: ITU Cell Types ...... 13.3.1: Virtual Disable Processor 13.3.2: Processor(EVP)Virtual Enable Instructio 14.1.1: Debug Unit (DBU) ...... 14.1.2: RegisterBus...... 14.1.3: Breakpointsof Number . 14.1.4: Core/VPPer Reso 14.1.5: Coherence Devices...... 12.3: SoftwareITU 12.4: ITU the Accessing Module...... 12.5: Error ITU Re 14.1: OCIDebug System Overview...... 13.1: Instruction Flow ...... 13.2: Data Flow ...... 13.3: Thread Management ...... 13.4: IndependentException Model ...... 14.2: InformationMore ...... MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 Chapter 14: MIPS On-Chip Instrumentation...... 14: MIPS Chapter 22 Chapter 13: Multithreading13: Chapter ...... em Programmer’s Guide, Revision 1.00 MIPS64® MIPS64® I6500Multiprocessing Syst 8
9 TLB architecture, TLB ster interface to each to each interface ster exception handler. also is space ster address programmablea parameter overview of the of overview ming examples of a clock domain a examples of ming for each block, as well as more in well as block, as for each scription of its functionality, and a and of its functionality, scription elements of the Translation Lookaside the Translation of elements lists each device ID on the bus. The pro- ID on the bus. The lists each device ing up cache coherency, handling cache coherency, cache ing up ption of the CP0 regi ption example of an example of . Themajority of blocks in the diagram have at ndalone mode (no cores enabled), reset detection, VP reset detection, cores enabled), (no mode ndalone on how to set the CPC base address in memoryis pro- address in base to set the CPC how on l exception vectors in memory covered. is also Alist ace. The section describes the registers used to per- section describes The ace. overview of the CM regi the CMoverview of in the same core, accessing a VP in another core, VP in another a core, accessing the same in ramtheto CM perform various functions,including set- ce of howce of changetoset or the various I6500 systemcomp For the exact revi- onents. and clockdomains the programmer can use to manage ects of theects of 64-bit MIPS I6500 MultiprocessingSystem the hardware using registers and assembly code. The regis- and assembly registers hardware using the Figure 1.1 s, system power-up policy, program policy, power-up s, system ring bus and associated table that table ring bus and associated ger, refer to the Release Notes. Release the refer to ger, along withassembly an language lization code for all three caches, sett three caches, for all lization code overview of the cache architecture, a de a cache architecture, overview of the amples show how the MIPS set instruction the MIPS can be used to perform theshow how amples same : This chapter provides an overview of how power is managed in the I6500 Mul- I6500 the in managed is power of how overview an provides This chapter : ackgroundinformation required bythe programmer in order tounderstand the as enabling as and initialization are provided : This chapter describes the programmable describes chapter : This that go into programing the caches. A descri caches. the into programing go that (CM): The I6500 MPS contains a third generation Coherence Manager. This chapter pro- contains(CM):The I6500MPS a third generation Coherence Manager. : describesThis chapter an overviewof exception processinganda definition of the interruptmodes. : This chapter provides an chapter provides This : provided.In addition, thechapter describes how toprog another VP accessing ting in memory, the base addresses and/or Debug Unit (DBU) reg- (CPC), Controller Cluster Power (GIC), Controller Interrupt the Global accessing isters viathe CM, andsetting theclock ratios between sionnumber of theCoherence Mana chapterThis also introduces themulti-cluster configuration that allowsmultiple I6500 Multiprocessing Systems to be connected throughNetwork-On-Chip a (NOC) interf access. a cluster-to-cluster form (CPC) Controller Power Cluster tiprocessing System and identifies the various power a procedure addition, In device. the consumptioninpower vided.Otherprogramming principlesincludesetting the device tocoherent or non-coherentmode, requestor register of CPC access (core or IOCU) description of the elements elements of the description initia as well provided, as cache is exceptions, the cache RAM. and testing Exceptions Informationonhow toprogram thereset, boot, and genera exceptionof priorities provided,is sta in up the CPC powering delay change, clock and change Memory Management (MMU) Manager Coherence CM register an overview of the vides ssing System. The first section gives an gives section first The System. Multiproce ssing I6500 the or TLB of Buffer descriptiona of its functionality and a description of theelements that go into programmingThe sec- theTLB. tionsthat follow specificcover informationon programming Lookaside for(TLB). Buffer the Translation Caches An access these devices. this information to grammer uses This documentdescribes the software-programmableasp • (MPS). The consistsdevice(MPS). of thelogic blocks shownin • ter-programming examplester-programming programmingdescribe a sequen least one dedicated chapter that describes how to control how least chapter that describes one dedicated code ex registers. assembly The using function. provides the relevant b chapter Each such Common examples examples. depth relativeexamples to thatblock. An overview of the material provided in this document is as follows: • • • MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 Architecture Overview Architecture Chapter 1 Chapter
and machine states to states machine and on, and systemimplementa- hip Instrumentation(OCI) ples that describe how variouspro-thatdescribe how ples functionality is already built into ssing registers in another power registers ssing such, it is not necessary for the pro- for necessary such, it is not em Programmer’s Guide, Revision 1.00 e setting the operating mode, setting up setting mode, operating the setting e e toe Linked-Load/Store-Conditional structions, registers, registers, structions, by programmer’s writing their own code to code own theirwriting programmer’s by (MD01041), This companion document provides fication,system integrati rface and external debugging ief interface overview of the t library, RTOS, or their own tool chain. However, most or their owntool chain. However, RTOS, t library, of virtualized systems. The Virtualization Module is virtualizedof systems. The Virtualization zing gating storage. The chapter describes the purpose for purpose the describes chapter The storage. gating zing incorporate the MIPS On-C the MIPS incorporate delays to help the programmer easily integrate integrate device the easily the programmer help to delays doperation the of Flush-to-Zerofunction. (FS) contained in the document suite. This documentcontains sup- e L1 data cache to minimize access latency. minimize access latency. cache to L1 data e : The ITU provides an alternativ ITU : The tohow enable MSA, how floatingto mappoint scalar registersto MSA ters, there are assembly language exam ters, ples. Some of these elements includ of Some ples. AMprovides connection a toon-chip memory or memory-mapped regis- examples when using Codescape as this Codescape when using examples MIPS64® I6500Multiprocessing Syst of the MIPS Codescape tool chain. As Codescape of the MIPS : This chapter describes how to program the various elements of the GIC using GIC using the of elements various the to program how describes This chapter : : This chapter describestheMIPS Single-Instruction-Multiple-Data (SIMD) : This chapter provides a br chapter provides This : I6500 Programmers Guide . I6500Programmers : This chapter provides information on how to enable the FPU, how to handle floating handle to FPU, how the enable to how on informationprovides chapter This : d MSAexception handling. : The Virtualization Moduleof new in definesa set The Virtualization : : This chapter provides an overviewof multi-threading the hardware mechanism in theI6500 : The optional Data Scratch Pad RAM (DSPRAM) block provides a general scratch pad RAM used for for used pad RAM a general scratch provides block RAM (DSPRAM) Pad Data Scratch The optional : hardware detailshardware about the device, including functional veri tion. 64-bit MIPS I6500 Technical Reference Manual Reference 64-bitMIPSI6500 Technical Guide SystemIntegrator’s Multiprocessing 64-bitMIPS I6500 architecture. It provides information on It provides architecture. an vector registers, plementalinformation to the MIPS SIMD Architecture (MSA) Architecture SIMD MIPS the map,addressGIC register layoutanddistribution, setting the address,GIC base determining the number of external interrupts, configuringand individualinterrupt sources. Unit (FPU) Point Floating point exceptions, howtoset the rounding mode, an debug system for multi-core designs. synchronization for fine grained multithreading by utili by multithreading grained for fine synchronization the ITUandthe configuration and programmingaspects. Multi-threading environment requiredtodebug MIPS processorsthat Virtualization (VZ) Virtualization CommunicationUnit (ITU) Inter-Thread MPS. On-Chip Instrumentation(OCI) domain, and fine tuninginternal signaland external system environment. into a (GIC) Controller Interrupt Global exam and code register examples both the I6500core implementationto manage the efficient with th accessed in parallel are which ters, run/suspend run/suspend RAMmechanism, local acce procedure, and wake-up shutdown designed to enablefullvirtualization of operating syst ems Guest the Operating Sys- and allows for execution of tems ina fullyvirtualized environment. DSPRAM temporary data. The DSPR storage of the Codescape software. the Codescape This document is meant to be used with companiontwoother documents: • • • • Throughoutallof theaforementioned chap gramming elements are handled in software. These examples can be used can be used examples in software. These elements are handled gramming particularprogram a block,for writing a or low-levelsuppor are part described examples the code of code these grammer to manually execute • • • • • • 10
11 maintains Level 2 (L2) cache maintains Level 2 (L2) provides a best in class power effi- in class best provides a t Architecture with full hardware multi- oherent interfaces, and L2 cache size. ltiprocessing System. The I6500 MPS contains the fol- the MPS contains I6500 The System.ltiprocessing er must thanbe less or equal to eight.All cores and r configurationsr as described in the following subsec- the core can be configured with a SIMD engine supporting engine a SIMD with configured can be core the The Manager I6500 Coherence multi-core microprocessor system that system multi-core microprocessor ith integrated L2-cache the Release 6 of the MIPS64 Instruction Se 6 of Release the n-chip (SoC) applications. n-chip (SoC) shows a block diagram of a single-cluster I6500 Mu I6500 single-cluster of a diagram block a shows ciency for use in system-o ciency andI/O devices. I6500The MultiprocessingSystem and systemlevel coherency between all cores, main memory, c I/O cores, number of variable configured a with (MPS) be can tions. Each I6500 core implements Each In addition, support. virtualization and hardware threading single and double precision, and floating andfixed integer, point operations. The MPS supportsI6500 both single-cluster andmulti-cluste Figure 1.1 Figure lowinglogic blocks: • Up tosix cores •(CM) w Manager Coherence • Up toeight Coherence UnitsI/O (IOCU) • Cluster Power Controller(CPC) • Global InterruptController (GIC) • Global ConfigurationRegisters (GCR) • Multiprocessor debug via in-system DebugUnit (DBU) InI6500the the totalMPS ofnumber cores and IOCUs togeth The I6500 series is a The highseries is I6500 performance IOCU’s are optionaland becan configured in any combinationIOCU’s of upto eight. 1.1.1 Single-Cluster Configuration MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 1.1Overview Product
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chapterthis of manual to provide various CM register programmingexamples. Core . Figure 1.1 Figure of Si Diagram Block System-level 0 1.3 interface. This interface is shown in For more information on the For thatis includedin the documentatio Manager the within blocks programmable the on information more For allows a core or VP in one cluster to access a core or a to access in one cluster or VP a core allows In addition to the si addition to the In For more information onthe For more information on the information moreon For ter of this manual.ter For more information onthe this manual. this For more information onthe
1.1.2 Multi-Cluster Core 12
13 rallel processing rallel processing VP Core ates a software-programmable ates VP lowing efficient pa lowing efficient ta is fetched and returned to the to is fetched and returned ta ration by keeping frequently accessed by keeping frequently accessed ration e manycompute-intensive e applicationsby CM3.5 Cluster 2 VP Core VP or" typethator" so your C/C++ code can makeuse of echnology incorpor ecution of high-level languages. Arithmetic and logic oper- logiclanguages. Arithmeticand high-level of ecution ed hardware. This programmable solutionallows for itecture, core-level main as system, and follow- described in the features ilers to further optimize code gene the request to the appropriate clus- appropriate to the request the onto the NOC. The NOC then routes en instructions improve performance by al sed on a fixed-length,regularlyencoded instructionset, and a it uses load/ uster 1 can access and update a register in a VP in Cluster 2 as shown. The 2 Cluster in update a register in a VP and 1 can access uster Network on Chip (NOC) Network on Chip VP Core In addition, the MSAIn addition,the is designed to accelerat VP Figure 1.2 Figure NOC Using the Accesses Cluster-to-Cluster CM3.5 Cluster 1 VP Core VP Single Instruction Multiple Data (SIMD) Instruction Multiple Single ing subsections. ing is ba 6 architecture MIPS64 Release The streamlinedissupporttooptimizedex data model. It store The I6500 arch contains the following MPS The I6500 ationsuse a three-operandformat, allowingofcompilers tooptimize complexexpressions formulation. Availability 32 comp general-purpose registers enables MD Architecture (MSA) t operations.vectorArchitecture (MSA) of The MIPS®SIMD requestingVP through the NOC. For more information, refer to Chapter 4, Coherency Manager. access is processed by the CM3.5 and driv CM3.5 by the processed is access da The cluster. destination in the is scheduled by the CM3.5 where the access ter For example, a For VP within a core in example, a Cl data inregisters. solutionto handlethose functionsnot covered by dedicat systemincreased flexibility. generic compiler support. enabling MIPSThe gcc compilerbeentuned has to theunderstand "vect SIMD vector features. 1.2.2 MIPS® SIMD Architecture 1.2.1 MIPS64®Release 6 Architecture MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 1.2 Features I6500
memcopy rtualized). The core element The core rtualized). te with the Hypervisor and with each Hypervisor and with the te k-On-Chip two allows (NOC), which em Programmer’s Guide, Revision 1.00 luster luster configuration address and 256-bit data paths ormance of workloads such as workloads ormance of set-associativity and reliability wideconcerns for a rangeof devices. about recommendations on which Hypervisors are Hypervisors which on recommendations about hardware assistance (fully vi (fully assistance hardware s per cluster. s per r Portal r otocol in the multi-c otocol r Networ connection to an external ting 8-way and ting 16-way 8-way liabilityof the systemby allowingtherest of thetoguestsreliably operate MIPS64® I6500Multiprocessing Syst roller significantly improves perf roller or managesor hypervis corrupted. The herwise becomes allmemory I/O privileges. (AUX) AXI-4port Customer Support through our Partne our through Support Customer MIPS •of the L1 data caches Inclusive •cache sizes 8 MB KB to 256 • Error correction and detection I6500 clusters together. to be connected I6500 clusters • High-speedL2 cache initialization •cores for power efficiency to shut down idle CPC • Up toeight IOCUs • modulesupport Virtualization •data transfers Cache-to-cache • Out-of-order data return • AXI-4 and ACE Provides fo interfaces • L2 cache prefetch cont Hardware •IOCU ports and core, memory, on ratios clock Independent • with 48-bit protocol supports the AXI-4 bus interface system SoC •bus pr ACE supports the interface system SoC • Supports up toauxiliaryfour • High bandwidthdata 128-bit paths corebetween each and theCoherence Manager • Software controlled levelcore and cluster levelpower management • Debug port supporting multi-coredebug (JTAG/APB) available for use. of virtualization is the Hypervisor, a small body of trusted and privileged code that sits above the hardware, managing hardware, the above sits that code privileged and trusted of body a small Hypervisor, the is virtualization of for each execution policies access defining by resources the It manages SoC resources. all of the and orchestrating but can communica from each other, Guests are isolated “guest.” or environment other via secure APIs. Thisensures re the ot fails or guests one even of the if Contact •cores R6 MIPS64 coherent six to Up •suppor controller L2 cache Integrated, Virtualization can be achieved with software only, or with or be achievedcan withonly, software Virtualization The hardware virtualization support addresses security, privacy hardwareThe virtualization supportsecurity, addresses 1.2.4 System-level Features 1.2.3 MIPS® Virtualization 14
15 t Architecture t 6 Instruction Se 6 ectionCode (ECC) protection able pagesize TLB (VTLB) and fixed page size TLB (FTLB) • 64-bit MIPS64 Release Full • 48-bitvirtual andphysical addresses • design efficient Power • Dualissue instructionfetch, andgraduatedecode, issue, •(VP) supportProcessor Hardware multithreading through seamless Virtual • support Virtualization • with Error Corr L1 caches •vari- second-level on-core programmable by fast backed ITLB/DTLB first-level with Unit Management Memory • Load and store bondingsupport • Unalignedload support / store in hardware •Accelerated support Uncached • Optional Communication Inter-thread Unit (ITU) • Support uncachedfor Conditional and paired Load-Lioperations nked (LL/SC) andStore • Optional PadData Scratch (DSP) temporaryRAM block for storage 1.2.5 Core-levelFeatures MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
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17 develop/tools/ C0_ITAGLO C0_DESAVE C0_ERRCTL C0_IDATAHI C0_DTAGLO C0_IDATALO C0_DDATAHI C0_DDATALO C0_CACHERR C0_PERFCTL1 C0_PERFCTL2 C0_PERFCTL3 C0_PERFCNT1 C0_PERFCNT2 C0_PERFCNT3 C0_ERROREPC ildroot, Yocto, and GEN- and Yocto, ildroot, itecture. Linux kernel and itecture. $25, 2 $25, $28, 2 $28, $27, 0 $27, $26, 0 $26, $25, 3 $25, $28, 0 $28, $31, 4 $31, C0_KSCRATCH3 $25, 7 $25, $31, 5 $31, 6 $31, C0_KSCRATCH4 C0_KSCRATCH5 $31, 2 $31, 3 $31, C0_KSCRATCH1 C0_KSCRATCH2 $25, 6 $25, 3 $28, $31, 7 $31, C0_KSCRATCH6 $28, 1 $28, 1 $29, 0 $30, $31, 0 $31, $29, 3 $29, Idiom Registe If the device is in Guest mode, only a only Guest mode, is in devicethe If https://www.mips.com/ Assembler (continued) ude Debian, OpenWRT, Bu OpenWRT, ude Debian, r, compilers, MIPS boot loader, and MIPS RTOS and andMIPS RTOS compilers,boot MIPS loader, r,
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Table 1.1 Table Registers CP0 of Mapping Assembler C0_SAAR C0_MMID C0_SAARI C0_WIRED C0_COUNT C0_INTCTL C0_STATUS C0_SRSCTL C0_ENTRYHI C0_HWRENA C0_CONTEXT C0_COMPARE C0_BADINSTR7 $16, Software Tools Software PS MIPS actively supports, develops and improves the Li the improves and develops supports, actively MIPS MIPS offers a complete a portfolioofMIPS offers thattools address allstagesproduct of development, including MIPS Linux, MIPS Android, CodescapeSDK, debuggeCodescape e CP0 registers available in Root mode. in available CP0 registers those indicates that the above table Note these registers are available. subset of IoT support. Someof toolsthe provided describedare in the followingsubsections. distributions that currently support TOO. For more information ontheMIPS Linux, $4,5 $9,6 $9,7 $3, 1$3, C0_GLOBALNUM0 $15, $4, 0 $4, $4, 2$4, 4$4, C0_USERLOCAL C0_DBGCONTEXTID3 $15, 2 $15, C0_ C0_CDMMBASE4 $25, $5, 0$5, C0_PAGEMASK1 $16, $5, 1$5, 0 $7, C0_PAGEGRAIN 0$8, 2 $16, C0_BADVADDR$9, 0 5 $16, $8, 2$8, C0_BADINSTRP0 $17, $6, 0 $6, $8, 1 $8, MI $11, 4 $11, C0_GUESTCTL0EXT1 $19, $11, 0 $11, $12, 0 $12, 1 $12, $10, 0 $10, 4 $10, 5 $10, C0_GUESTCTL1 C0_GUESTCTL22 $18, 3 $18, 2 $12, Idiom Name Register 1.5.1 MIPS Linux Assembler MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 1.5
Google.For every Android
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, https://www.mips.com/develop/tools/ izing andfacilitatingMIPS cores debugging.These include https://www.mips.com/develop/tools/ https://www.mips.com/develop/tools/ https://www.mips.com/develop/tools/ ader wealth of expertise in the form of Windows and Linux softwarewealth of expertise Windows inform theof MIPS64® I6500Multiprocessing Syst ound bug-fixes,in thefixed. These are process along withoptimiza- any MIPS (bare-metal and Linux), iaSIM simulator, simulator, iaSIM Linux), and (bare-metal gethera
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SDK include cross cross SDK include MIPS offers widea rangeof MIPS solutionsoffers for initial running on MIPS cores. MIPS on to make therunning most software of developers Debugger enables Codescape tures, the For more information ontheMIPS Debugger, Collection (G Compiler GNU maintains the and ports MIPS cape MIPS SDK. A wide range of otheravaila industry are also leading compilers For more information ontheMIPS Compilers, open-source and proprietary solutions to suitany requirement. For more information ontheMIPS Boot Lo MIPS debugenvironment for heterogeneous SoC de The CodescapeThe software development MIPS toolkitprovides and libraries developingfor and debuggingsoftware fo The MIPS The emulator can be built fromtheAndroid Open development tools, Instructions are on the web site. are on Instructions For more information ontheMIPS Android, releaseQA performeda is and bugsf tions, goon top of the Android branchrelease and get rel mended to download the latestMIPS releases to get environment. ment For more information onthesoftware, MI PS Codescape MIPS MIPS to brings Codescape, With 1.5.6 Boot Loader 1.5.5 Compilers 1.5.4 CodescapeDebugger 1.5.3 Codescape MIPS SDK 1.5.2 MIPS Android 18
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deeply applications and the IoT embedded space. For more informat has developed the MIPS Em MIPS offers a varietyof development board offers MIPS Real Time Operating Systems (RTOS) and the new generatio and Operating Systems (RTOS) Time Real ment process.Resources include development platform MIPS collaborates with open-sour with collaborates MIPS For more information on the MIPS Developer Re theMIPS Developer Formore informationon 1.5.8 DeveloperResources 1.5.7 MIPS RTOS MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 em Programmer’s Guide, Revision 1.00 MIPS64® I6500Multiprocessing Syst 20
21 ntrol for differ- blocks are not blocks soft- are th the information used to used the information th System. The first section or TLBWR) to move the data the move to TLBWR) or
s and provides access co access s and provides respectively. These These respectively. e numbermapsThe e DTLB VPs. only of 4 KB, e instruction (TLBWI e TLB is used as a backup structure for the ITLB.a the If for backup structure used as a is TLB e same virtual address space. The MMUalso enforces space. The same virtual address e itsfunctionality ofthe a description elementsand that go B inthe I6500 Multiprocessing coprocessor 0 (CP0) registers wi 0 (CP0) registers coprocessor core, to physical addresses used to access caches, memory memory caches, used to access core, to physical addresses tributes. The I6500 MMU implements a Translation Looka- The I6500MMUtributes. implementsTranslation a ess translation is especially useful for operating systems that must manage must that systems operating for useful translation is especially ess en executes a TLB writ executes en , thetranslation information is copied into the ITLB/DTLB for futureuse. the ITLB or DTLB, the VTLB attempts to translate it in the following clock following the to translate it in DTLB, the VTLB attempts or ITLB the addresses to 48-bit physical addresse to addresses ations for the instruction and data caches instruction ations the for . Number entries of ITLB onvaries based the numberof maps VPs. The ITLB only4 1 . Number of DTLB entries varies based on th 1 16 KB, or 64KBpages. isThe DTLB managed byhardware and is transparent to software. KB, 16orKB, pages.KB, 64 KB TheITLB is managed andby hardware transparent is tosoftware. cycle or when available. If successful when cycle available. or fetch address cannot be translated by translated be cannot address fetch –= 8 entries 1 VP – 2 = 14 entries VPs – 4 = 20 entries VPs –= 6 entries 1 VP – 2 = 12 entries VPs – 4 18 entries VPs = ware visible and are shown only completeness. for shown visible and are ware • V The larger VP. per (VTLB) TLB Variable 16 dual-entry ent page segments of memory. The core writes to internal of memory. segments ent page The MemoryThe ManagementUnit (MMU) inthe I6500consists core of four address-translation lookaside buffers (TLB): •(ITLB) TLB Instruction the protectiondefinesof memoryareas and thecacheat (TLB). side Buffer of the TL elements programmable the This chapter covers 48-bit virtual TLB translates The I6500 The MMUthe generated by The virtual addresses translates addr Virtual-to-physical devices. other and physical memory to accommodate multipleactive inth tasks ofa description the TLB architecture, gives anoverview of into programmingtheThe TLB. sections that follow cover specific information onprogramming for the TLB. the registers to the TLB. from •(DTLB) TLB Data initialize and modify entries in the TLB, th in entries and modify initialize 1.perform transl ITLB and DTLB address The 2.1.1 TLBTypes MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 2.1 Overview Memory Memory Unit Management Chapter 2 Chapter
included in the docu- included ation on the Guest ation on the is not found, the VTLB/ found, the is not size of the VTLB the an tically cleared whenever the associ- the whenever cleared tically Data em Programmer’s Guide, Revision 1.00 Hit/Miss Hit/Miss Instruction the TLB. For inform
andIndexmatch. TLB entries which have their G RAM RAM Cache
all VPs. The FTLBall extends VPs. The Cache I6500 Technical Reference Manual Reference Technical I6500 exception is taken. Similarly, when a data reference is to data reference is when a exception is taken. Similarly, Tag Tag Instruction Data Comparator Comparator inal translation requested. n. The OS should process the exception by overwriting a TLB overwriting by exception the process The OS should n. as the VTLB when a miss occurs in the ITLB/DTLB. in the miss occurs the VTLB when a as Entry Entry the VTLB when required, and automa the VTLB when ITLB FTLB DTLB MIPS64® I6500Multiprocessing Syst VTLB/ t. If the address is not present in the DTLB, the VTLB/FTLB is accessed. If is VTLB/FTLB the DTLB, the in not present is If the address t. of instructions used when accessing used when of instructions IVA DVA architecture, refer to the to architecture, refer the I6500 architecture. MMU the IVA DVA
TLB or FTLB with the orig with FTLB or TLB
address is to If address be translated, accessed the translation is the ITLB is first. Data Address Address Figure 2.1Figure Core I6500 the in of MMU Architecture Overview Calculator Calculator Instruction —TLB Invalidatesset entries based on Index of a match. —Invalidates a setof TLB entries based on ASID shows an overview of of an overview shows ated VTLB is updated. updated. ated is VTLB time same 512 at the entries and is accessed extra Entries are automatically refilled from are automatically Entries bitset to1 are not modified. TLBINVF TLBINV • 512dual-entry Fixed thatTLB (FTLB) isshared between Figure2.1 This section defines the various types the defines This section • TLB instructions used in Virtualization, refer to the Virtualization chapter of chapter thismanual. refer tothe TLB Virtualization instructionsused inVirtualization, • When an instruction When entry from the appropriate V the appropriate entry from FTLB is accessed. If there is a miss in the VTLB/FTLB, an in a miss If there is FTLB is accessed. accessed firs be is translated, the DTLB in the VTLB/FTLB, an exception is take is a miss there MMU informationthe on more For mentation package. 2.1.2 TLBInstructions 22
23 register is Index registers toregisters be shared translations. shared register. across cores and VPs. VPs. across cores and EntryHi ed bywrittened hardwarebe to PageMask bit MMID (versus the 10-bit bit d MMID. Either one can be can one Either MMID. d , and , and reduces contention. Even under Even under contention. reduces and virtual address. The address. virtual Select 5. There is one MemoryMapID is one There 5. Select ess Space Identifier (ASID) to create a (ASID) Space Identifier ess will be disabled. However, the VPID will be disabled.However, res/VPs GID + with the same MMID in a cluster, the I6500 uses a feature uses the I6500 in a cluster, mmon name space enables mmon sharing of name space enables same translations on different VPs. different translations on same section of this for more information. section chapter of a generation core. On previous cores, the FTLB registers. PageMask registers. est ID (GID) that is common ID (GID) est , and the TLB for a specific the TLB core supports both ASIDan acement The 16- for the ASID. PageMask n causes a random TLB entry select TLB a random causes n GlobalTLB Invalidate register located at CP0 Register 4, Register at CP0 located register used to replace the traditional Addr used , translations are common for all co are translations , ed with the same process and use the use and ed with the same process Bflush when recycling ASIDs, the co means that the VPID check in the FTLB VPID check in the the means that inthe legacy mode (Config5.MI = 0). or running the same applicationdata.In this situation, ondifferent some translations globalized TLB invalidates. globalized , and EntryLo0/1 EntryHi, EntryHi, EntryLo0, EntryLo1 EntryLo0, EntryHi, mmon across cores and VPs and will enable the hardwareidentifytothe VPs and will enable and cores across mmon — The TLB Write Random instructio Write TLB— The Global The — InvalidateTLB instruction providesa way to globally invalidate all TLBentries inmul- EntryHi, EntryLo0, EntryLo1 EntryLo0, the EntryHi, instruction causes Read The TLB — — The TLB Probe instruction is used to probe to is used instruction TLB Probe The — with the contents of the tiple Refer ways or theto theTLB. entire GINVT loaded with the address of the TLB entry the the contents of contents match the whose of the address loaded with loaded withthe contentsof entry the TLB pointed to byIndextheregister. to be written register Index the by to pointed TLB entry the instructioncauses Index Write The TLB — TLBWI with the contents of the TLBWR TLBR TLBP registerVP. per check is still needed when operating operating needed check when is still Constraints Software WhenMMIDthe function is enabled, kernel software mustto adhere the followingprogramming constraints: • AllVPs given for a GuestmustID (GID) have thesamesetting inConfig5.MItheirfield. • Themust FTLB be flusheda changebefore toConfig5.MI. • AllVPs givenfor a GID musthavethe same FTLB page size setting. • Rootand Guest need not have the same setting in their Config5.MI fields. CP0 MMID Register in the MemoryMapIDstored is MMID The global name space that is co is that space name global theI6500 tomaintain backward However, compatibility, Linux, multiple threads can be associat all cores a core and in all VPs across of FTLB translations sharing enable To be feature can This MemoryMapID. called selected using the CP0 Config5register. repl (MMID) I6500 is a core, the MemoryMapID the In for each Gu space global name a to create sufficient ASID) is a TL for need Aside from reducing the VPs translations and between (GID includes= root). 0 as GID This are common across VPs and sharing the translations increases the FTLB capacity increases the translations sharing and common across VPs are 1) (Config5.MI MMID = is enabled When that are working cooperatively are working cooperatively that • • • anslations across all VPs in VPs all across shared translations FTLB supports core The I6500 • translationsbut the the VPs, be multiple threads not. In manywere applthere can ications, were shared across entries • 2.1.3 Shared FTLB Translations MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
0 0 1 1 0 0 0 b ’ R2 R R/W R/W l entries in the VTLB/FTLB VTLB/FTLB the in entries l Read/ Write Reset State Read/ Write Reset State MMID shows only those bits that are new are those bits that only shows em Programmer’s Guide, Revision 1.00 Refer to the CP0 Config the register 5 to CP0 Refer Figure2.3 er Field Descriptions er all Instruction TLB (ITLB) and Data TLB (DTLB) entries that (DTLB) entries TLB Data and (ITLB) TLB Instruction all fer to the CP0 Config5 register for for register to the CP0 Config5 fer is used for FTLB translations. FTLB for is used 16 15 0, ASID(X) writes and reads will ASID(X) writes and 0, Refer to the CP0 Config5 register for register for to the CP0 Config5 Refer MI GI gister. MMID writes are dropped and MMID writes are dropped gister. structions are supported. In the I6500 are supported. In the structions 18 17 16 15 14 instructions are supported. instructions Description Description MIPS64® I6500Multiprocessing Syst Figure 2.3 Figure Format Register Config5 Figure 2.2 Figure Format Register MemoryMapID Table 2.2 Table Regist Config5 Table 2.1 Table Descriptions Register MemoryMapID Reserved more information. core, this field is hardwired to 2’b11 to that both global instruc- indicate to 2’b11 hardwired this field is core, invalidate cache and TLB tion more information. 0: ASID is enabled. 1: is MMID enabled. are writes ASID(X) and allowed, are and reads writes = 1, MMID MI If 0. MI and read as When = dropped access lower bits of the re the 8+2 return 0. reads 17 whether ASID or MMID Indicates the 14:0Re version. from previous changes No 15:0translation. the for used ID value map memory the Stores 31:18 from previous version. changes No 16:15 if global invalidate in Indicates 31:16 Reserved. Refer 5 Refer to the CP0 register Config The I6500 The core providesI6500 kernel software with the ability toglobally invalidate the VTLB/FTLB structure usingthe new GINVT (GlobalInvalidate TLB) instruction. Whenthis instruction is executed, al are invalidated in all cores and all clusters. In addition, In clusters. and all in all cores invalidated are match in the VTLB are also invalidated. GINVTThe instruction provides the optionto invalidatethe TLB entries in the following ways: CP0 Config5 Register CP0The Config5 register has new fieldsa 2-bit well mapping as is enabled, as thatindicateor MMID if the ASID fieldthat indicatesthat the core supports globalinvalidate instructions. in theI6500 core. All other Config5 bits remainthe same as before. GI MI MMID Name Bit(s) Name Bit(s) 2.1.4 Global TLB Invalidate Reserved 31 31 24
25 s across all cores and clus- and all cores s across the entries across all TLB information, as well as as an well information, as $16,4.thee is non-zero, such as If indicates the size of the VTLB. This the size of the indicates the field is 2’b11, ‘type’ In the I6500 core the VTLB size is fixed at 16 entries, is fixed size the VTLB core I6500 In the eld is 2’b10, the TLB entrie maps thatmatch theMemoryMapID valueas wellas thein standard are also provided toolslibraries chapter register), the select number notis shown in the #define ster is locatedatCP0 16,register select 4 ($16,4). The 2’b01, the TLB entries across all cores and clusters are all cores and clusters TLB across entries the 2’b01, ing options for theI6500MMU. Each sectionprovides ed to determine the required program the variousprogram the functions requiredtomanagetheMMU. Wired instructions used todetermine theVTLB size. field intheinstruction setto2’b00, is all cores andTLB entries in all all iting their own support library, RTOS, or tool chain. Notethat most of the RTOS, iting their own support library, number) are used when the select valu number) are used when the select to by their register name. For exam- their register name. are referred to by CP0 registers ument, the C0_Config4, withC0_ indicating the register is partof the CP0 register set. register (CP0 Register 16, Select 1) Register 16, Select register (CP0 Config1 0 (for example,6,0 for the MIPS Codescape SDK. MIPS Codescape d is 0x0F (15 decimal). field in the MMUSize ters are invalidated only for those memory mapsthat matchthe MemoryMapID value. invalidated onlythose for addresses thatmatch thevirtual address. #define C0_CONFIG1mfc0ext $16,1 addiu C0_CONFIG1 t0, 6 t0, 25, t1, 1 t1, t0 into and place register Config1 //read t1 into and place 30:25 in bits value //extract in t1 value 1 to the //add the virtual address. cores and clusters are invalidated only for those memory only for clusters are invalidated and cores clusters are invalidated,are clusters without forregard any virtualaddress of memory mapID mateh. •If the field‘type’ is Invalidate by virtualaddress only. value is loaded by hardware based on the system configuration. system the on based by hardware loaded is value fiel of so this the size VTLB Size Code Example the Determining followingThe example shows theassembly language Register Interface Register 6-bit The •‘type’ fi the If ID value only. Map by Memory Invalidate Throughout thecodeexamples inthis doc CP0 registerCP0 information listingtheregister and field(s) us into the incorporated as referred to register ple, is the Config4 A separate #definestatement indicates that the Config4 regi value. numerical only the compiler interprets and select variables (register number Both The followingThe subsections describesome of theprogramm assembly code example. assembly sectionintendedThis is toprovide examples ofhow to Itis a gooda reference programmer for wr functionality theprogrammingof examples provided in this register is of a select value statement andwill be interpretedas zero bythe compiler. • entire TLB.the Invalidate the ‘type’ If • Invalidate by virtualaddress and MemoryMapID value. If 2.2.2 Determining Size the VTLB 2.2.1 Assembly Language Conventions MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 2.2 MMU Programming
0 4 3 size. can be This R/W field inthe FTLB. Inthe I6500 core, em Programmer’s Guide, Revision 1.00 the 16 KB recommendation is when is 16 KB recommendation the 8 7 ze and organization ofze and organization the MMU. The num- Size FTLBWays FTLBSets ) determines) theFTLB page instructions used to select a 16 KByte page size. select used to instructions ) indicates the number number of ways the indicates ) ) indicates the number of FTLB sets per way. IntheI6500core, indicates) numberthe ofsets per way. FTLB 13 12 FTLB Page Size FTLB Sets FTLB Ways FTLB gisters are used to initialize the VTLB. initialize the are used to gisters field. er of TLB misses. One exception to One exception TLB misses. er of MIPS64® I6500Multiprocessing Syst register fields to determine the si the determine to fields register Config4 Config4 Config4 INDEX Index iguration are described in the following subsections. addressingcan be used the VTLB mustbeinitialized. is The FTLB initializedautomati- register ( bit definitionsbit Page FTLB Figure 2.4 Figure Fields FTLB Register Config4 CP0 register ( register ( Config4 Config4 Config4 See CP0 Register set See for programmed select pages sizes to of 164 KB, KB or 64KB. The traditional pagesize buthas been 4 KB most implementationsOS support 4 KB or 16MIPS recommends KB. usinga 16 KB page size toimprove perfor- the numb reducing by greatly mance usingthe Android OS which only supports 4a KB page size. This field encodedis as follows: thisread-only valuealways is fixed ways. 4 at #define C0_CONFIG4mfc0li $16,4 C0_CONFIG4 a0, insmtc0 2 a3, a3, 8, 5 a0, C0_CONFIG4 a0, into a0 and place register Config4 the // read register Config4 the of a0 into contents the // write a0 12:8 of in bits Size field Page FTLB // insert a3 into for a 16k Page size value set // thisread-only valuealways is fixed 64 sets at per way. – 0x1: 4 KB – 0x2: 16 KB – 0x3: 64 KB • Bits 12:8 theof This section describes the procedure for VTLB/FTLB initialization. When the core is first powered up the TLB is not is TLB the up powered first is core the When initialization. for VTLB/FTLB procedure the describes section This virtual Before for use. ready callyin hardware and does not require involvement.anykernel software Interface Register following CP0 and associated steps re The 1.to the CP0 zeros all Write Register Interface Register core uses the following CP0 The I6500 CP0 the using configurable size is FTLB page the Only core. I6500 the in fixed are ways FTLB and sets of FTLB ber Config4 register as follows. • the of 3:0 Bits The FTLB page size and conf size FTLB page The • Bits 7:4 of the Setting the FTLB Page Size Code Size Code Example FTLB Page the Setting followingThe example shows theassembly language 2.2.4 VTLB and FTLB Initialization 2.2.3 FTLB Size ConfigurationPage 31 26
27 reg- Index instructionTLBWI entry VTLB, which addedis to instruction. TLBWI the is also used for This register software intervention is requiredto initializetheFTLB. field. Each VP contains a 16- sfully translated by the core). translated successfully was address a particular ether INDEX ted on each VP before the can be used. TLB ted before on each VP // and invalidates all VTLB entries all invalidates // and Index invalidate is enabled. When this bit is set, the set, the is bit this When enabled. is invalidate TLBWI instruction.TLBWR register (CP0 register 0, Select0). bit to indicate that to indicate bit Index EHINV EntryHi TLBP instruction which failsto find matcha for the specified virtual bitaddress sets 31of the instruction (used to determine wh instruction (used to determine TLBP register determines which TLB entry is accessed by a accessed entry is TLB which determines register the 512 entry shared FTLB to determine the total number of TLBentries. #define C0_INDEXli $0,0 mtc0 0x0000010F t0, C0_INDEX t0, entries) (# of VTLB 255 + 16 field = Index //set register into Index value //write #define C0_INDEXli $0,0 mtc0 0x0000000A t0, C0_INDEX t0, 10 field = Index //set register into Index value //write Index #define C0_INDEX mtc0 $0,0 tlbinvf C0_INDEX zero, register the Index into a zero // move caches TLB internal flushes Flush Invalidate // TLB acts as a TLB invalidateoperation, setting validthe hardware bit associated with theentry TLB to the invalid Thisbitstate. is ignoredona Indexing the VTLB Example the Code Indexing followingThe example shows theassembly language instructions used toindex VTLB entry 10. ister, indicating a probe failure. ister, Interface Register 1.the Set Note that a that Note result of a of result Indexing the FTLB Code Example the Indexing followingThe example shows theassembly language instructions used toindex FTLB entry 255. Initializing the FTLB Code Example InI6500the FTLB is initializedthe in hardware. No kernel A 10-bitindex valueused tois indexup maximumto a 528 of thedualentries of VTLB and FTLB. This value is stored in bits9:0 of the The instruction sequence above must be execu instruction above sequence The 2. Execute instructiona TLBINVF to initialize entriesall thein VTLB. Initializing Example the VTLB Code Allentries inthe VTLBinitializedare at thesame time using the TLBINVF instruction. The 2. theappropriate TLB index Write to the 2.2.5 Indexing FTLB the VTLB and MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
. In this fig- In this . exception. registers. The registers. Figure 2.5 Figure EntryLo1 register is used to is used to register Index register. The ‘VPN2’ register. itable.bit this If a one, is the VTLB. If the value in the value VTLB. If the TLB ModifiedTLB and . e ASID. For more informa- e registerdepends on the page EntryHi r-up, is this registerset to 0, and r-up, n Linux, for example, each applica- example, for Linux, n EntryHi EntryLo0 e page size of the TLB entry. For the For TLB e entry. page size of the The by the operating system. ASID em Programmer’s Guide, Revision 1.00 be set to the page size of the when the FTLB size of page be set to the e translation is stored in is stored e translation are set in the MMU set in are s been written,s and/oris wr er (which along with the offset becomes the physical the becomes offset the with along (which er . translation will mostlikely storedbe inthe FTLB. nd correspondingfields to be programmed when -sizevirtual regionwhich mapsto a pair physicalof command is executed and the value in the in and the value command is executed TLBWR mber in theTLB data during normal operation. Each data entry can have one of three cache coherency data Each e first write that causes an exception. Software can use use Software can exception. an causes first write that e ed as a replacement for th for a replacement ed as e supported. For the FTLB, page sizes of 4 KB, 16 KB, or KB, 16 KB, 4 of sizes FTLB, page For the supported. e e appropriate data, then exe- the with above s the registers rtual to physical mapping. The TLB entries are filled using filled are entries TLB The mapping.physical to rtual of TLB flushing on a context switch. The ASID field Cached Coherent Read-Share or CachedCoherent , size of the VPN field in the size bit is a cleared, stores to the page cause a page cause the to cleared, stores bit is a anslationwill be stored to theVTLB. a tag portion and dual-data portion as shown in shown as portion and dual-data tag portion a e loaded with the appropriate information, the the appropriate information, the with loaded e ace identifier (ASID) register. register determines th This register. MIPS64® I6500Multiprocessing Syst Shared FTLB Translations command. When a TLBWI When command. PageMask command is executed. During reset or powe During reset or is executed. TLBWI command Uncached Accelerated Uncached , cations to co-exist in the TLB (i TLB to co-exist in the applications different multiple Uncached — Indicates the TLB page size. This register must register This the TLB page size. Indicates — TLBWR instruction. Note that the — Stores odd numbered physicalframe numberinthe—Stores TLB data during normaloperation. — Stores even numbered physical frame nu frame even numbered physical Stores — — Stores the virtual — Stores page numberin the TLB tagduring normaloperation. a — Used when stores tothe page are permitted.this If th on handler the exception in be set should bit D The thisbit to track pages that havebeen written toby clearing this bit when thepage is firstmapped. attributes: thisvaluewritten is toallVTLB/FTLB entries. PageMaskregister does notequal the FTLB page size, th the the FTLB page size, the PageMask register equals FTLB is accessed using a tr a slight chance the there is However, EntryHi EntryLo0 EntryLo1 PageMask address). TLBWI or •ha that the page D bit is the dirty flag and indicates The • •cache data for this page. to C field indicates how The ‘0’ indicates the even numbered TLB entry, and the‘1’ nomenclature indicates the odd numbered TLB‘0’entry. indicates the even numbered TLB entry, •numb frame physical corresponding PFN stores the The • • Index VTLB, page sizes of 4 KB to 1 GB in powers of four ar in powers 1 GB to sizes of 4 KB page VTLB, 64 KB are supported. allows translations for translations allows code and data lyingtiondifferent theinhas same region).virtualaddress (MMID) I6500 can be us core, the MemoryMapID the In tion,refer to the sectionentitled extends the virtual address with an 8-bit memory space identifier assigned identifier memory space 8-bit address with an the virtual extends designation indicatesthat thisaddressdouble-pagefor a is helps frequency to reduce the field The ASID pages. • • To fill an entry in theVTLB/FTLB, update kernel software To cutes a size as noted by the ‘x’ and ‘x-1’ nomenclature. The registers a ‘x-1’ nomenclature. ‘x’ and as noted by the size follows. listed as are the TLB accessing •the CP0 in is set PageMask • sp address (VPN2) and address Virtual the registers listed below. After the registers ar the registers After listed below. registers the determine whichentry will be written. Interface Register of VTLB/FTLB consists the TLB entry in Each ure, the following registersused to manageare the TLB entries. This section describes how to setup the TLB to create a vi a the TLB to create setup sectiondescribesto how This •the MMU in set are bits XI0/1 and RI0/1, G0/1, V0/1, D0/1, C0/1, PFN0/1, 2.2.6 TLB Entry a Programming 28
29
0 TLB Invalid TLB ASID One TLB Entry bit is always writable is always writable bit RI concatenated with the PFN concatenated x x-1 10 9 EntryHi TLB Tag TLB ddresses mustbe enabled bysetting Entry 1 Entry Entry0 TLB Data TLB VPN2 47 (Valid) bit is set. The is set. bit (Valid) en if the V (Valid) bitbit The is set. XI is writ- en if theV(Valid) V Logical AND Logical V0 4861 y, the G bits of both Entry 0 and Entry 1 reflect the reflect 1 Entry and 0 Entry bothof bits G the y, registers is writable and registers is writable entry G bit is a one, then the ASID comparisons are ASID comparisons the a one, then bit is G entry gical AND of the G bits in both the Entry 0 and Entry 1 Entry and 0 both the Entry in bits the G AND of gical 62 register is always set. register is D1 V1 D0 R is set, which is always the case in always the I6500 core. the case which is is set, 63 0 this bit is a zero, accesses to the page cause a the page to a zero, accesses is this bit EntryLo1 C1 1 C0 Flags = 1), even if the = 0 2 and PageGrain IEC 3 CDVG CDVG XI0 XI1 register. Setting this bit allows for 48-bit physical addresses. When thisWhen addresses. physical for 48-bit allows Settingthisbit register. VPN2 ASID G ts that are stored in bits 63:62 of the virtual address and divide the virtual the divide address and virtual of the 63:62 bits stored in are that ts 65 65 3 2 1 0 EntryLo0 bit the of RI0 RI1 PageGrain RIE 13 12 PageGrain R PageMask EntryLo0 PFNX/PFN PFNX/PFN exception ( EntryLo1 PageMask 41 TLBRI PFN0 PFN1 42 Figure 2.5 Figure TLB Entries and Registers CP0 Between Relationship PageMask 31 30 virtual page causes or a TLBXI exception, ev a TLB Invalid page causes virtual able onlyXIEthe if bitof the PageGrain register bit is set, accesses to are permitted. If the page set, accesses is bit exception. TLB G bit. the state of a a causes registers become the G bit in the TLB entry. If the TLB the G bit in the TLB entry. become registers a TLB entr from read On a during TLB matches. ignored in the I6500 the in core since the memory map into one of four regions. four of one into map memory CP0 the bitof ELPA the fieldof the the PFNX set, isbit field to form the full number. page frame 61 •the from instruction an fetch to attempt any entry, TLB a in set is bit this flag. If execute-inhibit the XI is The • If this is valid. page mapping, virtual the thus and entry, the TLB that and indicates flag the valid is V bit The •the lo TLB write, a Onbit. G bit is the “Global” The • page virtual the on data read to attempt any entry, TLB a in set is bit this If flag. read-inhibit the is RI The •bi region are the bits in R field The • physical a for large support used, than 32 bits are larger address sizes If Xl Xl 62 61 42 41 62 Rl Rl 63 63 63 MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
Wired register is reset to is reset to register TLBWI instruction. register specifies the register specifies thisfield of register Wired Wired field toavoid guestTLB Wired ire a TLB entry. In this example the In this entry. TLB a ire em Programmer’s Guide, Revision 1.00 field, which leaves at least one entry least at field, which leaves s non-replaceableare fixed, entries that register is dropped. The is dropped. register Guest.Config1.MMUSize Wired Config1.MMUSize e wired. If the value in wired. the If the value are VTLB the of 0 and 1, 2, configure the configure the register (CP0 register 6, Select 0). The register 6, register (CP0 //by 6 bits //by = 5,1,1,1 CDVG //load 5:0 bits into EntryLo field CDVG //insert page even EntryLo //write page, invalidate odd EntryLo //write KB to 16 page size //set register PageMask //write 4 entry VTLB //select register Index //write load TLB to instruction TLBWI //execute language instructions used to hard-w to used language instructions Wired field is set to 0 by default, indicatingdefault,field to 0 by is set that all but one of the VTLB entries , then the write to the the write to then , MIPS64® I6500Multiprocessing Syst Root should random entries in the VTLB. Wired entrie Wired the VTLB. in entries random Wired.Limit instruction. However, wired entries instruction.TLBWR can be overwrittenHowever, by a field can be set to the value in the the value in to set field can be Config1.MMUSize accomplished using the Limit #define C0_WIREDli mtc0 0x000F0005 t0, $6,0 C0_WIRED t0, = 5 field 15 and Wired field = Limit //set register into Wired value //write #define#define C0_ENTRYHI#define C0_ENTRYLO0#define $10,0 C0_ENTRYLO1 $2,0 #define C0_PAGEMASK $3,0 C0_INDEX $5,0 li mtc0 0x12340000 t0, li $0,0 $10 t0, li >> 6 0x23450000 t1, dinsmtc0 0x002F t2, t2, 0, 6 t1, 0 ASID = VA = 0x12340000, right //set value the PFN and shift PA = 0x23450000 //set mtc0 $2 t1, li $3 zero, mtc0 0x00007FFF t2, li $5 VA and ASID t2, with EntryHi //write mtc0tlbwi 4 t3, $0 t3, open for Guest random replacement. for Guest open randomization for replacingRoot wired entries. Example Code a TLB Entry Hardwiring shows the assembly following example The first 5 entries of the VTLB are wired. boundary between the wired and the wired boundary between zero by a zero Reset exception. by the core, I6500 the in that Note CP0 Programming Interface CP0 Programming I6500The core allows upto 15 entries of the tobeVTLB hardwired such that theycannot be replacedbya TLBWR instruction. This is Programming a TLB Entry Code Example Code a TLB Entry Programming to 0x12340000 address from virtual mapping to create a single how shows example language assemble following The and bitsG the of setentry to specific value. a physical address 0x23450000with theC,V, D, can be wired. The can be wired. cannot overwrittenbe bya wiredentriesThe thein VTLBmust be contiguous and startfromFor example, the0. if this indicates that entries 4, 3, 0x5, value of contains a is greater than register 2.2.7 Hardwiring VTLB Entries 30
31 y to index the entry. The y toindex theentry. mode does nothave permission modedoes tion is taken. This scheme is used is scheme This is taken. tion register must register be consistent with the FTLB set sizeto indexa particular toFTLB set in order main- kernel, user, andsupervisor modes. kernel, user, bit hashingis 1, is ignoredand the indexing entriesare register matches page size the FTLB currently sup- the register FTLB set and choose a random wa a set and choose FTLB EHINV Pagemask exception is taken whenexceptiontakensupervisor is EntryHi ere isa ere TLB hit,but the valid bitfor that TLB entry is notset. any miss. a mode, there is TLB exceptionAdEL is taken when supervisor mode does nothave permission exception is takenwhen user mode does nothavepermission for the exceptionis taken mode user when does not have permissionthe for either the VTLB or the FTLB, the I6500 core allows for the following types of types following the for allows core or the FTLB, the I6500 VTLB the either and TLBWIthe Instruction AdES AdEL registers. If not, a machine check excep check machine a not, If registers. PageMask and bit is 0. When the 0. When is bit EHINV exceptions(TLBL andTLBS) are taken under thefollowing conditions. EntryHi exceptions (AdEL and AdES) are used in AdES) are used exceptions (AdEL and exception (TLBL, TLBS) is taken on any TLB miss regardless of the operating mode and uses the fol- uses the and mode operating the of regardless TLB miss any on taken (TLBL, TLBS) is exception EntryHi is ignoredbit a TLBWRfor instruction. for the address being being accessed. for the address for the address being accessed. being for accessed. the address address being accessed. being accessed. address address being accessed. being accessed. address EHINV •insupervisorstore an AdES mode,a On • an mode, user in On a load • Addresserror (AdEL orAdES) •TLBS) Refill (TLBL, TLB •TLBS) Invalidate (TLBL, TLB • TLBRead Inhibit (TLBRI) • TLBExecute Inhibit (TLBXI) • TLBModified (TLBM) • Parity FTLB •Check Machine • On a loadinsupervisor mode,an • mode, an user in On a store • TLBLin non-store exception: On a • a TLB miss. TLBSstore in any mode, there is On a exception: • TLBL exception: On a non-store, th • TLBS exception:Onstore a in any mode,is a TLB hit,there but the valid bitfor that TLB entry is notset. TLB Refill TLB invalidated. a the TLBWRWhen and executed instruction is TLB exceptions. Error The Address EntryHi occurs in miss TLB a event that the In tainconsistency. the Index the FTLB, a TLBWIis targeting executed When instruction from the calculated only when the The I6500 core uses a hashing scheme based on VPN and page and VPN on based scheme hashing a uses core I6500 The ports, hardware uses the hashing scheme to calculate the calculate scheme to hashing the hardware uses ports, The opcodes. TLBS TLBL and lowing TLB Invalidate The TLB 2.2.8 FTLB Scheme Hashing MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 2.3 Handler Exception TLB
register. register. bitis not EHINV BadInstr capture address infor- capture EntryHi meof the information ssociated with that entry ssociated ructure that stores virtual- that stores ructure register that captures the the captures that register ster that captures the most the that captures ster the FTLB page size setting size page FTLB the eared, FTLB parity errors are parity errors FTLB eared, ster containing a pointer to an to a pointer containing ster the case in the I6500 core. I6500 case in the the lting instructionis ina branch the case in the I6500 core. the I6500 in the case use with the XTLB Refill handler, withuse theXTLB Refillhandler, onsistency. The machine check onsistency. thepage table entry (PTE) array. register is provided to allow accelera- allow provided to register is em Programmer’s Guide, Revision 1.00 register does not it duringa loadoperation, the bittheRI of register duplicates so register duplicates BadInstr register is a read-only BadVAddr a store and the Dirty bit a store a companion document theprovideddocumenta-in ) is set. If this bit is cl is bit If this is set. ) register is a read-only regi a is register PE . an operating system data st an operating ster does not correspond to does not correspond ster XContext ). register is used in conjunction with the with conjunction in used is register register is a read/write regi P ErrCtl BadVAddr bits whichare set, is always BadInstr XIE bits are set, which is always is which are set, bits CP0 RegistersCP0 anch instruction, when the fau instruction, when anch register is onlyregister set by exceptions which are synchronous to an cessor detects an internal internal inc detects an cessor ity error occurs on an FTLB read. FTLB parity exception is The ity error XContext BadInstr RIE FTLB Page Size Page FTLB register ( register register is primarily intended for e they are not addressing errors. addressing e they are not BadInstr PageGrain the exception to occur. The occur. the exception to Config4 MIPS64® I6500Multiprocessing Syst registers tomanage exceptions.TLB PageGrain at caused the exception. The the exception. caused at and XContext IEC Error Control Error and IEC exception (TLBXI) is taken when there is a TLB hit during an instruction fetch, the XI bit of XI bit fetch, the instruction an during hit TLB a is there when is taken (TLBXI) exception PageGrain register contains the prior br exception (TLBRI) is taken when there is a TLBh when there is taken is (TLBRI) exception P exception occurs when the pro when the occurs exception PageGrain (CP08,register Select 0):The 64-bit (CP0 register 8, Select 2): The (CP0 (CP0 register 20, Select 0): The register (CP0 (CP0 register 8, Select 1): The 64-bit The 1): Select 8, (CP0 register exception a is taken whenever par (CP0 register 4, Select0): Contains thepointer toan entry in exception is taken whenever there is a TLB hit on hit TLB a is there taken whenever is exception BadInstr to-physical translations.The The TLB Refill. on also loaded by hardware a is but provided in the BadVAddr register. provided in the BadVAddr delay slot. delay entry in the page table entry (PTE) array. This array is This table (PTE) array. entry page entry in the instruction. BadInstr BadInstrP BadVAddr Context XContext most recent virtual address th recent virtual most recent instruction which caused caused instruction which recent The tion of instructionemulation. The mation for cache or bus errors, sinc for bus errors, cache mation or • • • in bits12:8 of the Config4 register ( set. • • TLB Execute Inhibit Execute Inhibit TLB FTLB Parity Parity FTLB TLB Modified TLB Formoreinformation onreferthese registers, to the tion package. A CP0 the of 31 bit when only taken is not set. An ignored. The Machine Check TLB Read Read InhibitThe TLB entry is set, theand The the the entry is set, and •regi PageMask the FTLB and the to TLBWI instruction A •the FTLB/VTLB. across is detected a duplicate/overlap A TLBP instruction and • AnyTLB lookup anda duplicate/overlap is detectedthe across FTLB/VTLB. Interface Register uses the following CP0 core The I6500 exception can be either precise or imprecise depending on the type of error. The following The exceptionconditions can be eithera orcause precise imprecise depending on the type of error. machine check exception: • A TLBWI instruction totheand FTLB the index are notand VPN2 consistentwhen the 32
33 register so EntryHi 64-bit addressing modes, and modes, addressing 64-bit thischapterandprovides multi-threading considerations,guest lylanguage implementation of a TLB register as the memory address to read the to read the address memory as register register and their own scheme to access the correct to access register scheme and their own translation flow toillustrate the circumstancesunder Context XContext register instead example needs to read the XContext of register w to select between 32- and w BadVaddr Virtual Page Number (VPN) that missed to the to missedthat (VPN)Number Page Virtual , supervisor, user, anddebug operating modes. user, supervisor, , rityerrors,erroraddress detection, // Clear hazard barrier to insure CP0 write takes effect write takes CP0 to insure barrier hazard // Clear entry random TLB to // Write TLB exception from // Return The following example shows the assemb example shows The following lyuse thevalue thein CP0 serves as a supplement to Manual as serves Reference I6500Technical dmfc0 C0_XCONTEXT k1, 20) register (CP0 register XContext // Get .set noreorder .set #define#define C0_ENTRYLO0#define C0_ENTRYLO1 $2,0 #define C0_CONTEXT $3,0 C0_XCONTEXT $4,0 $20,0 dmfc0 C0_CONTEXT k1, ldld 4) register (CP0 register Context // Get dmtc0 0(k1) k0, C0_ENTRYLO0 k0, dmtc0 8(k1) k1, 2) register (CP0 CP0 EntryLo0 k0 to // Move C0_ENTRYLO1 k0, ehb 3) register (CP0 CP0 EntryLo1 k0 to // Move tlbwr eret K0 into EntryLo0 // Load k1 into EntryLo1 // Load TLBmiss32: the associated address mapping in the kernel in the address mapping the associated and root operating systems, and an in depth discussion of ho of discussion depth an in and systems, operating root and The MMUof The the chapter Note thatand do not some operating theContextuse systemslike or XContext Linuxuse a 3-levelregis- PageTable ters for page table lookup. Insteadthey use the CP0 For 64-bitaddressing modethe first instruction in theabove register: the Context which TLB exceptions are taken,FTLB pa page table entry. Refer to theLinuxdocumentation OS for details on thepagetable handling. page tableentry. additional information about the MMU, including an overviewof virtualto physical addresstranslation with 4 KByte, 16KByte, and 64 KByte page sizeexamples, address TLB Exception Handler Code Code Example Handler Exception TLB exception handler can direct The EntryLo0/1 settings. The processor also writes the writes also processor The settings. EntryLo0/1 it is ready to write the TLB entry. to it write the TLBis ready entry. 32-bitexception handlerfor addressing mode. MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 2.4 Information Additional em Programmer’s Guide, Revision 1.00 MIPS64® I6500Multiprocessing Syst 34
35 3 V P exceptions. well as cache initialization well as cache and instructions, hence the instructions, hence and 2 V P CPU n CPU 1 V P ndling cache ndling cache much faster than accessing main mem- faster much ion, L1 data, and shared L2. These and data, ion, L1 L1 Data Cache Data L1 L1 InstructionCacheL1 0 V P scription of the elements that go into program- go into that of the elements scription . The L1 instruction and L1 instruction The System. Multiprocessing I6500 to each cache is provided, as is provided, each cache to e L2 cache contains both data cache contains L2 e g up cache coherency and ha Shared L2 Cache L2 Shared same core. The L2 cache is shared by all cores. is The L2 cache core. same in the L2 cache, the main memory is accessed. memory is accessed. main in the the L2 cache, of information that can be retrieved retrieved be can information that of Coherence Manager (CM3) CoherenceManager ains the following caches: L1 instruct ains the de cache architecture and a 3 V P cache can be configured as follows: can be configured cache 2 V P Figure 3.1 Figure Caches System Multiprocessing I6500 CPU 0 CPU 1 V P L1 Data CacheL1 L1 Instruction CacheInstruction L1 0 V P shows the relative location of the caches within the within caches the location of the relative shows In the I6500 MPS, the size of each the size MPS, the I6500 In • L1 Instruction Cache:32 KB or 64 KB • L1 Data Cache: 32KBor 64 KB • L2 Cache: 256KB, 512KB,1 4 MB, MB, 2 MB, or 8 MB 3.1 Figure The I6500 Multiprocessing System cont System Multiprocessing The I6500 L1 data caches are shared by all VP’s in the VP’s shared by all are L1 data caches caches provide on-chip temporary storage temporary provide on-chip caches is not data first. If the accessed are and times access fastest the have data caches and dedicated L1 instruction The ory. Th the L1 cache, the shared L2 cache is accessed. in present not is If data the requested ‘shared’. name This of chapter provides an overview of the CP0 register interface description A caches. ming the code. Other programmable elements include settin MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 3.1 Overview Subsystem Cache Caches Chapter 3 Chapter
the line are the line Coherence Coherence ). The L2 communi- ). The L2 lly indexed and physi- indexed and lly t associativity of the cache. the of associativity t cache. the of associativity t tion Code (ECC) bits. bits. Code (ECC) tion CMrev ndexed and physically tagged, ndexed the line, for for a total of 64 the line, bytes. 1 MByte Total L2 2 MBytes 2 4 MBytes 4 8 MBytes 8 256 KBytes 256 512 KBytes 512 Cache Size is used when the cache size is 256 KB. 256 cache size is the when used is em Programmer’s Guide, Revision 1.00 re. the Software can check set size by struction cache is virtua cache is struction e error checking and correction process is handled and correction process checking error e . ECC code is generated across a 32-bit word. Sub- generated is ECC code . ze is fixed at 64 bytes. The number of sets and ways is is fixed at 64 bytes. ze Data cache is physically i is physically cache Data 8 16 16 16 16 16 data and associated ECC bits. associated ECC Alldata and bytes64 in corresponding to the 4-way se to corresponding the 4-way se to corresponding Ways L2communicateswith thecoresthroughthe proprietary Numberof physical address (dependingphysical on cache size), two coherentstate miss in the L1 caches. The L2 cache is larger than the L1 caches. In the L1 caches. than the L2 iscache The larger caches. the L1 in miss bit errors can be corrected bit MIPS64® I6500Multiprocessing Syst of 36-bit physical address physical 7 Error Correc bits and of 36-bit Th sequence. -modify-write e, a store operation can update all or a portion of the words in that line depend- in that line words the of portion a can update all or operation store a e, 512 512 2048 4096 8192 1024 Way cannot be changed by thekernel softwa Sets per Sets e L2 cache configurations. L2 cache e Table 3.1Table L2 Cache Configurations contains in tag and data. The two arrays: contains L1 64 bytes 64 64 bytes 64 64 bytes 64 bytes 64 64 bytes 64 64 bytes 64 LineSize shows the list of possibl shows the list chapter for more information. selected and during the build process The 16-way option is used for all other cache sizes. The line si 16-way option is used The address space. register Refer to the which ofis part the CMrev reading theGCR_L2_CONFIG register, MIPS CoherenceMIPS Protocol (MCP) bus. or 16 ways. The 8-way option 8 either be can cache of the L2 associativity The I6500 Multiprocessingthe L2cache System, the Coherence Manager is integrated into ( withcates external memoryviaAXI-4 an interface. The The L2 cache processes transactions that transactions processes L2 cache The cally tagged. An instruction cache data entry contains eight 64-bit doublewords doublewords in eight 64-bit contains entry cache data tagged. An instruction cally per set, tag and data arrays hold 4 ways of information The The L1 data. tag and two arrays: contains L1 data cache The eliminating a the chance of virtual aliasing. thus per set, tag and data arrays hold 4 ways of information The The L1 instruction cache L1 instruction The Manager Table 3.1 An instruction cache tag entry consists cache tag An instruction A tag entry consists of the upper 3534 or the of bits bits, and someECC bits. A data entry contains 64 bytesof stored with the tag. hence (2) the coherent state bits array in the data together, present in the cach resident is line valid a After store. of type the on ing data cache uses ECC so that single- The doing a read by handled are stores word entirelyby hardware and is transparent to kernel software. 3.1.3 L2Cache 3.1.2Cache L1Data 3.1.1 Cache Instruction L1 36
37 Cache Cache d the instruction. d to maintain inclusivity). program performance. PREF performance. program will perform the will specified perform the Cache column: s, the CACHE L2 Hit Invali- the CACHE L2 s, all instruction caches in a cluster. cluster. in a instruction caches all on cache line. This instruction should This instruction line. cache on g instructions: column. e core that execute e core invalidate all L1 instruction caches in the sys- caches in the L1 instruction invalidate all Code ations on the L1 instruction and data caches and the and caches and data the L1 instruction on ations ormed using the CACHE instruction. In this table, bits table, In this CACHE instruction. the using ormed from the cache, to improve from erations are globalized and erations D-Cache operations required D-Cache ction caches in all clusters. using the followin the using . em. In multi-cluster system In em. D Hit Invalidate, D Hit Writeback, or D Hit Writeback or D HitWriteback Hit D Invalidate,DHit Writeback, ing accessed as shown in the shown in as ing accessed ction caches in all clusters. ction caches Table 3.2 Table 500 and can be used to 500 a data cache line with an instructi with line data cache a ns only affect the L1 D-Cache of th the L1 D-Cache only affect ns on indicate the type of cache cache type be on of indicate the d on the L1I, L1D, caches and L2 L1I, the d on . instructions are "globalized", which means that they will invalidate the tar- the invalidate will they that means which "globalized", are instructions Invalidate CACHE I Hit — This performinstructionis— oper to various used — This instruction synchronizes — This instruction — This instruction is new to the I6 new to is — This instruction and — This instruction causes data to be moved to or to moved to be data — This instruction causes shows the various types of operations that can be perf that operations of types various the shows CACHE ions operat are described in These L2 cache. PREF does notcause addressing-related TLB exceptions. including exceptions, SYNCI be used whenwriting tothe program imagein memoryto make thenewly stored instructionopcodes visible to The on SYNCI instruction operates logic the instruction fetch via the I-Cache. means a L1 instru system, all multi-cluster this In tem. In a means tem. multi-cluster system, this all L1 instru In GINVI • Operations are performe Operations • • • The SYNCI syst caches in the L1 instruction cache line from all geted operation (including on all L2 caches in any L1 system the date, L2 Hit Writeback, and L2 Hit Writeback Invalidateand op L2Hit date, Writeback L2Hit Writeback, Bits 17:16 of the instructi Bits • cache indicates L1 instruction [17:16] = 2’b00 I — Bits •2’b01 [17:16] = data cache — Bits D indicates L1 Table 3.2 Table Note that the I6500 MPS does not globalize the CACHE the globalize MPS does not that the I6500 Note Invalidate instructions; these instructio For more information onhow these instructions refer are used, to the example inthesection entitled Initialization Routines 20:18the of instruction encodethetype operation of as shown inthe 3.1.4 Cache Instructions MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
regis- register. dirty, set the state of state the set dirty, and IDataHi rationis completed, ITagLo CP0 DTagLo register and DTagLo CP0 alization. Note alization. that Index IDataLo em Programmer’s Guide, Revision 1.00 e After that ope tag. e line is valid but not but valid line is e index into the CM GCR_L2_DATA register GCR_L2_DATA CM the into index ied index ied to invalid. DDataHi the and ECC bits are register tag IDataHi register, and the tag ECC bits are and the tag register, IDataHi index into the DDataLo register. index the register. into DDataLo software to invalidate the entire data cache by cache data entire the to invalidate software software to invalidate the entire instruction instruction entire the to invalidate software
Operation e specified index into the the into index specified e kernel kernel ces, except cache ces, during initi ne at the specified index into the CM the into index specified the at ne register at offset 0x0600. register at offset e at specif line the MIPS64® I6500Multiprocessing Syst read into the CP0 DTagLo register. DTagLo read the into CP0 CGR_L2_TAG_ADDR Read the data corresponding to the dword corresponding the data Read 0x0610. at offset Read the data corresponding to into the dword index the Read data corresponding the ters. CP0 to the stored bits are ECC data The register. stored to theCP0 ITagLo read the data corresponding to the word data corresponding read the The data ECC bits are read into the CP0 the into read are bits ECC data The If the state of the cache line at the specified index is valid and dirty, write the line back back line the write dirty, and is valid index specified the at line cache of the state the If cach by the specified address memory the to th line to invalid. If cache the state of the set invalid. to line the be by may used encoding This cache by stepping through all valid indices. through cache stepping by stepping through all valid indi all through stepping Store Tag should be used to initialize the cache power-up. the at should be used to initialize Tag Store For theL2 cache, this operationwill modify theL1 data caches asneeded to maintain inclusivity. This encoding may be used by kernel be used may encoding This y cache — Bits [17:16] = 2’b11 = 2’b11 y Bits [17:16] cache — Invalidate Table 3.2Table the of CACHE[20:18] Instruction Encoding Bits of S Tag Load Index li cache the for tag the Read D Index TagLoad th at line for the cache tag the Read D, S Index Writeback • L2 or secondar indicates S Code Cache Name 3’b001 I Tag Index Load the into cache index line at the tag the Read specified for the 3’b000 IInvalidate Index cach the the of state Set 38
39 regis- DTagLo DTagLo ITagLo te instruction. the cache line to invalid. cache the range of addresses from addresses from of range range of addresses from addresses from of range rresponding bits are set in the the bits are set in rresponding y and dword index specified. specified. dword index and y CHE Hit Invalida D (continued) taHi registers are used instead of the of instead used are registers taHi ataHi registers are used instead of the of the instead used are registers ataHi Lo register be ini- register be Lo ITag the that requires ware to initialize the entire data cache by cache data entire the initialize to ware caches, meaning that when executed, the the executed, when that meaning caches, software to invalidate a a invalidate to software a invalidate to software register.
Operation d address, set the state of set the address, d s. Doing so requires that the DTagLo register be ini- DTagLo requires that the so s. Doing not the globalize CA register contents at the wa the at contents register IDataLo e line at the specified index from the CM e line index from the the specified at the cache line at the specified index from the the from specified index cache line at the the register at offset 0x0600. register at offset register are used if the co used if the are register GCR_L2_ECC registers. nd data for the cache line at the specified index from the nd cache from CP0 the line at the data index for specified GCR_L2_DATA This operation may be used by kernel by used be may operation This range by the line size of the size cache. of line the the by the caches through address range stepping by is for the I globalized instruction This in the caches instruction L1 all from line cache targeted the invalidate will instruction system.For theL2 cache, the instruction would invalidateall targeted cache lines within all L2 cachesin all clusters. For theL2 cache, this operationwill modify theL1 data caches asneeded to maintain inclusivity. kernel used by be may operation This By default, the tag ECC value is automatically calculated. For test purposes, the ECC ECC the purposes, test For calculated. is automatically ECC value tag the By default, CM the from bits space. in CM address L2_CONFIG register GCR located CGR_L2_TAG_ADDR The hardware automatically generates the ECC bits to write into the cache. For test For test cache. the into write to bits ECC the generates automatically hardware The and DDa the ECC bits from the DTagLo purposes, valid indice all through stepping first. tialized the by hardware. generated The bits are always ECC automatically generated values when the ErrCtl.PO bit is set. ErrCtl.PO when the values generated automatically cache instruction entire the initialize to software by kernel be used may operation This so Doing valid indices. all through stepping by first. tialized and DDataLow bit is set. ErrCtl.PO when the values generated automatically may kernel soft be used operation by This The hardware automatically generates the ECC bits to write into the cache. For test For test cache. the into write to bits ECC the generates automatically hardware The and ID purposes, ECC bits from ITagLo the the ter. The data comes from the the from comes data The ter. range by the line size of the size cache. of the line by the caches through the stepping address range by the MPS does I6500 Note that This instruction only affects the L1 D-Cache of the core that executed the instruction. instruction. the executed that core of the D-Cache L1 the only affects instruction This Table 3.2 Table [20:18] CACHEthe of Instruction of Bits Encoding S Data Index Store CM the Write S Tag Index Store cach L2 the tag for the Write DInvalidate Hit invalid. to line cache of the state the set address, specified the contains line cache the If D Tag Index Store tag the a Write Code Cache Name 3’b011D I, Reservedas a no-op. Executed 3’b100 I, SInvalidate Hit specifie contains the line the cache If 3’b010 I Tag Index Store for (and data) the tag Write MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
L2 field of the GCR the GCR of field Writeback Invalidate, Writeback nd dirty, write the write dirty, nd t Writeback instruction. Writeback t range of addresses from from addresses of range L1 instruction data L1 and Hit Writeback Invalidate Invalidate Writeback Hit STATE STATE valid and dirty, write the write dirty, valid and (continued) ration to the locked line, or via an Index an Index via line, or locked the to ration s range by the line size of the cache. the line size of by the range s em Programmer’s Guide, Revision 1.00 ess and it is valid a is valid it ess and ches this operation executes as a this executes no-op. ches operation ndex Invalidate, Index ndex ready in the cache. In that case, the existing existing the case, In that cache. the in ready software to invalidate a a invalidate to software
Operation e specified address, fill it from memory and and from memory it fill address, specified e not the globalize D CACHE Hi field. register. specified address and it is and address specified (CCA). The cache coherency can be set in one of The three (CCA). ys at a given cache index. at a given ys Config.K0 MIPS64® I6500Multiprocessing Syst contents back to memory. After the operation is completed, leave the state of the line line of the state the leave completed, is operation the After to memory. back contents valid, state. but clear the dirty the does MPS I6500 Note that instruction. the executed that core of the D-Cache L1 the only affects instruction This For theL2 cache, this operationwill modify theL1 data caches asneeded to maintain inclusivity. ope Invalidate Writeback Hit Invalidate, or Hit caches. For the L1 instruction and data ca and L1 instruction the For caches. If the locked. and to valid state the Set replaced. being line the from data the writeback cache alreadycontains thespecified address, setthe state to locked.The way selected used. recently least is the memory from on fill I an executing by cleared is state lock The associated the in reset bit lock the with operation Tag Store the stepping the data cache by through addres the MPS does I6500 Note not globalize the that CACHE D instruction.This instructiononly affects theL1 D-Cache of the corethat executed the instruction. For theL2 cache, this operationwill modify theL1 data caches asneeded to maintain inclusivity. Tag RAM Cache Op Address Address RAM Cache Op Tag wa all lock to is illegal It The cacheline is refetchedeven if itis al addr specified the contains line cache If the copy in the cache is invalidated cache is the in copy contents back to memory. After that operation is completed, set the state of the cache cache of the state the set completed, is operation that After to memory. back contents invalid. to line the of state the set dirty, not but is valid line If the invalid. to line kernel used by be may operation This Fill the cache from address. specified Fill the Invalidate Table 3.2 Table [20:18] CACHEthe of Instruction of Bits Encoding L2 Fetch Lockand th does not contain cache If L2 the D, S HitWriteBack The I6500 core defines a set of Cache Coherency Attributes set core defines a The I6500 ways: •set coherency using the CP0 KSEG0 is space, In • Usingthe TLB entry for mapped address regions. •segments. Usingthe XKPHYS memory Code Cache Name 3’b111D I, Fetch Lockand not the I6500 The in and encoding is supported Fetch Lock 3’b110 S D, WriteBack Hit the contains line cache If the 3’b101 I 40 3.2Coherency Cache
41 : Use coherent data. Load Use coherent data. : from the cache. Stores to cache. Stores the from D-Cache before attempting rce a writeback from the L1 a writeback rce from all I-Caches in the system. The from all I-Caches in the system. er for more efficient bus utilization. bus efficient more er for ad misses request shared. e blockof instructionsit as invalidates theentire I- Attribute ed line in the cache, the line is updated to the exclusive exclusive the to updated is the line line in the cache, ed the I6500fetches the latestcore coherent data from the run-time, software must accommodate the Harvard run-time, software . s. When using cacheable memory accesses (CCA 3 or memory accesses = cacheable using s. When ndicated as uncached are not read uncached are not ndicated as be accomplished by or the SYNC and JALR.HB ERET be accomplished Table 3.3 Table ite-back, write-allocate, re write-allocate, ite-back, in memory, without changing without cache contents. in memory, in other L1 data caches are invalidated. L1 data other in e (will get exclusivethe if not data is being sharedbyanother CPU).Multi- ts 5:3 of the CP0 EntryLo0 and EntryLo1 registers. EntryLo1 and CP0 ts EntryLo0 the 5:3 of th new instructions at th new instructions Uncached stores gathered togeth are Uncached instructions can be used for this purpose. The SYNCI and CACHE I Hit Invalidate Hit I CACHEand SYNCI The purpose. for this instructionsusedbe can attributes is shownin : Addresses in a memory area i area in a memory Addresses : 1 3’b111 Accelerated. Uncached 3’b110#5). (code Mapped to ‘3b101 3’b011#5). to ‘3b101 (code Mapped Cacheable. 3’b1003’b101#5). (code Mapped to ‘3b101 wr coherent, Cacheable, 3’b0003’b0013’b010#5). (code Mapped to ‘3b101 #5). (code Mapped to ‘3b101 Uncached. K[2:0] such directly are writtenaddresses toma instructions. to fetch and execute the new instructions. This can new instructions. the to fetch and execute ich means they invalidate the targeted line the targeted they invalidate which instructions means are globalized, single Cache instruction. with a I Index Invalidate or GINVIIndex Invalidate I GINVI instructionGINVI can bewhen moreefficient writing a larg Uncached (code #2) Uncached (code Uncached Accelerated (code #7): (code Uncached Accelerated misses request data in the shared stat request misses bring into the cache in an exclusivedata state - no other Stores contain shared ple data in the state. caches can hits on a shar store line. If a same that contain can caches Cacheable, coherent, write-back, write-allocate, read misses request shared. (code #5) (code shared. request misses read write-allocate, write-back, coherent, Cacheable, state and any shared copies of the line the shared copies of state and any Table 3.3Table Register Config CP0 Field in the K0 the for Attributes Cacheability of Mapping L1 (includingD- and L2-Caches coresfromotherand fo there clusters) is no need to so D-Cache. Notethat unlike onsomeMIPS othercores, an I-Cache miss When the processor writes memory wi writes memory the processor When architecture and write-back policy of the I6500 L1 cache 2.processormustinstructions The wait ofhavethe newuntilall to the L1 been written CCA = 5), the followingsteps must be taken toprevent executionthe of previous (stale) contents of themodified memory addresses: 1.Invalidate,Hit CACHEI CACHEI-Cache.SYNCI, The the L1 mustfromstale instructionsbe invalidated Any The I6500 core supports the the following core supports The attributes: cacheability I6500 • • • cacheability mapping of The 1.to C the field field is also mapped This in bi MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 3.3 Self-modified Code
em Programmer’s Guide, Revision 1.00 ate CACHE or GINVI instruction (when or GINVI instruction CACHE ate L1 instruction and data caches, and the L2 instruction L1 ing instruction hazards */ ing instruction require synchronization, */ require synchronization, ze all caches around address */ around ze address all caches Register 16, Select1 Register 16, Select 0 Register 28, Select 0 Register 28, Select 1 Register 27, Select 0 1 Select 29, Register CP0 CP0 Register Number ion cache operations. cache operations. ion led after the new instruction stream is written to make those make to written is stream instruction new after the led Compare end address */ current with /* If size==0, *//*If size==0, /* Branch if moreto/*Branch if do */ /* Calculate end address + 1 */ address Calculate end /* /*branch around*/ Clear memory hazards */ /* /*branch around*/ /* branch around */ If no caches /* Synchroni /* /* Get step size *//*for Get step SYNCI /*Add instep size delay slot*/ /* Return, clear /* /* YNC instruction is required between the final SYNCI instruction in the loop the in instruction SYNCI final the between required is instruction YNC n could be replaced with an appropri replaced with be could n MIPS64® I6500Multiprocessing Syst instruction stream effective to the stream effective instruction r theinstructionr streamiswritten. instruction could be replaced with JALR.HB, ERET, or JR.HB instruction JALR.HB,could be replaced with and that the lable), ERET, tion on the CP0 registers used to manage the manage to used registers CP0 the on tion Config ITagLo IDataHi Config1 IDataLo CacheErr Table 3.4 Table Interface Register Cache Instruction ache ControlRegisters ache CP0Registers clears instruction hazards. instruction clears nop beq a1, zero, 20f a0, a1 daddu a1, rdhwrv0,HW_SYNCI_Step beq v0, zero, 20f nop daddua0, v0 a0, bne v1, zero, 10b nop sync sltuv1, a0, a1 nop DERET instructions, as appropriate. A S appropriate. as instructions, DERET and the instruction that and the /* * This routinemakeschanges to the * hardware. Itshould be calledafte effective. instructions are new * the On return, * * Inputs; new address of instruction stream* Start a0 = in* Size, a1 = bytes, of newinstruction stream */ 10: synci 0(a0) 10: cache. The I6500 core uses the following CP0 The registers I6500 for instruct This section provides informa This access to Coprocessor 0 is avai 0 Coprocessor to access ra jr.hb 20: The following example shows a routine which can be cal routine a example shows following The changes effective. The SYNCI instructio The effective. changes 3.4.1 Instruction C L1 42 3.4Interface Register
43 L1 instruction L1 ation (calculated by ation gister also stores the stores also gister e. The I6500 L1 instruc- EG0 region. memory e the associated instruction pre- e instruction the associated occurred. This register provides register This occurred. /written by the CACHE load tag/store CACHE load the by /written as number of sets, line size, and cache size, line sets, number of as cache. The I6500 L1 instruction cache sup- L1 instruction The I6500 cache. struction precode inform precode struction configuration and are built into the core. r the unmapped unmapped KS r the r a 32-KByte r cache). The re a cache error that cache register described above tostor L1D tag/data.FTLB tag/data, L2 or tag/data n cache. The I6500 cache. The associativity for the instructio n set is used to configure as a 32 KB cache, or 256 sets per way, which is used which way, per sets 256 or KB cache, 32 a as configure used to is IDataLo indicated by a value of 3 for this field. by indicated te cache, and bits 47:13 fo and te cache, g information of a cache line being read being line cache a of information g to obtain the L1 cache parameters such L1 cache parameters to obtain the tion opcodes) beingread/written bytheCACHE load tag/storetag operations. ndicates the line size for the instruction line size for the ndicates eld contains the cache attributes fo attributes the cache eld contains ) are needed to store both the data and in are needed to store both the data and ) y; during IP their values are determined IDataLo , IDataHi field (bits 18:16) indicates the 18:16) indicates field (bits r way in the instruction cach instruction way in the per of sets the number 24:22) indicates (bits field containsregister information regarding the typeof i (bits 21:19) field IA IS IL . . . Config1 Config1 Config1 associativity. The This register allows kernel software software kernel This allows register hardware unlessoverridden). Thisregister stores the64 bitsthe load of data. This register works in conjunction with the The CacheErr information such as: •error Correctable or uncorrectable • Array the error occurred;where tag/data, L1I •detected error was the way where The cache ta address the cache stores register This a 64-KBy47:14 for tag operations (bits ECC bits associated with the tag entry. Separate Valid and Error bitsindicate that the tagentry is valid,or an if ECC SeparateValid bitsECC associated with thetagentry. error has occurred. This register holdsthe data (instruc registers( Two tion cache supports 128 sets per way, which sets per way, 128 cache supports tion to configure a 64 KB cache. The In the Config register - the K0 fi the K0 the Config register - In ports a fixedlineofports a size 64 bytesas indicated bya valueof this 5 for field. The code bits, error information, and ECC status. information, and ECC code bits, error cache is fixed at 4-way set associative as associative fixed at 4-way set cache is read-onl are all fields These 3.4.1.2 Config1 Register (CP0 register 16, Select 1) 3.4.1.6 L1 Instruction Cache Register DataHi (CP0 register 29, Select 1) 3.4.1.3 CacheErr Register (CP0 register 27, Select 0) 3.4.1.40) Select 28, register (CP0 Register TagLo Cache Instruction L1 3.4.1.5 L1 Instruction Cache Register DataLo (CP0 register 28, Select 1) 3.4.1.10) Select 16, register (CP0 Register Config MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
EG0 memory region. occurred. This register provides register This occurred. em Programmer’s Guide, Revision 1.00 ng read/written by the CACHE load tag/ load CACHE the read/written by ng ng the L1 data cache. information about CP0 number configuration and are built into the core. r the unmapped KS r the cache error that cache Register 28, Select 3 Register 28, Select 3 Register 29, Select 3 Register 16, Select 0 Register 16, Select 1 Register 27, Select 0 way in the data cache. The I6500 L1 data cache sup- cache data The I6500 L1 cache. data the in way ta cache. The cache ta I6500L1 supportsa cache. data fixed the data cache. The I6500 L1 data cache is fixed at 4- at fixed is cache L1 data The I6500 cache. data the L1D tag/data.FTLB tag/data, L2 or tag/data yte cache). The register also stores also register cache). The 32-KByte 47:13 for a cache, and bits KByte MIPS64® I6500Multiprocessing Syst el software to obtain the followi el software to obtain the 0 registers cache operations. for data 0 registers eld contains the cache attributes fo attributes the cache eld contains Table 3.5 Table Interface Register Cache Data Config Config1 DTagLo DDataHi s in the L1 data cache data line caused the error data cache data the L1 in s DDataLo CacheErr y; during IP their values are determined CP0Registers field (bits 9:7) indicates the set associativity for the set associativity for indicates 9:7) field (bits field (bits 15:13) indicates the number of sets per sets of number the indicates 15:13) (bits field field (bits 12:10) indicates the line size for the da indicates field (bits 12:10) containsregister information regarding the typeof DL DA DS . . . Config1 Config1 Config1 The The Config1CP0 The register allows kern In the Config register - the K0 fi the K0 the Config register - In The CacheErr information such as: • error Correctable or uncorrectable • Array where the error occurred; L1I tag/data, • Fatal or non-fatal error •detected error was the way where The cache •word Which four one of of a cache line bei tag information the data cache address stores register This 47:14 for a 64- (bits tag operations store line size of 64linesize of bytesindicated as by a value of this5 for field. The The I6500 CP core uses the following The I6500 way set associative as indicated bya valueof way set associative 3 for this field. read-onl are all fields These ports 128 or 256 sets per way, which correspondsto ora 32 64 KB cache, respectively. KB ports per way, 128 or 256 sets The 3.4.2.2 Config1 Register (CP0 register 16, Select 1) 3.4.2.10) Select 16, register (CP0 Register Config 3.4.2.3 CacheErr Register (CP0 register 27, Select 0) 3.4.2.4 Register (CP0 register Cache28, L1TagLo Data Select 2) 3.4.2 Registers Cache Control Data L1 44
45 like the L1 instruction L1 instruction like the t indicates that an ECC error error ECC an that indicates t er contains the following CPC Local CPC GCR Global GCR Global GCR Global GCR Global GCR Global GCR GCR Global GCR Global GCR Global GCR GCR Global GCR Global GCR GCR Global GCR Address Space h do store L2 configuration informa- do h cache operations. Note that these regis- cache operations. Note that dicate if the hardware detected an ECC if the hardware dicate not located in CP0 CP0 located space in not g entry. An error flag bi flag An error entry. g or to the cache line. This the from or to data or stores h loads or to the cache line. This the from or to data or stores h loads s thats the L2 cacheinformation storedis in a memory- e configuration. This regist that the L2 cache has ECC logic. The L2_ECC_ENECC logic. The L2 cache has bit that the 0x0600 0x0300 0x0628 0x0308 0x0610 0x0038 0x0620 0x0618 0x0130 0x0240 0x0608 0x0008 Offset Address the loadas bit wellas data, a toin instruction, whic CACHE instruction, whic CACHE is unlike most previous MIPS cores whic is cores unlike most previous MIPS chapter for more information on accessing more these registers. chapter for ) uses the following GCR registers for L2 for registers GCR the following uses ) CM es information on the L2 cach the es L2 information on Table 3.6 Table Interface GCR Register Cache L2 the bits of loaddata. CR Control Registers CC_SUPPORTED field indicates CC_SUPPORTED address space at the offsets shown. They are space at the offsets address CM Coherence Manager Coherence CM L2_CONFIG GCR_L2_ECC GCR_L2_DATA GCR Registers GCR_L2SM_COP L2_RAM_CONFIG L2_PFT_CONTROL CPC_STAT_CONFIG GCR_L2_TAG_ADDR GCR_L2_TAG_STATE GCR_ERR_CONTROL L2_PFT_CONTROL_B GCR_L2SM_TAG_ADDR_COP register stores the the ECC information from register stores This is a for a specialThis staging register is error during the IndexLoadTag operation. error during the IndexLoadTag enables ECC. enables L2_Config register provid The information: In this register, the L2_E this register, In and data cache control registers. This This cache and control registers. data Refer to the Refer tion in the CP0 registers.The CP0 Config5.L2Cfieldindicate mapped register instead of CP0. register stores the lower 32 the lower register stores The I6500 Coherency Manager ( CoherencyI6500 The was detected by the index load tag operation. index the detected by was a for a specialThis staging register is the coherence state (MESI) and ECC bits associated with the ta the with associated bits and ECC (MESI) state coherence the ters are located in ters 3.4.2.63) Select 29, register (CP0 Register DataHi Cache Data L1 3.4.3.20x0130) (Offset Register L2_Config 3.4.3.10x0038) (Offset GCR_ERR_CONTROL 3.4.2.53) Select 28, (CP0 register Register DataLo Cache Data L1 3.4.3 G Cache CM L2 MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
instruction is exe- is instruction ations. The state machine ations. ate machine is idle or run- is machine ate ruction the is executed. If how the prefetch unit how handles the prefetch an L2 store cacheop is executed. store cacheop an L2 em Programmer’s Guide, Revision 1.00 L2 Load Tag CACHE CACHE Load Tag L2 L2 Store Data CACHE instruction is exe- instruction is CACHE Data Store L2 ates for the Tag RAM’s, Data RAM’s and Data RAM’s RAM’s, the Tag ates for bit is set then value of the DATA_ECC reg- bitsetthen is valueof the DATA_ECC n, flush, and burst oper n, flush, nimum operating systempage size. it indicates whether the L2 st indicates it L2 Store Tag CACHE instruction is executed. This reg- This executed. CACHE instruction is Tag L2 Store when the hardware cache initialization is complete. This initialization is complete. when the hardware cache enable bit, the number of bit, the number enable prefetcher includes a This cher. en a L2 Store Tag CACHE inst Tag L2 Store en a are set, the contents of the respective TAG_ECC and TAG_ECC of the respective set, the contents are s portion of the L2 Tag RAM when an L2 Store Tag CACHE RAM whenTag an L2 Store s portion theof L2Tag the L2 Tag and Data RAMs when the L2 Load Tag CACHE Tag Load and Data RAMsthe L2 when the L2 Tag L2 dynamic sleep mode, and L2 dynamic sleep wake-up delay. sleep L2 dynamic and mode, sleep dynamic L2 L2 Data RAMs when the L2 Load Data CACHE instruction is Data RAMs when the L2 Load Data CACHE instruction L2 the cache (set size, line size, associativity). and (set size, line the cache e L2 Tag RAMs and LRU information when the L2 Load Tag Tag Load RAMs and LRU information when the L2 L2 Tag e indicates the mi the indicates of this register is written to the tag state information portion of the L2 Tag Tag L2 the of portion information state tag to the written is register this of the ECC portion of the L2 RAM when RAM the L2 ECC portion of the bit is set then value of the TAG_ECC register is written to the ECC portion ECC portion the to written is register TAG_ECC of the value then set is bit MIPS64® I6500Multiprocessing Syst e machine during initializatio e written to the L2 Data RAM when an when RAM Data the L2 to written e Tag CACHE is executed. instruction Tag e address from the L2 Tag RAMs when the when RAMs from the L2 Tag address L2 prefetching enable per L2 port ID, and global code prefetch prefetching enable enable. eld, and a LRU state field. eld, and a DATA_ECC registers are written into written registers are DATA_ECC This register is loaded withregister is loaded This data information fromthe instruction If is executed. the GCR_L2_CONFIG.COP_DATA_ECC_WE executed. The value of this register is this of The value executed. field. 64-bit data a cuted. This register contains This register is loadedwith theECC information from is writtenister to the ECC portion of theL2 Data RAM wh GCR_L2_CONFIG.COP_TAG_ECC_WE L2 Stor a RAM when the L2 Tag of L2 cache stat the register controls This can be startedand stoppedusing theL2SM_COP_CMD field in bitsThe1:0.L2SM_COP_TYPE field theindicates b be performed. The L2SM_COP_MODE to of operation type CACHE instruction is executed. The value The executed. is instruction CACHE when an and WS RAMs the LRU data of RAM and the LRU a tag state fi contains ister rdware prefetcher, including including This register contains additional information prefetcher, ontheL2 hardware instruction is executed. This register is loadedwith stateinformation from th This register contains information on the L2 hardware prefet on the L2 hardware information contains register This mask that field a the and system, in L2 prefetchers coherent write invalidate requests, tag the withloaded is register This cuted. thisThe value of register is writtento the addres ds that indicate the number of wait st number of that indicate the 2-bit This register fields contains three Way Select RAM’s. Another read-only bit is set by hardware is bit Another read-only RAM’s. Select Way for HCI supported/done, support contains also register • Read-onlyfieldsthat of providethe organization • L2 bypass mode. • and dataECC protocol.write When these bits Tag 3.4.3.8 Register (Offset 0x0610) L2_DATA 3.4.3.90x0618) (Offset Register L2_DATA_ECC 3.4.3.100x0620) (Offset Register L2SM_COP 3.4.3.50x0308) (Offset Register L2_PFT_Control_B 3.4.3.70x0608) (Offset Register L2_TAG_STATE 3.4.3.40x0300) (Offset Register L2_PFT_Control 3.4.3.6 Register (Offset L2_TAG_ADDR 0x0600) 3.4.3.30x0240) (Offset Register L2_RAM_Config 46
47 require that CPC Local Status Status Local CPC llowing conditions conditions llowing the operation is complete complete is operation the where the operation begins. the operation begins. where ware cache initialization can initialization cache ware register as described in the previ- described register as at offset 0x0008 inCPC CM-local at address offset the L2_HW_INIT_EN bit in the bit L2_HW_INIT_EN the ber of ber lines tooperate onrelative to thestarting d indicates the address at address indicates the d y field that indicates when field that y iven low, indicating that automatic hardware initializa- ivenlow, y has expired, automatic hard expired, automatic has y to initialize the L2 cache: the L2 to initialize set the starting to the ess addr using in the cache setbefore hardware initialization can proceed. ther the L2 tag arraythe onlyL2tag ther (fast mode), or both the taganddata arrays rdware when the fo initialized by hardware be automatically to ormed is programmed into the L2SM_COP alization is enabled by setting enabled is alization rdware cache initialization rdware on, there are two types: are two on, there register (CPC_CL_STAT_CONF_REG) located register (CPC_CL_STAT_CONF_REG) andConfiguration space. begin. tion can proceed. •dela this expired. Once has L2 initialization delay The •initi hardware cache Automatic The I6500 MPS allows for the L2 cache MPS allows The I6500 are met at reset: are met • The external input pin(si_cpc_l2_hw_init_inhibit) is dr stem provides three ways provides three System Multiprocessing The I6500 • ha Automatically selected ning. The L2SM_COP_RESULT field inbits 8:6 is a read-onl ning.The L2SM_COP_RESULT •initialization hardware cache Manually selected • initialization cache Software For initializatihardware • arrayonly (fast) L2 Tag • and data arrays (slow) L2 Tag Manually selected Automatically cache hardware initializationselected (fast modeonly) initializes theL2 tagarray. hardware cache initializationei can initialize (slow mode). For software initialization by the kernel, one or both arrays can be initialized depending on the design of design on the depending initialized be can arrays both or one by the kernel, initialization software For mode). (slow the software. of Each these options are described inthe following subsections. and if errors errors were encountered. and if this register is used operations, burst For L2 cache field in bits47:6. Thisfiel L2SM_COP_START_TAG_ADDR ous subsection. hardwareThe initialization operationsdescribed in sectionthe entitled Cache L2 Initialization Options the L2_HW_INIT_ENbit (24)this of register is address. Theactual operation to be perf The L2SM_NUM_LINESThe field inbits 63:48 indicates the num 3.4.3.11 Register (Offset L2SM_TAG_ADDR_COP 0x0628) 3.4.3.120x0008) (Offset Register CPC_CL_STAT_CONF 3.5.1 AutomaticHardware Cache Initialization MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 3.5 Cache L2 Initialization Options
L2 L2 Cache Op L2 register ion to proceed. ion to L2 RAM Configura- L2 initialization process. initialization process. this register is present. A ‘1’ present. A is this register L2 Cache Op State Machine State Cache Op L2 the MBIST operation is com- operation is the MBIST 0x1 in this field indicates that this in 0x1 il the MBIST MBIST completed. has il the . em Programmer’s Guide, Revision 1.00 e initialization to be performed using the performed using be e initialization to is starts the L2 cache the L2 starts is in GCR address space. Software can poll this bit to bit this poll Software can space. address GCR in is automatically automatically hardware. No initializa-initialized by is lized by hardware. The user can choose to initialize only initialize to choose can user The hardware. by lized ivenhigh, indicating thatautomatic initializa- hardware lization does not begin until until not begin lization does L2 Cache Op State Machine L2 Config/Control CacheOp State amming fieldinthe L2SM_COP_TYPE bits 4:2of the ialization does not begin does not unt ialization r cache initializat order for idle, in machine is e Initializing theLevel2 Cache in GCR address space to determine if determine to address space GCR in complete, hardware sets the HCI_DONE bit in the the in bit sets the HCI_DONE hardware complete, that this type of initialization is is of initialization this type Note that by software. initialized manually register(GCR_L2SM_COP).of A value L2 Cache Op State Machineregister L2 Config/Control CacheOp State e L2SM_COP_CMDe field inbits the1:0 of MIPS64® I6500Multiprocessing Syst led, the cache initia led, re initialization options described above. The code used to performsoftware flush, burst, and abort operations. and abort flush, burst, register (GCR_L2SM_COP). A value of 0x0 indicates the process is still running. is still process the indicates 0x0 of A value (GCR_L2SM_COP). register kernel software indicates the type of cach of the type software indicates kernel ious subsection is not selected cannot proceed. and subsection is not ious n in the section entitled n in the ine Config/Control ine must be 0, indicating the stat 0, must indicating the be register (GCR_L2SM_COP) to a value of 0x1. Th value of 0x1. to a (GCR_L2SM_COP) register State Machine Config/Control Machine State A valueof 0x1 indicates thatthe process completed withno errors. Config/Control ess space to determine the state of the L2 state state the determine space to 0x0620 in GCR address address offset at (GCR_L2SM_COP) This bit machine. Cache Op State Mach State Op Cache only the Tag RAM is initialized. A value of 0x2 in this field indicates that both the Tag RAM and DataRAMis RAM is initialized.Avalue 0x2 of in thisfieldindicates that boththe Tag only the Tag initialized.RAMNote only. thatthis operation sloweris than initializingtheTag in thisbit indicatesthe flush that cacheoperation is supported. (GCR_L2SM_COP) at offset address 0x0620 at offset (GCR_L2SM_COP) tion described in the tion described in the prev plete. Even if the plete. the cache init if delay has expired, Even 3. Setthe operationtype of toperformed be by progr 5. field inbits the8:6 of determine the result of theinitialization, poll the L2SM_COP_RESULT To 4.th setting L2 state machine by the Start 2. Read L2SM_COP_MODEthe bit inthe followingprocedure. 1. Read L2SM_COP_REG_PRESENTthe bit inthe For manual cache initialization, This section describes the L2 cache describes This section The I6500 MPS allows for the L2 cache to be for the MPS allows The I6500 Once all of these conditions are met, the L2 cache Tag RAM Tag cache the L2 of are met, these conditionsOnce all is initialization the Once required. is code tion hardwa the than either of much slower is show cache initialization register (GCR_L2_RAM_CONFIG) at offset address 0x0240 address offset at (GCR_L2_RAM_CONFIG) register tion determine thewhen initialization is complete. manually initia be to the L2 cache for allows MPS I6500 The RAMand when Data RAM, thefollowing conditionsmetare at reset: RAM,both or theTag the Tag • The external input pin(si_cpc_l2_hw_init_inhibit) is dr •If it is enab not MBIST enabled. is 3.5.3 Cache Initialization Software 3.5.2 Manual Hardware Cache Initialization 48 3.6 L2 Cache Flush, Burst, and Abort
49 register to a register register to a register L2 Cache Op L2 validate. A value validate. register order for flush operationorder for ddresses in the cache. Burst ddresses this register is present. A ‘1’ present. A is this register _TYPE 4:2 field in bits of the eld indicates Hit In indicates Hit eld of cache lines requested must be less less be must cache lines requested of GCR L2 Cache Op State Machine Tag Address Tag Machine Op State Cache L2 GCR _TAG_ADDR_COP) at _TAG_ADDR_COP) (GCR_L2SM register ndicates Hit Writeback. ndicates e state machine is idle, in is idle, state machine e performed on a range of a L2 Cache Op State Machine Config/Control CacheOp State L2 so less than 65,536. less than so L2 Cache Op State Machine Config/Control Machine State Cache Op L2 flush the entire L2 cache in one L2 flush the entire cache in the operation,perform L2 Cache Op State Machine L2 Config/Control CacheOp State in GCR address space to determine if to address space GCR in register. A value of 0x4 in this fi this in 0x4 of A value register. andvalue a of 0x6 i field in bits 63:48 of the of 63:48 in bits field L2 Cache Op State Machineregisterto determine L2 Config/Control CacheOpthe State L2 Cache Op State Machineregisterto determine L2 Config/Control CacheOpthe State ing procedure. Note that the number Note procedure. ing rformed on each line using the L2SM_COP the using rformed on each line t must be 0, indicating th indicating be 0, must t it must be 0, indicating the state machine is idle, in order for the CacheOp to the CacheOp for order in idle, is state machine indicatingthe 0, be mustit s in the cache and al cache and s in the e the flush operation begins into the L2SM_COP_START_TAG_ADDR field e the flush operationbegins into the L2SM_COP_START_TAG_ADDR register. A valueof 0x0indicates theprocessstill is running.value A 0x1 of register. indi- e full cache flush operation. flush e full cache mpleted with no errors. the cache flush operation. the value of 0x1. This starts value cates that the process co that the cates State MachineConfig/Control State state of the L2 state machine. This bi of the L2 state state th of selects 0x0. This value to proceed. in thisbit indicatesthe flush cachethat operation is supported. register toindicate the number of lines to be flushed from the starting definedaddress in step 1. Machine Config/Control Cache Op State L2 b This machine. state of the L2 state proceed. GCR L2 Cache Op State Machine Tag Address Tag Machine in bits47:6 Op State of Cache the GCR L2 address 0x0628in GCR address space. offset (GCR_L2SM_COP) at offset address 0x0620 address at offset (GCR_L2SM_COP) of 0x5 indicates Hit Writeback Invalidate, 0x5 Writeback indicates Hit of 5. of the 8:6 in bit field L2SM_COP_RESULT the poll operation, flush the of result thedetermine To 4. ProgramtheL2SM_COP_CMD field in bits1:0the of 3.the of 4:2 bitsin field L2SM_COP_TYPE the Program 2. Read the L2SM_COP_MODEbit inthe 3.be pe operation to the type of Program 2.L2SM_COP_NUM_LINES the Program operations can be executed using the follow the using be executed can operations line available cache to the or equal than 1. Programthestarting address wher The L2CacheThe supportsthe following burst operations(CacheOps): •Hit_Inv • Hit_WB_Inv • Hit_WB and can be software operations can be requested only by These followingsteps: 1. Read the L2SM_COP_REG_PRESENTbit inthe An operationL2 flush canonly be initiated To by software. 4. Read the L2SM_COP_MODEbit inthe 3.6.2Cache Burst Operations L2 3.6.1 Flush Cache L2 MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
L2 L2 Cache Op Cache L2 invalidation across L2 Cache BurstL2 Cache d configuration parame- ruction can be used in one AutomaticCache Hardware routine, or the GINVI instruction. The instruction. or the GINVI routine, em Programmer’s Guide, Revision 1.00 e cache in a known state. This is accom- is This state. known cache in a e cache, whether local specified single cache, or a the case where all remote caches where are to be all remote the case in all clusters are to be invalidated. In this case, this invalidated. case, In be are to all clusters in decoding the cache sizes an cache decoding sizes the ribed in the section entitled in the section ribed rent request is generatedduringis request the initialization rent pro- of the instruction. of the ster systems. The GINVI GINVI inst ster systems. The ribed in the previous section). This section provides indi- provides This section section). in the previous ribed nter to 32nter generalone of purpose registers(GPR) inthe 4, program4, theL2SM_COP_CMD field inbits 1:0 of the all cores and all clusters simultaneously clusters all and all cores register toa value of 0x1. This initiates the CacheOp starting fromthe ing either the a software invalidation software a the either ing er-up or reset to place the lines of th of place the lines to or reset er-up des subroutines such as des MIPS64® I6500Multiprocessing Syst L1 instruction cache to manage L1 instruction architecture andused is register. A valueof 0x0indicates theprocessstill is running.value 0x1A of register. indi- , and cache burst operations desc cache , burst operations and struction cache is also fully invalidated in fully invalidated also is struction cache ates all remote instruction caches, primary all ates mpleted with no errors. ine Config/Control e Instruction Cache L2 CacheFlush L2 then field is 0, all L1 instruction caches of all cores , no coherent requests are permitted. Even if a cohe a if Even permitted. are requests coherent no , , coherent requestscan generatedbe during this timenot butare allowed. It is up tosoftware to mange rs . Cache Op State Mach State Cache Op performed be to operation The 2. in step defined lines of number for the continuing and in step 1 defined address in step 3. cache lines is defined the in selected each of cates that the process co that the cates State MachineConfig/Control State plished via the boot code (or, for the L2, by hardware as desc as by hardware L2, the for code (or, via the boot plished are included. registers the CP0 from ters us initialized can be cache Instruction The invalid instruction fully GINVI The cache must be initialized during pow be initialized during must cache The instruction, L1 data, and L2 caches. data, and L2 initializing L1 the instruction, L1 for vidual routines A sampleboot codeis shown followingin the subsections. This code is designed to be portablemicroprocessorsto ISA, implement and provi the MIPS that the R6 is new in GINVI instruction The Duringthe automatichardware initializationprocess described thein section entitled Initialization all incores the system, including single-cluster and multi-clu twoof ways: • entries all L1 instruction cache in Invalidate 5.in step determined idle the as state machine is If •cluster any core in any cache of L1 instruction all entries in a specific Invalidate fieldinrs bitsThe 20:16 of the GINVI instructionisa poi the If core. or remote. The local primary in remote. The local or rs Whichfield on the invalidated. nds cache is invalidated depe cedure, itis not allowed the pipelineto enter untiltheprocedure is complete. For the manual initializationhardware procedure described inthesection entitledCache Manual Hardware Initialization 6. of the 8:6 bit in field L2SM_COP_RESULT the poll operation, flush the of result thedetermine To based on thevalue in the rs field, the core executing the GINVI instructioninvalidates all entriesitsown of L1 Operations the flowtheserequests during of the initialization process.Thisis also true for the Flush operationsdescribed in the sectionentitled 3.7.1.1 L1 Instruction Cache Invalidation Using the GINVI Instruction 3.7.1th Initializing 3.6.3 Abort Operations 50 3.7 Routines Initialization Cache
51 register are register at if the rs field in at if the field a non-zerois e all other request to register. If there is a is If there register. rs ains a value of 5. Hardware ains all VP’s in a core. As such, in VP’s all Global Number in a 4-core single-cluster sys- in Global Numberregister to corresponding L1 instruction be done four times, once per core. four times, once per done be d core number. For example, d core number. at it is not required for the GINVI for the required it is not at nect blockused to with communicate in th turn broadcasts CP0 GlobalNumber each core in a cluster, and each cluster. This and each cluster. a cluster, in each core fields of the CoreNum field of the instruction cont the of field rs field and compares that register value to the value in the to the value in value that register field and compares rs register per core. Therefore, per register nvalidated automatically. No GPR register register compare is per- No GPR automatically. nvalidated tire system to have a unique ID number level. So a unique ID down to the VP to have system tire that core Note th and the operation is complete. that corresponding cluster numberan ClusterNumand lization routine. e compare of the CM request would request the CM of compare e ares the value in ares the request to theirthe value own GlobalNumber ruction cache to be invalidated. Note th to be invalidated. ruction cache and independentlyone of another. the request through the CM to all other cores in the cluster. Ina multi-cluster the request through the CM to all otherinthe cores cluster. register is not used. theCM3.5through thecoherent intercon and compare the contents to its own to its contents the and compare ction cache initia t throughout the en t e of the GPR identified by the of the GPR identified e tion, the core sends a request to the CM,request to sends which a core the tion, n cache is invalidated for cache is n struction cache is shared between shared cache is because the L1 instruction level the VP Globalthe not compare. used during is Numberregister register, which contains the which register, register assigns a number to each VP in a core, a number to each VP in assigns register CP0 GlobalNumber fieldthe of // Can be skipped if Config7.HCI is set (Hardware Cache Initialization) Cache set (Hardware is Config7.HCI if Can be skipped // mfc0ext 7 C0_CONFIG, TEMP1, bne HCI, 1 TEMP1, TEMP1, nop done_icache zero, TEMP1, is: I$ the how big Determine // Config7 CP0 // Read mfc0 HCI // extract C0_CONFIG1 CONFIG1_a2, C0_Config1 // read size Set line // addiuILINE_SIZE zero, LINE_SIZE_v1, fixed values are and associativity line size Since the // cache of the the size what determines cache is in the of sets the number // register the C0_CONFIG value in the from determined is set size Here the // ext 64 li 3 CFG1_ISSHIFT, CONFIG1_a2, SET_SIZE_a0, TEMP1, sllv SET_SIZE_a0 TEMP1, SET_SIZE_a0, IS // extract ways) of cache (number Set associativity // addiu IASSOC zero, ASSOC_a1, (LINES_PER_ITER) li TEMP1, way Sets per // I$ LEAF(init_icache) VPID value, the core reads the valu the core reads value, CP0 Global Number instruction, and the the GINVI executes core 0 that assume read GPR 5 registerwould the then the L1 instructio match, invalidate their own caches. L1 instruction their invalidate to instructing them and clusters, cores the GINVI If instruction. the using caches invalidated can also be L1 instruction Individual instruction instruction cache. In addi the instruction is 0 as described above, the caches are i caches above, the described 0 as is the instruction formed and the This section provides the instru This section tem, there are four L1 instruction caches, so th so caches, instruction L1 are four there tem, determine if itmatches their unique clusterthe match, numberand core is a If there s. there is one that is invalidated. Note cache If there is not a match, the core sends a there match, is not If the request is also routed by system, in core system. Each other the comp clusters the compared to determine the exact L1 inst the exact L1 to determine compared operate at instruction to All compares are done simultaneously compares are done All The Global Number each processing elemen allows whenrequestis thesent out by the CM, boththe 3.7.1.2 L1 Cache Initialization Routine MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
// make ending address ending // make em Programmer’s Guide, Revision 1.00 // write C0_ITagLo // write t2 t3 MIPS64® I6500Multiprocessing Syst ta cache initialization routine. dmuldmul ASSOC_a1 SET_SIZE_a0, SET_SIZE_a0, dmul LINE_SIZE_v1 SET_SIZE_a0, TOTAL_BYTES, of bytes number Total // TEMP1 LINE_SIZE_v1, BYTES_PER_LOOP_v0, which (0x80000000) of kgeg0 at the beginning address starting Set the // of sets number Total // per loop bytes // Total cache 0 of the 0 index to way corresponds // dlidsrl 0x0000000080000000 CURRENT_ADDR, daddu 1 BYTES_PER_LOOP_v0, TEMP1, CURRENT_ADDR TEMP1, CURRENT_ADDR, daddu TOTAL_BYTES CURRENT_ADDR, END_ADDR_a3, dsubu BYTES_PER_LOOP_v0 END_ADDR_a3, END_ADDR_a3, registers Clear TagLo/TagHi // // -1 mtc0 C0_ITAGLO zero, at a time lines 8 cache loop does this efficient To be more // the clears tag entry, the invalidates Op Tag Cache Index Store // LRF bit the and clears lock bit, // daddu address line starting next Get BYTES_PER_LOOP_v0// CURRENT_ADDR, bgeuc Done yet? next_icache_tag// CURRENT_ADDR, END_ADDR_a3, nop is jalr) instruction (following slot R6 forbidden MIPS64 for needed // #include
53 // D$ Sets per way Sets per // D$ address ending // make // Read CP0 Config7 // Read HCI // extract .set.set noreorder noat instr. synthetic for use r1(at) to the assembler allow // Don't instructions. to reorder the assembler allow // Don't Initialization) Cache (Hardware set Config7[HCI] if Can be skipped // mfc0ext 7 C0_CONFIG, TEMP1, bne HCI, 1 TEMP1, TEMP1, nop done_dcache zero, TEMP1, mfc0C0_CONFIG1 CONFIG1_a2, size Set line // addiuDLINE_SIZE zero, LINE_SIZE_v1, in of sets number the fixed values are and associativity line size Since the // C0_Config1 // read is set size the Here the cache. size of the determines is what the cache // register C0_CONFIG in the value from the determined // extli 3 CFG1_DSSHIFT, CONFIG1_a2, SET_SIZE_a0, sllv 64 TEMP1, SET_SIZE_a0 TEMP1, SET_SIZE_a0, ways) of cache (number Set associativity // addiu DS // extract DASSOC zero, ASSOC_a1, (LINES_PER_ITER) li TEMP1, dmuldmul ASSOC_a1 SET_SIZE_a0, SET_SIZE_a0, dmul LINE_SIZE_v1 SET_SIZE_a0, TOTAL_BYTES, of bytes number // Total TEMP1 LINE_SIZE_v1, BYTES_PER_LOOP_v0, which (0x80000000) of kgeg0 at the beginning address starting Set the // of sets number // Total per loop bytes // Total cache 0 of the 0 index to way corresponds // luisrl 0x8000 CURRENT_ADDR, addu 1 BYTES_PER_LOOP_v0, TEMP1, CURRENT_ADDR TEMP1, CURRENT_ADDR, addusubu TOTAL_BYTES CURRENT_ADDR, END_ADDR_a3, BYTES_PER_LOOP_v0 END_ADDR_a3, END_ADDR_a3, registers Clear TagLo/TagHi // mtc0 // -1 2 C0_TAGLO, zero, not size is the line assumes the code restrictions, field due to offset // 64 bytes than // more C0_DTagLo // write Op Tag Cache Index Store // bit the LRF clears bit, and the lock clears entry, the tag // Invalidates (DLINE_SIZE*-2)(CURRENT_ADDR) 0x9, cache #define LINES_PER_ITER 8 // number of cache instructions per loop per instructions cache of number 8 // LINES_PER_ITER #define LEAF(init_dcache) next_dcache_tag: (DLINE_SIZE*-1)(CURRENT_ADDR) cache 0x9, (DLINE_SIZE*0)(CURRENT_ADDR) cache 0x9, (DLINE_SIZE*1)(CURRENT_ADDR) cache 0x9, MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
L2 em Programmer’s Guide, Revision 1.00 used during the software initialization during the used alization is invoked as describedin the section entitled lization routine. This routine is only routine. This routine lization t2 t3 MIPS64® I6500Multiprocessing Syst , thenthis routine is notused. the Level 2 Cache .set.set noreorder noat instr. synthetic for to use r1(at) the assembler allow // Don't instructions. to reorder the assembler allow // Don't bnez0. core done from Only done_L2_cach_init// r8_core_num, // Read L2 Configuration register ld GCR_L2_CONFIG(r22_gcr_addr) CONFIG_L2_a2, dlidins 0x1 TEMP_s1, sd 20, 1 TEMP_s1, CONFIG_L2_a2, register Configuration Write L2 GCR_L2_CONFIG(r22_gcr_addr)// CONFIG_L2_a2, register Configuration the L2 Read back // ld (bypass) to uncached // set bits // Insert GCR_L2_CONFIG(r22_gcr_addr) CONFIG_L2_a2, // Isolate L2$ Line Size dext 8, 4 CONFIG_L2_a2, LINE_SIZE_v1, L2$ if No Skip ahead // LINE_SIZE // extract daddu CURRENT_ADDR, BYTES_PER_LOOP_v0// Get next starting line address starting next Get BYTES_PER_LOOP_v0// CURRENT_ADDR, daddu yet? // Done next_dcache_tag CURRENT_ADDR, END_ADDR_a3, bgeuc nop is jalr) instruction (following slot R6 forbidden MIPS64 for needed // #include
55 // Insert bits // Insert beqnop done_l2 zero, LINE_SIZE_v1, dlidsllv 2 LINE_SIZE_v1 TEMP_s1, TEMP_s1, LINE_SIZE_v1, bytes size in line true L2$ decode for // // Isolate L2$ Sets per Way dextdli SET_SIZE_a0 4// extract 12, CONFIG_L2_a2, SET_SIZE_a0, dsllv way per sets decode for 64 SET_SIZE_a0// TEMP_s1, TEMP_s1, SET_SIZE_a0, // Isolate L2$ Associativity dextdaddiu ASSOC_a1 extract 0, 4// CONFIG_L2_a2, ASSOC_a1, # of ways 1// for decode ASSOC_a1,ASSOC_a1, (LINES_PER_ITER) TEMP_s1, dli dmuldmul ASSOC_a1 SET_SIZE_a0, SET_SIZE_a0, dmul LINE_SIZE_v1 SET_SIZE_a0, TOTAL_BYTES, per loop Total bytes of bytes // number TEMP_s1 // Total LINE_SIZE_v1, BYTES_PER_LOOP_v0, L2 sets in number of total // Get dlidaddu for cacheops address a KSeg0 load 0x80000000// CURRENT_ADDR, TOTAL_BYTES CURRENT_ADDR, END_ADDR_a3, dsubu per loop address // -1 bytes ending // make BYTES_PER_LOOP_v0 END_ADDR_a3, END_ADDR_a3, Tag registers Clear L2 // sd 0x600(r22_gcr_addr) zero, sd 0x608(r22_gcr_addr) zero, sd 0x610(r22_gcr_addr) zero, // GCR_L2_TAG_ADDR entry. the tag Op. Invalidates Cache Store Tag L2$ Index // // GCR_L2_TAG_STATE // GCR_L2_DATA Op Tag Cache Index Store // LRF bit clear the bit, and lock clear the entry, the tag // Invalidate (L2LINE_SIZE*-2)(CURRENT_ADDR) 0xB, cache (L2LINE_SIZE*-1)(CURRENT_ADDR) 0xB, cache (L2LINE_SIZE*0)(CURRENT_ADDR) 0xB, cache (L2LINE_SIZE*1)(CURRENT_ADDR) 0xB, cache (L2LINE_SIZE*-4)(CURRENT_ADDR) 0xB, cache (L2LINE_SIZE*-3)(CURRENT_ADDR) 0xB, cache (L2LINE_SIZE*2)(CURRENT_ADDR) 0xB, cache (L2LINE_SIZE*3)(CURRENT_ADDR) 0xB, cache Done yet? // next_L2_cache_tag END_ADDR_a3, CURRENT_ADDR, bne BYTES_PER_LOOP_v0 CURRENT_ADDR, daddu line address next starting Get // next_L2_cache_tag: done_L2_cach_init: L2) ByPass (enable Clear L2 // ld dins GCR_L2_CONFIG(r22_gcr_addr) a0, 1 zero, 20, a0, sd GCR_L2_CONFIG(r22_gcr_addr) a0, done_l2: register L2 Configuration // Read jalr register L2 Configuration // Write nop ra zero, MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
em Programmer’s Guide, Revision 1.00 Cache may contain the only copy of data only Cache contain the may to force modifiedtoforce data to be writtenback from the L1 D- MIPS64® I6500Multiprocessing Syst e data cache initialized. e has been data write-back policy, which meansthat the D- write-backpolicy, mfc0C0_CONFIG1 CONFIG1_a2, // Isolate D$ Line Size C0_Config1 // read ext done_flush_dcache 3 CFG1_DLSHIFT, CONFIG1_a2, LINE_SIZE_v1, D$ if No Skip ahead // zero, beq LINE_SIZE_v1, nop DL // extract lisllv in bytes line size true D$ have Now 2 LINE_SIZE_v1// TEMP1, TEMP1, LINE_SIZE_v1, extli 3 CFG1_DSSHIFT, CONFIG1_a2, SET_SIZE_a0, sllv 64 TEMP1, SET_SIZE_a0 TEMP1, SET_SIZE_a0, DS // extract - 1 == D$ Assoc Config1DA // extaddiu(LINES_PER_ITER) 3 CFG1_DASHIFT, CONFIG1_a2, ASSOC_a1, 1 ASSOC_a1, li TEMP1, way Sets per D$ // DA // extract dmuldmul ASSOC_a1 SET_SIZE_a0, SET_SIZE_a0, dmul LINE_SIZE_v1 SET_SIZE_a0, TOTAL_BYTES, lui TEMP1 LINE_SIZE_v1, BYTES_PER_LOOP_v0, srl 0x8000 CURRENT_ADDR, addu 1 BYTES_PER_LOOP_v0, TEMP1, CURRENT_ADDR TEMP1, CURRENT_ADDR, of bytes number // Total addu of sets number // Total per loop bytes // Total subu TOTAL_BYTES CURRENT_ADDR, END_ADDR_a3, LINE_SIZE_v1 END_ADDR_a3, END_ADDR_a3, for cacheops address a KSeg0 // Get Op Cache invalidate Index writeback // address ending // make clears entry, the tag invalidates memory, back to data modified // Writes any // -1 bit the LRU clears bit, and the lock // (DLINE_SIZE*-2)(CURRENT_ADDR) 0x1, cache (DLINE_SIZE*-1)(CURRENT_ADDR) 0x1, cache (DLINE_SIZE*0)(CURRENT_ADDR) 0x1, cache (DLINE_SIZE*1)(CURRENT_ADDR) 0x1, cache (DLINE_SIZE*-4)(CURRENT_ADDR) 0x1, cache (DLINE_SIZE*-3)(CURRENT_ADDR) 0x1, cache (DLINE_SIZE*2)(CURRENT_ADDR) 0x1, cache (DLINE_SIZE*3)(CURRENT_ADDR) 0x1, cache LEAF(flush_dcache) fnext_dcache_tag: END(init_L2) Cache to the L2-Cache (e.g. before poweringCache to the L2-Cache (e.g. before downthecoreor when interacting withnon-coherent ThisDMA). sec- tion describesthe routine for writing back and invalidating all data from D-Cache.the L1 Notethat this routine beshould executednot th until after The I6500 L1 D-Cache uses a D-Cache L1 The I6500 stored by the core. In somesituations,software needmay 56 3.8 Cache L1 Data the Flushing
57 address resides in resides address at address. If the at ss (not KSGE0 uncached).(not ss For tothe I6500 the set CCA is CCA for KSEG0cannot be executed froma KSGE0 address. // CCA for coherent // CCA address is set by the TLB entry for th for entry TLB the by is set address ry Space Cache Coherency Cache ry Space daddu CURRENT_ADDR, BYTES_PER_LOOP_v0 CURRENT_ADDR, daddu yet? // Done fnext_dcache_tag CURRENT_ADDR, END_ADDR_a3, bgeuc nopline address next starting // Get sync is jalr) instruction (following slot forbidden R6 MIPS64 for // needed jalrnop ra zero, END(flush_dcache) #defineLEAF(change_k0_cca) C0_CONFIG CCA for Set uncached). (not KSGE0 in KSEG1 be executed code must NOTE! This // $16,0 to cacheable kseg0 mfc0 li C0_CONFIG t1, 5 t2, C0_Config0 // read ins ins mtc0 ra zero, jalr.hb t2, 0, 3 t1, nop C0_CONFIG t1, END(change_k0_cca) K0 // instert C0_Config // write done_flush_dcache: coherent because all cached access for the I6500 are coherent. the for access coherent because all cached the KSGE0 memory range, theCCAis theset in Config.K0 field. Thefollowing code shows howthis is done. that that the modification of does the code the Note it mustbedone in KSEG1 or anuncached addre Rather, The Cache Coherency attribute for a mapped Cache Coherency attribute for The MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 3.9the KSEG0 Memo Setting em Programmer’s Guide, Revision 1.00 MIPS64® I6500Multiprocessing Syst 58
59 . Table 4.5 Table . ovides three types the which are core, the register fields that can register Interrupt Mode Interrupt , or external , to or n of the current instruction stream and instruction current the of n dicated hardware interrupt pins. When pins. interrupthardware dicated tion and branch to a dedicated kernel tion and dedicated branch to a watch address match,reserved instruc- function of the Coprocessor 0 of the Coprocessor function Overview of Exception Processing Overview of the way interrupts are handled to provide full support full support to provide are handled way interrupts the e I6500 e core is identicalI6500 theto imple- behaviorof an in memory is also covered. A list of exception priorities of exception A list is also covered. memory in zation andvectoring interrupts.of The presenceof this register. Note that the Global Interrupt Controller (GIC) serves as (GIC)Controller Interrupt Global the that Note register. Config3 the system is in EIC mode.Refer tothe GIC chapter inthis manual for re, which are known as internal events as internal known which are re, at causes the core to halt normal execu to halt normal the core at causes The kernel software then halts executio The kernel software then halts Table 4.1 Table Modes Interrupt rrupt. These are generated by asserting de asserting by These are generated rrupt. determine and resolve the interrupt. The MIPS architecture pr the determine interrupt. The and resolve bit in the in bit ception handler. The exception handler is responsible for determining and then resolving and then resolving determining for responsible is handler exception The handler. ception VEIC shows the current interrupt mode of the processor as a processor shows the current interrupt mode of the for an external interruptcontroller that handles prioriti mode is denoted by the by is denoted mode mentation of Release 1 of the Architecture. the 1 of Release mentation of thatinterrupt. the external interrupt interrupt the controller when external more information. The I6500 The core includesI6500 supportthree for interrupt modes: • InterruptCompatibility mode, inwhich thebehavior thof • Interrupt (VI)mode, which abilityadds the to a prioritize handler dedicated to interrupts and vector to Vectored •redefineswhich (EIC) mode, ControllerInterrupt External An exception is defined as any event th as any event defined is An exception ex called an routine software the exception. can co occur within the Exception events ts include Internal events arithmetic external events. known as overflows, traps, tions, misses inthetranslation (TLB), lookasideetc. A complete listof buffer exceptions is shown in This chapter provides an overviewof exception andprocessing a definition of the interruptsmodes.Information on vectors general exception and reset, boot, to program the how is provided, along with an assemblylanguage example of an exception handler. An external event is known as an inte external event is known as An is taken. an exception asserted, pin is a handler to to the interrupt branches hardware interruptof modesas described in thesection entitled FollowingI6500reset, the core defaults toInterrupt Compatibilitymode. 4.1 Table affect the mode. affect 1x x 0 x x x x x x Compatibility Compatibility StatusBEV CauseIV IntCtlVS Config3VINT Config3VEIC MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 4.1 Exception Processing of Overview Exceptions Chapter 4 Chapter
is an example of example an is cannot be non-zero if non-zero cannot be VS register is the address of can be used to identify the to identify be used can IntCtl EPC for debug exceptions)is suffi- EPC Interrupt Mode Interrupt tified. A bus error A bus tified. e execution can restart after the can restart after execution e ch instruction immediately preceding instruction immediately ch DEPC em Programmer’s Guide, Revision 1.00 has completed and potentiallyafter following neither Vectored Interrupt nor External Interrupt Con- nor External Interrupt Interrupt Vectored neither is implemented. mode troller for errors or or errors for n in program order. order. program in n (continued) terrupts(enabledor disabled). This contextsavedso is ErrorEPC (or t locationthe restart exceptions, inthe ) register with the location wher register), the address of the bran the address register), EPC thefollowing actions: tion execution tion on handler located at a specific address specific located at a on handler EPC ( for which no return address can be iden address return no which for
or, if theinstruction executingwas or, in the delayslot forbidden or slot a of Cause MIPS64® I6500Multiprocessing Syst ce of instruc ce of Table 4.1Table Modes Interrupt bit in the in bit ception. For precise ception. the exception has been serviced. been exception has the BD 0000 x 1 x 0 x 0 1 Compatibility 0Interrupt Vectored Interrupt Controller (EIC) External because occur Cannot tected, the core takes tected, the core takes are taken that after the instructioncaused them are “x” denotes don’t care denotes don’t “x” Exception Program Counter exception has been serviced • Enters kernel mode •the software execution of Forces excepti Once invoked, theexception handlerincluding shouldthecontents savetheof contextthe program of theprocessor, thecurrent operatingmode, and thestatusof the in counter, that it can be restored when be restored it can that the slot. imprecise exceptions are those Conversely, cient to restart execution. It also ensures that exceptions are take also ensures execution. It to restart cient exceptions Imprecise instructions have completed. When a precise exceptionWhena precise condition occurs, the instruction causing the exceptionandall those thatfollow itin the have referenced conditionsthatmayexceptionlater conditionsand any stallany Accordingly, pipelineare cancelled. thisinstruction are inhibited. The valuein the When an exception is de When • Loads the Exceptions maybe precise or imprecise. exceptions are those for which the Precise • Suspends the normal sequen the instruction that caused the exception the instruction by the indicated (as branch instruction that caused the ex instruction that an imprecise exception. an imprecise 01 01 01 xx 4.1.3 ExceptionConditions 4.1.2 Detecting an Exception 4.1.1 ExceptionTypes StatusBEV CauseIV IntCtlVS Config3VINT Config3VEIC 60
61 When this bit is is this bit When manual. in the lower 512 Both of these options are options Both of these stored in a local register, meaning register, local a stored in by clearing the clearing by the512lower MBytesphysical of global register space. global ftware can program to set the base set can program to ftware or somewhere with or I6500 Technical Reference I6500 Technical 0xBFC0_0. This default setting sets the BEV to a This default setting sets 0xBFC0_0. of physical memory of 4 GByte memory space. physical 4 and pertains to all VP’s in the core. This means that all VP’s meansin the core. This that all VP’s andpertains all VP’s to r Address 512 MBytes of the Physical default for the field is 00, which00, directly maps tophysical ofaddress 0x0000_0000_1FC0_0000. her the exception vector vector her is mapped to the exception in CM register space that kernel so kernel space that CM register in set, the first instructionis fromfetched the bootexception vectorin (BEV) BASE field are used to place the vect Register (GCR_CL_RESET_BASE)Register in detail inthe CM chapter of the . reset vector code in memory. vector code reset Figure 4.1 e BEV_BASE field are forced by hardware to a binary valuee of 3’b101, causingtheto BEV ector is placed in the lower 512 MBytes lower placed in the ector is ector is stored in a stored global register ector in is nversely, the reset exception vector is vector the reset exception Conversely, the same BEV during boot-up. access will VP can have its own each that of 512 MBytes lower vector to the the exception maps the device whether also indicate these registers in bitsControl or within4lowerGBytethe as described inaddress range the following subsections. physical memory, of these registers are described Both cleared, bits 31:29 of th 31:29 of cleared, bits (always uncached). 1 address space in the KSEG reside 28:12 of the BEV_ bits remaining The e GCR_BEV_BASE register located in the the CM located in GCR_BEV_BASE register the bit in BEV_BASE_MODE configuration space. The hardware MByte virtualaddress of FFFF_FFFF_BFC0_00 This conceptis shown in The boot exception v boot exception The memory, as in the legacy mode, or anywhere within the or anywhere within mode, legacy the as in memory, When the processor is powered up or re or up is powered processor the When memory. Registers in the determine whet determine Registers the in memory. described in thefollowing subsections. located registers contains two The I6500 address for the resetand boot exception locationsvector memory:in • Register (GCR_BEV_BASE) BEV Base •Base Exception Local Reset VP v boot exception The 4.2.1 Mapping thethe BEV to Lowe MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 4.2 Locations Vector the Exception Defining
0000_0000 FFFF_FFFF 1FC0_0000 When this bit is is this bit When be used. In this case the BEV global register space. global em Programmer’s Guide, Revision 1.00 4 GByte Virtual Address Virtual GByte 4 e XKPhys uncached space which startsXKPhys at e physical address space by setting the physical address the Physical Address ubsection,a 4 GByte mapping can Lower MBytes 512 FFFF_FFFF_BFC0_0000 virtual address virtual FFFF_FFFF_BFC0_0000 address. physical to 1FC0_0000 maps MIPS64® I6500Multiprocessing Syst . placed anywhere in the 4 GByte placed anywhere in the Lower 4 GBytes of KSeg1 Figure 4.2 64-bit AddressVirtual Figure 4.1 Figure Address Default MIPS Using the MBytes 512 Lower in the BEV the Mapping In the case where it is necessary to be able to map the boot exception vector in physical memory to a location outsidelocation a memoryto physical in vector exceptionboot the map to able be to necessary is it case where the In 512lowerthe of MByterange described intheprevious s one, bits 31:12 of the BEV_BASE field to mapare used the bootexception vector anywhere within4theGByte 32- physical address space. bit 64-bit to th virtual address the bit maps Setting the BEV_BASE_MODE addressvirtual 0x9000_0000_0000_0000. This mapstoa physical ofmemory space (0x0000_0000_0000_0000 - 0x0000_0000_FFFF_FFFF). This conceptis shown in KX bit register in the CP0 Status mustbe set to enable 64-bitkernel segments. be vector can boot exception The the CM located in GCR_BEV_BASE register the bit in BEV_BASE_MODE 4.2.2 Mapping the BEV to 0000_0000_0000_0000 FFFF_FFFF_A000_0000 FFFF_FFFF_BFFF_FFFF FFFF_FFFF_FFFF_FFFF 62
63 FFFF_FFFF 0000_0000 be used. In this case the memory to a location outside outside location a to memory somewhere within the somewhere 512 within e Physical Address setting sets theBEV toa virtual CMlogic ‘0’ space. A Local address dress space by setting the space by dress in the KSEG 1 address space (always 1 address space KSEG in the in the previous subsection, where subsection, in the previous 4 GByte Virtual Address Virtual GByte 4 e RESET_BASE field are forced by hard- by forced RESET_BASE field are e the boot exception vector described above. The main dif- The main above. vector described exception the boot ed to place the reset vector reset ed to place the ubsection,a 4 GByte mapping can the 4 GByte physical ad the 4 GByte mapsto physical 0x0000_0000_1FC0_0000.address of Lower 512 MBytes of th Lower 4 GBytes of the Physical Address BEV can be mapped anywhere in anywhere mapped be can BEV space. address 4 GByte physical the 512memorybyof physical MBytes the clearing . ESET_BASE register. Whenthis bitis set to one, bits 31:12of the ESET_BASE register. default for the field is BFC0_0. This bootexception vectoranywhere within the GByte32-bit 4 physicaladdress en this bitbitsiszero, 31:29 of th Figure 4.1 RESET_BASE_MODE is 0 as described described 0 as is RESET_BASE_MODE e GCR_CL_RESET_BASE register located in GCR_CL_RESET_BASE register e XKPhys(CCA = 2) 64-bit AddressVirtual Figure 4.2 Figure Mode 64-bit in Vector Exception Boot the Mapping address of FFFF_FFFF_BFC0_0000,address of which directly in shown same as the is This concept t exception vector in physical in vector exception reset the be able to map to necessary is it where case the In in this field indicates legacy mode. Wh field indicates legacy in this to reside causingexception vector of 3’b101, value the reset a binary to ware uncached). 28:12 of the RESET_BASE field are us bits remaining The 512lowerthe of MByterange described intheprevious s The reset exception vector is mapped in the same manner as same manner the in mapped is vector reset exception The l VP’s in the core, whereas the reset exception vector is local to each VP in the to each VP in local is vector whereas the reset exception core, the in VP’s that ference the BEV is global to all is reset exception vector. VP own can have meaning that each its core, reset exception vectorThe is placed inthe lower bit in th RESET_BASE_MODE MByte space. The hardware configuration space. The MByte RESET_BASE field are used to map the used to field are RESET_BASE when from space. This is different KX bit register in the CP0 Status mustbe set to enable 64-bitkernel segments. reset exception vector can be placed anywhere in The GCR_CL_Rbit in the RESET_BASE_MODE 4.2.4 to the Mapping the Reset Vector 4.2.3 to the Mapping the Reset Vector 0000_0000_0000_0000 9000_0000_0000_0000 9000_FFFF_FFFF_FFFF FFFF_FFFF_FFFF_FFFF MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
ster to jump to to jump ster exception vector. vector. exception on an exception, the boot exception, an on BEV_BASE + BEV_BASE 0200 BEV_BASE + 0300 BEV_BASE tion. Notethat the IVbit in the thanthegeneral em Programmer’s Guide, Revision 1.00 BEV CR_CL_RESET_BASE regi CR_CL_RESET_BASE ogramming the SELECT_BEV bit (0) in the in bit (0) SELECT_BEV the ogramming [31:7] || 7’b0000000 [31:7] || Status ess to the XKPhys uncached space which starts at space which starts uncached XKPhys the to ess ich exception vector is used used is exception vector ich 0x100 0xFFFF_FFFF_BFC0.0000 0xFFFF_FFFF_BFC0.0480 0xFFFF_FFFF_FF20.0200 28..12 DebugVectorAddr RESET_BASE + (SELECT_BEV = 0) + (SELECT_BEV RESET_BASE ring concatenation ring 0x000 has the fixed value of has fixed the 01 EBase . 63..12 se address as a function of the excep function of as a address se 31..30 the 64-bit virtual addr the 64-bit 1 dicated exception vector offset, rather dicated exception vector offset, V and Exception Vectors Reset MIPS64® I6500Multiprocessing Syst EBase EBase VP uses the address stored in the G the address uses VP ‘||’ denotes bit st ‘||’ 63..30 Figure 4.2 Address per Exception Type EBase Note that 2’b10. exception vector. This is accomplished by pr by accomplished is This vector. exception Table 4.2 Table Addresses Base Vector Exception = 1 1 and Pro- = = 0 and = 0 and shows the offsets from the vector ba vector the from shows the offsets register causes interruptsto use a de Exception DmxSegEn DmxSegEn DmxSegEn DmxSegEn = 0 in the VP_Control1 0 = in the VP_Control1 = 1 in the CP0 VP_Control1 CP0 1 in the = the corresponding Reset exception vector. the corresponding Reset the to jump to in the GCR_BEV_BASE register ss stored addre the VP uses then the bit is 1, the SELECT_BEV If global boot exception vector. Table 4.3 Cause GCR_CL_RESET_BASE register located at offset 0x0020 in CM GCR local address space. 0x0020 in CM GCR local address offset located at GCR_CL_RESET_BASE register the then 0, is bit SELECT_BEV the If The I6500 core provides a way for the programmer to select wh programmer the way for a core provides I6500 The virtual addressvirtual 0x9000_0000_0000_0000. This mapstoa physical of memory space (0x0000_0000_0000_0000 - 0x0000_0000_FFFF_FFFF). in shown same as the is This concept or the reset vector exception RESET_BASE[31:29] RESET_BASE[31:29] to a fixed value,are set the the of reset location forcing of vector lower 512 into the MBytes addressthe 4 GByte space. physical maps the RESET_BASE_MODEbit Setting 4.2.6 Base Exception Vector 4.2.5 Selecting Between the BE Reset NMI Debug with Other DCRDVec DCRDVec register. Debug with Debug with = 1 in the VP_Control1 register. = 1 in VP_Control1 betrap the RDVec RDVec register. Cache Error Cache 64
65 ) = 1) = = 0 = = 0. 0. = VP_Control1.RDVec VP_Control1.RDVec [28:12] 0x100 [28:12] VS 1 VP_Control1.RDVec VP_Control1.RDVec = 0) e at offset 0x0680. This register is register This 0x0680. at offset e IntCtl esses as a function of the state that the of function a as esses + 0x200 VS 2 0x000 0x180 0x200 Vector RESET_BASE or RESET_BASE BEV_BASE) Vector Offset Vector 0x0020. This register is instantiated per- This register is instantiated 0x0020. [63:12] 0x000 [63:12] [63:12] 0x180 [63:12] [63:12] 0x180 [63:12] [63:12] 0x200 [63:12] [63:12] 0x180 [63:12] (IntCtl RESET_BASE 7’b0000000 (if 7’b0000000 0b1 EBase BEV_BASE + 0300 BEV_BASE + 0380 BEV_BASE + 0400 BEV_BASE + 0380 BEV_BASE + BEV_BASE 0x380 BEV_BASE EBase EBase EBase EBase EBase 0xFFFF_FFFF_FF20.0200 0xFFFF_FFFF_BFC0_0000 [31:7] [63:30] EBase ring concatenation ring 0xFFFF_FFFF_BFC0_0480 (if 0xFFFF_FFFF_BFC0_0480 DebugVectorAddr register located in GCR address spac address register located in GCR
that contains all possible vector addr vector all possible contains that ProbeTrap
‘x’ denotes don’t care, ‘x’ denotes don’t DmxSegEn denotes bit st ‘||’ Table 4.4 Table Vectors Exception register in CM3 GCR address space at offset address GCR in CM3 register
or Base Address Base or
Table 4.3 Table Offsets Vector Exception
IV Cause
EXL Status have its own reset vector. vector. have its own reset Exception
Boot Exception Vect Exception Boot
BEV Status = 1 IV = 0 combines these three tables into one tables into one three these combines EXL VPLocal Reset ExceptionBase Cause Table 4.4 Table can affect the vector selection. To avoid avoid complexity inthe table, it is assumedthat the To vector selection. can affect General Exception General Interrupt, TLB Refill, TLB Reset,NMI (uses None either Exception VP, allows which each VP to VP, instantiated per-core. instantiated Debugxxx11 RefillTLB 0 0 x x x TLB RefillTLB 0 1 x x x TLB RefillTLB 1 0 x x x M xxxxx NMI Debugxxx0x TLB RefillTLB 1 1 x x x Reset Cache Error 0 x x x x Cache ErrorInterrupt 1 x 0 x 0 x 0 x x x Interrupt 0 0 1 x x InterruptInterruptAll others 1 1 0 0 0 0 x 1 x x x x x x x All others 1 x x x x 2. global from the Derived 1. from Derived MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
Root Root Root Root Guest Debug Debug Debug
DINT Debug.DSS field. field. Controller (GIC) Controller It is recommended ror). When several exceptions several When ror). occurs during the TLB occurs bit in the DBU Break DBU Break in the bit signal. When an NMI inter- NMIsignal. an When part of a guest (second step) (second of a guest part or root TLB. It recom- or root TLB. is em Programmer’s Guide, Revision 1.00 bit. Status.NMI DINT one can single-step into inter- one can single-step into translation, root TLB opera- and have many When have causes. this have many When have causes. this a guestaddress translation (first SI_NMI General Interrupt General Interrupt operation (write, operation probe). ng a lookup, the exact cause is encoded by ng a lookup, the exact cause is encoded by lated. This exception This lated. Root.PageGrain.MCAUSE Guest.PageGrain.MCAUSE eck be synchronous. eck synchronous. be et signal. In this case the device is reset. No is reset. device the case this In signal. et bit. bit. bit. Note that there is one DINT bit per VP. one DINT bit per is there that Note bit. rupt (or other asynchronous) handlers. asynchronous) other (or rupt CP0 the sets hardware occurs, exception a DSS When bit. the setting input, appropriate by or is of the which part register, the assertion of the Indicates asynchronous exceptions, that so exceptions, asynchronous specific register is written when a Reset exception occurs. exception Reset a when written is register specific register set. Refer to the GIC chapter of this manual for more more for manual this of chapter GIC the to Refer set. register information. CP0 the sets hardware occurs, exception DINT a When Debug.DINT CP0 sets a exception occurs, hardware the When DDBLImpr Debug.DDBLImpr CP0 hardware sets the rupt occurs, lookup process and can only occur as only occur can process and lookup address root translation, address for guest (write, whether tion probe) the assertion the by the of external Caused assertion Debug Interrupt. that Machine-Check be synchronous. mended the check exception can Machine A duri exception occurs in the CP0 hardware that the Machine-Ch that the check exception can Machine A duri exception occurs in the CP0 hardware Guest TLBrelated. of This part only occur can as TLB step), and guest e highest priority is taken. The number of the exception takenis recorded ofthe exception The number highestpriority e is taken. MIPS64® I6500Multiprocessing Syst register. register. Table 4.5 Table Exceptions of Priority Cause NMI DINT Interruptoccurred. interrupt root-enabled A DDBLImpr Debug Imprecise. Data Break Load. Exception Description Mode field of the CP0 CP0 the of field contains a list and a brief description of all core level exception conditions. The exceptions are listed in the in the are listed conditions.Theexceptionexceptions level core all of description and a brief a list contains ExcCode occur simultaneously, the exception with th exception the simultaneously, occur Table 4.5 Table er bus (Load/store lowest to (Reset) priority highest from priority, relative their of order in the 0 0x00 24 0x18 Check Lookup - Machine Root TLB re or Root, n/a n/a n/a n/a DSS including above exceptions, other Prioritized Step. Debug Single n/a n/a Resetof SI_Res Assertion n/a n/a n/a n/a Field Encoding Cause.ExcCode Decimal Hex 66 4.3 Priorities Exception Core-Level
67 Root Root Root Root Root Guest Guest Guest Guest Guest Guest Root or register register register Root.WatchHi Root.WatchHi d because EXL was a EXL was d because register. In addition, In register. This can occur due to a Root or Root a due to occur can This struction fetch or a data load. tch was detected on an instruc- on detected was tch tch or a data load. This can can This load. data a or tch on occurs in Root mode, hard- in on occurs on occurs in Guest mode, hard- in on occurs on occurred during a fetch (I), a fetch a during occurred on ction fetch exceptions ction to allow fetch ion fetch or load. A Root TLB fetch or load. A ion ion occurred during a fetch, a ion occurred est.Cause register. In addition, In est.Cause register. ot TLB entry mapping the address address the mapping TLB entry ot guest context TLB entry guest TLB mapping context entry Root.Cause on Breakpoint (DIB) condition was condition (DIB) on Breakpoint alignment error. A non-word-aligned A non-word-aligned error. alignment (continued) by an instruction fetch. exceptions to allow exceptions above fetch instruction exceptions to allow exceptions above fetch instruction ruction addresses. ruction ruction addresses. ruction tch deferre exception, tected on an instruc- tch detected match was address rred EXL a because was defe exception, watch register. register. Debug logic ‘1’ when the exception was detected, was asserted after after asserted was detected, was exception the when ‘1’ logic went to ‘0’. EXL excepti Whena deferredWATCH CP0 in bit WP the sets ware hardware sets the I, R, or W bits in the CP0 in the R, or W bits I, the sets hardware excepti the on whether depending (R), a store (W). load or after asserted was detected, was exception the when ‘1’ logic went to ‘0’. EXL excepti Whena deferredWATCH Gu CP0 in bit WP the sets ware CP0 in the R, or W bits I, the sets hardware except in whether the depending a load. or store, fetch. tion Prioritized inst on illegal watch asserted. Prioritized above instru above Prioritized asserted. addresses. illegal instruction on break the of DBP bit the writes hardware occurs, exception DIB a When CP0 watch ma address guest context A fetch. tion Prioritized inst on illegal watch Instruction fetch address fetch address Instruction addresswas loaded intothe inPC the current mode. Root TLB/XTLB refill - Instruct miss occurred on occurred an instruction miss fe due to a Rootoccur or Guest translation. Guest TLB/XTLB refill - Instructionfetch or data load.A Guest either in miss occurred on an TLB The valid bit was zero in the zero in valid bit was The referenced address the The valid bit was zero in the Ro in zero bit was valid The fetch. an instruction by referenced Guest translation. An EJTAG Debug Instructi EJTAG An Refill - DIB Table 4.5 Table of Exceptions Priority AdEL Interruptoccurred. guest-enabled interrupt A Exception Description Mode fetch load or instruction fetch or load or fetch instruction TLB Invalid - instruction TLB Invalid 0 0x00 4 0x04 2 0x02 TLBL/XTLBL 23 0x17 Instruction - Fetch WATCH wa root context A n/a n/a- Root Deferred Watch wa Root deferred A n/a n/a- Guest Watch Deferred deferred Guest A n/a n/a Field Encoding Cause.ExcCode Decimal Hex MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
Root Root Root Root Root Root Root Root Guest Guest Guest Guest Guest Guest Guest Guest Guest Root or Root or Root or Root or Root or field of the by the setting setting the by DExcCode Root.Config5.MSAEn. em Programmer’s Guide, Revision 1.00 ss to a coprocessor was per- to a coprocessor ss bits, but denied bits, ction for a coprocessor that is that for a coprocessor ction n occur due to due a Root oroccur to n Guest the MSA unit was permitted by MSA unit was permitted the to a Root or Guest translation. above, but occurs during the above, Guest or Root address translation, Root or Guest valid Guest TLB entry which had which TLB had entry Guest valid on is executed in guest-mode. a Guest addresstranslation, or n wasexecuted. When this occurs, guest context TLB entry guest TLB mapping context entry instruction. Root or bits. Instruction. Instruction. struction. exception is similar to the higher-priority to the higher-priority exception is similar (continued) on - Root. on - Guest.Status.CU1-2 lid bit was zero in the Root TLB entry mapping the address address the mapping entry TLB the Root in bit was zero lid Root.Status.CU1-2 register. Debug TLB Execute Inhibit. TLB Coprocessor unusable - guest. Acce unusable Coprocessor by the mitted the of TLBRoot related. This Check listed exception Machine the lookup. TLB rather than during operation TLB a as part of occur can only This root- in executed is TLBP/TLBWI/TLBGP/TLBGWI a when or mode. Guest TLBrelated. of This part only occur can as when a TLBP/TLBWIinstructi Floating exception. Point Execution of Execution SYSCALL of in Execution BREAK of Execution a Reserved of Execution a coprocessor instru of coproces- CP1 the and supports The CP0 core I6500 not enabled. sors. MSA Disabled excepti MSA Disabled - guest.Access to but denied by , Guest.Config5.MSAEn The valid bit was zero in the valid bit was The store. a referenced during address the had which Root TLB entry valid matched a instruction An fetch due set. XI occur This can bit the referenced during a store. This ca during referenced translation. An instruction fetch matched a instruction An fetch set. XI bit the hardware programs a value of 0x9 into the into 0x9 of programs a value hardware A Cache error occurred on an instruction fetch. on an instruction occurred Cache error A CP0 MIPS64® I6500Multiprocessing Syst 2 1 1 1 1 1 RI Bp Sys FPE Table 4.5 Table of Exceptions Priority CpU TLBXI SDBBP SDDBP instructio EJTAG An MSADis Exception Description Mode I-cache - Error I-cache TLBOperation instruction fetch instruction (Validity exception) (Validity (Validity exception) (Validity (Validity exception) (Validity (Validity exception) (Validity (Validity exception) (Validity (Execution exception) 9 0x09 3 0x3Invalid - store TLB va The 6 0x06 - fetch IBE instruction an instruction fetch. on Bus occurred error A 8 0x08 11 0x0B 21 0x14 15 0x0F 24 0x18Check - Machine 10 0x0A 20 0x14 30 0x1E n/a n/a Field Encoding Cause.ExcCode Decimal Hex 68
69 Root Root Root Root Root Root Root Guest Guest Guest Guest Guest Guest Guest Guest Root or Root or Root or Root or Root or Root Root or
Table Debug.DDBL Debug.DDBS bit if tected on the address tected field. Refer to Refer field. legal data addresses. legal that all of the execution excep- execution of the all that The exact type of exception is exception exact type of The tch was detected on the address the on was detected tch ting of VzGuest exception pri- of VzGuest ting unaligned address, or an was asserted. Prioritized above y) or a data break on store store or a data break on y) the current processor was mode the processor current was mode the processor current occur due to a Root occur Guest or occur due to a Root occur Guest or st TLB entry was found, but the TLB entry was st is encoding encompasses all types encoding encompasses all is ruction that overflowed. that ruction condition true). is condition ess Break. A precise EJTAG break data Break. A precise EJTAG ess (continued) on to allow break il h de match was address GuestCtl0.GExcCode a matching root TLB entry was found, but the entry matching root TLB was a found, a matching root TLB entry was found, but the found, but was root TLB entry matching a address alignment error. An alignment error. address for more information and a lis a and more information for On a data load, a matching guest TLB entry was found, but the entry was found, TLB a data load, a matching guest On valid bit zero. (V) was valid bit zero. (V) was This can translation. Load TLB miss. A root TLB miss occurred on a data access. This This access. on a data occurred miss A root TLB miss. TLB Load translation. Guest or occur due to a Root can data access. on a occurred guest TLB miss A valid bit zero. (V) was This can translation. gue a data store, a matching On valid bit zero. (V) was addressthat wasinaccessible in referenced by a load or store. or by a load referenced address ma watch context guest A store. or by a load referenced addressthat wasinaccessible in instruction. by a load referenced by a store instruction. referenced When this exception occurs, hardware sets the CP0 the sets hardware occurs, exception this When occurred a load, or the if the error during bit a store. during occurred error the on load/store (address onl match (address load/store on condition + data match) (address data fetch exceptions 4.6 orities. Execution of Execution inst an arithmetic of trap Execution a trap (when of Note exception. Guest Virtualized Th priority. same have the tions guest exceptions. virtualization of the CP0 to written oot or Guest mode. or Guest miss in Root TLB Store 2 2 2 Tr Tr Ov Table 4.5 Table of Exceptions Priority TLBS VzGuest data access Exception Description Mode (Execution exception) (Execution exception) (Execution exception) 3 0x3 Invalid data store TLB - a data store, On 52 0x05- Data Access AdES 0x023 Store - refill TLBL/XTLBL 2 0x03 0x2- data TLB loadInvalid a data load, On 4 0x04- AdEL Data Access or an address, An unaligned error. ent alignm address Load 23 0x17 data access- WATCH context watc root A 12 0x0C 1327 0x0D 0x1B n/a n/a DDBL / DDBSAddr Data Precise Debug Field Encoding Cause.ExcCode Decimal Hex MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
Root Root Root Root Root Guest Guest em Programmer’s Guide, Revision 1.00 y) condition was asserted. Prior- asserted. was condition y) ng root TLB entry was found, and was found, entry TLB root ng Break. A precise EJTAG break data A precise Break. EJTAG (continued) ss, a matching guest TLB entry was found, was found, guest TLB entry a matching ss, On a data read acce a data read On set. and RI bit was the onl + data match (address load on in complete must access data the of aspects all because last itized match. value data do a to order TLB Read Inhibit. TLB matchi a a data read access, On was can set. This RI due ora Root occur the bit to Guest transla- tion. referenced by a store instruction. referenced the address mapping entry guest TLB bit was zero in the dirty The by a store instruction. referenced Precise Data Address Precise Debug MIPS64® I6500Multiprocessing Syst Table 4.5 Table of Exceptions Priority DDBL TLBRI Exception Description Mode ptions the have priority level. same TLB Modified mapping the address root TLB entry the in was zero dirty bit The have same priority level. the 7 0x07 DBE Data bus error- Imprecise. bus error. or store Load 1 0x01 19 0x13 30 0x1E data access- Error Dcache or cache data reference. A error occurred store a on load n/a n/a Field Encoding Cause.ExcCode Decimal Hex 1. exce Validity Instruction the All of 2.exceptions Execution the All of 70
71 Cause.ExcCode be set in order be set in be set in order be set in fieldshown.In addi-as cal Address is available. is Address cal exception condition is est Virtual Address avail- Address est Virtual est Physical Address avail- register for more more for register GuestCtl0 = 1 (as appropriate) before any before appropriate)= 1 (as ERL nel mode, but the instruction was not mode, but the instruction was not nel e Guest Physical Address is not avail- e estCtl0 must register estCtl0 must register able exception would be taken in exception would be able . When one of the guest-related excep- guest-related the . When one of CP0 context, regardless of whether the of context, regardless CP0 ption is raised before raised is exception this root-mode 1, = GuestCtl0.GExcCode RI ss to core functions. ss Root.Status mode and the Guest Physi Guest the and mode Table 4.6 at any time. When an at d changes are not d recognized. ion be can taken. coding 0x1B (27 decimal) in the CP0 the CP0 in (27 decimal) 0x1B coding = 1 or = 1 d Root TLB exception has Gu d Root TLB exception has Gu d Root GuestCtl0 Sensitive instruction. Sensitive instruction. EXL Instruction Redirect. Instruction Field Change Field event. Cause.ExcCode field,indicating a virtualization related exception. Root.Status e condition requires a switch to root mode, the switch is made before any before is made switch the mode, to root switch a requires condition e able. related TLB Root in a results translation TLB initiated mode Guest a when Set mode and th Root in occurring exception able. CP0 of Note Gu the (29) that the MC bit is bit If this change. initiated hardware a on occur to interrupt an the for initiate hardware cleared, able. related TLB Root in a results translation TLB initiated mode Guest a when Set in Root occurring exception the guest-mode guest-mode except the This exception is taken when execution Sensitive a Guest Privileged of was attempted from guest-ker Instruction CP0 Refer to the mode. for guest-kernel enabled enabling acce on information CP0 of Note Gu the (29) that the MC bit is cleared, bit this If change. initiated software a on occur to interrupt an the for recognized. not are changes initiated software A Reserved Instruction MDMX Unus or Instruction A Reserved When mode. guest t mode when the exception was detected. detected. exception was t the mode when all exception states are stored into root states all exception HC Hypercall GPA initiate Guest mode GRR Guest Reserved GPSI Guest Privileged Table 4.6 Table Values GExcCode GuestCtl0 Mnemonic Description tion,control can be returnedto root mode exceptions entry, which appears as en which appears exceptions entry, toallof the Guestrelated exceptions described in VZGuest 0x02 0x03 0x00 0x01 GSFC Guest Software 0x0A , the , Table 4.5 Table 9 0x09 GHFCevent. Change Field Guest Hardware 8 0x08 GVA initiate Guest mode 2 3 0 1 10 other state is saved. This ensures that ensures This other is saved. state processorexecuting was in root or gues tionsin the tableistaken, theactual exceptiontypeencoded is into the tion,hardware writesa valueof 0x1B to the CP0 field, corresponds corresponds field, In During guest mode execu guest mode During detected during guest mode execution and th guest during detected affected. CP0 exception not statecontext is a result, in the guest As saved. is exception state switchThe torootmode achievedis by setting 4 7- 4 0x7- 0x4 RSV Reserved. 11 - 31 11 - 0x0B 0x1F - Reserved Exceptioncode value Decimal Hexadecimal MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 4.4 Priorities Exception Hypervisor
Table notbe modifiedby register unless it e same basic processing basic processing e same registerdependent is on Cause bit notis changed inthe at which execution is restarted. is executionwhich at BD EPC es appropriate to the exception. The to es appropriate . bit in the the in bit em Programmer’s Guide, Revision 1.00 BD EPC r the exception and need r the exception register is loaded with the PC the loaded with is register stored in EPC/ErrorEPC/DEPC stored register is not loaded and the and loaded not is register EPC are modified */ are modified EPC register. loaded into the The value register. BD with registers are loaded the valu Cause CP0 PC registers,the including rnel software need not look at not the software need rnel MIPS64® I6500Multiprocessing Syst tions, exceptions have th have exceptions exceptions, Debug and error, e Cause struction that actually caused the exception. struction register. ting at the exception vector. exception at the ting registerthe is set, register is zero, the register register represents the restart address fo Status fields of the EPC No Address of theinstruction Yes(PC-4) instruction or jump branch the Address of Status Status is 1, all exceptions go through the general exception vector */ vector exception general the go through exceptions 1, all is 0 EXL BD = 1 then In Branch/Jump ExcCode EXL Table 4.7 Table EPC,in ErrorEPC, DEPC or Stored Exceptionon Value Delay/Forbidden Slot? Delay/Forbidden Value bit inthe bit in the in the bit vectorOffset 0x000 vectorOffset PC - 4 PC - EPC BD = 1 PC EPC BD = 0 Cause bit is setin the and bit is set appropriately in the appropriately in bit is set register. register. EXL EXL CE EXL BD endif */ of exception type of the a function as vector offsets Compute /* then = TLBRefill ExceptionType if else endif vectorOffset 0x180 vectorOffset if (DS) fieldloaded, is butnot defined, for any exception typethan other a coprocessor unusable exception. shows the value stored in each of shows the value The Ifthe /* and neither the EPC nor Cause the EPC and neither /* /* If Status CE if (expn) if Status Cause else 4.7 whether the instruction is in a forbidden slot, or the delay slot of a branch, or a jump which has delay slots. has delay which jump a or of a branch, slot delay the or slot, forbidden a in is instruction the whether • The exception handler in the normal case. Ke case. in the normal exception handler wishes to identify oftheaddress the in descrip- the in noted is This registers. other additionalinformationintoload may individualexceptiontypes that Note tion type. of each exception Operation: •If the the flow: •If With the exception of Reset, NMI, cach Reset, exception of the With • The processorbegins execu value loaded into the The • The 72 4.5 Processing Exception General
73 expected debug exceptions to debug exceptions expected mode. The DERET instruction ction must be used at return from be used at return must ction 0b00000)) VS ) 29..0 = 0) then */ = 0) VS (IntCtl rnel software. Note that un software. rnel = 0) then = 0) VS vectorOffset 29..0 = 1) or (IntCtl = 1) or RIPL BEV n caused the exception. The DERET instru the exception. The DERET caused n /* No carry between bits 29 and 30 */ bits 29 and between carry /* No = 1 then = 0) then */ = IV VEIC = 1) or (IntCtl = 1) or register. = 1 then */ = 1 then BEV (vectorBase EXL DEPC = 0) then = 0) VecNum Cause VecNum VecNum VIntPriorityEncoder() VecNum 0xFFFF_FFFF_BFC0.0200 IV 63..30 contain flowcharts for the followingexceptions and guidelines for their handlers: vectorOffset 0x200 vectorOffset if Config3 else endif + (VecNum 0x200 vectorOffset = 1 then 1 ExceptionType else endif /* if (Status /* if endif vectorOffset 0x180 vectorOffset if (Status BEV Figure 4.4 endif /* if (Cause /* if endif if (Cause else FaultingCoprocessorNumber EXL CE ExcCode and endif /* elseif (ExceptionType = Interrupt) then */ = Interrupt) (ExceptionType /* elseif endif elseif (ExceptionType = Interrupt) then = Interrupt) (ExceptionType elseif vectorBase vectorBase vectorBase Cause */ address base the vector Calculate /* if Status endif /* if Status /* if endif Cause endif */ vectorOffset and vectorBase sum of PC is the Exception /* PC Status Figure4.3 • General exceptions •exceptions TLB miss ke byserviced then and hardware by are handled Exceptions the debug exception vector at 0xFFFF_FFFF_BFC0_0200may be viewedreservedinstructionas a since uncon- instructio of an SDBBP execution trolled in orderthe debugto leave debug exception modehandler, and returnto non-debug returns tothe address in the MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 4.6 and Servicing Flowcharts Handling Exception
em Programmer’s Guide, Revision 1.00 0 Mode) Comments ; EXL ; 0 EPC (except interrupt if masked by IE) * After EXL=0, all exceptions allowed * Unmapped vector so TLBMod, TLBInv, or TLB Refill exceptions not possible * EXL=1 so Watch and Interrupt exceptions disabled avoidto all otherOS/System exceptions * * Only Reset, Soft Reset, NMI exceptions possible. * ERET is not allowed in the branch delay slot of another Jump Instruction PC * * LLbit (Optional enable Interrupts - only to while keeping Kernel MIPS64® I6500Multiprocessing Syst 1 Cause , 0, IE 0, bits: Status ERET STATUS , , MTC0 - MTC0 EXL = 1 = EXL MTC0 - MFC0 - 0, EXL 0, EPC Figure 4.3 Figure (SW) Guidelines Servicing Exception General Service Code EPC Set Status , Cause value & Jump to UM appropriate Service Code Check Context 74
75 Context and write into the TLB 0 EntryLo Comments ; EXL ; EXL 0 EPC Reg. Move it to * There could be a TLB miss again during the mapping during the mapping again a TLB miss be could There * of the data or instruction address. The processor will jump to the general exception vector since the EXL is general the in refill level first the complete to (Option 1. exception handler or ERET original to the instruction and take the exception again) * Load the mapping of the virtual address in * ERET is not allowed in the branch delay slot of another Jump Instruction PC * * LLbit LLbit * * Unmapped vector so TLBMod, * or TLBTLBInv, Refill exceptions not possible Watch, Interrupt EXL=1 so exceptions* disabled to OS/System * all other avoid exceptions Only Reset,* Reset, NMI exceptions Soft possible. CONTEXT Figure 4.4 Figure (SW) Guidelines Servicing Exception TLB ERET Service Code MFC0 - MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
*/ VS = 0) or vector offset 0x200 (if 0x200 offset or vector 0) = IV e Caus em Programmer’s Guide, Revision 1.00 , theI6500 supportsinterrupts three modes. entered when a Reset exception occurs. In this mode, inter- In this mode, occurs. Reset exception a entered when s are notimplemented have or been disabled. in each of these modes. each of look for in handler might /* and mask with IM bits */ with IM mask /* and */ 16..23 k0 = IP7..IP0; bit set, first /* Find IntCtl software emulate to /* Shift MIPS64® I6500Multiprocessing Syst ndler for compatibilitymode: = 1 (if it were zero, the interrupt exception would have to would exception interrupt the were zero, 1 (if it = IV 1, or = = 0, or = = 0, which is the case 0, if vectored interrupt which is the case = IV BEV VS laaddujr VectorBase k1, k0, k1 k0, nop k0 */ vectors of 8 interrupt base /* Get */ offset base and from target /* Compute */ routine exception to specific /* Jump mfc0mfc0 C0_CAUSE k0, andi C0_STATUS k1, and k0, M_CauseIM k0, */ from Cause IP bits only /* Keep k0, k1 k0, bits */ for IP register Cause /* Read bits */ for IM register Status /* and beqclz zero, Dismiss k0, xori k0 k0, sll */ interrupt - spurious bits set /* no k0, 0x17 k0, k0, VS k0, 7..0 */ => /* 16..23 = 1). This mode is in effect when= 1). This mode the any of isfollowingineffect conditions are true: IV /* analogous interrupt, a specific processes routine processing Each interrupt * routine processing each Since mode. EIC interrupt VI or in reached to those * know to the context it has line, interrupt particular to a is dedicated * further to look may need routine Each processing was asserted. which line * requests interrupt multiple if the interrupt of source actual the to determine * the performed, task is that line. Once IP a single on together are ORed * ways: of two in one processed may be interrupt * * The interrupt). simple UART a level (e.g., at interrupt - Completely * this type. of an example below is routine SimpleInterrupt * this In interrupts. other re-enabling and state sufficient - By saving * /* Assumptions: * - Cause * Cause Status IntCtl * be isolated from the general exception vector before arriving before vector exception the general from isolated be * here) * are available k0 and k1 - GPRs * SW1..SW0) (HW5..HW0, is IP7..IP0 priority - The software * * base exception 0x200 from Offset Location: * */ IVexception: Here is a typical exception ha is a Here • • • The following following how aninterrupt subsections show The is the defaultThis interruptthe processorandmodefor is (if 0x180 offset vector exception though and dispatched are non-vectored rupts Cause As described sectionin the entitled Overviewof Exception Processing 4.7.1 Mode Interrupt Compatibility 76 4.7 Examples Mode Code Interrupt
77 /* Get restart address */ address restart /* Get */ in memory /* Save value */ Status /* Get */ in memory /* Save bit */ the IM at least include this must /* */ include and may interrupt, current for the /* */ others /* */ of Status in copy bits /* Clear k0 */ bits in ERL, EXL KSU, /* Clear */ mode, to kernel switch mask, /* Modify */ interrupts re-enable /* bits so that “lower” priority interrupts are interrupts priority “lower” so that bits IM /* Return to interrupted code */ code interrupted to /* Return */ be required - may not interrupts /* Disable */ and EPC /* */ and EPC /* /* Save GPRs here, and setup software context */ context software setup here, and Save GPRs /* mfc0sw C0_EPC k0, mfc0sw EPCSave k0, C0_STATUS k0, li StatusSave k0, ~IMbitsToClear k1, and */ interrupt for this to clear IM bits /* Get ins k0, k1 k0, (W_StatusKSU+W_StatusERL+W_StatusEXL) S_StatusEXL, zero, k0, mtc0 C0_STATUS k0, /* interrupt. device clearing including here, interrupt Process * in running the core done with may be this environments In some * of scope beyond the is well an environment Such user mode. kernel or * this example. * */ di lwlwmtc0 StatusSave k0, mtc0 EPCSave k1, C0_STATUS k0, C0_EPC k1, */ EXL set) (including Status saved /* Get */ value original the /* Restore eret NestedException: /* registers, and Status the EPC saving require typically Nested exceptions * disabling routine, exception nested by the be modified may GPRs that saving any * loop, putting an interrupt to prevent Status bits in IM the appropriate * code The sample interrupts. re-enabling and kernel mode, in the processor * only intended and is this processing of all nuances cover below cannot * concepts. the to demonstrate * */ /* restored must be values the saved processing, interrupt To complete * restarted. code interrupted original and the * */ * also disabled. The NestedInterrupt routine below is an example of this type. this of an example is below routine NestedInterrupt The also disabled. * */ SimpleInterrupt: /* request the interupt clear and here interrupt the device Process * to be may need registers some do this, order to In at the device. * ERET an that is such state 0 The coprocessor restored. saved and * code. interrupted to the return will simply * */ * case the software model determines which interrupts are disabled during disabled are interrupts which determines model software the case * single the is either this Typically, interrupt. of this the processing * some or processed, being the interrupt to corresponds bit that StatusIM * Status of other collection * MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
l the following conditions are the l em Programmer’s Guide, Revision 1.00 mode is in effect when al when effect is in mode zes pending interrupts and generates a vector which can be which a vector generates and interrupts pending zes bypasses the entire sequenceof code followingthe atching directlyto the interruptprocessing routine. /* Clear bits in copy of Status */ of Status in copy bits /* Clear k0 */ bits in ERL, EXL KSU, /* Clear */ mode, to kernel switch mask, /* Modify */ interrupts re-enable /* /* this must include at least the IM bit */ the IM at least include this must /* */ include and may interrupt, current for the /* */ others /* */ be required - may not interrupts /* Disable */ and EPC /* /* Dismiss the interrupt */ interrupt the /* Dismiss MIPS64® I6500Multiprocessing Syst a dedicated handler routine. VI a dedicated = 0 = 1 = = 0 0 = 1 = VInt VEIC
IV BEV VS mfc0sw C0_EPC k0, mfc0sw EPCSave k0, C0_STATUS k0, li StatusSave k0, */ address restart /* Get ~IMbitsToClear k1, */ value Status /* Get */ interrupt for this to clear IM bits /* Get */ in memory /* Save */ in memory /* Save andins k0, k1 k0, (W_StatusKSU+W_StatusERL+W_StatusEXL) zero, S_StatusEXL, k0, mtc0 C0_Status k0, */ interrupt device clearing including here, interrupt Process /* di lwlw StatusSave k0, EPCSave k1, */ EXL set) (including Status saved /* Get /* Restore GPRs and software GPRs /* Restore software state and */ eret NestedException: /* registers, and Status the EPC saving require typically exceptions * Nested loop, interrupt an to prevent in Status IM bits the appropriate * disabling sample The interrupts. re-enabling and mode, in kernel processor the * putting only is intended and processing of this nuances cover all cannot below * code concepts. the demonstrate * to */ IntCtl Cause Status Config3 Config3 /* restored must be values the saved processing, interrupt To complete * restarted. code interrupted original and the * */ • • A typical software handler for Vectored Interruptmode A typical software handlerfor Vectored labelshownfor the compatibility IVexception modehandler codeexample described previoussubsection.in the Instead,thehardware performs the prioritization, disp A nested interruptis similar to thatshown for compatibility mode.Sucha routine might look as follows: In Vectored Interrupt (VI) mode, a priority encoder prioriti encoder a priority mode, (VI) Interrupt Vectored In each interrupt to to direct used true: • • • 4.7.2 Mode Interrupt Vectored 78
79 to prevent to IPL Status to label exception IV RIPL zes thesezes interrupts with by kernel software to enable or enable to software kernel by Cause rrupt logic is configured in order to order to in configured is logic rrupt ) and the timer, performance coun- performance timer, the and ) ms the prioritization, dispatching IP1..IP0 code following the following code Cause e stateofe thisbit is EIC_MODE reflected in the ) to thewhich GIC, prioriti to power upinlegacy mode,then switchto EIC mode. nnel, and performancecounterinterrupts,and directly sup- ) register. This bit can be written This bit can be written register. ) TI/PCI/FDCI /* Clear KSU, ERL, EXL bits in k0 */ bits in ERL, EXL KSU, /* Clear es the entire sequence of entire sequence the es Cause /* Save in memory */ in memory /* Save /* and EPC */ and EPC /* */ hazard /* Clear */ interrupt the /* Dismiss above. Instead, thehardware perfor redefines the way that the processor inte the way that the redefines GIC_VL_CTL state of the ( state interrupt requests of lof the following conditionstrue:are an example of such a isroutine: Here such an example of interrupting thehandler. bit= 1 indicatesregister supportfor EIC mode. Th = 1 = 0 0 = 1 = VEIC VEIC
IV BEV VS mfc0mfc0 C0_CAUSE k1, srl C0_EPC k0, sw k1, S_CauseRIPL k1, mfc0 field */ RIPL justify /* Right sw */ RIPL value to get Cause /* Read EPCSave k0, C0_STATUS k0, insins */ address restart /* Get StatusSave k0, Status */ copy of RIPL in IPL to 6 /* Set k1, S_StatusIPL, k0, */ value Status /* Get (W_StatusKSU+W_StatusERL+W_StatusEXL) zero, S_StatusEXL, k0, */ in memory /* Save mtc0mtc0 C0_STATUS k0, ehb C0_EPC k1, eret */ value original the /* Restore Config3 NestedException: /* registers, and Status the EPC saving require typically exceptions * Nested loop, interrupt an to prevent in Status IM bits the appropriate * disabling interrupts. re-enabling and mode, in kernel processor the * putting and is this processing of all nuances not cover can code below sample * The the concepts. only to demonstrate * intended */ Status Config3 IntCtl Cause directlyto the interruptprocessingroutine. also copy must It mode. for compatibility shown that to is similar interrupt nested A • • lower priorityinterrupts from The provide supportThe interrupt controllerforis responsible prioritizingan externalfor interrupt all inter- controller. fast debugcha rupts,including hardware, software, timer, plyingtothe processor the vector numberof the highest priorityinterrupt. al if EIC interruptmode is in effect • External Interrupt Controller (EIC) mode mode (EIC) Controller Interrupt External ter, andfast debug channel interruptrequests ( ter, • other hardware interrupts. bypass EIC mode for handler exception typical A Compatibility-modeshown for the handler disable EIC mode. This is useful for systems that may want that may for systems useful This is EIC mode. disable InEICmode, the processor sends the read-write bit of the GIC VL Control ( Control VL GIC bit of the read-write 4.7.3 External Interrupt Controller Mode MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
em Programmer’s Guide, Revision 1.00 /* Modify IPL, switch to kernel mode, */ mode, to kernel switch IPL, /* Modify */ interrupts re-enable /* MIPS64® I6500Multiprocessing Syst mtc0 C0_STATUS k0, */ interrupt device clearing here, including interrupt Process /* /* above. VI mode for shown to that identical code is completion The interrupt * */ 80
81 programming, including the eight I/O coherence units coherence eight I/O in the I6500Multiprocessing System table that lists each device ID on device the lists ID table each that . The devices connected to the CM are The devices . roller, which facilitates communication which facilitates roller, vices. An overview of the CM register address space is the CMregister address space An overview of vices. A directory-based coherence effi- protocol is used to directory-based A S, to achievesystem-wide coherence. multi-clusterIn a have up to 6 cores per cluster. per cores 6 to up have the same core, accessing a VP in another core, accessing core, in another VP a same core, accessing the each I6500 core, with up to I6500 core, with each programtheCM to perform various functions,including set- bes information necessary for necessary information bes rent access to the L1 Data and L2 caches. access rent system devices via a register ring bus ring devices via a register system Ring Bus and Device ID’s external Network-on-Chip (NOC)Network-on-Chip cont external . The I6500 Multiprocessing System can System I6500 Multiprocessing . The Figure5.1 The CM communicates with the various with the various CM communicates The shownin This section provides an overview of the CM and descri the CM overview of provides an This section es with all cores and other devices other and Manager es (CM) communicat cores with all The Coherence as wellas devices(MPS), coherent externalto I6500the MP an system, the CM also interfaces to register ring bus anddevice register map. ID informthe CM and ation, between clusters. L2 an cache. integrated low-latency shared includes The CM of data caches the L1 among ciently maintain coherence cohe subsystem the I/O (IOCUs), providing associated CM register ring bus and This of chapter provides an overview the these de access to information this uses The programmer bus. also provided.In addition, thechapter describes howto the General InterruptController (GIC), Cluster Power Controller (CPC), and/or Debug Unit (DBU) registers via the numberof the revision For the exact components.system I6500 the various between ratios clock the and setting CM, to the Release Notes. refer Manager, Coherence ting the base addresses in memory, accessing another VP in VP another accessing addresses in memory, base the ting 5.1.1 CM Interface — Register MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 5.1 Overview CM Coherence Coherence Manager Chapter 5 Chapter
. These val- . Unit CPC (DBU) Debug Figure 5.1 Figure bus, indicated by the indicated by bus, S M M S e ID number matches thatmatches number ID e to maximizethroughput.The to S MCP 6-bitID value stored in thedestina- IOCU 7 em Programmer’s Guide, Revision 1.00 GCR a device initiates an access to the regis- device to the initiates an access a From I/O From rnal proprietary bus called the MIPS bus rnal proprietary Custom usinga register ring AXI4 the above figure, note In the operations. in-flight S Figure 5.1 AXI4 packet. Only the device whos device Only the packet. NOC as both Master (M) and Slave (S). All other devices, devices, (M) All other and Slave (S). both Master as IOCU 0 IOCU From I/O From d IOCUs together. For example,there if are four cores, dIOCUs together. MCP ee unidirectional channels used channels unidirectional ee ribedinthe followingsubsections. All valuesnot shownare AXI4 ACE lists the ID values for each logic block shown in the ID values for each logic block shown lists MCP S Memory dest_id / src_id / dest_id Coherence Manager3.5 Core 5 achdevice on theringbus is assigned a MIPS64® I6500Multiprocessing Syst (Hexadecimal value) DeviceAccessed g ID is attached to the attached to the ID is g fields of the packet being sent. When being packet fields of the IOCU’s connect to the CM via inte an IOCU’s Table 5.1 Table the various devices shown in devices the various MCP GIC S Table 5.1 Table Values ID Bus Device Ring Register asedprotocol toallow multiple simultaneous Core 0 Core 012345 0x00 0x01 0x02 0x03 0x04 0x05 Core 0 Core 1 Core 2 Core 3 Core 4 Core 5 16 0x10 IOCU0 MCP dest_id / src_id (Decimalvalue) Figure 5.1 Figure CM to the Interface Bus Ring Register and Ports Interface GCR Register RingBus S =S Slave = M Master Legend: S S Certain devices such as the cores and such as Certain devices Coherence Protocol (MCP) bus. This bus consists of thr of consists bus This (MCP) bus. Protocol Coherence bus implements a credit-b bus implements a thatthe I6500 MPS supports uptoa total eightof an cores to four IOCUs.only be up can there accesses the registers of The CM dotted line. As shownabove,the CM and DBU can function including the cores, are slave devices. E tion source ID (dest_id) or ID (src_id) of another device, the correspondin ters transaction. the the packet accepts in ues are used to write to registers in these blocks as desc blocks as these used to write to registersues are in reserved. 82
83 , and drives this request drives this and , involved in the example Table 5.1 Table color indicates the the data return color indicates CM GIC CPC GCR blue AUX 3 AUX AUX 1 AUX 2 AUX AUX 0 AUX IOCU2 IOCU3 IOCU4 IOCU5 IOCU6 IOCU7 IOCU1 Memory DBU Master (continued) No Destination No OK Destination User Defined GCR’s Defined User DBU dmxseg_debug DBU No Destination Error No Destination DBU dmxseg_normal , except only those devices , to read a register from the GIC. The data path for this read a register from the GIC. The data path for this to . In this example. thefollowing actionswould occur. Figure5.1 s as indicated. as s 0x11 0x19 0x20 0x18 0x21 0x22 0x29 0x12 0x13 0x14 0x15 0x16 0x17 0x23 0x24 0x25 0x28 0x3F 0x3E 0x2B 0x1A 0x2A dest_id / src_id / dest_id its dedicated register ring bus Slave port. (Hexadecimal value) DeviceAccessed Slave on the ring bu color indicates the access the request path, and . This figure. similar is to red 62 63 25 26 32 33 42 43 34 17 18 19 20 21 22 23 24 35 41 36 37 40 Table 5.1Table Register Ring Bus Device ID Values Figure 5.2 dest_id / src_id (Decimalvalue) onto registerthe ring bus through itsport. Master directly because it is only a is because it directly 3.match. bus and gets a on the ID the The GIC decodes 4. The GIC then fetches the requested dataanddrivesthedata ontothe ring bus. 5. Data is returnedto the CM through transaction are shown. The are shown. transaction enumerated in Figureis path. The following sequence 5.2 access is shown in is access 1.registers GIC 0cannotaccess the NotethatCore MCPthe‘Request’ bus. the CM overto request 0sendsa Core 2.in as defined number ID the appropriate assigns request, this CM processes The The following example shows the path taken in order for core 0 for in order taken the path shows example following The MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
Table 5.2 Table GCR Base S = Slave = S M = Master Legend: M Core-Redirect aining to the global aining sys- 6500 core). reg- 6500 Contains as defined inthe 2 into another core’s Core-Local Core-Local core’s another into ssuing the request. Each has its core Each the ssuing request. em Programmer’s Guide, Revision 1.00 access thisbloc k registers. of Description (aliased for each I6500 core). This block of This block I6500 core). each for (aliased GCR_BASE (aliased for each I (aliased for each for more information on how these ID values ID these on how for more information cessing this space, the the space, this cessing Contains global registers useful in debugging the debugging in global registers useful Contains 3 Control Block Control Control Block Control
S
GIC in the Local Control sub-block must be set with the CORE- the Local Control sub-block must be set with the in Debug Block.
4 MCP ther Register Usage Register ther re 0 over the dedicated MCP ‘Response’ ‘Response’ bus. MCP dedicated the 0 over re isters pertaining to the I6500 i core to the I6500 pertaining isters this block. registers within of copy own Core-Other a window gives each Core addresses Block. Control Before ac Register Core. target the NUM of Global MPS. I6500 Core-Local . Contains registers pert Block. Global Control All cores can functionality. tem ed when accessing these various devices. when accessing ed 6 MIPS64® I6500Multiprocessing Syst . For simplicity, the MIPS defaultvalue 0x0000_1FBF_8 of is used for the simplicity, For . Coherence Manager3 S Core 0 Core Figure 5.3 Core-Local and Core-O Core-Local 1 Figure 5.2 Figure Registers IOCU0 of 0 Access Core of Path Data 3-channel bus MCP Table 5.2Table to GCR_BASE[47:15]) (Relative Map Address Space Control I6500 5 . This 32 KByte register block can be mapped anywhere in memory on a 32 KByte boundary. TheAddress . This32 KByteregister blockcan be mapped anywherememoryin on32KByte a boundary. Address Range Register RingBus GCR_BASE[47:15] Size (bytes) S GCR base address. Each register block contiguous is assigneda to as 8 KB space shownin the figure. This conceptis described in Range column shows bits 47:15. Bits 14:0 are always zero so as to align on a 32 KB boundary. Range columnshows bits 47:15. Bits 14:0 are always tozeroso as align 32 on a KB boundary. Refer to the section entitled entitled the section to Refer us the sequence programming and are assigned The 32 KB CM GCR register block is divided into four 8 KB subblocks which perform different functions. perform different which 8 KB subblocks four into is divided block CM GCR register 32 KB The shows the address map of the four, 8 KB GCR sub-blocksrelativeto the shows themap addressfour, the of 6.data to Co back requested the sends The CM Register 0x0000_4000 0x0000_5FFF- 0x0000_4000 KB 8 0x0000_6000 0x0000_7FFF- 0x0000_6000 KB 8 0x0000_2000 0x0000_3FFF- 0x0000_2000 KB 8 0x0000_0000 - 0x0000_1FFF - 0x0000_0000 KB 8 5.1.2 CM GCR Register Map 84
85
Core-Redirect Debug Block Debug Core-Local Block Core-Other Block Core-Other Global Control Block . A core can access its own Core-Local its can . access A core register in itsown Core-Local block with the 0x0000_1FBF_E018 0x0000_1FBF_E010 0x0000_1FBF_E008 0x0000_1FBF_E000 0x0000_1FBF_FFFF 0x0000_1FBF_A018 0x0000_1FBF_A010 0x0000_1FBF_A008 0x0000_1FBF_A000 0x0000_1FBF_8018 0x0000_1FBF_8010 0x0000_1FBF_8008 0x0000_1FBF_8000 0x0000_1FBF_C018 0x0000_1FBF_C010 0x0000_1FBF_C008 0x0000_1FBF_C000 0x0000_1FBF_9FFF 0x0000_1FBF_DFFF 0x0000_1FBF_BFFF atus registers for a given core and/or Virtual Processor givenatusregisters for a core and/orVirtual core.Parameters include base address assignments, reset Core-Redirect +0x2000 +0x2000 +0x2000 ers are per-core, and some are per-VP are and some are per-core, ers another core. Before a corespace, the the Core-Other can access 0x0000_1FBF_E000 0x0000_1FBF_A000 0x0000_1FBF_C000 MIPS Default: 0x_0000_1FBF_8 15 GCR_BASERegister Figure 5.3 Figure in GCR_BASE Default MIPS the Using Scheme Addressing CM Register GCR_BASE register in that core’s own Core-Local Control Blockmust be set withthe core number (CORENUM)the of target that register core’s in would program the particular core a this case, In core. e cores have access to, and provides a way for one core to core for one way provides a to, and have access of the cores Core-Otherthat all a single block The GCR block is of registers Core-Local the access The Core-LocalThe GCR block contains the configuration and st (VP). Some of the (VP). Core-Local regist Some of block to determine the configurableparameters for that etc. exception base, 47 5.1.4 Core-Other GCRs 5.1.3 Core-Local GCRs MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
. Table 5.2 If a core wishes to modify wishes core a If eeps one copy of the regis- copy one eeps VP . Core e request to the appropriate the cluster appropriate request to e VP ects the core number and writes this writes the core number and ects cluster, the I6500 allows for clus- also cluster, ster to be accessed into the Core-Other into accessed to be ster em Programmer’s Guide, Revision 1.00 that are instantiated per-core, the CM per-core, that are instantiated Figure 5.4 CM et address 0x0018. The actual register in the in register 0x0018. The actual et address Cluster 2 VP Core VP core that is accessing them. accessing is that core e Core-Local block located at the address range shown address the Core-Local block located at e space contains the GCR registers for that core. The Core- The core. for that space the GCR registers contains gisters for another core’s Core-Local GCR block. gisters for another core’s e located e at theMIPS default of 0x0000_1FBF_8000.address CR registers of another core, it sel core, it registers of another CR physical memorythis if option is selected duringconfiguration. IP If this onto the NOC. th The NOC then routes gisters, it writes to th to writes it gisters, ers in a core or VP of another cluster in a registers one cluster to access the in VP or terface. This interface is shown in is interface This terface. MIPS64® I6500Multiprocessing Syst gisters in these blocks. For registers gisters blocks. For registers in these For registers that are instantiated per-VP, the CM k the CM per-VP, instantiated are that registers For uster 1 can access and update a register in a VP in Cluster 2 as shown. The 2 Cluster in update a register in a VP and 1 can access uster e CM in the destination cluster. Network on Chip (NOC) VP -to-core and VP-to-VP accesses within the same accesses within VP-to-VPand -to-core Core VP , CM providesthe two blocksof registers. CM Cluster 1 Figure 5.4 Cluster-to-Cluster Register Accesses Using the NOC VP register in itsown Core-Local block at offs Core-Redirect Table 5.2 Table . If a core wishes to program the G If a core wishes to program . Core VP • range Core-Local0x2000 (offset - 0x3FFF) • range Core-Other 0x4000 (offset 0x5FFF)- Table 5.2 Table ter-to-cluster accesses. This allows a core a This allows accesses. ter-to-cluster through in (NOC) the Network-On-Chip where the access is scheduled by th scheduled is the access where keeps one copy of the register per core. per of the register copy one keeps For VP within a core in example, a Cl and driven the CM by is processed access Inaddition tofacilitating core Other address space allows a core to access the the GCR re access to a core space allows Other address address space. address As listedin selected copy re maintains of The a CM given Core-Local address core. The in a for each VP ter can be located anywhere in registers These the to registers corresponding represents block Core-Local The core number to be accessed. The core would then write the contents of the regi the of contents the then write would core The number to be accessed. core option is not selected,the locationregisters ar these of the contents of its own set of CM GCR re its of contents the in valueinto the other core tobe written would use the correspondingin the Core-Otherblock offset shown in 5.1.6 Cluster to Cluster Accesses 5.1.5 Core-Local Usage Register and Core-Other 86
87 . Global e it is placed onto the RRB of it is placed e Cluster Access to Cluster Cluster . If the If ID’s. Device and Bus Ring On-Chip intercon- (NOC) coherent at move the access from the cluster to from the cluster access the move at clustera uniquehas number. ID are read-only and allow kernelsoftwareread-only quicklyand allow to are ectional bus is used to manage coherence as shown above. as shown coherencemanage to is used bus ectional are hardare values wiredbuilt, these vice is into the CM Interface — Register — Interface CM transfer the access request wher access the transfer bove, the NOCis not the access is placedused and onto the er for the current cluster. Each the current cluster. er for cluster access, refer to entitledthe section refer access, cluster hardware interface to the Network- to the hardware interface read Communication Unit is present read Communication cated unidirectional AXI bus interfaces th bus AXI unidirectional cated registerprovides the followinginformation: ribed in the section entitled entitled the section in ribed e system,the in the numberof ofcores customer the number selects I/Ocoherency units System Configuration register at offset address 0x0000. register All at offset of these fields Global Configuration nect. • present is — Unit Indicates if a Debug 40 Bit •the type of Indicates 43:41 — Bits • Bits 7:0 — Numberof cores in thesystem (upto 6) •8) to (up IOCU’s of Number — 11:8 Bits • Bits 19:16 —Number MMIO regionsof address • Bits 22:20 —Number auxiliary of memory ports • Bits 29:23 —Number clustersof in thesystem •— Indicates if an Inter-Th 31 Bit • Bits 39:32 —Indicatesthe ID numb determine the system configuration. determine the system Interface CM GCR Register Reading the For a programming example of a cluster to a cluster programming example of For a the destination cluster. There are dedi There are cluster. destination the A separate bidir the cluster. to NOC the from and NOC, the register access is to another cluster, the NOC is used to the NOC is used cluster, access is to another register Register Ring Bus (RRB) desc Bus Ring Register At IP configuration time,the If a register access is within a is showngiven cluster as within a a access registerIf a andthe numberof address regions. When thede (IOCU’s), Configuration MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 5.2 Overall Verifying
. Up to 5 Up to . Table 5.3 Table GCR_IOCU_BASE ers. Note that this this that Note ers. GCR registers. This Register. Note that this this that Note Register. different locations using different region must reside on a must reside on region register. Note that this region this that Note register. register. that region Note this register. Description disabled the bit via GGU_EN in se Address register. Sets the base se register. Address se Address register. Setsthe base se register. Address e base address of the IOCU. This block base IOCU. Thise address the of em Programmer’s Guide, Revision 1.00 GCR Custom Base GCR GCR as summarized in as summarized GCR containsthe and associatedIOMMU registers. the IOCU be disabled The via region may in the IOCU_REG_EN bit Note that thisregister. boundary. KB 32 address of GIC. address the This region may be GIC the via GIC_EN bit in disabled the GCR_GIC_BASE reside boundary. a 128 must KB on region be CPC may of CPC. This address the bit in the via CPC_EN disabled the GCR_CPC_BASE reside must a 32KB boundary. on address of GCR regist address the KB boundary. 32 a must reside on region of Customer address the region be may the KB boundary. 64 a must reside on region e aforementioned regions at regions aforementioned e ry using the associated Base Address register. Each ryusing the associatedBase Addressregister. registers located in the in located registers MIPS64® I6500Multiprocessing Syst se Addresses in Memory Addresses se Offset Address FieldName Bits Table 5.3Table Setting the Base Address for the CM Peripheral Devices provides an example of memory mapping for all of th all of for mapping of memory example an provides GCR_CUSTOM_BASE 0x0060BASE CUSTOM_ 47:16Sets the base Base register. Address Custom This sectiondescribes howsetthetobase of addressthe various CM logic blocks. Interface CM GCR Register of set through a address map is programmable The Figure 5.5 Figure register indicates the starting address of that block in memory. register address indicates the starting of that blockin memory. fixed-sizeregionscanbe mapped anywherein memo physical the MIPS default base address. default base the MIPS GIC GCR_GIC_BASE 0x0080 GIC_BASE_ADDR 47:17Ba GIC CPC GCR_CPC_BASE 0x0088 CPC_BASE_ADDR 47:15Ba CPC GCR GCR_BASEGCR 0x0008 GCR_BASE_ADDR 47:15 Setsthe base Base GCR Addressregister. IOCU GCR_IOC_BASE 0x0100 IOC_BASE_ADDR 47:15 Sets th Block RegisterName Custom Custom 88 5.3 Programming the Ba
89 above. above. GIC Base Figure5.5 companion document. field theof 0x0000_1BDE_0000 0x0000_1BDD_FFFF 0x0000_1BDE_7FFF 0x0000_1FBF_FFFF 0x0000_1BDE_8000 0x0000_1FD1_FFFF 0x0000_1FC0_0000 0x0000_1BDC_0000 0x0000_1FD2_0000 0x0000_1FD2_8000 0x0000_1BDB_FFFF 0x0000_1FD2_7FFF 0x0000_1FBF_8000 0x0000_1FBF_7FFF GIC_BASE I6500Registers IOCU Main Memory Main Main Memory Main CPC (32 KB) Main Memory Main Main Memory Main GIC (128GIC KB) CM GCR (32 KB) C. Thissets the base address of C. the GIC registers. (32 K x Number of IOCU’s) Figure 5.5 Figure Example Programming Map Address field has a fixed size of 32 KB. 1. Program the GIC_BASE field 1. 2. Program the Program 2. field CPC_BASE 3. Program the GCR_BASE field Program 3. 4. Program the IOCU_BASE field Program the IOCU_BASE 4. This field has a fixed size of 32 KB. This field has a fixed size of 128 KB. register located at offset 0x0080register with valuelocated a 0x0000_1BD at offset of of the GIC Base register at offset 0x0080. of the GIC Base register at offset of the 0x0088. CPC Base register at offset of the GCR Base register at offset 0x0008 of the GCR Base register at offset of the IOCU Base register at offset 0x0100. of the IOCU Base register at offset The followingThe programmingregister sequence is used to configure the memory mapas shownin For more information on the corresponding Base Address register, refer to therefer to Formoreinformationthecorresponding on register, Base Address 1. set the base address of theGIC registers to theMIPS default, program the To with the MIPS default of 0x0000_1FBF_8. This MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
GCR chapter ng bit of ng CPC Base fieldthe of it to 0 mapping field of the registers by program- by registers field of the of field the correspondi CPC Programming CPC GCR_BASE a core, with b a IOCU_BASE_ADDR CPC_BASE Global Access Privilege registerGlobal Access to the CP0 CMGCRBase register. In this this In register. CMGCRBase CP0 the em Programmer’s Guide, Revision 1.00 provided access to the CM the to access provided s is granted to the requestor the is granted to for both the CM GCR s ogrammer need only clear need ogrammer register located at offset 0x0120. Bits5:0 and 23:16register located at offset this case, the base value is read and an offset is added is read and an offset value case, the base this questor can be either a core or an IOCU. The CM allows CM The IOCU. an core or a either can be questor nce, a valuence, a 0x0000_1FBF_8 of is used (MIPS default)to estor’s have readpermission estor’s toall GCRCM registers,but bits 5:0, each bit bit 5:0, corresponds to each bits gisters to the MIPS default, program theprogram default, MIPS the to gisters ontroller (CPC)Referregister block. to the $15,3 4 bits by left in t1 value // shift base KSeg1 // assign e CM registers bythatignored. requestorare sters to the MIPS default, program the program default, MIPS the to sters led. This example reprograms the CM the led. This example reprograms MIPS64® I6500Multiprocessing Syst e CM GCR registers is programmed into CM GCR registers e described acces above, write GlobalAccess Privilege CSR CM global control registers. In registers. control global CM register located at offset 0x0100withlocated register at offset a valueof 0x0000_1FD2. pond to a specific requestor. In a requestor. specific to pond field of the the of field programmer can decide which requestor’s are requestor’s decide which can programmer act register address. register located at offset 0x0008 registerwith located of 0x0000_1FBF_8.a value at offset baseof the addressThis sets the 32 KB ACCESS_EN Base block of GCR registers. This block isdivided intofour 8 KB subblocks that contain theGlobal, Core-Local, blocks. register Debug and Core-Other, mfc0dsll c0_CMGCRBASE t1, li t1, 4 t1, 0xA000_0000 t2, t1 into register CP0 CMGCRBase of contents // move #define c0_CMGCRBASE #define IOCU Base Address register located at offset 0x0088register with valuelocated a 0x0000_1 at offset of BDE_0. This sets thebaseregis- of the CPC address ters. to itto derive the ex By default all IOCU’s and cores are enab cores are and IOCU’s By default all example, the base address could be any value. As a refere As be any value. address could the base example, of the locationbase the indicate core 0. only IOCU0 and enable Note that of by setting one these bits Note thisfieldtozero and all write requests to th Power C the Cluster well as as register block, in thismanual information.for more PermissionsRegister Access CodeExample th of location address for the base The mingthe core 0 andbit 5 mappingto core 5. For bits 23:16, bit16 maps to IOCU0, and bit 23 maps toIOCU7. The MIPS meaning thatinall the systemrequestor’s (all default cores and allfor this field is 0x0000_0000_00FF_00FF, to the CM register set. access have IOCU’s) pr the requestor, access registers for a particular to the disable To 4. base set the address of theIOCU registers to the default,MIPS program the To 3.of the CM GCR re address base the set To A requestor can request access to selected CM registers. A re registers. to selected CM access request can requestor A up to eight requestors in a system in any combination of cores and IOCU’s, from 8 cores and no IOCU’s, to 8 IOCU’s to 8 IOCU’s no IOCU’s, 8 cores and from IOCU’s, cores and of combination in any system a in requestors eight to up and anywherenocores, or in between. Notethat all requ 2. regi of the CPC address base the set To write access to these registers must be granted. registers to these write access Interface CM GCR Register the boot time, During of this field each corres this field each of 90 5.4 Access Permissions Register CM
91 VP- bit 31 of the VP 31 bit CT) thisof register indi- , indicating that the transac- , indicating en accessing registers in other accessing registers en accessed. In this case, a different VP case, a different In this accessed. register located at offset address located at offset register address in core 1, facilitate VP 2. To other values toallow core-other Core-Local Reset Exception Base the Global Interrupt Controller” USTER_REDIRECT_EN TER_REDIRECT_EN bit 31 of the VP TER_REDIRECT_EN bit 31 register located at offset 0x0018.address In located register at offset field of this same register same this of field e registers are instantiatedinthe I6500 per-VP core. registers withinthesamecore, but corresponding to a ould be 0 to indicate the Core-Local block of registers. of the Core-Local block to indicate 0 be ould register being modified is in the Core-Localregister e that the access stays in this cluster, and bysettingthe stays in this cluster, the e access that cate that the access stays in this cluster. Alsoset the stays in this cluster. the cate access that VP-Local GCR Redirect ock was being accessed by VP1, the value in this field would field in this value the accessed by VP1, beingwas ock ss 0x0018,ss indicating the transactionis intendedSoft- for core 1. l Processor (VP)in the Same Core” VP-Local GCR Redirect s Corresponding Anotherto Core” Processor (VP) in Same Core the // create VA from CGRBase VA // create only core0 and IOCU0 to enable value // set plus in t1 address to the base in t0 value // write of 0x120. offset // an al and Core-Other Registers in al er per VP. As such, there can be up to As such, there VP. per regist er of this is one instantiation There the CM to accomplish the following following tasks: the the accomplish CM to Core-Local registers, set the CLUS Core-Local registers, This is accomplished by setting the CL setting by accomplished is This k. The BLOCK_REDIRECT field supports 1, VP 0 wants to modify the reset exception base reset exception themodify to VP 0 wants 1, P). This is done using the register located at offset addre at offset register located re, the I6500 allows different register blocks wing one VP to access the a given co different another VP withinI6500 allows re, Core-LocalReset Exception Base Address register 0x0020.address located at offset Both of thes orlisd t1 t2, t1, 0x0001_0001 t0, (t1) 0x120 t0, Section5.5.1 “ProgrammingAnother Virtua Section 5.5.2Section GCR’ Local “Programming Section 5.5.3Section CM” the via CPC Local Registers the “Accessing Section5.5.4 “Powering Up theDebug Unit (DBU) viatheCM” Section5.5.5 “Settingthe ClockRatios Between theI6500 System Components” 5.5.7Section Core-Loc the “Accessing tion intendedis for 2. VP Software would thenwrite the modified valueto the Local GCR Redirect Local GCR Redirect register at offset 0x0018Local to GCR Redirect register0 to indi at offset BLOCK_REDIRECT25:24 to field in bits 0 to indicate should be redirectedthe access that toblockthe Core-Local registers. of allo addition to In within the same VP to be accessed. same the within Local GCR Redirect register at offset 0x0018Local to GCR Redirect register0 to indicat at offset of the 25:24 BLOCK_REDIRECT field in bits ware would ofalso program a value 2 intoVP_REDIRECTthe this example, the this Address The I6500 The MPS providesI6500 theability forgivento a core access Processor (V Virtual different This section describes how to program how describes This section • However, if a Global register block or Debug registerbl or Debug blockregisterGlobal a if However, bloc register appropriate reflect the block of VP2, so the value in the BLOCK_REDIRECT field w field value in the BLOCK_REDIRECT the VP2, so of block 0x0018 in the Core-Local register block. register Core-Local the in 0x0018 fourinregistersthesegiven(in a 4-VPa of core configuration).Bits13:8 (CORE_REDIRE be to VP indicate the (VP_REDIRECT) and bits 2:0 core to be accessed, the cate core. the same accessed inside is being core that example, assume For thistransaction,kernelwould software programvalue a of 1 into the CORE_REDIRECTfieldin bits 13:8the of When accessing another core or VP's or accessing another core When • • • • • accesses to be redirected to other blocks such as the Global such to to be redirected other blocks accesses Debug block wh block or clusters. Interface CM GCR Register 5.5.1 Programming Virtual Another MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 5.5 Examples Programming CM
register compan- register located e Core-Other block at block Core-Other e 0x1FBF_C020 0x1FBF_FFFF 0x1FBF_E000 0x1FBF_DFFF 0x1FBF_C000 0x1FBF_BFFF 0x1FBF_A018 0x1FBF_A000 0x1FBF_9FFF 0x1FBF_8000 0 0 I6500 Registers I6500 0x2 to program the GCR registers the GCR program to 8 78 2 3 VP-Local GCR Redirect VP Local RedirectVP Local vector location for core 1, VP 0 by 1, VP 0 for core vector location that core boot the other cores in the other cores in boot the that core re 1 writes the appropriate value into appropriate value into the writes 1 re 0x01 12 11 em Programmer’s Guide, Revision 1.00 1413 register located in th in located register RESET_BASE . This indicates. thatthe register to be programmed 31 31 first. Then core 0 is used Then first. field (bits 13:8)of the ddress of 0x1FBF_A018). This indicates that the register the register that This indicates 0x1FBF_A018). of ddress field (bits 2:0) of the Reset Exception Base
Core-Local Core-Other Debug Block Global Control VP_REDIRECT is instantiated on a per-VP basis, Co per-VP a is instantiated on VP-Local CORE_REDIRECT MIPS64® I6500Multiprocessing Syst core 0core would program the boot exception . gister programmingtothe gister example. Refer sequencefor this 1. Program the Program 1. Figure 5.6 2. Program the Program 2. field (bits 31:12) of the of 31:12) (bits field at offset 0x1FBF_A018. at offset at offset 0x1FBF_C020.at offset Exception Base register in Exception Core-Other address space Core-Other address space Figure 5.6 Figure VP 1, 2 Core of BEV_BASE GCR the 0 Accessing 1, VP Core the Core-Local address space RESET_BASE field of the field RESET_BASE Reset EXCBase of the VP Local Redirect register in the of offset 0x0020(physicaloffset address of 0x1FBF_C020). in its own Core-Local block at offset 0x0018 (physical a (physical 0x0018 at offset block Core-Local own its in the to be programmed correspondsto2 of core 1. VP correspondsto core 1. located at offset 0x0018 located(physicaloffset ofaddressat 0x1FBF_A018) This conceptis shown in 3. register Base Exception Reset the Since Ina multiprocessor system, it is commononecorefor boot to up first, thenhave The following steps show the re show the steps following The 2.the 0x2 to a value of writes 1 also Core system. In the following example, assume core 0 is booted up booted is core 0 assume example, In the following system. iondocument for more information onthis register. 1.1writes Core a 0x01value of to the in core 1. in This example examines how core CORE_REDIRECT and VP_REDIRECT fields 5.5.2 Corresponding to Another Core ProgrammingLocal GCR’s 92
93 reg- compan- register y of the other of the y register located register . VP-Local Redirect I6500 Registers I6500 Figure 5.7 regardless of the number of the number of regardless register in that core’s own register in that core’s Reset Exception Base Reset Exception VP-Local Redirect fault addressing andscheme , the numberof towritten the core be field (bits2:0) of the field as described in step 2 above. The actual as field concept is shown concept in is VP_Local Redirect . This indicates. thatthe register be programmedto . field (bits31:12) the of field (bits 13:8) of the of 13:8) (bits field cal 0x1FBF_C020).address of core Because setting0 is core, the write is donetheto Core-Otherblock. address des in the Core-Other block, Core-Other des in the VP_REDIRECT VP_REDIRECT field as described in step 1 above. Similarly, thenumber of field as described instep1above.Similarly, field in the the field in example uses the MIPS de the MIPS uses example , this means that when one core wants to access an access to wants core one when that means this , is written to. This re-Other block as described in step 3 above. 3 step described in re-Other block as Reset_Base programmedcorresponds toVP 1.0 of core Table 5.2 Table CORE_REDIRECT CORE_REDIRECT e registers associated with another core another with registers associated e weredup through CPC.the the If core has nottobeenpowered refer the up, CORE_REDIRECT CORE_REDIRECT gister programmingthe to gister example.Refer sequencefor this opriatevalue into the Accessing the CPC Local Registers via the CM CPC Local Registers Accessing the correspondsto core 1. located at offset 0x0018 located(physicaloffset ofaddressat 0x1FBF_A018) ister. This indicates that the register to to be register that the This indicates ister. the valueReset base foropposed1, as core toitsown located in the Core-Other 0x0020block(physi at offset 2. Inaddition, Core 0 also writes a value0x0 of to the 3.appr the 0 writes Core is programmed into that cores local local cores that into programmed is Whenever one core reads or writes to th core Whenever one register to be programmed is accessed via the Co via the is accessed be programmed register to in block one Core-Other only is there Since assumes that core 1 has already been po been has already core 1 assumes that sectionentitled setting its Reset Exception Base register. Notethat this setting Exceptionits Reset register. Base Core-Local space determines which core the which data Core-Local core space determines the VP to be written is programmed into that cores local cores that into programmed is VP to be written the cores in the system, the register to be accessed always resi accessed to be the register system, the in cores of the state The system. the in cores CM GCR Register Interface Register CM GCR show the re following steps The iondocument for more information onthis register. 1.the to of 0x01 a value 0 writes Core MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
register register located register ). This indicates Core-Local 0x1FBF_C020 0x1FBF_9FFF 0x1FBF_8000 0x1FBF_FFFF 0x1FBF_E000 0x1FBF_DFFF 0x1FBF_C000 0x1FBF_BFFF 0x1FBF_A018 0x1FBF_A000 0 0 0x0 uses the default addressing default the uses Reset Exception Base Reset Exception 8 78 2 3 thedestination as describedcore VP_Local Redirect field in its own power up core 1. This sequence is 1. core power up 0x01 12 11 em Programmer’s Guide, Revision 1.00 1413 bit of the bit of CORENUM RESET_BASE address space, or anywhere within the 4 GByte anywhere within or address space, 31 31 up. Note that thisexample ception Base Register of Core 1 Core of Register Base ception field (bits 13:8) of the 13:8) (bits field ProgrammingLocal GCR’s Correspondingto Another Core RESET_BASE_MODE Core-Local Core-Other Debug Block field used to indicate the number of field used in the GCRCore-Local address space. Global Control CORE_REDIRECT MIPS64® I6500Multiprocessing Syst Registers via the CM in the lower in 512 MBytes of the companion documentmore for information on this register. the programming of the of programming the CORE_REDIRECT bed inthe section entitled sequence for this example would be as follows: for sequence 0x1FBF_C020. I6500 Registers offset 0x1FBF_A018. offset register located at offset 0x0028 register locatedat offset Figure 5.7 Figure Ex Reset the Accessing 0 Core Core-Other address space at offset Core-Other address space Reset Base Exception register in the in its own 0x0018Core-Local block (physical at offset address of 0x1FBF_A018in Figure 5.5 thatthe register to be programmed correspondsto core 1. 1. Program the CORE_REDIRECT and 2. Program the RESET_BASE field of the the RESET_BASE field Program 2. address space, depending on depending space, address The reset vector can either be placed either be placed reset vector can The in #1canabove,determinea core its own core numberby reading the This the example showsCore Core-Local and Core-Other registers 0 uses to how different that the one descri different located in the Core-Other 0x0020.block at offset This bitcanbe set during device configuration andis normally not changed once it is set. Notethat in addition to the Identification above, which assumes that core 1 has already been powered has 1 that core above, which assumes CM GCR Register Interface CM GCR Register registerThe programming 1.the to 0x01 of a value writes 0 Core scheme. Refer to the scheme. Refer register in the Core-Local at address space VP_REDIRECTVP-Local Redirect fields the of 5.5.3 Accessing the CPC Local 94
95 . The ring The . 0x1BDE_4000 0x1FBF_C000 0x1FBF_BFFF 0x1FBF_A018 0x1FBF_A000 0x1FBF_9FFF 0x1FBF_8000 Table 5.1 Table 0 0 register located in the register 0x0 0x3 43 to indicate that Core-Other 8 78 2 3 field (bits13:8) ofthe 0x01 ). A value of 0x3 in this in 0x3 value of A 5.5). Figure 1413 g Unit by accessing the DBU copy of the copy DBU the by accessing Unit g Power to Core Up 1 CPC Local CommandCPC Local CORE_REDIRECT 63 63 e VP-Local Redirect register that this example uses the MIPS default addressing MIPS default the that this example uses field (bits 3:0) of the of 3:0) (bits field CM Core-Local CMD CM Global Control e CPC Core Local Register ug Unit (DBU) that usedis to perform debug and analysis onthe various er up the core in the indicated er up the CPC Core-Other Command . ion describes how to power up the Debu the how to power up describes ion bug Unit (DBU) via the CM 0x1FBF_A018. Figure 5.8 register. register. 0x1BDE_4000. and VP_REDIRECT fields of the VP-Local Redirect register in the Figure 5.8 Core 0 Using th Core-Local address space at address Core-Local address space CPC Core-Other block at offset 0x0000 (physical address of 0x1BDE_2000 in of 0x1BDE_2000 address (physical 0x0000 offset at block Core-Other CPC field indicates to the pow CPC to VP_Local Redirect This conceptis shown in The I6500 MPS contains a dedicated Deb dedicated MPS contains a The I6500 components in the system. This sect in the system. This components in described as or 0x23 35, of value IDring a has DBU The register. Command Core-Local CPC IDvalue of 35is used inCORE_REDIRECT the field of th 2.the into 0x3 of a value writes then 0 Core accesses should target the DBU copy of the register. Note the DBU copy of the register. should target accesses scheme. Interface CM GCR Register 1. Software 1. Software programs the CORE_REDIRECT CPC Local Command register in the Core-Other address space at access Core-Other address space 5.5.4 Powering Up the De 2. Software programs the CMD2. Software field of the MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
register located register ). This indicates 0x1BDE_4000 0x1FBF_A018 0x1FBF_A000 0x1FBF_C000 0x1FBF_BFFF 0x1FBF_9FFF 0x1FBF_8000 0 0 register located in the register 0x0 field(bits 13:8) of the 0x3 43 8 78 2 3 0x23 ). A value of 0x3 in this in 0x3 of value A 5.5). Figure VP-Local Redirect 1413 em Programmer’s Guide, Revision 1.00 CORE_REDIRECT . to theRefer I6500Registers companion CPC Local CommandCPC Local 63 63 to run at various clock frequencies relative to each other. various clock frequencies relative to each other. at run to field (bits 13:8) of the of 13:8) field (bits e DBUas described thein previoussubsections, the I6500 field (bits 3:0) of the of 3:0) field (bits CM Core-Local CPC Core-Local CMD CM Global Control tween the I6500 System Components CORE_REDIRECT MIPS64® I6500Multiprocessing Syst . ence for this example would be as this follows would be as example for ence llows these different elements different these llows Figure 5.9 register, which in thiscase theis DBU (0x23).register, at address 0x1FBF_A018. at address 0x1BDE_4000. CPC Core-Other address space CPC Local Command register in the Figure 5.9 Figure Unit Debug Power Up the to Register Core Other CPC 0 Using the Core CPC Core-Other block at offset 0x0000 (physical address of 0x1BDE_4000 in of 0x1BDE_4000 address (physical 0x0000 offset at block Core-Other CPC fieldindicatespowerup thecomponent to indicatedthe CPC to in the in its own 0x0018Core-Local block (physical at offset address of 0x1FBF_A018in Figure 5.5 GCR Redirect thatthe register to be programmed correspondsto the Debug Unit(DBU). and VP_REDIRECT field of the VP-Local Register in the Core-Local address space 2. Software programs2. Software the CMD field of the documentinformationfor more on this register. 1. the to of 0x23 0 writes a value Core Inaddition topowering upelements such as cores and th a System also Multiprocessing The registerThe programmingsequ This conceptis shown in 2.the into 0x3 of a value writes then 0 Core 1. Software 1. Software programs the CORE_REDIRECT 5.5.5 Setting the Clock Ratios Be 96
). ). 97 compan- Figure 5.5 Figure register located register ). This indicates is set, then then the clock set, is I6500 Registers I6500 is set, then the clock change clock change then the is set, VP-Local Redirect of the CPC register. Note that this that Note register. the CPC of CPC Local Clock Change Control ANGE_EN field 8) of (bit the CPC Local ClockChange field (bits 13:8) of the of 13:8) field (bits field (bits3:0) of the e clock domain to change rates when the clock change the clock when rates to change clock domain e offset 0x0018 (physical address of 0x1BDE_4018 in 0x1BDE_4018 address of (physical 0x0018 offset CLK_RATIO zero, then the clock change has completed. has change the clock zero, then register in the CPC address in space. the CPC The register 16, value IOCU a of 0 has ring ID CORE_REDIRECT ther accesses should target the IOCU copy copy the IOCU target should accesses ther by writing a value of 0x1 into the SET_CLK_RATIO field (bit 0x8) theof by writing valuea 0x1 of into the SET_CLK_RATIO If thefieldCLK_CHANGE_ACTIVE (bit10) . . The ring ID value of 0x10 is used in the CORE_REDIRECT field of the VP-Local of the field CORE_REDIRECT the in is used 0x10 of ID value The ring . register instep1to determinethat IOCU the0 is device tobe programmed with the gister programmingthe to gister example.Refer sequencefor this rmation on these registers. these rmation on Figure 5.10 Table 5.1 Table defaultaddressing. VP-Local Redirect CPC LocalClockChange Control in its own 0x0018Core-Local block (physical at offset address of 0x1FBF_A018in Figure 5.5 register located in the CPC Core-Other block at block Core-Other CPC the in located register associated clock ratio. Control register located in the CPC Core-Other0x0018 block(physicalatoffset of address 0x1BDE_4018 in Figure5.5).A valueof 0x1in this field enablesth sequence is started. GlobalCPC Clock Control register intheCPC 0x0028 Global (physical blockaddress at offset of 0x1BDE_0028). (bit 8) 0x0028(physicaloffset address of 0x1BDE_0028). If the field SET_CLK_RATIO thatthe clock ratio tobeprogrammed corresponds to IOCU 0. A valueof 0x3 in this field indicatesclock a ratio of 4:1 betweenthe prescaled clock IOCUand 0. Hardware the reads change sequence is still pending. sequence is still change sequence If bothis in process. fields are Redirect register to indicate that Core-O that to indicate register Redirect or 0x10 as described in as described 0x10 or This section describes how to set a 4:1 clock ratio between the core clock and IOCU 0 by writing to an IOCU 0 copy0 IOCU an to 0 by writing IOCU andclock between core the ratio clock 4:1 a howto set sectiondescribes This the of 3.0writes Core a value of 0x1 into CLK_RATIO_CH the 4.sequence the clock change Initiate 5. Poll for clockchanges complete by readingthe CPC Global Clock Controlregister in the CPC Global blockat 2.0 Core then writes a value of 0x3 intothe example uses the MIPS example uses Interface CM GCR Register show the re following steps The This conceptis shown in iondocument for more info 1.the to of 0x10 a value 0 writes Core MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
0x1BDE_4018 0x1FBF_C000 0x1FBF_BFFF 0x1FBF_A018 0x1FBF_A000 0x1FBF_9FFF 0x1FBF_8000 0 0 0x0 e target cluster, core, cluster, target e 0x3 43 8 78 2 3 een selected, the CLK_RATIO CLK_RATIO selected, the een 0x10 1413 e IOCU e Clock Ratio 0 em Programmer’s Guide, Revision 1.00 rnel software writes th software writes rnel 63 63 Register to Set th r theany of programmable clockdomains. For example, to ID 26. Once the device has b device 26. Once the ID ware must use the GCR_CL_REDIRECT register. There is one is There register. the GCR_CL_REDIRECT use must ware it. Then an access Then an access bit. the CLUSTER_REDIRECT_EN setting with CM Core-Local CU in the cluster. Theke CU inthecluster. CM Global Control ses the CM to drive the request to the NOC for transfer to the target cluster. target the transfer to for NOC the to request drive the to CM the ses MIPS64® I6500Multiprocessing Syst CPC Clock Change Control een the prescaled clock and all selected devices to a value between 1:1 and 1:8, value between 1:1 and devices to a selected clock and all the prescaled een , the I6500or CM allows a core IOCU in one cluster a to access software visible regis- Section5.1.6 address 0x1BDE_4018. space at offset 0x1FBF_A018. at offset space Figure 5.10 Figure Local CPC Core the Using 0 Core program the clock ratio for IOCU 1, simply substitute a value of 0x11 for 0x10 in the above example since IOCU 1 is 1 IOCU since example above the in 0x10 for 0x11 of a value substitute 1, simply IOCU for ratio clock the program to setthe mainmemo ryclock ratio,simply located ringbusID substitute 17. Similarly, at a value of 0x1Ain the at ring bus main memory is located since example above The above procedure can be used to set the clock ratio fo the clock to set be used above procedure can The field to set the ratiocan be used betw excepttheCM, whichlimited is toa clock ratio of 1:1or 1:2. GCR_CL_REDIRECT register per VP and IO and VP per register GCR_CL_REDIRECT As described in cluster. a different in ters the kernel soft cluster, remote a on register a access To VP, and target register block into this register, along register block into this register, and target VP, to the target device's Core-Other block cau device's target the to Infollowingthe example, 1 in Clustercore 1 reads theGlobalCause CMError in 2 to register Cluster thedetermine of an error. cause Redirect register in the VP-Local address and VP_REDIRECT fields of the VP-Local in the CPC Core-Other at address space 1. Software programs the CORE_REDIRECT1. Software 5.5.6 Cluster to Cluster Access the CPC Local Clock Change Control register 2. Software programs the CLK_RATIO field of programs the CLK_RATIO 2. Software 98
99 VP- compan- register is register to the other cluster. The other cluster. the to I6500 Registers I6500 register at offset 0x0008 registerat offset GIC Core-Other Core-Other GIC CAUSE register. The result The result register. CAUSE Global Controller Interrupt be used during boot-up and boot-up be used during ster in the Core-Other block at the Core-Other block ster in the Global Interrupt Con- Global the register located in its own Core- in its own register located either a coherent or non-coherent either a coherent pin. The state of this pin is reflected in reflected is this pin state of pin. The dicate that Cluster 2 is being accessed. 2 is Cluster dicate that register in step 1 to determine thatread should be 018. This indicates an access to Cluster 2. The value 2. The Cluster to access an indicates This 018. cluster 1, but rather a GCR register inside 1, cluster the CM. register. This register resides in the CM local register in the CM local This register resides register. VP-Local Redirect Redirect VP-Local ster basis. The setthat is instantiatedonper-VP a oherent mode should only oherent Core-Local Coherence Enable e register ring bus except the e register ring bus except sends the access through the NOC the through the access sends , and, devicesother non-core on the registerringbus. This and reads its local GCR_ERR_ reads and Coherence Enable Coherence 6500companion Registers documerelease. in the nt included 25:24 set is to 0x1toindicate that a register in the CM GlobalRegis- VP-Local Redirect VP-Local d Core-Other Registers in Core-Other d d in bits 21:16 is set to 0x02 to in d , Core-Local, and Core-Other registers of the CM have been used to modify to used been CM have of the registers Core-Other and Core-Local, , ws each power domain to be placed in be to each power domain ws gister programmingtothe gister example. Refer sequencefor this not execute any cacheable memory accesses (instruction fetch or load/store) while ng normal operation. The non-c register is used to select the target VP copy of the register to access when a VP copy of the register to access when a target the to select register is used use of the CLUSTER_REDIRECTuse of the field. ter Block of the destination cluster is to be accessed. destination the Block of ter example as the access is not to a specific core of VP not of core access to a specific of is the example as routed to cluster 2. Based on this information, the CM 2. Based on this cluster to routed CM in the destination cluster decodes the information decodes the cluster the destination in CM is then returned through the NOCtothein1. CM cluster offset address 0x0048.the reads offset Hardware writtento this is registerbrokendown follows: as • Settingthis bitenables The CLUSTER_REDIRECT_EN bit31isset to enable request cluster. toanothera •BLOCK_REDIRECT Thefield in bits •fiel The CLUSTER_REDIRECT Local block at offset 0x0018 (physical address of 0x1FBF_A address of (physical 0x0018 offset at block Local • The field inCORE_REDIRECT bits 13:8 VP_REDIRECT field in bits2:0 notare programmedin this bit 11 (COH_EN) of the Core-Local Status and Configuration(COH_EN) the of Core-Local Status bit11 address 0x0008.per power domain.registers There is one of blockthese at offset For morerefer to the informationI onthis register, in the Core-Local register block. in the Interface CM GCR Register external the asserts is enabled when hardware Coherency parameters in other cores, other VP’s withinthe samecore cores,VP’s parametersotherotherin allo System Multiprocessing The I6500 mode.Because theI6500implements directory-based a coherence MIPS protocol,recommends that each domainbe duri mode in coherent placed Software should power-down. In the previous subsections, the VP-Local subsections, previous the In programmingmechanism is applicable for all devices onth The following steps show the re show the steps following The 2. regi (GCR_ERR_CAUSE) Cause then reads the value in the GCR Error 1 Core coherence is disabled.coherence is CM,the the is either enabled or coherency using disabled In iondocument for more information onthe registers in thisdiscussed example. 1.1 writes Core a 0x0000_0000_8102_0000value of tothe own Core-Local and Core-Otherregi (GIC). The GIC has it’s read or written. For more information, refer to the GlobalInterrupt Controllerof (GIC) chapter thismanual. Local Redirect Local troller 5.5.7the Core-Local an Accessing MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 5.6 Enable Coherency
e L2 Prefetch Control regis- L2 Prefetch Control e ere then are 8 cores,there em Programmer’s Guide, Revision 1.00 emisdetermined bythe user duringIP bit of this field corresponds to a single port. There a single to corresponds field of this bit cher used to enhance The L2 L2 performance. to enhance used cher L2 prefetching is monitored prefetching is set,L2 is givenbit a If etc. ’s, 300 inthe GCR Global This read-onlyregister space. t ID. If the bit is set, the corresponding CM port is mon- is CM port set, the corresponding is bit If the ID. t e NPFT field (bits 7:0) of th of 7:0) (bits field NPFT e or eight. if th For example, or itiated, the caches must be to itiated, the power state is in the caches must ange greater than0in order for this bitto have meaning. ching. These ports correspond to the (up to) six cores and (up to) six (up the to correspond These ports ching. determine thenumber implemented. units of prefetch . L2 prefetching can be selected for some of alloffor these ports usingbe selected the8-bit prefetching can . L2 MIPS64® I6500Multiprocessing Syst PS contains an L2 prefet contains PS // an offset of 0x2008 to access the Coherence Enable Coherence the to access of 0x2008 offset // an // register. , L2 prefetching does not occur. occur. does not L2 prefetching , Figure 5.1 implemented inthe MultiprocessingI6500 Syst li t1, CPC_BASE_ADDR t1, CPC_BASE_ADDR li t0, 0x0000_0001 li t1 into value CPCBase // move (t1) t0, 0x2008 sd coherence Enable // plus in t1 base address to the in t0 value write // itored for prefetching. The CM allows up to 8 ports to be selected for L2 prefet for to be selected to 8 ports up CM allows The The number of prefetch units number of The configuration.Thisvalue is programmed hardware into byth as shownin to) eightIOCU’s Each register. GCR_L2_PFT_CONTROL_B in the field PORT_ID uptothe maximum can be any numberof cores and IOCU’s IOCU4 and cores or 4 total8, or make a to IOCU’s 0 bemust cleared is the bit port. If for that field allows kernel software a convenient way to software a convenient kernel field allows The coherence manager in the I6500 M the I6500 coherence manager in The ter (GCR_L2_PFT_CONTROL) located at offset address 0x0 (GCR_L2_PFT_CONTROL)ter offset located at Interface CM GCR Register Note Prefetching thatthe is numberenabled of by setting thePFTEN bit in the GCR_L2_PFT_CONTROL register. prefetchunits implementedas described abovemust be Note that if a power domain is in coherent mode and a ch mode and a coherent is in a power domain that if Note flushedto prior disabling coherence mode. Example Enable Code Coherency enable prefetcher managedis using two GCRCM registers. • L2 PrefetchControl (GCR_L2_PFT_CONTROL) register0x0300 at offset • L2 Prefetch2nd Controlregister (GCR_L2_PFT_CONTROL_B) 0x0308 at offset the followingregisters control These L2capabilities: • Minimum operating systempagesize (supports - 64K4K in pages multiples of two) •Prefetch • Coherentinvalidate requests •enable prefetch Code • por a CM tocorresponds bit ID. Each port prefetching L2 5.7.2 for L2 Prefetching Select Ports 5.7.1 Prefetch Enable 100 5.7 L2 Cache Prefetch
101 reg- Global Custom Base . Code prefetching is enabled by setting by enabled is prefetchingCode . register at offset address 0x0068 in GCR Global address GCR Global in address 0x0068 at offset register ck register (GCR_SEM) at offset 0x0640 atin offset the ckregister (GCR_SEM) I6500 written in step #1, then a semaphore has been acquired, else acquired, has been a semaphore then #1, step in written register located at offset 0x0068.customIf register a locatedat offset block is imple- = 0 or if the SEM_LOCK bit is currently 0. is if bit the SEM_LOCK = 0 or tionin the systemis selectedduring IP Configuration.this If option is designer to implement a 64 KB block of custom registers that can be used be can that registers custom of block KB a 64 implement to designer allows prefetching of the code stream prefetching of the code allows Global Custom Status GCR block is connected to the CM. connected to GCR block is Global Custom Status (GCR_SEM) addressregister 0x0640. locatedatoffset go tostep #1. space. This bit indicates that a custom that a indicates space. This bit Interface CM GCR Register the registers: of custom the implementation handle to registers two global CM provides The The CM provides the ability for the system for the ability the provides CM The the CEN bit in the GCR_L2_PFT_CONTROL_B register. the CEN bitin GCR_L2_PFT_CONTROL_Bthe register. Interface CM GCR Register acquire the semaphore: To 1. thisregister with bit 31 Write = 1 and thelowerbits withthe VPID.threads 2. Read register. the 3.same as the value as the is #2 in step read value the If and then instantiated into the defined designer by the system to are control system registers level functions. These design. a custom GCR implementa existence of The bit is set in the GGU_EX the selected, A writeA to registerwith this writedata bit 31 1 is inhibited = if theSEM_LOCK bit is alreadywriteto1. A this regis- the data has bit 31 write if proceeds normally ter companion document. Registers The I6500 The CM providesI6500 a mechanism for managing uncachedsemaphores. mechanismThis is managed bythe GlobalCM Semaphore semaphore: the release To 1. theregister withbit 31= 0. Write For more information, refer to the CM GCR SemaphoreLo In addition to data prefetching, the CM prefetching,addition In to data The field is organized as cores followed by IOCU’s starting bitfrom So in a 4-core0. 2-IOCUand system, 0 - 3 bits followed cores as byfieldIOCU’s isorganized The 5ofBits4- the field would representIOCU 0 - 1 respectively. thefieldwouldof represent 0 - 3 respectively. cores Bits 6 - 7 would not thisbe used in example. ister at offset 0x0060, and the at offset ister 5.7.3 Enabling Code Prefetch MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 5.9GCR Implementation Custom 5.8 Management Uncached Semaphore CM
bit. If Global CM tected, infor- tected, bit becomes and GGU_EX this registerto deter- this RO case, the second case, error the GGU_EN R/W Global CM Error Cause Global CM an error is de an Access Access . The only. exception is if second error, only the error second error, connected to the CM, then the to the CM, then connected 0 GGU_EN bit GGU_EN GGU_EN bit GGU_EN 1/0 State State Enable/disable custom GCR region. address Bit has no meaning. has Bit em Programmer’s Guide, Revision 1.00 the type of error. For more information, refer refer more information, For the type of error. CM GCR CM CM GCR CM , kernel software can read kernel software , Global CM Error Cause RegisterError CauseGlobal CM RO RO Access Access this bit depends on the state of the bit depends this CM Error Multiple Register CM Error re andresoftwareerrors. When register. Note thatfor the register. 1 0 GGU_EX bit GGU_EX GGU_EX bit GGU_EX dicating that a custom GCR is GCR is custom a that dicating State State Signal and the GGU_EX and GGU_EN Bits at Reset at Bits GGU_EX and GGU_EN the and Signal . When. this field is written,also hardware updates the 58-bit manual. eld. When an error occurs an error When eld. this bit is set, in this . MIPS64® I6500Multiprocessing Syst Table 5.4 Global CM Error Cause Global CM on where the registers will reside must be enabled by setting the GGU_EN bit inbit the GGU_EN by setting enabled be must reside registerswillthe where on Logic 1 Logic 0 Logic ng custom GCR is connected to the CM, that no then the No custom GCR block. Figure 5.11 associated error address. error associated register. Note that the accessibility of that the Note register. register. Notethat field doestheCUSTOM_BASE not default a have addressand base this register. Custom GCR block present. hardware updatesthe read-only ERR_TYPE field (bits 63:58)of the . The encoding of these registers is determined by The encoding of these registers . I6500 Technical Reference I6500 Technical GU_Present GU_Present bit becomes R/W and is accessibleby kernel software. and is R/W bit becomes cleared (zero), indicati is (Hardwired to 0) Global Custom Base Global Custom Global Custom Base Global Custom Block CM GCR Register Interface CM GCR Register an error occurs, When mationthat maybe useful in debugging theerrorcaptured is in the This conceptis described in to the in registers the RO and is not accessible by the kernel. If not accessible by the kernel. is and RO field is undefined at reset. Therefore, it is programmer’s responsibility to program the base address into this field dur- fieldthis into address responsibility programmer’s program the base to Therefore,is it reset. at undefinedis field ingboot time a custom if GCR block is implemented. regi address selected the addition, In the The CM detects, reports, and handles several types of hardwa of types several handles and reports, CM detects, The GGU_EX GGU_EN Error Address Register mented, the startingin address ofmemory the 64KBblock is determined usingfieldin the 16-bit CUSTOM_BASE the overwrites the first error stored inthe register with theone of values listed in of this fieldERROR_INFO Theorganization variesfield thatprovides additional information about the error. fi the ERR_TYPE in the value on depending type is captured, not the the not captured, is type mine the typeof error andtakethe appropriate actions. a detected,seconderror If is it is captured in bits63:58 of the In this an L2 RAM correctable error (MP_CORRECTABLE_ECC_ERR). was the first error Custom GCR Custom Figure 5.11 Figure CM_Present the Between Relationship 102 5.10 Error Processing
103 = 1 = = 1 = = 1 = = 1 = = 1 = 1 = 1 = 1 = 1 = 1 =
error in more detail and GCR_ERROR_CAUSE. fields can be cleared by be cleared can fields ription type of each error and . tothe rated theif correspondingbit for that Signal Interrupt if Interrupt if Signal CM_ERROR_MASK[11] Signal Interrupt if Interrupt if Signal CM_ERROR_MASK[10] The error is corrected is error The if an interrupt Signal CM_ERROR_MASK[1] if an interrupt Signal CM_ERROR_MASK[3] Signal an interrupt if if an interrupt Signal CM_ERROR_MASK[4] Signal an interrupt if if an interrupt Signal CM_ERROR_MASK[5] Signal an interrupt if if an interrupt Signal CM_ERROR_MASK[6] CM_ERROR_MASK[7] Signal an interrupt if if an interrupt Signal CM_ERROR_MASK[8] Signal an interrupt if if an interrupt Signal CM_ERROR_MASK[9] Respond with an error to the original the to error with an Respond requestor. if an interrupt Signal = 1 CM_ERROR_MASK[2] interruptis generated in additionto the normal then an ERROR response is returnedof regardless the located at offset address 0x0040 address located (physicalat offset address type. For a detailed desc error GCR_ERROR_MULT.ERR_TYPE I6500 Technical Reference Manual Reference I6500Technical GCR_ERROR_CAUSE.ERR_TYPE is loaded, an interruptmay be gene An error occurred during an AXI An occurred error during request. An error occurred on the Register Register the occurred An on error a register access. Bus Ring during A occurred correctable ECC error during an L2 cache access. ECC error An uncorrectable access. an L2 cache during occurred A parity error was detected in the L2 L2 the in detected was error parity A the of core coming from either data the memory. If an L2 fetch and (FNL) lock an L2 fetch and If when only one processed is cacheop zeroor waysof the cacheare including unlocked, pseudo-locks, fails. FNL the then A decoding error was detected dur- detected was error A decoding BIU. a request on the ing The BIUdetected a parityerror. Signalan interrupt if The BIU detected a response error error detected a response The BIU the was on AXI bus. detected A decoding error was detected in the error was detected in the decoding A request. field theand Table 5.4 Table Types Error CM ERR_INFO field for each ERR_TYPE . Global CM Error Mask Register setting. Themask setting controls whetheran ECC_ERR MP_FNL_ERR DECODE_ERR RBI_BUS_ERR MP_PARITY_ERR CMBIU_WID_ERR CMBIU_REQUEST_ register. register. IOC_REQUEST_ERR CMBIU_PARITY_ERR Global CM ErrorCM Global Cause Register CMBIU_AXI_RESP_ERR MP_UNCORRECTABLE_ lists the errors detected by the CM. The following subsections describe each type of The following subsections CM. the by detected the errors lists MP_REQUEST_DECODE_ERR MP_CORRECTABLE_ECC_ERR GCR_ERROR_CAUSE the encoding of the each error encoding code field, refer to the 0x1FBF_8040). Notethat in theCM, response error the is independentof the masksetting, from thewhichpreviousdifferent is gen- eration theCM2. If normalresponse should ERROR,be an eitherreset or bya writing thecurrent value of error response. error 5.4 Table provides the encoding of of the the encoding provides When the When Error Mask Error Register The ERR_TYPE typeof error is set in the 0-Reserved- 1 4 5 6 7 8 9 2 3 11 10 TYPE Error Name Description Action ERROR MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
Global = 1 = = 1 = = 1 = = 1 = allowed to write allowed CM Control Global that bit 13 of this reg- ed in the design. This field is This field design. the ed in om that IOCU are IOCU that om em Programmer’s Guide, Revision 1.00 O_REQ_LIMIT) at offset 0x6F8.O_REQ_LIMIT) at offset Signal Interrupt if Interrupt if Signal CM_ERROR_MASK[15] Signal Interrupt if Interrupt if Signal CM_ERROR_MASK[14] CM_ERROR_MASK[13] CM_ERROR_MASK[13] CM_ERROR_MASK[12] CM_ERROR_MASK[12] ng cache coherency between the CM and CM the cache coherency between ng , the number of MMIO address regions is regions address of MMIO number the , 0 space. in CM GCR address Each bit rnal PCIe devices. The MMIO registers devices. rnal PCIe ng limit is reached. Note ng limit register (GCR_CONFIG) located at offset register (GCR_CONFIG) located at offset If GCR address space. thisbit is set, IOCU e error.e Interrupt if Signal error. Interrupt if Signal (continued) of uncached requests inorder to avoid potentialdead- to fourEachMMIO regions. region is assignedan upper directly programmable. However, the IOCU can be indi- directly programmable. However, was received by received was GlobalConfig hed by programming the by programming is accomplished This tanding. cates the number of IOCUsinstantiat the number cates the corresponding bit is set, accesses fr accesses set, is bit the corresponding An illegal request the REGTC. The main pipeline received erroran half-pipe. from the The detectedIOCU a parity IOCU detected a respons The 0x0010 in CM GCR address space. GCR address in CM 0x0010 Request Limit register (GCR_MMI register Limit Request MIPS64® I6500Multiprocessing Syst used withcommunicating withexte I/O Coherency Units (IOCU) for managi for (IOCU) Units Coherency I/O Verifying Overall System Configuration System Overall Verifying register (GCR_ACCESS) at offset 0x012 register (GCR_ACCESS)at offset Table 5.4 Table Types Error CM register (GCR_CONTROL) at offset 0x0010 in CM register (GCR_CONTROL)at offset IOC_RESP_ERR HALF_PIPE_ERR IOC_PARITY_ERR RBI_REGTC_REQ_ERR register (GCR_CONTROL) at offset Control CM 0x0000 of CM GCR address space and indi space GCR address of CM 0x0000 filled byhardware duringIP configuration. accesses to MMIO regions are blocked once the MMIO outstandi to MMIO accesses must ister be 0 for this bit to have meaningas described above. Privilege CSR Access Global corresponds to one of eight IOCUs. If IOCUs. eight to one of corresponds registers. (CPC) Controller Power and Cluster the GCR • IOCU requests toexternal devices are counted toward theoutstanding requestlimit when bit the12 of •of the 13 the bit by setting regions to MMIO issued being from are prevented requests IOCU •23:16 of the bits programming by the CM GCR registers access to allowed can select which IOCUs are Software determinedat IP configuration time.Thesupports I6500 up and lower bound.address intended to be are MMIOThe regions allowcounting for of number of non-speculative code fetches Software can setthe numberof MMIO requests that can be in-flight at any given timeby programming the MMIO MMIO_REQ_LIMIT of the field lock condition by having too many requests outs many requests having too condition by lock As described in the section entitled section in the described As MMIO_REQ_LIMIT field. MMIO_REQ_LIMIT field. The I6500 CM contains up to eight up contains CM I6500 The external devices. The IOCUis a hardware block and is not rectly the followingcontrolled using register fields: •of the The read-onlyNUMIOCU field in bits11:8 15 14 13 12 TYPE Error Name Description Action 5.12.1 CM GPR Register Interface ERROR 104 5.12 MMIO Address Regions 5.11 IOCU Interface
105 MIT. When this bit is bit this When MIT. ound MMIO region reg- MMIO region ound be set to indicatethat allow for forward progress). allow for standing MMIO request is per- MMIO standing fined by the MMIO_REQ_LIMIT by fined ed to reside in to reside determined is request a in the following in equation: the See section 5.13. 5.13. See section comparison above is further qualifiedby whether e if e the request falls into Region.an MMIO The Q_LIMIT) register at offset 0x06F8 inGCRaddress atoffset Q_LIMIT) register Boundregister wheredetermines the request will be Lower Bound can Register feature, allowing any amount of outstanding requests to requests outstanding of any amount allowing feature, by the CM, which can be useful to avoid deadlock when avoid to useful be the CM, which can by s willconsidered be eligible tohit the MMIO region. If requests. The limit is de is limit requests. The CCA= UCA. MMIO_CCA If 0x3,then the request= is part of the MMIO limit (to part ither UCAUC or requests can match the MMIO region. ledor disabled by programmingthe MMIO_EN bit that used todetermine whethertherequest is to an MMIO region CM_MMIO_IOCU_ENABLE_REQ_LI an Auxiliary interface. 0x01, thentheaddress CCA are used to determin CCA registerregions, address thenthe lowest-numbered enabled MMIO regionhit r each MMIO region, with each register containing a 32-bit address bound value. bound address a 32-bit containingregister eachwith MMIO region, each r which MMIO region the request matches. Once matches. MMIO region the request which nge of each MMIO region is defined using the Upper and Lower B Upper and the using region is defined MMIO of each nge Each of MMIO Each the four regions listed above can be enab resides in the Lower Bound register for each MMIO region (GCR_MMIO[0-3]_BOTTOM). If region is the MMIO the for each MMIO Lower Bound register region in (GCR_MMIO[0-3]_BOTTOM). resides then the request address and enabled, In addition, the address ra addition, the In qualified by CCA = UC or CC = UCA. words, In other e anaddressIf hits in multipleMMIO determining for precedence takes isters. A pair of registers are used fo are pair of registers A isters. at: located registers are These •bound Lower of 0x0700 MMIOregion 0 (GCR_MMIO0_BOTTOM) at offset •0x0708 Upper bound MMIO at offset regionof 0 (GCR_MMIO0_TOP) •bound Lower of 0x0710 MMIOregion 1 (GCR_MMIO1_BOTTOM) at offset •0x0718 Upper bound MMIO at offset regionof 1 (GCR_MMIO1_TOP) •bound Lower of 0x0720 MMIOregion 2 (GCR_MMIO2_BOTTOM) at offset •0x0728 Upper bound MMIO at offset regionof 2 (GCR_MMIO2_TOP) •bound Lower of 0x0730 MMIOregion 3 (GCR_MMIO3_BOTTOM) at offset •0x0738 Upper bound MMIO at offset regionof 3 (GCR_MMIO3_TOP) shown region as a MMIO to is access to determine if the used is decoded address MMIO_BOTTOM_ADDR[47:16]phys_address[47:16] <= MMIO_TOP_ADDR[47:16] <= bitsIf 47:16physicalthe of address fallbetween thevalue in MMIO_BOTTOM_ADDR[47:16] and MMIO_TOP_ADDR[47:16],the correspondingthen theaccess is to MMIO region. MMIO_CCAIf is set0x0,to thejust is request address the requestCCA has UC. = In otheronly words, UCrequest MMIO_CCAis set to 0x2, then the requestis qualified by as shown above. shown If MMIO_CCAset above. to as is space. Once the limit is reached, the CM stops serializing uncached and code fetches until a response to limit is reached, the CMa an MMIO response the uncachedserializing until space. and Once stops code fetches out field indicates one received. value For example, a of 0x01 in this been request has field in bits7:0the of MMIO Request Limit(GCR_MMIO_RE routed. Options routed. are the main memory port or coherent incoming also service that bridges PCIe accessing an MMIO region, that region MMIO_PORT field in the Lower an MMIOthatregion, region MMIO_PORT MMIO requests issued of the total number limit can user The requeststo the particular MMIOregion should not be limited. By default, IOCUconsidered requests are never uncached the GCR_CONTROL. via this is controllable However, mitted. Setting this value to 0x00 disables the MMIO limiting MMIO the disables 0x00 to value this Setting mitted. occur. The MMIO_DISABLE_REQ_LIMIT bit in the region's occur. 5.12.2Region Control MMIO MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
ternally from outside the ternally . cluster supportscluster up to four AUX port 0 AUX port 1 AUX port 2 AUX port 3 AUX Main memory Main Port Accessed Table 5.5 ere are up to 4 MMIO MMIO regions. Each 4 ere are up to em Programmer’s Guide, Revision 1.00 (GCR_CONFIG) at offset 0x0000 (GCR_CONFIG) in GCR atoffset the cluster or provided ex the cluster Values of 32, 64, 128, 256 and 512 are supported. The supported. are 512 and 256 64, 128, 32, of Values 0x0 0x8 0x9 0xB 0xA provided clock is assumed to be asynchronous to the clus- to be asynchronous toassumed is clock provided ndependentclock ratio.An externally provided clockcan s instructionor SRAM. Each MMIO requests. In this case, IOCU uncached requests are requests uncached case, IOCU this In requests. MMIO MMIO_PORT Field MMIO_PORT AUXwidthaddress 48 is bits. Thenumber AUX of is ports called buses, AXI4 AUX0- AUX3. The AUX master ports are rnal clock is done during IP configuration. configuration. IP during is done clock rnal to. This field is encoded as shown in as field is encoded to. This GlobalConfiguration register the MMIO GCR control registers. Th registers. MMIO GCR control the MIPS64® I6500Multiprocessing Syst be provided internally by internally be provided 5:2 Table 5.5 Table of Encoding Field Name Register Bits Encoding MMIO_PORT cluster. Each internally provided AUX clock can have have clock an i Each internally provided AUX can cluster. externally An pin.clock theAUXonexternal provided be Selectionbetween an internalversus exte ter. AUX ports are memory mapped by The field bitsin 5:2 thatindicates which listedregisterGCR_MMIO
107 to individual elements in ous clock domains that can clock ous em power-up policy, program- policy, em power-up ers are instantiated on a per-domain on a per-domain instantiated are ers . . is is true for each power domain domain and power each is true for is Clock Domains a low-power state. The vari Power Domains the CPC to control the power power the control to CPC the manage power consumption in the device. In addition, a In addition, device. the in consumption power manage k frequency to the individualfrequencytheclock to the CPC to control the d in theI6500Multiprocessing System andidentifies the handled bythePower Cluster Controller(CPC).The wer andwer clocking throughout the device. Using registers, andexternal signal delayseasily to programmer help the Manager (CM). The various power domains that can be be can that domains power various The (CM). Manager nce Manager (CM), and memory. In addition to clock man- clock to addition In (CM), and memory. Manager nce s are instantiated for each for instantiated are Registers System. Multiprocessing access of CPC registers, syst CPC registers, of access s in order to reduce overall power consumption. the I6500 MultiprocessingSystem,theCPC also providesthe ability to mains in the I6500 in mains dually controlled by kernel software. Th by kernel dually controlled the power and managementclock schemes implemented in the I6500Multipro- shows the various power do shows the various power elements in the system such as cores, IOCU’s, Cohere IOCU’s, cores, as in the system such elements individually controlled are defined inthe sectionentitled in agement for the various devices into and put the caches the clock ratios in memory, change the system such as cores, IOCU’s, and the Coherence and the IOCU’s, as cores, such the system be individually controlled are defined inthesection entitled Figure 6.1 Figure power domain toallow for individual control. Note that in thisfigure,core 1 throughcore n are optionalblocks dependingon the systemconfiguration. This section provides an overview of provides an This section basis so that the domain can be indivi that the domain basis so each clock domain. • For powerthe domains, kernel softwareinregisters uses •registersusesin software the clock domains, Forkernel cessing System. The CPC implements two types of domains; power and clock. In each case, regist case, In each clock. power and domains; of types two CPC implements The Power management intheI6500 Multiprocessing Systemis I6500 CPC uses theconceptdomains of to manage bothpo domain these or disable the can enable programmer This chapter provides an overviewof how power is manage onhowtoset procedure the CPCinmemory base address provided.Otheris programming principles includesetting requestor non-coherent mode, to coherent or the device ming examplesa clockdomainof change andclock delaychange,powering upCPCthe instandalone mode (no local RAM shutdownand wakeupprocedure,mechanism, enabled), reset detection, VP run/suspend accessingcores internal tuning fine and domain, power another in registers various power and clock domains the programmer can use to can use programmer the and clock domains power various environment. system the device into a integrate 6.1.1 Power Domains MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 6.1 Overview Power Management Power Chapter 6 Chapter
its 3:0) of the its Memory Memory ClockDomain Registers companion docu- AUX3 AUX3 Clock Domain e, if there are two cores, there can- cores, two there are if e, ng the CMD field (b the ng I6500 CM3.5 CM3.5 em Programmer’s Guide, Revision 1.00 ClockDomain ocal registers that can be used to indepen- used to can be registers that ocal Core 5 Core Core n Core ght. So for exampl ght. Power Domain AUX0 AUX0 Core 5 Core Core 5 Core Clock Domain Clock ClockDomain there cannot be more than four IOCUs, etc. than four IOCUs, more there cannot be following four power states by programmi four power states following MIPS64® I6500Multiprocessing Syst IOCU7 IOCU7 there are four cores, there DBU Core 1 Core Core 1 Core the CPCregister interface. ClockDomain Debug Unit Power Domain Power Domain , except the CM, contains its own set of Core-L its contains except the CM, , Core 1 Core Core 1 Core Register. For more referinformation tothe on this register, Register. Clock Domain Clock Figure 6.2 Figure System Multiprocessing I6500 Domains in the Clock Figure 6.1 Figure System Multiprocessing I6500 in the Domains Power Figure 6.1 showsthe maximum possible number of cores and IOCUsthat can be instantiatedinto the I6500 MPS. showsthe various clock domainsin the I6500 MultiprocessingSystem.Each clock domain showncanbe CM3 CM3 Core 0 Core Core 0 Core Power Domain Power Domain Power Core 0 Core IOCU0 Core 0 Core dently place each device into one of the dently place each Each device in Each CPC LocalCommand Figure6.2 However, the total number of cores and IOCUs cannot exceed ei exceed cannot IOCUs and total number of cores the However, notbe morethan six IOCUs. If Figure6.2 individually using controlled ment included in the release. the ment included in IOCU0 ClockDomain ClockDomain 6.1.4 Overview of Power States 6.1.3 Coreand IOCU Selection 6.1.2 ClockDomains 108
109 Clock- ions thisin document . a previous command has command previous a executed in coherent mode, executed in state. A domain in the A domain state. programmed into the4-bit . state of the domain. state of the a previous command has has com- previous command a . Refer to the section entitled the section Refer to . programmedintothe4-bit CMD . However, the previous steady state state steady the previous . However, ClockOff ers address space. The CPC location CPC location address The space. ers PwrDown command enables power for the domain, enables power for command settings. If the domain was active before andbefore wasdomainactive If the settings. ClockOff register. All address locat All register. PwrUp Enabling CoherentMode state when a valueof 0x2 is programmed into the 4- command to the CPC before CPC commandtheto to an operational steady to state when a value of 0x1 is programmed into the 4-bit the into is programmed 0x1 a value of when state command. ent mode. If a is command If mode. ent the has transitioneddevice fromcoherent modeto non- state when a value of 0x3 is when a state to the CPC before command state when a value of 0x4 is PwrDown ClockOff register. This command uses setup values in the in values uses setup This command register. PwrDown PwrUp GCR_CPC_BASE Reset register. This command uses setup values in the values in the setup command uses This register. register. If the domainwas powered down before, the power-on register. ClkOff et to be et redirected towards to the newly programmed state is reached the newly programmed et to be redirected towards towards be redirected et to register. This commandallows a domain inthe non-coherent operation to register. CPC_CL_STAT_CONF_REG the global, core-local, and core-oth global, core-local, the register. register. Theexecution of thiscommand depends on the previousdomain register. in a the powered-down state, er Register Address Map informationfor more on enablinganddisabling coherence mode. to operation usingthe PwrUp operation. Sending a Sending operation. CPC_CL_CMD_REG CPC_CL_CMD_REG CPC_CL_CMD_REG CPC_CL_CMD_REG command giventodomain a in coherent operation remains inactive until thedeviceleft has the . domainA power is broughtinto - a power domain is brought into is brought domain - a power - A powerdomain- A is broughtinto - A power domain- A power broughtis into state can be sent in state can be ClockOff command given to a domain in coherent operation will remain inactive until the device has left device the untilinactive remain will operation coherent in a domain to given command PwrDown CMD fieldthe of field theof ClockOff sequence is applied according to according applied is sequence CPC_CL_STAT_CONF_REG CPC_CL_STAT_CONF_REG was innon-coherentwas operation, the power domain broughtis into the the coherentmodeof the A the CPC domain targ causes completed CMD fieldthe of domain is If the power state. appliesthe clocks and reset, and bringsthedomain into an operational state. Reset PwrUp be sentreset. It also can be mode.Theto a domainor domainclock-off inpower-down willthen become leads active, and a reset sequence is executed which Off A coherent modeoperation. of Sendinga CPC domain targ the pleted causes can be observed temporarily before Enabling CoherentMode PwrDown bitCMD field of the • • • • The states are as follows: states are as The This sectiondescribes thesome of programming functions thatcanbe performed via the CPC registers. within memory locations CPC uses The withintheCPU mapaddress is determined by the the command is queued, but not processed by the CPC until by the CPC not processed queued, but the command is entitled to the section refer For more information, coherent mode. Note that each command can in non-coher only be executed that each command Note are relative to this base address. this are base relative to 6.2.1 Cluster Power Controll MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 6.2 CPC Register Programming
for more informa- more for core. Contains core. regis- Contains gister andgister store it ning system to the global to the Cluster Power Control- the Cluster to a set of registers that is single Figure 6.3 em Programmer’s Guide, Revision 1.00 Description window into another Core. into window . Aliased for each I6500 core. This block of block of This core. I6500 each for . Aliased . for each I6500 Aliased section contains section load/stores. In addition, the block offsets shown offsets block the addition, load/stores. In . Contains registers pertai // Locate CPC Locate // GCR_CPC_BASE // the system and writes that the system and writes is storedin bits 47:15the of Cluster Power Controller Control Block Control Control Block Control
, bit, 0 is set, toenablethe region for the address CPC.
register located in the CM3. Refer to the located CM3. in register visible to all CPUs. visible Global Control Block Control Global address This functionality. Core-Local ters pertaining to thecore issuing request. core the Each has its own copy registers within this of block. Core-Other addresses giveseach Core a theCPC registers resideon a 32KB boundary. located at offset 0x0088addrin CM located ess at offset space. The remaining bits (14:0) MIPS64® I6500Multiprocessing Syst . later use in r30_cpc_addr using the KSEG1 equivalent address, and is now done now is and address, equivalent the KSEG1 using r30_cpc_addr in use later 8 KB 8 KB 8 KB GCR_CPC_Base Size (bytes) Figure 6.3 Table 6.1 Table GCR_CPC_BASE[31:15]) to (Relative Map Address CPC in the GCR_CPC_BASE re read the in value the GCR_CPC_BASE used to code example is init_cpc , all registers are accessed using 32-bit aligned uncached aligned 32-bit using accessed are registers all , // copy to register CPC_BASE_ADDR li r30_cpc_addr, ra jr nop CPC_P_BASE_ADDR li a0, (r22_gcr_addr) GCR_CPC_BASE sd a0, Block Offset Table 6.1 Table 0x0000 0x1FFF - 0x0000 0x3FFF - 0x2000 0x4000 0x5FFF - 0x4000 Then the code stores this address for address this stores the code Then setting up theCPC. This completes the CPS initialization and thecodereturns to start. done_init_cpc: END(init_cpc) This conceptis described in The followingThe Also address. physical is a This Register. Base Address ler of the addressthe of zeroare always to indicate that Base AddressBase register (GCR_CPC_BASE) locally for futureuse. LEAF(init_cpc) of CPC within the location value of uses the known code The As mentionedabove, addressthe base of theCPC registers In tion on how to use this register. tion howon tothis use register. are relative tobits 31:15 theof 6.2.2 CPC Base Address 110
111 compan- those locations are those CPCControlGlobal Block CPC Core-Other Block CPC Core-Local Block ssed from other cores by first writing first by from other cores ssed y beaccessed y usingaligned 64-bit some CPC registers, a some set of registers CPC registers, I6500 Technical Reference Manual Reference I6500Technical companion document. in theCore-Local ControlBlockthe of CM. 0x0000_1BDE_0018 0x0000_1BDE_0010 0x0000_1BDE_0008 0x0000_1BDE_0000 0x0000_1BDE_4018 0x0000_1BDE_4010 0x0000_1BDE_4008 0x0000_1BDE_4000 0x0000_1BDE_2018 0x0000_1BDE_2010 0x0000_1BDE_2008 0x0000_1BDE_2000 0x0000_1BDE_5FFF 0x0000_1BDE_3FFF 0x0000_1BDE_1FFF de and should only be accessed using aligned 64-bit uncached uncached 64-bit aligned accessed using and should only be de I6500 Registers the CPC chapter in the the are 64are should onl bits wide and ace return 0x0, and writes to those to those writes 0x0, and space return the CPC address in lated registers core in the I6500 MPS. In the case of In the case MPS. the I6500 core in +0x2000 +0x2000 domain. These registers can also be acce be registers can also domain. These 0x0000_1BDE_2 0x0000_1BDE_4 0x0000_1BDE_0 ulated registers in the CPC address space return 0x0, and writes to address space in the CPC registers ulated e registers, refer to the registers, refer to e these registers, to refer these 15 CPC Local Control Block LocalCPC Control Core-LocalRedirect Register (GCR_CL_REDIRECT) GCR_CPCBASE Register GCR_CPC_BASE 47 ion document. ion For more information on silently dropped withoutgenerating anyexceptions. For more information onthes All registers in the registers in All All registers in the Global Control Block are 64 bits wi bits 64 are Block Control Global in the registers All unpop load/stores. Reads from uncached load/stores. Reads from unpopu Reads load/stores. uncached locations are silentlydropped without generatingany exceptions. of for each these registers exists A set clock domain or per power exists per the GCR Figure 6.3 Figure 0x0000_1BDE_0 of Address Base an Example Using Scheme Addressing CPC Register 6.2.4 Local and Core-Other Control Blocks 6.2.3 GlobalControl Register Map Block MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
at offset 0x120 offset at companion document companion s in the CM local register in s be used during boot-up and boot-up be used during d tod it toderive the exact reg- an IOCU. The requestor may requestor The IOCU. an register located rresponding to that core or IOCU, and or IOCU, core that to rresponding either a coherent or non-coherent either a coherent em Programmer’s Guide, Revision 1.00 to the CP0 CMGCRBase register. As a As CP0 CMGCRBase register. to the pin. The state of this pin is reflected in reflected is this pin state of pin. The I6500Register access to the CPC register set. To disable access to disable access set. To register to the CPC access companion document included in the release. in the document included companion to indicate the base locationthe globalof CM control register. reside This register register. Global Access Privilege oherent mode should only oherent register and an offset is adde is and an offset register Coherence Enable Coherence boot time,the programmer determines which requestor’s itiated, the caches must be to the power state is initiated, the caches must ange register is located. is register I6500 Registers field (bits5:0) of this registerselects uptosix cores,and bits 23:16 $15,3 4 bits by left in t1 value // shift base KSeg1 // Assign rnel software need only clear the bit co software need only clear rnel MIPS64® I6500Multiprocessing Syst ws each power domain to be placed in be to each power domain ws e CM GCR registers is programmed in CMGCR registers is programmed e field is 0x3F, meaning that all cores in the system have access to the CPC register to the CPC register system have access the meaning that all cores in field is 0x3F, ACCESS_EN registers by programming the programming by registers not execute any accesses (instruction cacheable memory while fetch or load/store) to CPC Registers to CPC ng The non-c normal operation. Core-Local Status and Configuration Core-Local Status Core Local Coherence Control Local Coherence Core ACCESS_EN mfc0dsll c0_CMGCRBASE t1, li t1, 4 t1, 0xA000_0000 t2, t1 into register CP0 CMGCRBase of contents // move #define c0_CMGCRBASE #define the registers for a particular requestor, ke requestor, a particular for registers the all write requests to the CPC registers by thatrequestor willignored. be For more refer to the informationCPC register on thislisted register, in the release. in the included By default, coherence is disabledinthe I6500 MPS. flushedto prior disabling coherence mode. EnableCoherent Mode Code Example th of base address for the location The block at offset address 0x0008.per power domain.There is one of registers theseblock at offset For more refer to the information onthis register, ch coherent mode and a is in a power domain that if Note bit 11 (COH_EN)the of bit11 The I6500 Multiprocessing System allo System Multiprocessing The I6500 nothave unrestricted access to the registers.CPC During mode.Because theI6500implements directory-based a coherence MIPS protocol,recommends that each domainbe duri mode in coherent placed Software should power-down. Register Interface Register or core be either a can A requestor in a system. eight requestor’s to up CPC allows The are provided access to the CPC to provided access are enable access for IOCU7 through IOCU0 respectively. through IOCU0 respectively. access for IOCU7 enable for default MIPS The allow IOCU7 through IOCU0 IOCU7 through allow to set 23:16 are bits addition, In set. in theCMThe6-bitregister map. reference, a valuereference, a of 0x0000_1FBF_8 is used (MIPS default) CP0 read from the value is case, the base In this registers. the address where ister coherence is disabled.coherence is Interface Register external the asserts is enabled when hardware Coherency 6.2.6 Enabling Mode Coherent 6.2.5 Requestor Access 112
113 register located at register cluded in the release. cluded is set. Thisisbit set. must set be Section 6.2.8.1, "Clock Domain Domain "Clock 6.2.8.1, Section e CP0 CMGCRBase register. As a refer- CMGCRBaseregister. e CP0 field in bits 26:23 of this register to determine to determine register of this 26:23 bits in field select the prescaler ratio. the prescaler select ..... Description No prescaling to indicate the virtual address base location of theindicateCPC theto virtual of location address base CPC Prescale Clock Change Control e prescaler). A valueofindicates 0xFF a 1:256 ratio bit thisof register (bit 8) Divide input Divide clock by 2 input Divide clock by 3 input Divide clock by 4 input Divide clock by 5 Divide input clock by input 254 clock by Divide Divide input clock by input 255 clock by Divide input 256 clock by Divide step of the1 procedure in . companion document in companion document Registers
CM PRESCALE_CLK_RATIO // Create VA from CGRBase VA // Create coherence // Enable Enable Coherence the access to 0x2008 of an offset // // register. d the output of the prescaler. the prescaler. of the output d e CPC registers is programmed into th into is programmed CPC registers e be programmed followsas to field (bits 7:0) to set the clockratio. A valueof 0x00 indicatesa 1:1 clock ratio field can be changed. be field can ogram these fields, refer to refer fields, ogram these ..... 0x00 0x01 0x02 0x03 0x04 0xFF 0xFE 0xFD Table 6.2 Table CLK_PRESCALE Field of the Encoding Encoding PRESCALE_CLK_RATIO_CHANGE_EN CLK_PRESCALE CLK_PRESCALE the current clock prescaler ratio. clock prescaler the current (no difference between (no inputdifference andoutput frequencyof th between input clock an the master orlisd t1 t2, t1, 0x0000_0001 t0, (t1) 0x2008 t0, plus in t1 address to the base t0 in value // write before the 3. Programthe For an example of how to pr ChangeExample —Register Programming Sequence" For morerefer to the information onthis register, The base address for the location of th of base address for the location The 0x0000_BBDE_0000of valueused (MIPSdefault) a is ence, The 8-bit CLK_PRESCALEThe 8-bit field can registers. The clock prescaler is used to reduce the frequency of all devices in the system simultaneously. the system in of all devices is used to reduce the frequency clock prescaler The CP0 Interface global the using as follows can be programmed prescaler The offset address 0x0048.offset 1. the that Verify 2.the programmer can read the Optionally, 6.2.7 Master Prescaler Clock MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
CPC CPC Prescale ClockCPC Prescale Clock Domain Change Domain Clock companion documentfor mplished by programming the mplished by programming MHz, program theindividual register located at offset address offset register located at em Programmer’s Guide, Revision 1.00 4 speed. To set the ratio of the clock the clock set the ratio of To 4 speed. the clock prescaler is enabled and the prescaler the clock 2 at quarter-speed to save power. Assume the Assume power. save to at quarter-speed 2 te that this register is global and is seen by all by is seen globaland is register this that te shown above, the outputfrequencythe of register locatedaddress 0x0018. at offset For programming global the in the figure. This is acco figure. This is in the 1 so it operates at 250 operates so it 1 ce supplied by the clock prescaler, each device can further can device each clock prescaler, by the supplied ce ESCALE_CLK_RATIO field in bits 23:16 of this register is a isregister this of 23:16 bits in field ESCALE_CLK_RATIO step 2 of the procedure in the section entitled section the procedure in of the 2 step . // Enable clock prescaler and set divide ratio to 4 ratio set divide and prescaler clock // Enable plus in t1 address to the base in t0 value // write Clock Global the CPC to access of 0x48 offset // an register. // Prescale at full speed. Core 1 is running at 1/ at running Core 1 is at full speed. CPC Prescale ClockCPC Prescale Change Control MIPS64® I6500Multiprocessing Syst ed in the I6500 MPS. In this example, In this I6500 MPS. ed in the CPCLocal Clock ChangeControl its input clock as shown as input clock its ock Ratio Modification input tothe clock prescaler is 1 GHz. As s how to run core 0 at full speed, and core full how to run core 0 at s caler for this example: for this caler si_ref_clk register located at offset address 0x0048 as follows. No follows. as 0x0048 address at offset located register generators for core 0 so it operates at 1 GHz, and core at 1 GHz, for core 0 so it operates generators lilisd 0x0000_BBDE_0000 t1, 0x0000_0103 t0, t1 into VA value register CPCBase // move 0x48(t1) t0, 0x0048. This value sets the CLK_PRESCALE field to a value of 0x00, indicating a 1:1 relationship between the betweenrelationship a 1:1 indicating0x00, of a value to fieldCLK_PRESCALE the sets 0x0048.This value bitto indi- input clockand the outputclock.This value also setsthePRESCALE_CLK_RATIO_CHANGE_EN fieldisthe I6500Registers Refer to valid.CLK_PRESCALE the that the value in cate more information onthis register. • system 2-core • 1 VPper core •GHz 1 of frequency input si_ref_clk • output Prescaler of 1 GHz •0input Core frequency1 GHz of •1input Core frequency250 of MHz CLK_RATIO field(bits2:0)of each CLK_RATIO 2.this 0 example the core is running In an example of how to program this field, refer to refer field, program this to of how example an Based on the input clock frequency to each individual devi individual each to frequency on the input clock Based reducethe byclock a frequency rangeof 1:1 to 1:8, except for the CM, whichcanbe programmed withfrequency a 1:1 or 1:2 relative to either ratio of By default, the clock prescaler is disabl is prescaler By default, the clock clock divide ratio is set to divide by 4. Note that the PR the that Note4. by divide to set is ratiodivide clock read-only field thatis updated byhardware and allowskernel software to quickly read this register todetermine the currentclock ratio.In this example thisfieldis ignored. Change Control cores and allindividual devices (clock domains)in the system. Interface Register program the clock pres To 1. a valueof 0x100 theto Write global Example — Register Programming Sequence The following example show following example The following: the this example, In This accomplished ratio is by also 1 GHz. is example in this prescaler 6.2.8.1Sequence Programming — Register Example Change Domain Clock 6.2.8 Individual Device Cl 114
115 so in this case so each in this 1 GHz CPC Local ClockCPC Local Change 250 MHz 250 Core Clock Frequency register located at offset 0x0028 register to initi-located at offset one per clock clock domain, per one tio 4:1 1:1 bit 10 (CLK_CHANGE_ACTIVE)0. If is Clock Clock Ra ine when bit 8 (SET_CLK_RATIO) is 0. If is ine whenbit 8 (SET_CLK_RATIO) the CPC Local Clock Change Registers Registers Change Clock CPC Local the field (bits 2:0) of the corresponding of the corresponding 2:0) (bitsfield clock change has completed. At this point,couldthischange another clock completed.At has change clock // write value in t2 to the base address in t1 plus in t1 address the base to in t2 value // write Clock Global the CPC access to of 0x48 offset // an register. // Prescale to 0 number 0 and VP number to CORE // set at register GCR_CL_REDIRECT to contents // store GCRBase from // 0x2018 to 1:1 ratio and set change clock // enable 0x4018 at register CPC_CO_CC_CTL to contents // store to 0 number 1 and VP number to CORE // set participating in the clock3in 0change, which- this example.iscores CPC Global ClockCPC ChangeControl 3’b000 3’b100 registers. registers. asThis register is instantiated CLK_RATIO Value CLK_RATIO shows the programming of the CLK_RATIO of the CLK_RATIO programmingthe shows SET_CLK_RATIO thechangeis 1, requeststill is pending. SET_CLK_RATIO CLK_CHANGE_ACTIVE clock 1, thechangeis = inprogress. be requested. 0 1 register located at offset 0x0018.address register locatedat offset Core // Set the core number to 0 in the GCR_CL_REDIRECT register in the GCR_CL_REDIRECT to 0 core number Set the // lisd 0x0000_0000 t2, sync 0x2018 (t0) t2, (1:1 ratio) to 0 field CLOCK_RATIO register CPC_CO_CC_CTL the //Program lisd 0x0000_0100 t2, register in the GCR_CL_REDIRECT to 1 core number Set the // 0x4018 (t1) t2, li 0x0000_0001 t2, #define c0_CMGCRBASE#define $15,3 t0, GCR_BASE_ADDR li t1 into register for CPCBase Store VA // t1, CPC_BASE_ADDR li into t0 value GCRBase // move register CPC_PRESCALE_CC_CTL in the to 1:1 ratio divide clock prescaler Set the // lisd into t1 value CPCBase // move 0x0000_0100 t2, 0x48(t1) t2, to 1:1 ratio set divide and prescaler clock // enable Local ClockLocal Change Control core has its own register since each core is in its own domain. domain. core is in its own each register since has its own core ate a clock change for all clock domains for all clock change ate a completed. has clock change the once cleared by hardware is This bit •register determ to Read the CPC_CC_CTL_REG •when to determine Read the CPC_CC_CTL_REG •the zero, both of these bits are When Table 6.3Table of Field CLK_RATIO the Programming 3. the in bit SET_CLK_RATIO the Set Control Table 6.3 Table Poll thefollowing completed. registershas change to determinethe clock when ClockChange Code Example Ratio MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
CPC Global companion l state. If the CM is already is already state. If the CM l a given device connected to device given a register is used to optimize used to is register I6500 Registers er. If the CM is not operational at operational If the CM is not er. wered-up even if no core is powered-is if no core even wered-up em Programmer’s Guide, Revision 1.00 all clock domain ratios are low. For example,if all all clockdomain ratiosare low. CPC Global Control Clock current state to an operationa ks should not be a problemand leaving this valueatits e programmer to determine when e be used toextend thestatedelay perioddesired. if // store conents to GCR_CL_REDIRECT register at register GCR_CL_REDIRECT to conents // store // 0x2018 to 4:1 ratio and set change clock // enable at 0x4018 register CPC_CO_CC_CTL contents // store t2 in to register CPC_CC_CTL_REG // load REG in the CPC_CC_CTL bit the SET_CLK_RATIO // set copy and t2 8 with OR bit - logically // register enable change clock sets the t2. This into // back reg CPC_CC_CTL to the t2 back value in new // store t2 into CPC_CC_CTL_REG of contents // read t2 into copy result 0x0500, t2 and // AND a indicating low, and 10 are bits 8 until // loop change clock // successful The I6500 allows for the CM to be po be to CM for the allows I6500 The MIPS64® I6500Multiprocessing Syst e value of the delay could be reduced. The intent is that clock domain changesdomain clock is that reduced. The intent couldbe delay the of value e field bitsin 29:20 of the more information on this register. this on information more register (CPC_ROCC_CTL_REG) at offset 0x0040 toset. Refer the register is (CPC_ROCC_CTL_REG) atoffset CPC_CC_CTL_REGCC_DELAY sdsync (t0) 0x2018 t2, ratio) (4:1 to 3 field CLOCK_RATIO register Change Clock CPC Local the //Program lisd 0x0000_0103 t2, CPC_CC_CTL_REG 8 of the bit program - change based clock register Initate // 0x4018 (t1) t2, from CPCBase 0x0018 at offset register // ldori(t1) 0x0028 t2, t2, 0x100 t2, sd Loop: 0x0028 (t1) t2, low. 10 are 8 and until bits register control change clock Poll CPC_CC_CTL_REG // ld andi (t1) 0x0028 t2, bne t2, 0x0500 t2, loop r0, t2, nop operational, settingthis bithas nomeaning and the registerwrite is ignored. up. Thisuseful for systemis debug/setup viatheDBU. Interface Register This functionalitycontrolled is by the CPC Global Powe(CPC_PWRUP_CTL_REG) r Up register located at offset address 0x0030. the of CM by writing power-up one-time a 1 a toexecute this DBU may The regist its from transition will it DBU, the by is set bit this time the The Reset Occurred The CM provides a series of read-only bits that allow th allow that bits read-only of series a provides CM The ed-up if any core is powered-up. Conversely, CM is the automatically pow- automatically is the CM powered-up is if any powered-up.core Conversely, Normally, all cores are powered-down. if ered-down of the bit is reset, the corresponding a device Whenever itself. CPC theincluding reset, beenhas CM the current clock ratios are less than 1:4 th than less clock ratios are current do not happenvery often, sosetting thedefault of 80cloc default delayrecommended. couldis This register also the amountof delayduring clock a change. This can be done if document included in the release for included in the document 6.2.8.2 Clock Change Delay 6.2.10Detection Reset 6.2.9 Powerup CM Standalone 116
117 regis- 012345 register. If a If register. register can register VP Run VP Run registeris set, setting register contains a 4-bit a 4-bit containsregister VP Running that indicates the type of the type indicates that register in VP places the e bits, kernel software must must software bits, kernel e VP Run s is instantiated per core. instantiated per s is VP Running VP Run e. Writing a 0 to any of the bits in the bits in the to of the any 0 a e. Writing ed core is reset. The 1617 ur. Prior to setting one of thes setting to Prior ur. VP The in theI6500 system. Multiprocessing system sup- stem. Each of these register stem. Each to stop a VP. If a givenIf a bit in the to stopVP. a to set each VP to the run state. The the run state. to VP to set each reset whenever the associat the reset whenever register is already set, setting the corresponding bit in the inbitcorresponding the set, setting registeris already running by reading the corresponding bit in the in bitcorresponding the reading byrunning d watchdog timer reset. The functionality reset. The timer watchdog and warm reset, reset, external cold e CPCGlobal OccurredRegisterReset . 31 30 29 register places the VP in the VP suspend in stat register places the VP Running register is cleared, setting the corresponding bit inthe VP Stop , as well as as the Debug unit. well , Figure 6.4 register (RO) Figure 6.4Figure System Multiprocessing I6500 the in Detection Reset VP Running register (WO) register is a write-only register used write-only is a register register (WO) register is a Write-only register used register register is a Write-only 63 CM ResetCM CPC Reset CPC DBU Reset DBU register has no effect. register has no effect. CORE4 Reset CORE4 Reset CORE3 Reset CORE2 Reset CORE1 Reset CORE0 CORE5 Reset CORE5 VP Stop VP Run VP Stop VP Running VP Run Register Interface The • the corresponding bit in the the in the corresponding bit the run state. If a given bit in the in the bitgiven a run state. If the VP Stop Three registers are used tocontrol the power each of state ports up to four VP’s per core,and upper to six cores per sy ports VP’s up to four reset for the CPC block. Reset options ar options Reset block. the CPC for reset thisof register is shownin Inaddition tothereset detection, this register contalso field (RESET_CAUSE) a 2-bit ains ter has no meaning.ter The valuein this register is given bitin the • also be cleared by also hardware be cleared The field, where each bit is dedicated to a particular VP, up to fo VP, particular to a dedicated is bit each where field, already not that the VP in question is ensure Three registers are used to controlThree registers thisfunctionality: • Cause of CPC Reset Cause 6.2.11 VP Run/Suspend MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
a fraction of their register c) Shut- to be placed into either run state using bits 23:16 kernel software as registers by ks are running at are running ks is cleared (logic ‘0’), the RAM’s on RAM’s (logic ‘0’), the is cleared em Programmer’s Guide, Revision 1.00 ty to power cycle its own local RAM local power cycle its own ty to VP Stop 2 is already in no the Suspend state and 2 is already register. Once awoken, the CPC delays the delays Once awoken, the CPC register. Run state, kernel software sets bit 2 of the bit 2 kernel software sets Run state, and CPC Local RAM Sleep Control Local RAM Sleep CPC e, kernel software sets bit software sets kernel is Suspend state, in the VP2 at VP Run the deep sleep state to the CPC_CL_RAM_SLEEP that power domainrunning are at a fractionof their normal CPC_CL_RAM_SLEEP nstate, kernel software would dothe following, at indicates the run state of each VP in a at bits These given core. the run stateindicates are in a of each VP VP’s correspondto the register as follows: bits VP’s f, or Deep Sleep mode where the cloc or where Deep Sleep mode the f, range from1to clocks. 255 (0xFF) MIPS64® I6500Multiprocessing Syst / Shutdown and Wakeup Delay and Wakeup Shutdown / programmed timefor tothe RAMs intoprovide thisfieldinsufficient order to domain, so each domain has the abili domain has each domain, so register. If this If bit is already set, VP2 is already runningand actionno need be register. this bit is alreadyIf cleared, VP register. registerset, indicatingis thatVP2 is in the register is cleared, indicating th register is ) located at offset 0x0050 ) (or locatedatoffset 0x2050 relativetothe CPCbase address). VP Running VP Running register to set VP2 to the Run state. Run the to VP2 set to register VP Running VP Running register is a read-only register th register a read-only register is register to set VP2 to the Suspend state. VP2 register to set VP Run VP Running 2 theof taken. action taken. need be VP Stop VP Stop CPC_CL_RAM_SLEEP • Bit0 = VP0 • Bit1 = VP1 • Bit2 = VP2 • Bit3 = VP3 to the Ru given core of a VP2 For to set example, 1.the 2 of Read bit described above. that forNote each of these registers, the four This register is instantiated per power This register is instantiated 2.bit If of2 the 2.bit If 2 of the devices. Whenbit 31 (RAM_DEEP_SLEEP_DISABLE)of the The CM allows the local RAM’s within a given power domain (cores, CM, IOCU,et a domain (cores, within given power local RAM’s allows the The CM are turned of clocks where down the mode The e, kernel softwarestat would dothefollowing, Suspend the to core given a of VP2 set To 1.the 2 of Read bit transition to the run state by the value state to the run transition wake upfrom Deep Sleep.The delaycan the local device enter the Deep Sleep low power state when the CPC power state for the device reaches the ClockOff ClockOff the the device reaches for state power CPC the low power state when Sleep enter the Deep device local the within In thisclocksstate. statethe to the local RAM’s frequency. CPCThe also providesa way to delay the transition from set and clearedby hardware based on theprogramming the of ( normal frequency. This functionalitycontrolled is throughthe normalfrequency. RAM_DEEP_SLEEP_WAKEUP_DELAY) of the of the RAM_DEEP_SLEEP_WAKEUP_DELAY) 6.2.12.1 RAM Deep Sleep Mode 6.2.12 Local RAM Deep Sleep 118
119 Rail Core-Local and Core-Local order to meet order sys- to registers. This registers. e CPC Global Control Block, con- e is cleared (logic ‘0’), the RAM’s on RAM’s (logic ‘0’), the is cleared transitioning to theoperational state. ace using the Core number and the VP the Core number and the using ace cal and Core-Other cal s are used to help accommodate a wide a used to help accommodate are s tened accordingly in tened to provide sufficient time for the RAMs for the time sufficient provide to e off. The RAM’s remain in theShut- TheRAM’s off. e register. Once awoken, the the CPC delays Once awoken, register. re or VP, refer to the section on the to refer VP, re or this register provides the programmer with the ability to ability the with programmer the provides register this counteddown totozero. Refer thesection entitled 002, indicating a 2-cycle delay. However, should addi- However, 002, indicating a 2-cycledelay. to delay theassertionexternal of signals relativeto one device reaches the PwrDwn the reaches the device for state CPC power the 1-cycle delay 1-cycle delay 2-cycle delay 3-cycle delay 4-cycle Description ese registers to modify the power parameters for a given for a power parameters registers to modify the ese CPC_CL_RAM_SLEEP CPC_CL_RAM_SLEEP chapter of this manual. this of chapter ) located at offset 0x0008 in th ) located at offset CPC_CL_RAM_SLEEP CPC_CL_RAM_SLEEP ers in Another Power Domain ers in Another ribes the number of clock cycles each domain sequencer state machine will state sequencer domain each cycles clock of the number ribes contains its own setof CPC Core-Lo lue programmed into this field in order order field in this into programmed lue stem. Signals can be lengthened or shor or Signals can be lengthened stem. n sequencer state machine. These register sequencer state machine. These n and External Signal Delays CM Programming CM 0x000 0x001 0x002 0x003 e local RAM’s within that that ar power domain within local RAM’s e Encoding Figure6.1 CPC_SEQDEL_REG Table 6.4 Table MICROSTEP Field of Encoding accessing the CPC registers of another co of registers the CPC accessing usage in the usage for more information. tem timing. tem ( register Sequence Delay The Whenbit 15 (RAM_SHUT_DOWN_DISABLE)of the another, as well as the internal domai internal the well as as another, constraints sy in the timing variety of This section describes those register fields that can be used be can that fields register those describes section This Each power domain shown in in shown domain power Each Core-Other Register Core-Other allows master devices such as a core or IOCU to access th core or IOCU to access a master devices such as allows sp address registers within the CM by writing to accomplished is This domain. numberof the deviceto accessed. be For on more information the low power state enter the Shutdown local device when to th state the clocks In this state. without ClkOff state changes to power down power state even if low the CPC CPCThe also providesa way to delay the transition from shutdownthe statetothe runstateusing bits7:0 of the RAM_SHUT_DOWN_WAKEUP_DELAY) tional delay be required based on the system implementation, system the on based required be delay tional The 10-bitThe MICROSTEP fieldencoded follows:is as tains a 10-bit MICROSTEP field that desc that field a 10-bit MICROSTEP tains advance take to the next state.to 10-bit The fieldMICROSTEP containsa defaultvalue 0x of necessary. delay as the sequence increase field has Domainsequencing begins once theRAILDELAY Delay the transition to the run state by the va transition to the run state the to wakeupfrom the ShutDown state. Thedelay can rangefrom 1 to 255(0xFF) clocks. 6.2.14.1 Global Sequence Delay Count 6.2.12.2 RAM Shut Down Mode 6.2.14 Internal Fine Tuning 6.2.13 Accessing the CPC Regist MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
signal 1 RailEnable section in the System System in the section should a problem arise where problem arise should a . The power-up sequence starts after sequence The power-up . for the exact name and usage of this for the em Programmer’s Guide, Revision 1.00 ...... Global SequenceDelay Count ount-downconcluded.tozero has Atconfiguration IP this registerprovides the programmer with the abilityto 5-cycle delay 5-cycle 1-cycle delay 1-cycle delay 2-cycle delay 3-cycle delay 4-cycle delay 5-cycle Description Description to be changed. However, be changed. However, to I6500 Integrator’s Guide Integrator’s I6500 1022-cycle delay 1022-cycle delay 1023-cycle 1022-cycle delay 1022-cycle delay 1023-cycle 1024-cycle delay 1024-cycle 1024-cycle delay 1024-cycle for more information. for more information. C to C compensate for slew rates at the gatedrail. register are preset. However, for fine tuning, for theregister be writtencan at are preset. However, register ) located at offset 0x010 in the CPC Global Register Block contains a 10-bit a contains Block Register Global CPC the in 0x010 offset at located ) MIPS64® I6500Multiprocessing Syst ) delays the power-up sequence per domain per sequence power-up the delays ) ...... 0x004 0x000 0x001 0x002 0x003 0x004 0x3FF 0x3FF 0x3FE 0x3FE 0x3FD 0x3FD Encoding Encoding Table 6.4 Table MICROSTEP Field of Encoding Table 6.5 Table Field of RAILDELAY Encoding lustration purposes. Refer to the purposes. Refer to lustration ) used to scheduledelayed start of power domainsequencing the after I6500 Integrator’s Guide I6500Integrator’s RAILDELAY CPC_RAIL_REG CPC_RAIL_REG RAILDELAY has been loaded into the internal counter and a c internal counter and the loaded into been has signal. has been activated by the CPC. This allows the CP has been activated by the CPC. This The Rail Delay register ( Rail The additional delayis required in order tomeet systemtiming, necessary. as the delay increase For more information onhow this counteris used, refer to the Integrationchapterof the The defaultThe valuefor thisregister been has determined as by MIPS the valuethat should work in themajority of sys- temimplementations. As such, this valueshould not need run time. follows: as field is encoded 10-bit RAILDELAY The RAILDELAY counter field ( time, the contents of the the contents of time, The 10-bit counter value ( counter 10-bit The 6.2.14.2 RailDelay 1.signal is shown only for il This 120
121 Reset ) at offset at offset rs are used to delay are used rs CPC Global Reset Global Reset CPC CPC_RES_REL_REG section of the I6500 Integra- the of I6500 section should a problem arise where problem arise should a CPC_RESETLEN_REG) . Once this counter reaches 0, the this counter reaches Once . . series down-counteof A nt of delaynt of betweenthe time the configuration Table 6.6 ...... ed toed loada secondary internal counter withthe value Reset_Hold with a delay value between1valueand 1024a delay clockwith cycles. The this providesregister the programmer with the abilityto reset is activeuntil the domain responds byasserting the 1-cycle delay 1-cycle delay 2-cycle delay 3-cycle delay 4-cycle delay 5-cycle Description to be changed. However, be changed. However, to Global Sequence Delay Count Global 1022-cycle delay 1022-cycle delay 1023-cycle 1024-cycle delay 1024-cycle ster — Core Reset Release (RESREL1) Release Reset — ster Core allowing them to comeoutreset. of Table 6.6 Table ) at offset 0x0018. Thisregister field programmed is with) at offset a delay the CPC Global Reset Reset Release Register ( the CPC Global and the time that the core reset is released. Global Reset Width Counter ( register Global Reset Width and the corresponding hardware signals that can be delayed, refer to the to the refer can be delayed, that hardware signals the corresponding and ..... 0x000 0x001 0x002 0x003 0x004 0x3FF 0x3FE 0x3FD Encoding Table 6.6 Table Field RESETLEN the of Encoding illustration purposes. to the illustration Refer CPC_RESETLEN_REG This register usedis todetermine the amou ( signal. However, the signal. However, signal is deasserted to the signal core(s), to is deasserted 2 Reset_Hold section in theI6500 Guide Integrator’s for more information. During the power-up sequence, reset is applied. Typically, sequence, Duringresettheis applied. power-up Typically, internal Domain_Reset_n Programming the Global Reset Release Regi Release Reset Global the Programming outputThe the of RESETLEN counterdescribed above is us programmed into the RES_REL_LEN field of valuebetween 1 and 1024 clockcyclesas shown in various reset pinsusedto bootthe CM as described in thefollowing subsections. defaultThe valuefor thisregister been has determinedas by MIPS the valuethat should thework in majority of sys- temimplementations. As such, this valueshould not need additional delayis required in order tomeet systemtiming, necessary. as the delay increase counters on these information more For Programming the Global Reset Width Counter Register (RESETLEN) Register Counter Width Reset Global the Programming RESETLEN The down counter is used to extend the various resetsignals usingbits 9:0of the Delay Counter Register Width 0x0018resetallowstobe extended beyondtheassertion of located at offset 0x0038. offset located at the respective core(s), at are stable signals (RES_REL_LEN) are programmedregister thisBits 9:0 of encoding of is identical this field toencoding theRESETLEN field shown in tor’s Guide for more information on the usage of this signal. usage the on information more for Guide tor’s 6.2.14.3 Reset Delay 2. only for shown is This signal MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
. signal is deas- is signal ) located at offset located at offset ) core(s), allowing the core to allowing the core core(s), load both the RESREL1 and both load Domain_Reset_n I6500 Integrator’s Guide I6500 Integrator’s ready to begin execution. Note that Note execution. begin to ready em Programmer’s Guide, Revision 1.00 CPC_RES_REL_REG register is used to used register is chapter of the of chapter signal is asserted to the signal is asserted Domain_Ready signal, indicating that the core is that the core is signal, indicating CPC_RES_REL_REG MIPS64® I6500Multiprocessing Syst requiresthe RESREL1 counter that has reached zero before countingcan CPC Global Reset Release Register ( CPCGlobal section in the Systemsection in Integration Domain_Ready ese counters are loaded and the signals affected once the counts reach once zero, refer to the counts ese counters are loaded and the signals affected GlobalSequence Delay Count RESREL2 counters. counters. RESREL2 counter third internal (RESREL2)The counter reaches 0, the Once the RESREL2 begin. 0x0038. This register is used to determine the amountof delaybetween timethe the Programming the Global Reset Release Register (RESREL2) — Ready Register Domain Release Reset Global the Programming outputThe the of RESREL1 counter used to loadis a irdth internal counter (RESREL2) with thevalue programmed into the RES_REL_LEN the field of d (RES_REL_LEN) of the of (RES_REL_LEN) field same register the serted, and the deassertion of the of the deassertion and serted, begin execution. For more information on how th the 122
123 ion in memory, memory, ion in es and code exam- es tine is specifically is tine th register exampl th signed its own locat signed its ents is accomplished through an inter- is ents routine. This rou those whichrequire immeThese diate attention. n intothe interrupt controlsystem, allowingseparate externaland interrupt to any VP within theI6500 MPS number externalof interrupts,and configuring individual des in memory. Each time an interrupt event is detected, thedetected, is event an interrupt time Each in memory. des e interrupt service e interrupt related Root and Guest registers. Refer to the chapter on Virtualization in Virtualization on chapter the to Refer registers. Guest and Root related ram flow and requireservicing to determine the typeof the and reasonfor e various elements of the GIC using bo e up 256to external interrupts in multipleswell8, numerousas of as internal rity events. The servicing of these ev servicing of these The rity events. ttingthe operatingGIC registerthesettingaddress map, up mode,layout and processes. This chapter contains informationThis on virtualizationprocesses. as it relatesto at originate outside of the I6500 Multiprocessing System and require servicingrequire Systemand MultiprocessingI6500 the of originateoutside at em incorporates virtualizatio em ated from and how they can be resolved. Internal events are those that occur within the within those that occur are events Internal be resolved. they can how from and ated ized by priority. are High priority events by priority. ized The main difference is that in VI mode, each interrupt type is as each interrupt mode, VI in is that main difference The ples. Some of these elements include se of these Some ples. distribution,setting the address, determiningGIC base the interruptsources. The GICThe supportstwo types operatingof modes: • Non-EICmode • External InterruptController (EIC) mode Inter- Vectored also andmode, interrupt of basic type mostthe Compatibilitymode,both includes mode non-EIC The mode. rupt (VI) The I6500 Multiprocessing Syst Multiprocessing The I6500 interruptcontrollersand for guest root GIC- the of interrupts the programming and information. more for manual this to determine where they origin they where determine to I6500 Multiprocessing System.Internal eventscan include performance counters,watchdog timers,software, and FastDebug Channel (FDC). Interrupts eventsare which interrupt prog External events are defined as those th those as events are defined External TheGlobal Interrupt Controller (GIC) processes internal and external interrupts inthe I6500 MultiprocessingSys- supports in the system tem. cluster Each interrupts. TheGIC is responsible for mapping eachinternal for servicing. are categor event. Events before the lower prio handled are events resi that software of piece a is which routine,servicerupt designed to deal with the interruptevent. chapterThis describes how to programth program flow is interruptedandthe code branchesto th 7.1.2.1 Non-EIC Mode 7.1.2 GIC Operating Modes 7.1.1 GICVirtualization MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 7.1 Overview Global Interrupt Controller Interrupt Global Chapter 7 Chapter
bit. address address bit is I6500 Reg- I6500 -Other CONFIG3.VEIC access should be access CONFIG3.VEIC register termines the source of the the of source the termines companion document. rol registers. For more infor- t address spaces as shown in as shown spaces t address her registers are local to a partic- are registers her GIC_VL_CTL.EICMODE an index to reference the appropri- an index 0x0018 (physical ofaddress ysical address and the VP number of number VP the and address ysical is used to give quick user-mode read user-mode quick give to is used field to select the correct the desired the correct field to select the em Programmer’s Guide, Revision 1.00 overhead of system calls to read GIC overhead of system calls I6500 Registers read-write register bit. Refer to the to Refer read-writeregisterbit. of any other VP by using the VP VP other any of of this of setor pintoclear the CP0 field to the desired VP target and setting the setting and target the desired VP field to e change is reflected e in the CP0 change is number onto the six interrupt pins prior to driving the to driving prior pins interrupt six the onto number REDIRECT_VP vector and kernel software de rrupts byencoding the valueon interruptthe six pinsof appropriatecontthe subset of that are located at differen at that are located register located at offset at located register bit to 1 to that a GICindicate VP-OTHER1 bit to User-Mode Visible Register Visible User-Mode . VP_REDIRECT on on this register. The state of the The state of this on register. on tween all VP’s in the system,while ot tweenallVP’s GIC_VL_CTL.EICMODE fied by the VP number information). re command. The VP number is used as used VP number is command. The re uncached load/store commands. The ph commands. The load/store uncached MIPS64® I6500Multiprocessing Syst vebeen established through the GIC. registers.Byusing theVP numberinformation, thehardware the writes/reads available to the programmer: available to GIC_REDIRECT_EN em, any VP can access the registers registers the VP can access any em, changes the state of this bit, th VP-Local GCR Redirect pin. Hardware then uses the then state pin. Hardware gisters pertaining to that VP. Software does not need to explicitly calculate the register explicitlycalculatethe to need Software does not thatVP. pertainingtogisters ster blocks described above bit allows tobootkernel software up in non-EIC mode, switchthen to EIC mode once byfirstwriting the VP-Local GCR Redirect GCR of to these fields are in the VP-Local 0x1. Both field (GCR_CL_REDIRECT) GCR registerRedirect in the . Some of the registers are shared be are registers Some of the . GIC_VL_CTL.EICMODE GIC_REDIRECT_EN “Other” VP is specified is “Other” VP redirected. valueThe this of register is used by hardware indexto the mation, refer to the the called section additional an this manual, in Also 0x1FBF_A018) before accessing address spaces. Set these the of registers and set the subset VP the requester is the supplied for each load/sto requester ate the instantiated control subset of re subset of the control correct indexthe for core inquestion. This doneentirely byhardware. made “windows” are address Two •speci “Local” VP (as A window for the Syst I6500 Multiprocessing the In spaces. write the Software must the to avoid section is meant this of The use registers. specific GIC to access resources, such as counter registers. • The an A “Other” VP that allows that second windowfor VP to access totheanother set belongingregister VP. The driven onto the SI_EICPresent Figure7.2 This relationship is shown in Figure7.1 VP. ular The GIC contains various regi The value to the appropriate VP. valueto the appropriate VP. the setting by mode EIC enable Softwarecan with accessed is GIC address space The error. In addition,for both Compatibility and VI modes,thesixinterrupt pinsas ontheindividualare used error. VP inter- not encoded value as in an the EIC mode. are and rupts, EIC The modeprovides support for up to63 individual inte vector proper the encoding for responsible GIC is The VP. each whereas inCompatibilitywhereas mode interruptsall goto the same the appropriate interrupt connections ha interrupt connections the appropriate companion document more informati for companion isters bit. Therefore, if kernel software kernel if bit. Therefore, 7.1.2.2 EIC Mode 7.1.4 GIC Register Distribution 7.1.3 GIC Register Types 124
125 often thatoften itmakes her VP. by which the VP. her VP23 for more information. for more s in the system using this using in the system s The use of thissection is address space. Software address space. ular VP, the EIC encoder is encoder the EIC VP, ular GIC_VL23_xxx GIC_VO23_xxx ers that are read so ers -Local section of anot -Local registered, masked, and assigned to a particu- a to assigned and masked, registered, are registered, masked, and assigned to a par- are to registered, masked, and assigned a anexample base 0x1BDE_0address of used. is out requiring a system call. a system out requiring Figure 7.1.2 to Figure Refer register. IC) mode is used for a partic a for is used mode IC) rticular interrupt pin of another VP. Usingthe VP-other rticular interrupt pin of anotherVP. her VP by using the VP-Other her VP can setup the GIC for all VP VP for moreinformationfor on the derivationof these addresses. gister block,and thewithin corresponding register offset VP2 GIC GIC GIC_VL2_xxx GIC_VO2_xxx sections are meant to be located in privileged system virtual address virtual system privileged in to be located meant are sections shared by all VPs and all cores in VPs the system. and all cores all shared by initialize and update the interrupt controller. and the initialize interruptupdate controller. (sharedamong all VPs) calls to read GIC resources, such as counter registers. Currently, the only such as counter registers. Currently, calls to read GIC resources, -Other GIC_SH_COUNTER sectionGIC registthatcontainsaliases for GIC SharedRegisters — GIC_SH_xxxx VP1 , and VP and , Figure 7.1 Figure Distribution GIC Register GIC_VL1_xxx GIC_VO1_xxx section in which interrupts local to a VP are are VP a to which interrupts local in section -Local ace Configurationace section in which the external interruptsources I6500 Technical Reference Manual Reference I6500Technical , VP , -Local section in which the local VP can access the VP in which the local VP can access section -Other User Mode Visible Mode User VP Shared VP0 sters. In this figure In sters. regi GIC the of mapping the shows GIC_VL0_xxx GIC_VO0_xxx register aliasedinto thisspace is the meant to avoid the overhead of system meant sense to make them available to user-mode programs with programs to make them available to user-mode sense interrupt can be registered, masked, and assigned to a pa can and be registered, interrupt masked, the registers of anot access can the "local" VP segment, register VP-Local 0x0018locatedthe atoffset (physicalGCR write Redirect addressof 0x1FBF_A018)must to index the appropriate this value register is used by hardware of Register these spaces. The before accessing One core(s). the other for registers control of the subset section. ticular VP and interruptpin.This section is lar interrupt pin. If External Interrupt Controller Mode (E Mode ControllerInterrupt External If pin. interrupt lar instantiated here. •64 A KByte The GIC address space into four blocks: is divided GIC address The • A KByte32 Shared Figure7.2 space, inwhich only kernel mode software can In the GIC, the In •VP 16 KByte A Each registermappedEach is using theGICaddress,the base re thatblock. totheRefer •KByte 16 A 7.1.5 GIC Address Sp MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
(32 KBytes) GIC Shared Block GIC Core-Local Block (16 KBytes) GIC Core-Other Block Core-Other GIC (16 KBytes) GIC User Mode Visible Block GIC User Mode Visible (64 KBytes) em Programmer’s Guide, Revision 1.00 0x0000_1BDC_7FFF 0x0000_1BDC_0000 0x0000_1BDC_8000 0x0000_1BDC_BFFF 0x0000_1BDD_0000 0x0000_1BDC_C000 0x0000_1BDC_FFFF 0x0000_1BDD_FFFF MIPS64® I6500Multiprocessing Syst +0x4000 +0x8000 +0x4000 +0x10000 e high or active low active high or e ess and Enabling the GIC and Enabling ess 17 • activ Level Sensitivity, • dual or single edge (falling rising)or Edge Sensitivity, GCR_GIC_BASERegister GCR_GIC_BASE 47 • Configurationof interrupt sources • External interruptsource configuration This sectioncovers the followingprogramming for the tasks. • Setting Base Addrthe GIC • Routingof interruptsexternal tospecific processors • Enabling disablingor interrupts • Inter-Processor Interrupts (IPI) • Local deviceinterrupt configuration Figure 7.2Figure 0x1BDC_0 of Address Base Example an Using Scheme Addressing Register GIC 126 7.2 Programming GIC
127 . The Shared . a1 GCR_GIC_BASE register. This register is register. companiondocument . This examples assumes a0. This examples assumes the system. This code reads the This system. number of external interrupts of external interrupts number register in CM address space, then CM in register ers. The GIC base address is a 31-bit is a ers. The GICbase address instruction. li . For. more information, refer to the GCR GIC Base I6500 Registers instruction. Then bit 0 is set, which enables which set, is 0 bit Then instruction. instruction.sw li the GIC which is loaded into loaded is the GIC which field in the the in field r of r external interrupts in GIC_SH_CONFIG the value of the register into NTERRUPTSfieldin bits 23:16. Interruptare config-sources GCR_GIC_BASE External Interrupts in the System External Interrupts se Addressinto Register a1 using the the base address of the GCR_GIC_BASE of the GCR_GIC_BASE base address the dress and Enabling the GIC Enabling the and dress address of the Shared section of section the Shared of address address of the GIC memory-mapped regist of memory-mapped the GIC address chapter for more information on this register. register. information on this more chapter for the following defines to make the code easier to read: easier make the code to defines the following at offset 0. The code loads The code 0. at offset the GCR_GIC_BASE register using the the (GIC_SH_CONFIG0x0000) atoffset inthe terrupts inthe system. register and isolates the NUMI the and isolates register C base address into the address register sets the GIC and C into enablebase bit. Coherence Manager li a1, GCR_CONFIG_ADDR + GCR_GIC_BASE GCR_CONFIG_ADDR a1, li li a0, (GIC_P_BASE_ADDR | 1) // Physical address + enable | 1) // Physical (GIC_P_BASE_ADDR a0, li 0(a1) a0, sw inthe #define GCR_CONFIG_ADDR 0xffffffffbfbf8000 // KSEG1 address of the GCR registers of the GCR address // KSEG1 0xffffffffbfbf8000 GCR_CONFIG_ADDR #define the GCR address of Boot // Post 0xffffffffbfbf8000 GCR_CONFIG_ADDR_PB #define registers GIC of the address physical // GIC_P_BASE_ADDR0x000000001bdc0000 #define the GIC of KSEG1 address // GIC_BASE_ADDR0xffffffffbbdc0000 #define GIC of the address Post Boot GIC_BASE_ADDR_PB0xffffffffbbdc0000// #define 16 NUMINTERRUPTS #define 8 NUMINTERRUPTS_S #define GIC_SH_CONFIG GIC_SH_CONFIG valuethatintois programmed 47:17bits the of ured inured inthe core groups 8. Thisof fieldindicates how many groups of 8 thehas.core the GIC_BASE_ADDRis define The located register is Configuration there are 40 external in are 40 there Setting the GIC Base Address Code Example Code Address Base GIC the Setting uses example code The following The following code example determines determines code example following The physical GI the loads located at offset address 0x0080located inoffset theGlobal at ControlBlockthe registers.of CM Refer to the the GIC. This value is stored to to is stored value This GIC. the Register Interface Register Thistime. at build configured fixed value a is sources of external interrupt number The The code then loads a0 with the physical address of the GIC using the address of the GIC using physical the code then loads a0 with The in thesystemstored is inthe "GIC ConfigurationRegister", The code loads the address of the GIC Baof the GIC address code loads the The Register Interface Register is the starting GIC base address The GlobalConfiguration Register the contained release. in example used to determine the numbe code following is a The the Register Register 7.2.2 Determiningthe Number of 7.2.1 Setting Base Ad the GIC MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
I6500 Regis- time by processor 0, or by 0, by processor time ared by all processors. While processors. by all ared . This example is expecting 40 expecting is This example a3. em Programmer’s Guide, Revision 1.00 pin. Hardware uses this pin to update the update to pin Hardware uses this pin. disable this mode. disable (GIC_VL_CTL at offset 0x0000) inthe (GIC_VL_CTLatoffset // load GIC KSEG0 Address KSEG0 GIC // load gisters in the GIC that are sh in the GIC gisters SI_EICPresent the EIC_MODE bit in the Local interrupt Control Register, Register, Control interrupt Local the in bit EIC_MODE the ect this value, it executes a debug breakpoint to stop at a breakpoint debug it executes a value, ect this at is determined during IP configuration time. TheGIC and accordingly to enable or accordingly to enable // set bit 0 // set 3) select 16, (reg Config3 // read MIPS64® I6500Multiprocessing Syst expected value of NUMINTERRUPTS into NUMINTERRUPTS into value of expected bit toindicate support for and theEIC mode. status of Local Interrupt Control Register LocalInterruptControl mber of interruptgroups. C_MODE bit is driven onto the onto is driven bit C_MODE Config3.VEIC lw a0, GIC_SH_CONFIG (a1) a0, GIC_SH_CONFIG lw // GIC_SH_CONFIG li a1, GIC_BASE_ADDR li li a3, 4 a3, li a3, configure_slices a0, bqe nop of 40 interrupts Failed assertion // sdbbp ext a0, NUMINTERRUPTS, NUMINTERRUPTS_S NUMINTERRUPTS, NUMINTERRUPTS_S ext a0, NUMINTERRUPTS //extract // Read CTL local Read CTL // a1, GIC_BASE_ADDR li a1, 0x08000 a1, daddiu GIC_VL_CTL // read a0, GIC_VL_CTL(a1) lw KSEG0 Address GIC space // load addressing for local offset // add CP0 Config3 and read in GIC_VL_CTL 0) (bit Set EIC_MODE // li a2, 0x1 0, 1 a0, a2, ins sw a0, GIC_VL_CTL(a1) a0, GIC_VL_CTL(a1) sw 3 a2, $16, mfc0 GIC_VL_CTL // write cores of the system the are programmed by hardware system of cores Code Example Setting EIC Mode Notethat the interruptmode is a system widesetting th The triggering of interrupts is configured through several re several through is configured interrupts of triggering The Register Interface Register setting by software kernel through controlled is mode EIC This bitdefaultsto0, vectored interrupt mode.For GIC_ VPi_CTL. Setting thisbit enables EIC mode for that VP. more information, refer to the companion document included in the release. included companion document ters that the state of the EI Note the CP0 state of Number of External Interrupts Code Example Code Interrupts of External Number 5GIC is "slices" of 8interrupts giving 40 interrupts. // Verify all processors can access these registers, in all are practice they processors can access these registers, usually programmed at boot Then the code extracts the nu Then the code For this example, loads code the For the this point wheredebug a be used to evaluateprobe can the problem. interrupt1times(4 sources+ 8). If the code does notdet 7.2.4 Configuring Interrupt Sources 7.2.3 EIC Mode Setting 128
129 normalized to normalized llotted in groups of llotted in specific interrupt in specific d. In d. this case thecontents nd active low. In this case the case In this low. active nd ng and falling edges of the edges falling ng and and active high. In this case this high. In active and iggered the edge of on falling iggered iggered on the rising edge of edge the of rising on iggered _DUAL have no meaning _DUAL ) and) dualedgecontrol regis- gering enabled. is gering enabled. is at control interruptthe triggering con- ng interrupt char- corresponding bit, the n oup. Interrupts are a Interrupts are oup. r settingther interrupt which register and dual-edge-sensitive using the polarity con- polarity the usingdual-edge-sensitive characteristics of each characteristics negative (asserted low) polarity. Similarly, Similarly, negative(asserted low) polarity. GIC_SH_TRIGx_y would control interrupts 63:0, the next 127:64, and the next 127:64, 63:0, control interrupts would of the GIC_SH_POL have no meaning because inter- the have meaning of GIC_SH_POL no the risi occur on both rupts signal. the of GIC_SH_DUAL no meaning contents the have trig level because the signal. the signal. the contents the of GIC_SH trig level because and falling edges are used to set the interrupt register. the interrupt register. to set edges are used and falling bal Interrupt Trigger Type registers", GIC_SH_TRIGx_y. The GIC_SH_TRIGx_y. registers", Type Trigger Interruptbal . The ‘n’ in the table entries denotes that it can be any bit of a given of a bit any be can it that denotes entries table the in ‘n’ The . terrupttype supportedby the CPUinterrupt inputs. Each register in a group is 64 group bits so each reg- in is a register register group. Each in each bit Single/DualEdge (GIC_SH_DUAL[n]) Description Table 7.1 Table rst register in each group group in each register rst (OS). There are three register groups th register groups are three There (OS). l-sensitive, single-edge-sensitive, or single-edge-sensitive,l-sensitive, register denotesregister which edgeis used fo ), the trigger typecontrol registers ( Polarity conjunction with one another to define the with one another conjunction can have either positive (asserted high) or same bit of each register. each register. bit of same from the GIC to the VP, allof are the interrupts interrupts are driven fromthe). When GIC to theVP, Trigger (GIC_SH_TRIG[n]) GIC_SH_POLx_y Table 7.1Triggering and Table Sensitivity, Edge Polarity, Interrupt Selecting GIC_SH_DUALx_y registers (
0 1 0 Interrupt single edge tr is 1x 1 1 0 1 Interrupt single edge tr is Interrupt dual edge triggere is 1 0 x Interrupt level is sensitive 0 0 x a sensitive level is Interrupt positive, level-sensitive signalsthis as is the in Forsingle-edge signaling, the Register Interface Register "Glo four of up made is group register typetrigger The interrupt corresponding the configures register the in bit each Setting sensitive. edge or level to set be can type trigger esponds to an interrupt. So for a give for a So the interrupt. of to system. Each bit each register an corresponds the boot code for the operating system figuration. •type register group Trigger • Edge typeregister group •group register Polarity by one represented is interrupt source Each The fi sources. interrupt controls 64 ister so on. Since there can be 256 interrupt sources there are 4 registers in each gr registers sources there are 4 256 interrupt be there can on. Since so from8, 16 to256. sources of the interrupt Each leve be either can sources of these any trol edge is ignored. For double-edgedsignaling, both therising These three registers work in These acteristics would be defined as shown in shown as defined be would acteristics be but must the register, ters ( Polarity 7.2.4.1 Register Group Type Trigger (GIC_SH_POL[n]) MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
companion doc- companion rising edge toggle and set- SH_POLx_y. This register This SH_POLx_y. (GIC_SH_POLx_y) inthe I6500 Registers I6500 should be set. For more informa-should For more be set. em Programmer’s Guide, Revision 1.00 bit configuresthe correspondingbit inter- Global InterruptDual Edge Registers Polarity Registers", GIC_ l sensitive.For example, to set theinterrupt source 64to register group has no effect if the edge type was set to dual set ifthe edge type was grouphasregisterno effect ource bitconfiguresource thesource to bit in this register group each bit edge. Setting or dual single (GIC_SH_TRIGx_y) in the (GIC_SH_TRIGx_y) itive, bit0of the second Global Dual Edge register Global InterruptPolarity Registers // trigger bits for interrupt sources 0 - 63 0 - sources interrupt for bits // trigger address be uncached must NOTE: // registers. companion document. ource to betodual ource edge andclearingit it configures to be single edge.For MIPS64® I6500Multiprocessing Syst sensitivity of theSetting source.each of four "Global of four "Global Interrupt C_SH_TRIG C_SH_TRIG register (GIC_SH_TRIG127_64) must be uncached address // NOTE: itit configures to be activelow. I6500 Registers Global Interrupt Trigger Type Registers Type Trigger Interrupt Global companion document. #define GIC_SH_TRIG63_0 0x0180 0x0180 GIC_SH_TRIG63_0 #define for base address the GIC from offset // GIC_BASE_ADDR a1, dli 0x0000000080000000 a0, dli the GIC of address base virtual // load (bit 31) 31 source // interrupt a0, GIC_SH_TRIG63_0(a1) sd sensitive) // (edge I6500 Registers edge sensitive. For more information,edge sensitive.For more therefer to ting clearing it configure it to be falling edge toggle.fallingbeedgetoThis configure it clearingitting group is used to determine the polarity high, rupt and clearing to be active theIf interrupt is single-edge-sensitive,then setting the s Register Interface Register Thisedge The groupregistertype register made is up of four "Global DualEdgeGIC_SH_DUALx_y. Registers", trigger if the effect has no and edge sensitive is set to section previous the in described type used if the trigger is group can be either The edge type set to level sensitive. is type configures the corresponding interrupt configures s the corresponding example,to setinterrupt 64to source dualedgesens (GIC_SH_DUAL127_64) shouldmore information, For be set. refer tothe CodeEdge Example Type followingThe code exampleprograms interruptsource 31 tobe dual-edge sampled. dual for the GIC base address // offset from 0x0200 GIC_SH_DUAL63_0 #define 0 - 63 sources interrupt bits for registers address of the GIC // load virtual base GIC_BASE_ADDR a1, dli 31 (bit 31) // interrupt source 0x0000000080000000 a0, dli // Dual GIC_SH_DUAL63_0(a1) sd a0, Interface Register polarityThe register group madeis up (GIC_SH_DUALx_y)in the edge sensitive bit0 of the second GI the to refer tion, ument. Code Example Type Trigger followingThe code exampleprograms interruptsource 31 tobe edge-sensitive. to be edge sensitive and clearingitconfigures it to be leve 7.2.4.2 Register Group Edge Type 7.2.4.3 Register Group Polarity Type 130
131 external interrupt pins external and interrupt 0x08F8 GIC_SH_MAP254_PIN 0x08F4 GIC_SH_MAP253_PIN 0x08F0 GIC_SH_MAP252_PIN 0x08FC GIC_SH_MAP255_PIN 0x08EC GIC_SH_MAP251_PIN AP_VP— maps the interrupttospecific a VP number. 255 0x3FE0 GIC_SH_MAP255_VP 254 0x3FC0 GIC_SH_MAP254_VP 253 0x3FA0 GIC_SH_MAP253_VP 251252 0x3F60 0x3F80 GIC_SH_MAP251_VP GIC_SH_MAP252_VP terrupt source. The mapping of terrupt source. The mapping External Interrupt Offset RegisterName //polarity bits for interrupt sources 0 - 63 0 - sources interrupt for bits //polarity address be uncached NOTE: must //registers . Table 7.2 fic input specificon a VP is controlled by the setting2registers. of GIC_SH_MAP8_VP - GIC_SH_MAP8_VP - GIC_SH_MAP8_PIN - GIC_SH_MAP8_PIN GIC_SH_MAP247_VP GIC_SH_MAP247_PIN Table 7.2 Table Interrupts on External Based Mapping Register 0x0520 0x0518 GIC_SH_MAP6_PIN 0x0514 GIC_SH_MAP5_PIN 0x0510 GIC_SH_MAP4_PIN 0x05000x0504 GIC_SH_MAP0_PIN0x0508 GIC_SH_MAP1_PIN GIC_SH_MAP2_PIN 0x08E0 0x08E4 GIC_SH_MAP248_PIN 0x08E8 GIC_SH_MAP249_PIN GIC_SH_MAP250_PIN 0x051C GIC_SH_MAP7_PIN 0x050C GIC_SH_MAP3_PIN 0x08DC 0x3EC0 - 0x3EC0 dli a1, GIC_BASE_ADDR a1, GIC_BASE_ADDR dli 0x0000000080000000 a0, dli a0, GIC_SH_POL63_0(a1) sd (bit 31) source 31 // interrupt the GIC of base address virtual //load for 31) // (high/rise #define GIC_SH_POL63_0 0x0100 0x0100 GIC_SH_POL63_0 #define for base address the GIC from //offset 7 0x20E0 GIC_SH_MAP7_VP 6 0x20C0 GIC_SH_MAP6_VP 5 0x20A0 GIC_SH_MAP5_VP 01 0x20002 0x2020 GIC_SH_MAP0_VP3 0x2040 GIC_SH_MAP1_VP 2484 0x2060 GIC_SH_MAP2_VP 249 0x3F00 0x2080 GIC_SH_MAP3_VP 250 0x3F20 GIC_SH_MAP248_VP GIC_SH_MAP4_VP 0x3F40 GIC_SH_MAP249_VP GIC_SH_MAP250_VP the registers that themcontrol is listedin •GIC_SH_MAP_PIN Global — mapsInterrupt Mapinterrupt to to a specific signal Pin on a Register, VP. in external each each There of these registersis one of for The routingThe of interrupts toa speci • Global GIC_SH_MInterrupt Map to Processor register, Polarity Type Code Example Code Type Polarity followingThe code exampleprograms interruptsource 31 for activehigh or rising edge: 8 - 2478 - 0x2100 External Interrupt Offset Register Name 7.2.5 Interrupt Routing MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
view theRootof invirtu- Number Core3, VP0 Core3, VP1 Core3, VP2 Core3, VP3 Core3, VP0 Core4, VP1 Core4, VP2 Core4, VP3 Core4, VP0 Core5, VP1 Core5, Core5, VP2 Core5, VP3 Core5, Core and VP Core the interruptsin the system, between . These registers external map each em Programmer’s Guide, Revision 1.00 12 13 14 15 16 17 18 19 20 21 22 23 ore, and 16 external interrupts, where external interrupt where external interrupts, 16 external and ore, rtualized mode, as well as the well mode, as as rtualized tion, refer totion, refer the Global InterruptMapto VP registers based on the number of VP’s per core. For example, if if example, For core. per VP’s of number the on based P_VP Field to Core and VP and Number Field to Core P_VP the system, the mapping would be as follows: companion document. bit field which allows each external interrupt to be mapped to up to a maxi- mapped be to which externalallows each interrupt field bit MIPS64® I6500Multiprocessing Syst to VP (GIC_SH_MAPi_VP) Registers", to Number MAP_VP Bit e system. The ‘i’ indicates the number of The the number ‘i’ indicates system. e Core0, VP1 Core0, VP2 Core0, VP3 Core0, VP0 Core1, VP1 Core1, VP2 Core1, Core2, VP2 Core2, VP3 Core2, Core1, VP3 Core1, VP0 Core2, VP1 Core2, Core and VP Core I6500 Registers 0VP0 Core0, 1 2 3 4 5 6 7 8 9 11 10 MAP_VP Bit Table 7.3 Table of MA Mapping Physical shows the physical mapping in the system. Note VP of number and the MAP_VPactual core fieldthe to The following example shows a system with 2 cores, 2 VP’s/c 2 cores, with system a shows examplefollowing The 4 is mapped to core 1, VP1. 16 and 256. Each register contains a 24- contains Each register 256. 16 and informamore For (6 cores x 4 VP’s/core). mum24 of VP’s (GIC_SH_MAPx) inthe Table 7.3 thatthe encodingthis of fieldfixedand is not changedoes mode. alized there are two VP’s per core and two cores in and two cores per core two VP’s are there interruptsource specificto a VP in th • 0 in core MAP_VP bits 0 and 1 wouldrepresentthe two VP’s • MAP_VP bits 3 would2 and not be used • 1 in core MAP_VP bits 5 would4 and representthe two VP’s • Allotherbits in the MAP_VP field are unused Notethat thismapping scheme represents theview in non-vi Register Interface Register "Global There Interrupt Map are 256 7.2.5.1 Mapping an Interrupt Source to a VP 132
133 VP0 VP1 VP0 VP1 CORE 0 CORE 1 CORE individual interrupt can interrupt can individual of 256registers, one per the first example, external external the first example, rrupt pin on a core. The ‘i’ indicates the on rrupt pin to be mapped. external interrupt are interpreted. In External InterruptController (EIC) d 16 externalinterrupts. In Hence there are a maximum are Hence there 0 rmation on how the 24-bit MAP_VP field is organized, refer refer is organized, field MAP_VP 24-bit the how on rmation 123456789 t pin of a given VP. There are 256"Global Interrupt Map toPin Registers" t pinofgiven a VP. p each external interrupt to a specific inte interrupt to a specific each external p rrupt pin 3 of coreVP 1, 1. GIC contains a 6-bit field which allows each 6-bit field which allows a contains ng each external interrupt to a particular VP as ng to described above, each each external interrupt 10 Hardware Mapper Hardware External Interrupts External GIC_SH_MAP4_VP 11 Figure 7.3 Figure 1 a Core 1, VP to 4 Interrupt External of Mapping Example 121314 , the , GIC_SH_MAP4_VP is registerprogrammed with a value of 0x00_0020to select Core 1, VP 1 as . 24’b0000_0000_0000_0000_0000_0010_0000 Figure 7.3 Table 7.3 15 In numberof the interrupts inthe system, between8 and 256. the destination VP for external interrupt 4. For more info more 4. For interruptexternal VP for destination the to Interface Register mappi addition to In also be mapped to a specificinterrup (GIC_SH_MAPi_PIN) used to ma interrupt. Each register interrupt. Each typeinterruptThe of mode determineshow the interruptpins mode, interrupt each levels. In non-EIC encoded up value to 64 different that can decode 6-bit field is an the mode, individual pin anis interrupt, allowing for total a of six interrupts. 1 — Non-EIC Example Mode Configuration Interrupt an followingThe examples show a system with 2 VP’s/core interrupt4 is mapped tointe 7.2.5.2 Mapping an Interrupt Sourceto a Specific Processor Pin MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
VP0 VP1 VP0 VP1 CORE1 CORE 0 CORE SI_Int[5] SI_Int[4] SI_Int[3] SI_Int[2] SI_Int[1] SI_Int[0] SI_Int[3] SI_Int[2] SI_Int[1] SI_Int[0] SI_Int[5] SI_Int[4] SI_Int[5] SI_Int[4] SI_Int[3] SI_Int[2] SI_Int[1] SI_Int[0] SI_Int[5] SI_Int[4] SI_Int[3] SI_Int[2] SI_Int[1] SI_Int[0] the first example, external external the first example, specific VP up to 24 in the sys- 24 in the to up VP specific of 0x03, which selects interruptpinselects which 0x03, of em Programmer’s Guide, Revision 1.00 d 16 externalinterrupts. In it 31of the GIC_SH_MAP4_PIN registerto is set 1 to bit in this field represent a bit in this field represent Indicates non-EICmode 0 0 0 0 0 123456789 register is programmed with a value a withprogrammed is register to 0 to indicate non-EICinterrupt mode. of core VPof interrupt 1, 1, level15. MIPS64® I6500Multiprocessing Syst MAP[5:0] = 6’b000011 5 for the core/VPmapping this of register. GIC GIC_VL5_CTL Hardware Mapper Hardware 10 External Interrupts External Table 7.3 GIC_SH_MAP4_VP GIC_SH_MAP4_PIN , the GIC_SH_MAP4_VPprogrammedthe is register , toselect Core VP 1as the 1, destinationVPfor exter- 11 12 1314 Figure 7.4 Figure In 3 of the VP selected by the GIC_SH_MAP4_VP register. B theVP3 of selected bythe GIC_SH_MAP4_VP register. indicate the externalinterrupt correspondstoaninterrupt and notanNMI. Note thatthefieldis an MAP encoded valueand represents a binaryvalue for interrupt pin of3 the VP. Bit0 of the GIC_VL5_CTL register is set 2 — EIC Mode Example Configuration Interrupt an followingThe examples show a system with 2 VP’s/core interrupt4 is mapped tothe interrupt pins nal interrupt 4. Note that this is not an encoded value. Each value. encoded an is not this that Note 4. interrupt nal tem. Refer to Refer tem. The MAP field of the GIC_SH_MAP4_PIN of the MAPfield The Figure 7.4Figure Mode — Non-EIC 3 Int VP 1, 1, 4 to a Core Interrupt External Mapping of Example 1 24’b0000_0000_0000_0000_0000_0010_0000 23 31 31 15 134
135 VP0 VP1 VP0 VP1 CORE1 the GIC that are shared by that are shared the GIC CORE 0 CORE SI_Int[5] SI_Int[4] SI_Int[3] SI_Int[2] SI_Int[1] SI_Int[0] SI_Int[3] SI_Int[2] SI_Int[1] SI_Int[0] SI_Int[5] SI_Int[4] SI_Int[5] SI_Int[4] SI_Int[3] SI_Int[2] SI_Int[1] SI_Int[0] SI_Int[5] SI_Int[4] SI_Int[3] SI_Int[2] SI_Int[1] SI_Int[0] corresponds to externalinterrupt 15. presents a specific VP up to 24 in the to VP up a specific presents 001111 lue in this field represents one less than the actual one less represents field lue in this interrupt mode. In this mode, the interrupt level sent to level sent to interrupt the mode, this In mode.interrupt rammedwith a valueof 0x0E, which routestheencoded ed throughseveraled inregisters AP4_VP register. isIt important to notethat whenAP4_VPpro- register. Indicates EIC mode 0 0 0 0 1 123456789 the actualinterrupt describedlevel as above. indicates the value on the interrupt bus on the interrupt indicates the value encodedEach value.bit in this field re MAP[5:0] = 6’b001110 5 groupsfor enabling,disabling and pollinginterrupts. of GIC GIC_VL5_CTL 10 Hardware Mapper Hardware External Interrupts External GIC_SH_MAP4_VP GIC_SH_MAP4_PIN , the GIC_SH_MAP4_VPprogrammedthe is register , toselect Core VP 1as the 1, destinationVPfor exter- 11 12 1314 Figure 7.5 Figure 24’b0000_0000_0000_0000_0010_0000 In The enabling, disabling and pollingconfigurenabling,is disablingof interruptsand The all VP’s. all VP’s. There registers are 4 shared • Enabling an interruptusing the "GIC Set Mask Registers",GIC_SH_SMASK nal interrupt4. Notethat thisis not an system. MAPThe field of the GIC_SH_MAP4_PIN register is prog grammingGIC_SH_MAPi_PINthe registersin EIC mode, theva EIC interruptlevel.In this case, a value of 0x0E represents interrupt level Bit15. 31 of the GIC_SH_MAP_PINreg- is set to 1 toister indicate theexternal interrupt corresponds to an interrupt andnot an NMI. EIC indicate to 1 to set is register GIC_VL5_CTL the of 0 Bit a VP is 6-bitencoded valuebetweenthe target 0 and63, with 0 meaningnointerrupts. of a 6’b001110 this value example, In than one less is the register value in The interruptlevel of 15to selectedthe VP by the GIC_SH_M 1 23 31 31 Figure 7.5 Figure Mode EIC — 15 Level Int VP 1, a Core 1, to 4 Interrupt External Mapping of Example 15 7.2.6 Enabling, Disabling, and Polling Interrupts MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
source bit enables the inter- bit enables source ding interrupt is disabled. register group. Each register in a in a register register group. Each em Programmer’s Guide, Revision 1.00 the actual number of interrupts may be ed by reading the NUMINTERRUPTS field of field by reading the NUMINTERRUPTS ed sources there are 4 registers in each there group. are 4 registers in sources ite-only register. Setting the ite-onlyregister. interrupts.made It is up of "GIC Set MaskRegisters", rst register in each group would control interrupts sources interrupts control would group each register in rst If it is clear it the correspon is If upt state using "GIC Mask Register", GIC_SH_MASK "GIC Mask Register", upt state using ed to disable external interrupts. The GIC supports a maximum of 256 exter- of 256 a maximum The GIC supports external interrupts. to disable ed determine if anexternal interrupt is enabled. madeIt is theup of following MIPS64® I6500Multiprocessing Syst t source is represented by one bit in each in one bit by t represented source is xedvalue configured buildat time, so registers are read-only. are read-only. registers
er of system interrupts can be determin be can systeminterrupts of er
esponds to an external interrupt. Setting a bit to one resets and disables the correspond-the disablesand resets one interrupt.to an externalSetting to a bit esponds
d so on. Since there can be 256 interrupt be 256 Since there can so on. d GIC_SH_MASK_127_64 GIC_SH_MASK_191_128 GIC_SH_MASK_255_192 GIC_SH_RMASK_191_128 GIC_SH_RMASK_255_192 GIC_SH_RMASK_127_64 less than 256. The actual numbactual The than 256. less Configurationthe "GIC Register",GIC_SH_CONFIG. Interface Register GIC register Set Maskgroup is used to enable external The GIC_SH_SMASK. For synchronizationFor GIC_SH_SMASK. purposes this is a wr rupt. Interface Register us is group register Mask Reset GIC The nal interrupts.GIC The Reset Mask register group is madeup of four write-only "GICReset Mask Registers": • GIC_SH_MASK_63_0 • • GIC_SH_RMASK_63_0 • group is 64 bits so each controls 64 interrupt sources. The fi sources. interrupt 64 controls bits so each 64 is group fi is a interrupt sources number of The • Disablinganinterrupt usingthe"GIC Registers",Reset Mask GIC_SH_RMASK •of an interr state Enable/Disable Determining the • Polling the interruptactive usingstate the "GICPending Register",GIC_PEND_MASK interrup Like the trigger registers, each 0 - 63, the next 127 an - 64 • a bitIf set the correspondingis interruptsourceenabled. is • • corr bit in these registers Each Interface Register GIC The Mask register group is used to These GIC_SH_MASK register. • inginterrupt. 7.2.6.1 Enabling External Interrupts 7.2.6.2 Disabling External Interrupts 7.2.6.3 Determining the Enabled or Disabled Interrupt State 136
137 ese bits are set by hardware hardware by are set bits ese riate VP. The hard- VP. appropriate the to rrupt register isset register If the correspond-by hardware. . interrupt level is 15. VP ternalinterrupt active.Th is If itis the clear correspondinginterrupt inactive.is GIC_SH_PEND upof the following GIC_SH_PENDread-onlyregisters. register tosendand the the VP interrupthe appropriate t to bit is set, the GIC delivers the inte the delivers GIC the set, is bit register are set, enabling all 64 interrupts. enabling register are set, . pondingbit inthe 0, VP 1, and VP the receiving 1, 0,
GIC_SH_MASK
GIC_SH_MAP_VP Figure 7.6 GIC_SH_SMASK register to set the interrupt pins for that that for pins interrupt the set to register upt occurs, the corres • External interrupt8is asserted • Allbits of the GIC_SH_PEND_255_192 GIC_SH_PEND_127_64 GIC_SH_PEND_191_128 • The core is receiving VP In the following example: the following In Register Interface Register GIC The Pending register groupis toused determine a ex if whenan interrupt event occurs. The group is made ing interrupt enable bit in the in the bit enable interrupt ing GIC_SH_MAP_PIN • GIC_SH_PEND_63_0 • ware does thisby usingthe • • a bitIf set thecorrespondingis interruptsourceactive. is When an interr When This example is shown This in example is 7.2.6.4 Polling for an Active Interrupt 7.2.6.5 Programming Example MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
0 Write-Only 0 Write-Only Software writes a value writes Software of 0x1000_000E toindicate Int[15] as theinterrupt of the destinationVP. GIC_SH_RMASK63_0 Interruptsentto VP1, interrupt15 in EIC mode. 0x0000_0000_0000_0000 em Programmer’s Guide, Revision 1.00 63 Writing to theGIC_SH_RMASK Writing register allowssoftware to reset any bitinthe GIC_SH_MASK to0 a as way to disablegiven a interrupt. Note: Software can the RMASK use Software Note: register to disable from interrupts certain this in used not is It generated. being example. GIC_SH_TRIG registers. GIC_SH_TRIG 0 0 GIC_SH_MAP_PIN 0x1000_000E is a sharedis a register used todeliver an interrupt to 31 rnal devices. The interrupt sources chosen for this purpose for this chosen interrupt sources The rnal devices. Hardware reads the GIC_SH_MAP_VPreads the Hardware andGIC_SH_MAP_PIN registers to determine thedestination andVP interrupt pin thefor interrupttoprocessed. be Write-Only ere are two fields two in the fields are ed an to clear interrupt. There ng the appropriate bits ng in the appropriate Hardware Check GIC_SH_MASK GIC_SH_SMASK63_0 0 t any other processor. Each inter-processor interrupt configured is Each inter-processor just like t any other processor. MIPS64® I6500Multiprocessing Syst 0xFFFF_FFFF_FFFF_FFFF 63 63 Writing tothe GIC_SH_SMASK Writing register allows software set any to bitin the GIC_SH_MASK to1as a way toenablegiven a interrupt. 0 0x00_0002 Read-Only Figure 7.6 Figure GIC the in Interrupts of Mapping and Masking GIC_SH_MAP_VP* Read-Only the interrupt. 23 0x00_0002 indicate to GIC_SH_PEND63_0 Interrupt8 is assertedby external hardware. Register Interface Register can interrup in the system processor Each an external interruptusing sources not beingusedby exte mustbeconfigured to be edge sensitive by setti GIC_SH_WEDGE register usedGIC_SH_WEDGEto register do this. The "Global Interrupt Write EdgeRegister", GIC_SH_WEDGE "GlobalThe Interrupt Write another processor (onlyone per system).It is also us Interruptpending status writtenby hardware based on externalinterrupt activity. 0x0000_0000_0000_0100 Software writes a Software value of writes 7.2.7Interrupts Inter-processor Write-Only 63 *24’b0000_0000_0000_0000_0000_0010 core 0, VP 1 as the recipient of as the recipient 1 0, VP core 138
139 Write-Only GIC_SH_WEDGE GIC_SH_WEDGE.INTERRUPT e) using the GIC_SH_MAPi_VP the GIC_SH_MAPi_VP using e) er into the Edge Detect hardware hardware er into the Edge Detect bit in the internal Edge Detect register, Edge Detect register, in the internal bit eated equivalently to having the edge detection detection edge the having to equivalently eated effect on the state of the state on the a direct effect has Edge register e GIC_SH_WEDGE.INTERRUPT 70 Software write 0x28 to field to bypass theinterrupt detection logic and send an interruptmessage directly by toggling register. the Edge Detect bit in a Software can set bits in the in can set bits Software register toregister bypass the interruptdetection logic andsend an interrupt message directlyby toggling in register. a the Edge Detect bit this case, kernel software writes a value of 0x28 into the rdware determinesrdware that interrupt being toggled belongs to et VP (VP1 in this exampl this in (VP1 VP et ed to be rising,falling, or dual sensitive.edge 0 0 (WEDGE) register is tr is register(WEDGE) register can be used to bypass the edge detection logic. Thus, it does not it Thus, logic. detection the edge can be used to bypass register writes the value in the WEDGE regist the value in writes register in turn sets the corresponding the in turn sets register register can be used to bypass the interruptdetection logic and assert interrupt Write Edge Write Edge Write 32 Interruptsentto the appropriate VP and interruptpin. Write Edge EDGE_DETECT Mapping Function GIC_SH_PEND Write Edge Write External Interrupts External InterruptMasking and Interrupt Detection Logic fieldshould be set to theinterrupt numbertocleared.beset or Figure 7.7Figure GIC the in Interrupts Inter-Processor Sending 63 63 ) or cleared. Setting this bit delivers an interrupt and interrupt an delivers bit this or cleared. Setting ) (delivered set being is interrupt if the determines bit shows how the shows how INTERRUPT RW Read-Only clearing thebit clears the interrupt. • The forcinginterrupt an andto be generated allowinginterrupts within for inter-processor GIC. the directly. Settingbit a in the directly. matter whetherthecorresponding interrupt configur is GIC_SH_WEDGE the into programmed is used be to interrupt the of number 1, the VP interrupt to wants 0 VP When targ to the mapped be must selected interrupt The register. register). For example, assume VP 0 wantsto toggle interrupt 40. In bypassing effectively theedge detection logic.register, Ha GIC_SH_WEDGE register. Hardware then Hardware GIC_SH_WEDGE register. 1, notVP 0. TheVP GIC routing thenlogic routes interrupt 40onto the appropriate 1 VP interruptpins. Figure7.7 A write that sets the R/W bit of the of bit the R/W sets that write A logic see an active edge. the programming of the Writ Because an active logic see the register, Edge Detect internal • The 7.2.7.1Example Programming Register WEDGE Hardware Register (not software visible) (not MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
of a proces- of a the interrupt by the interrupt register. In practical register. er is also available (read er is e difference is that the is that difference e interrupt is to be cleared. e interrupt and clear e interrupt GIC_CORE_COMPARE interrupt whenthey match. Description em Programmer’s Guide, Revision 1.00 igured and mappedlocally tothe pro- GIC_SH_CONFIG cessors in the samehave thesamecluster time ref- // Offset to base of IPI interrupts. base of to // Offset IPI. this // Clear Source number for the first IPI. for the first Source number er before executingERET theinstruction.NOTE: only l compare register, register, compare l er within each processor. Th each er processor. within processor. Thiscounterregist processor. 0280)) Address the of GIC_WEDGE_REGISTER. in the GIC and activates an the in inter-processor interrupt.inter-processor First the#defines: inis the sharedsection of theGIC memory map. The counter mustbe d is do whatever action intended for th of described the GIC in section:this the User Mode Visible Section of the GIC. Section User Mode Visible the in the processor conf GIC are and the MIPS64® I6500Multiprocessing Syst Value Value I numberand the cpu number and write it totheGIC_SH_WEDGE register GIC_SH_COUNTER 32 GIC_SH_COUNTER) registeris global to the cluster thatso all pro #define li k0, (GIC_SH_WEDGE | GIC_BASE_ADDR) | (GIC_SH_WEDGE k0, li C0_EBASE k1, mfc0 k1, 0, 10 k1, ext 0x20 k1, addiu CP0 EBase // Get CPUNum // Extract GIC_SH_WEDGE = 0x80000000 + FIRST_IPI + cpu_num ; cpu_num + + FIRST_IPI = 0x80000000 GIC_SH_WEDGE sw k1, 0(k0) 0(k0) k1, sw sor with a global counter, sor withglobal a counter, FIRST_IPI GIC_SH_WEDGEint*) (0xbbdc *((volatile unsigned • GIC_VO_WD_COUNT. 32- a bit decrementing counter, Timer Watchdog GIC tim similar to the CP0 Count/Compare is interval timer The stopped before it is set. This is donebitthebysetting of the COUNTSTOP GIC_SH_ COUNTER writing the interruptnumber to theGIC_SH_WEDGE regist The GIC also controls how devices with how devices GIC also controls The void set_ipi(int cpu_num) { // Add the enablebit,the IP first the indicating that cleared the R/W bit is the write so before number is set the interrupt Code Example of Clearing an Inter-Processor Interrupt an Inter-Processor of Clearing Code Example the Once interrupt routine shoulreceived, Example of Sending an Inter-Processor Interrupt — C Code Interrupt an Inter-Processor of Sending Example an of sending example C code following is a The cessor. There are 2 devices that are added as part •loca compares a that timer a 64 bit - Interval Timer GIC use the counter is usually setbyOS an at boot time by one only) in user mode located at offset 0 of located at offset mode user only) in erence. Counter Registers counter register ( The 7.2.8.1 GIC Interval Timer 7.2.8 Configuration Local Timer 140
141 register. register. GIC_VLi_COMPARE GIC_SH_Counter e count value equals the compare value count value equals the compare e and the Compare value is 0x1_FFFF_FFFF 0x1_FFFF_FFFF value is and the Compare sserted) by writing to the is an reached,hardware internalgenerates interrupt. BITS’ is the value in the COUNTBITS field of the field in BITS’ the COUNTBITS is the value register is used to set up the width of the width the set up to used is register terrupt is cleared terrupt (de-a is is located in the local section of the GIC memory map making the count the making map memory GIC of the section the local in is located lue between 32 and 64 bits in increments of 4. For example, 32 bits, 36 bits, 36 bits, 32 For example, 4. of increments in bits 64 and 32 between lue s can be written at any time. When th When be written at any time. can s , the , width of thecounter64-bits, is GIC_SH_CONFIG Figure 7.8 GIC_VLi_COMPARE) register. which correspondsto8G clock cycles. When thiscount For example, if the COUNTBITSfieldcontains a valueof 0x8, theoverall width of thecounterwould be: = 64 bits x 4 32 + 8 va be a can design, the counter GIC the In 40 bits, etc. Example Interrupt Based Counter in the example shown In register. register. Width Counter the Determining the followingformulaused: is derive the total widththe of counter, To x 4 32 + COUNTBITS Where: ‘32’ is the minimum width of thecounter and ‘COUNT IntheGIC design,this fielda default value has of 0x8, indicating a total counterof size 64-bits. Registers Compare ( compare register The specific to each processor. These register to each processor. specific an intervaltimer interrupt is asserted. Thein GIC_SH_CONFIG The COUNTBITS field of the of field COUNTBITS The MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
. When these two . When these GIC_SH_COUNTER Compare register Compare em Programmer’s Guide, Revision 1.00 GIC_VL_Compare register GIC_SH_COUNTER register 0 0 Software writes 0x0000_0000_0000_0000 to set the initialcount tozero GIC_VL_COMPARE 0 Software programs the programs Software 0xFFFF_FFFF_FFFF_FFFF value of with a register for a valuefor of 8Gcounts. In the GIC_SH_CONFIG register, In the GIC_SH_CONFIG hardwarethe sets value of COUNTBITS to 0x8 to implement a 64-bit counter. Hardware compares the value in value compares the Hardware with thevalue in values are equal,are values hardware internal an generates interrupt. MIPS64® I6500Multiprocessing Syst 23 This value is used to determine to used is value This the width of thecounter Hardware Compare 0x8 Hardware bitsets 1 of the register GIC_VLi_PEND further processing. for 27 24 GIC_SH_COUNTER 28 63 Figure 7.8 Figure Generation Interrupt Counter-Based of GIC Internal Example 63 63 Software writesSoftware 0x1 to the COUNTSTOP bittheGIC_SH_CONFIG of register to stop the counter before programming the register. GIC_SH_COUNTER COUNTSTOP After programmingthe a the 0 to software writes registers, COUNTSTOPbit torestart thecounter. 142
143 each processor and is used to and is used processor each r expires for the second expires the for r register local to each processor to each local register ate controlled by the Cluster Power the Cluster ate controlled by een Software and a Hardware a hang t signal t is sent to all processors in the timer. This is one mode where the inter- the where mode one isThis timer. med to be a hardware issue. Therefore, Therefore, issue. to be a hardware med interrupt to a normal instead be routed d is what happens in this mode when the what in this is mode happens reloaded the is and time starts counting boot the kernel software should reload the software should reload the boot kernel Behavior d be used in a time slicing OS. be used in a time d wing three registers. wing (default value) causes the countertocauses (default value) stop counting happens when the timer reaches 0. when the timer happens time the reaches time counter 0. distinguish betw distinguish again, all cores are reset. reset. are cores all again, ter tostopter countingwhen the VP enters debug mode. ith the value in the GIC_VLi_WD_INITIAL register. ithForthevalue inthe GIC_VLi_WD_INITIAL register. eristics of the timer. of eristics ", GIC_VLi_WD_CONFIGeach processor and to is local ", GIC_VLi_WD_INITIAL", to is local instructionor is in a low power st controlledby the follo ", GIC_VLi_WD_COUNT is a read only ", is a GIC_VLi_WD_COUNT WD_CONFIG register this register determines what register determines this This mode provides mode This a way provides to This interrupt. NMI routed to the is Interrupt Timer the hang. Usually Watchdog reboot. That soft to processor causes the the first expires time. timer the re during a software hang this was If itself does processor the expiration. the If second thus avoiding Timer, Watchdog then interrupt, it respond to the is assu not is the asserted, initial interrupt count An again interrupting each down time before being reloaded before time time a rese the expires the second when count system. interval a per-processor mode provides This not be routed to NMI. It shoul should rupt the interrupt coul where example for Table 7.4 Table Modes Timer Watchdog GIC and configures the charact and t valueof the countdown. One TripOne NMI). an (typically stops timer the and is asserted interrupt An Interval Timer (PIT) Timer Interval Watchdog Timer Count Register Timer Watchdog GIC Watchdog Timer Configuration Register Timer GIC Watchdog Watchdog Timer Initial Count Register Timer Watchdog Whenthis bitis set the count continues countingdown. that contains the curren that WAIT a is executing the processor when Controller(CPC). Setting thisbit itcauses to continuecounting down. set the timer interval. reports informationstate 0x0 0x1 Countdown Second is If the time asserted and the timer reloads. interrupt An 0x2 Programmable • The bits TYPE field in 3:1 of Clearing the WD_START bit disables the timer and when it is set it enables the timer. Writing WD_START with a 1 WD_START Writing bit disables thetimer and whenitis set itenables the timer. ClearingtheWD_START a reloadthetriggers of GIC_VL_WD_COUNTregister w • ClearingtheDebug bit (defaultvalue)causes the coun GIC Watchdog Timer Configuration Register Configuration Timer Watchdog GIC Configurationcontainsregister bits that controlTimer the functiontimer. the of GIC The Watchdog •bitGIC_VLi_ of ClearingtheWAIT • The " • The" Register Interface Register timer that is VPEach supports a Watchdog • The " Encoding Mode 7.2.8.2 Timer GIC Watchdog MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
)
reg- register RMASK Watchdog Timer Timer Watchdog GIC_VLi_SMASK register then the counter then the . In non-EIC mode,only In non-EIC . register ( register Local Interrupt Mask ) at offset 0x000C.address ) at offset Watchdog Timer Map-to-Pin Timer Watchdog SI_Int[2] this register and this em Programmer’s Guide, Revision 1.00 companion document included in the document included companion For example, if kernel software programs example, if kernel software For Watchdog Timer Initial Count Register Timer Watchdog Local Interrupt Pending pins the interruptwill be driven onto. Innon- VLi_WD_INITIAL register each time the GIC_VLi_RMASK a read only register that contains the current value the current that contains register only read a NMI Local Interrupt Set Mask Interrupt Local or (GIC_VL_WD_CONFIG)0x0090 at offset in the companion document in document includedthe release. companion register. register ( the WatchDog timer is programmed to generate a hardware a hardware to generate is programmed timer WatchDog the e counter should be disabled by clearing the WD_START bit WD_START the clearing by disabled be should counter e then reads the state of bit 0 in the reads then SI_Int[5:0] acteristicsthe of interrupt, theit uses I6500 Registers er", GIC_VLi_WD_INITIALer", andprocessorusedto to is each is set local and the countdown value loaded loaded into and value the countdown rated, hardware sets bit 0 of the Local Interrupt Mask MIPS64® I6500Multiprocessing Syst used to select one of 6 VP interrupts. interrupts. 6 VP of one select to used reloaded with the value in the GIC_ is register using the write-onlythe usingregister is register to enable the Watchdog timer interrupt, or it can set bit 0 of the 0 of bit set can or it interrupt, timer Watchdog the enable to register Local Interrupt Reset Mask Interrupt Local Watchdog Timer Config Register Timer Watchdog SMASK . ) at offset address 0x0008 to determine whether the Watchdog timer interrupt has been masked. The has been masked. interrupttimer Watchdog the whether to determine0x0008 address at offset ) ) at offset address 0x0004. Hardware at offset ) register is read-only. read-only. register is (GIC_WD_COUNT)0x0094 inthe at offset I6500 Registers SI_Int[5:0] GIC_VLi_PEND GIC_VLi_MASK WD_START bit inthe GIC_VLi_WD_CONFIG registermoreinformation, For is set. refer tothe WD_START Register Count in the GIC_VLi_WD_CONFIG register Count Register Timer Watchdog is GIC_VL_WD_COUNT Register", Count Timer "Watchdog The countdown. This register is the of release. Mapping and Masking Timer Watchdog Interface Register timer interruptis gene Once a Watchdog I6500 release. in the Registersincluded document companion Register Initial Count Timer Watchdog Interface Register Initial Count Regist Timer "Watchdog The th time first the for counter start the To interval. timer the enabled by setting the WD_START bit. For more information, refer to the enabled by setting the WD_START (GIC_WD_INITIAL) 0x0098inthe at offset EIC mode, bits 5:0 of this register are register of this 5:0 bits mode, EIC timerinterruptdrivenontobe will valueof 0x2,then the Watchdog a fieldthiswith Once hardware has determined the masking char masking the determined has Once hardware GIC_VLi_MASK more information, refer to the ( Software can affect the state of th the state can affect Software encodings 0 - 5 are valid. InEIC mode, encodesthe VP this field tosupport up to 64 interrupts. For example,kernelsoftware programs if this timer interrupt correspondsto interrupt 32. This encodedvalue field is then withvalue a of 0x20, then theWatchdog driven onto ( Software sets bit 0 of the bit sets Software at offset address 0x0010andthe at offset reset, the reset cannot be maskedbythe ister to disable Watchdog timer interrupts. Note that when that Note interrupts. timer Watchdog disable to ister register at offset address 0x0040register at offset to determine which 144
145 0 0 Write-Only Watchdog Timer Watchdog pins Watchdog TimerWatchdog Write-Only 0 NMI GIC_VLi_RMASK Interrupt sent toSI_Int[n] or NMI thepins of VP. s the appropriate signal. the s 31 If necessary, software can set bit 0 of software can set If necessary, thisregister to disable Watchdog timerinterrupts. the DEBUG bit of the the 1 0 0 1 GIC_VLi_WD_MAP 31 t is cleared, counting is stopped. Note that the DM bit of that Note stopped. is cleared, counting is t Write-Only this register and assert this register and Software writes the Software GIC_VLi_WD_MAPwrites register to Hardware0 of set bit the register. MASK determineon whichSI_Int[5:0] or to drive the Watchdog interrupt.timer Hardware reads to drive the Watchdog accomplished by clearing the WAIT bit of the bit clearing the WAIT by accomplished s no effect on the Watchdog timercounting process. on nothe Watchdog s effect Hardware Check Hardware accomplished by clearing GIC_VLi_MASK GIC_VLi_SMASK 0x0090.When thisbit is cleared, countingis stopped, including whenlow Software writes bit0 of this enable Watchdog register to timerinterrupts. 31 31 ) must ) be set to place thedevice in debug mode. DM 0 1 Read-Only a the WAIT instruction. the WAIT a DEBUG register ( Read-Only Figure 7.9 Figure GIC the in Mapping and Masking Interrupt Timer Watchdog Debug register located at offset address at offset located register register located at offset address 0x0090. When this bi this When 0x0090. address offset at register located GIC_VLi_PEND power modeentered is vi Config Watchdog Timer and Mode and Debug Timer Watchdog timerUnder operation certain whileconditions, the I6500 kernel software mayMultipro- wanttosuspend Watchdog can be cessing System is in debug mode. This If theIf DEBUG bitset, enteringdebugis mode ha Watchdog Timer and Low Power Mode Power and Low Timer Watchdog timerUnder operation certain whileconditions, the I6500 kernel software mayMultipro- wanttosuspend Watchdog cessing System is in low power mode. This can be Config the CP0 31 Hardware sets bit 0 of this register to timer indicate thata Watchdog interrupt has occurred. MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
mode, each bit mode, of each of the local . . . ing the boot exception vector ing es the whether a given local inter- a given local whether the es pt Pending bits in the CP0 Cause Cause CP0 the in pt Pending bits at maps the local interrupt to a spe- to a interrupt the local at maps em Programmer’s Guide, Revision 1.00 er indicates the status er this register. givenIf a bit set, is interrupt are dis- thisregister. status for the local each of register manages the mask status manages themaskreset function for eachof the local is mapped to a specific interrupt pin using the 6-bit MAP the 6-bit using pin interrupt specific a to mapped is ecimal). For vectored interrupt (non-EIC) For vectored interrupt ecimal). LocalInterrupt Routingand Masking LocalInterrupt Routingand Masking LocalInterrupt Routingand Masking cause the core to soft boot us cause ). This write-only register allowsthe programmer to dis- dog timer interrupts described in the previous section. The section. previous in the described interrupts timer dog so provides the ability to mask interrupts using the following using mask interrupts to the ability provides so ). This read-only regist read-only This ). ). This read-only register indicat read-only register This ). ed as describedined theas following subsections. bit (31) of the corresponding register is set, indicating that the interrupt the that is set, indicating registercorresponding the of (31) bit each local interrupt source to Interru interrupt source each local GIC_VL_RMASK gister for each local interrupt source th each local interrupt source for gister MIPS64® I6500Multiprocessing Syst GIC_VL_PEND atoccur withinthe I6500 Multiprocessing System. routingThe and masking of GIC_VL_MASK to interrupt processing. processing. to This interrupt eld indicates interrupt 33 (d eld There are two bits, MAP_TO_PIN and MAP_TO_NMI that control the type of input that of input type the control that MAP_TO_NMI and MAP_TO_PIN bits, are two There NMI bit in the CP0 Status register. This in essence will essence in This register. in the CP0 Status bit NMI as the start of the interrupt of routine. the start as of theMAPof field corresponds to one of six interrupt pins. field of this register. This field contains the encoded valueof the the interrupt field contains This (0 - 63) in EIC mode. example,For a this register. field of in the MAP fi 0x20 of value register of the core. If the MAP_TO_PIN register interrupt actual the pin, an interrupt to mapped is source rupts has been enabled prior rupts has interrupts listed at the beginning of thesection entitled abled for the correspondingabledfor the interrupttype. Thisregister interrupts listed at the beginning of thesection entitled able oneor more of the local interrupts by setting thebits of interrupts listed at the beginning of thesection entitled Register Interface Register core al the I6500 routingof interrupts, to the additionIn registers: •( register Pending Interrupt Local • thistheMAP_TO_NMI bit (30)of register If is set, thisindicates thatthe interruptwill source be mapped to the There is a Local Interrupt Map-to-Pin Re Local There is a cific input on the processor. processor. the on input cific Only one of these bits can be set at any one time for each interrupt. time set at any one be bits can these interrupt source. Only one of the to is assigned • registers map The local MAP_TO_PIN • LocalReset Mask register ( Interrupt If this bit is set by the kernel, entering low power mode has no effect on the Watchdog timerthis If countingbitis set by the process.kernel, enteringlow power modeon no has the Watchdog effect events Local interrupts are internalth local interrupts is handled in a similar manner to the Watch to manner a similar in is handled interrupts local follows: as interrupts are defined local • Count/Compare interrupt • interrupt timer CPU Local • interrupt counter Performance •software interrupts Two •Debug Fast Channelinterrupt (FDC) mask can be routed and of these interrupts Each • Local Interrupt( Mask register 7.2.9.2 Local Interrupt Masking 7.2.9.1 Local Interrupt Routing 7.2.9 Local Interrupt and Masking Routing 146
147 register register are each assigned a each assigned are bit. The GIC can be e local interrupts e to the shared section the shared to register VZP GuestID. This GuestID . ively, since the number of number since the ively, assigned a GuestID for this assigned a companion document includedcompaniondocument lows the programmer to enable to lows the programmer = or 1) non-virtualized Local Interrupt Local Interrupt Mask Local InterruptPending VZE GIC_CONFIG tion of th for each been added for virtualization should be should virtualization for added been number of sources field beenhas added be disabledbybeappropriate settingthe bitsof sources, is assigned a assigned sources, is I6500 Registers I6500 Local Interrupt Set Mask GIC_CONFIG. GuestID al interrupt source. Alternat source. interrupt al register. If a given bit is set, interrupts are enabled for for enabled are is set, interrupts bit given a If register. s must s be ignored(loadsreturn are dropped). 0s, stores is external interrupt source ) at offset address 0x000C. atoffset ) ). This write-only register al write-only register ). This implementation may chooseto group external interrupt fields toinitializingprior interruptsinthe system. Local Interrupt Routing andMasking. register manages func the set mask register hardware of sets the corresponding the ared and VP-Local sections that have have that sections VP-Local and ared GIC_VLi_RMASK GIC_VL_SMASK rmediate configuration such that some configuration such that rmediate virtualized ( in either operate e per-external-interrupt source e per-external-interrupt ternal Source Interrupts register ( maintained in the fully populated root context. expected to program these expected to program these registers. = 0) modes. = ) at offset address 0x0010. Conversely, interrupts can Conversely, 0x0010.address atoffset ) rrupt has been masked. If a bit in this register register this in bit a If masked. been has interrupt the whether determine to 0x0008 address offset at ) ) at offset 0x0004.address ) at offset then Hardware reads thestateof the VZE one or more of the local interrupts by setting the bits of this the bits setting by interrupts of the local more or one This the type. corresponding interrupt listedatthe beginning of thesection entitled considered reserved and read-only. and considered reserved bothin 0) EIC and non-EIC modes. Local InterruptReset Mask GIC_CONFIG. GIC_VLi_PEND GIC_VLi_MASK GIC_VLi_SMASK programmed by kernel software to When any of the local interrupts occurs, of occurs, the local interrupts any When is set, the corresponding interruptis ignored. Local interrupts can be enabledby setting bitsthe appropriate of the The developer may choose to assign one GuestID to each extern each to one GuestID to assign choose may developer The interrupt sources may be large (up tointerrupt256 maysourcesinterrupts), an be large provide an inte GuestID, or by sources purpose. TheHypervisor is Each external a source, logicalinterrupt or Each groupof external interrupt GlobalInterruptPin Map to maybea maximum of 8-bits.Th Register Interface Register 1 in the logic a byindicated as support Virtualization provides GIC I6500 The The I6500 The MPS supportsI6500 virtualization andtheconcept guest of and root modes.The following list shows someof the changes madeEach theto GIC to supportVirtualization. • Local InterruptSet register Mask ( •Core-Local state is Any • The GIC interfaceto the guest context inthe core, known as the Guest Interrupt Bus, is always inactive (always • guest accesse all virtualization, for the core is enabled If In the GIC non-virtualized mode, the following rules apply: rules following the mode, non-virtualized GIC the In •Sh the in fields any or registers, Any Each of the registers listed in the above examples can be found in the in found be can examples above the in listed registers the of Each ( ( ( the ( in the release. in the 7.3.2 Routingof Guest Ex 7.3.1 Mode Enabling Virtualization MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 7.3 Support Virtualization
each Core- each Such configuration Such CP0 register field. ID a subsetGIC registers of ered external interrupts. a 64-interrupt system where where 64-interrupt system a remaining sources are divided are sources remaining GuestCtl1 em Programmer’s Guide, Revision 1.00 t. The individual interrupts are repre- The individual t. manage all 256 possible interrupts. manage all stbe qualified interruptsthe to avoideffecting 3_0, where n = 63 and m = 0. As such, for all 0. As = and m 63 n = 3_0, where interrupt's type (e.g., polarity, edge/level etc), edge/level polarity, (e.g., interrupt's type companion document included in included document companion Registers I6500 physical core. These resident GuestIDs will be These resident GuestIDs will core. physical PI) and clear EDGE regist EDGE clear PI) and D register. For example, in For example, register. D assigned a GuestID. An example intermediate solutiona An example intermediate GuestID. assigned ing of interruptsGIC are registers etc.subset Since a Ds and theremaining sources are divided upinto groups t software may require access to require access t software may e case where a case physicalwhere e GuestID register does not exist for assigned GuestIDs, while the GuestIDs, assigned n-zero a guest. GuestID specifies Inaddition, Software Access to GIC registers Access Software or notor a physicalGuestID registerexiststhe ('1' in bit) or not('0' in bit) the ere are four registers of each type to of each type registers four are ere MIPS64® I6500Multiprocessing Syst for the specification of each the specification of for ng scheme.This vector is 256 bits wide, which theis maximum numberof r example, GIC_SH_PEND_6 w need to be directly accessed by gues by directly accessed be w need to e GuestID resident inthe ss than 256 external interrupts. than 256 ss first 32 interrupts [31:0] 32 interrupts first uting etc. However, the gues the etc. However, uting group with a GuestID. with a group with theintended guest. One guestID for group 8interrupts of [63:56] One guestID for group 8interrupts of [55:48] One guestID for group 8interrupts of [47:40] One guestID for group 8interrupts of [39:32] One guest ID for each of the One 256'h00000000000000000000000000000000000000000000000001010101FFFFFFFF registers using the n_m nomenclature, th the n_m nomenclature, registers using • (I Inter-Processor-Interrupts to cause - GIC_SH_WEDGE for reading interruptpending information, masking and clear associated are not that registers listed belo shared section The sented using the n_m nomenclature, of interrupt. Fo = the range n_m where shared by multiple guests and root, any guest-specific reads/writes mu reads/writes guests and root, any guest-specific by multiple shared Local section in the GIC is aware of th aware is in the GIC Local section brought into the GICviathe SI*_GID input ports and thisis equal to thecorescore uration registers. configuration requires access to the GIC the root software (hypervisor) only general, In for thatbits correspondingexternal interrupt source. Inth the release. By convention,a GuestID 0specifies of root, whilea no are registers to, include, but not limited ro assignment, interrupt Core external interrupt sources supported by the I6500 GIC. However, only the relevant lower indexed bits will take effect effect take will bits indexedlower the relevant only However, GIC. I6500 the by supported sources interrupt external GIC is configured for le the when bitinthisvectorEach whether represents that external interruptsource, an external interrupt sourcethe next GuestID value from whatever the uses lower GuestI physical a has which source interruptexternal indexed Software can determinethe GuestID grouping scheme configuredatbuild time by reading this 256-bit GuestID grouping vector registers. For more information,torefer the ID Group Configuration Registers in the 0x0098 through 0x0080 offsets at (GIC_SH_GID_CONFIG) To facilitatethe configurationGuestID of grouping, a 256-bit wide vector is providedTo whichneedstoset at build be groupi GuestID the required per time as up into groups 8,of each the 1st 32interrupt sources are individually assigned GuestI 8,of the 256-bit GuestID grouping vector would be configuredwith thevalue shownbelow: GuestID, while the remaining remaining are grouped,whilethe GuestID, group is and each is one where the 1st 32 interrupt sources are individually are individually sources interrupt 32 the 1st one where is 7.3.3 Qualification of Root or Guest 148
149 -Local section. -Local section. ster is added to each Core- is ster rnal interrupt source. Guest rnal al interrupt source valid vec- valid interrupt source al licated for guest context for guest reg- licated gister to each Core gister ounter value that is commonto root In addition, value registersthe compare In ed to be directly accessed by guest soft- to be directly accessed ed st access to this register, but it is safe to do but it is safe this register, to st access register and also cannot disable the counter by cannot disable and also register for guest access to this register, but it is safe to but it is safedo so. to this register, access for guest ompareregister bits are rep directly set its compare sampling after value its offset sters contains one bit per exte per contains one bit sters of this of chapter. value, a GIC_VLi_COFFSET regi a GIC_VLi_COFFSET value, GIC_SH_COUNTER identified reason for gue identified reason field. bits for external interrupts. r-external-interrupt source valid vector. source r-external-interrupt a counter which is offset by an n-bit(set counterwhichto 8 by default) a is offset value is used for itesto the WEDGE register qualifiedare by gatingthis drivingof per-exter- each core to set compare independently. independently. set compare each core to to program this offset value register. toprogram valuethisregister. offset gister, theencoded interruptnumber gister, valuegets decoded outto drive the per- nd these are added as GIC_VLi_Compare re are added nd these rrently no identified reason no identified rrently COUNTSTOP Compare Timer Interrupts Timer Compare plicated VP-Local section registers may ne plicated VP-Local section registers may GIC_SH_CONFIG counter value. so. where i= 0 towhere 31, themax numberof configured cores. of these registers is described in sections Each the previous The following guest context re following guest The accesses to each of these per external interrupt source bits are qualified with a per-extern a with qualified bits are source external interrupt per these of each to accesses to guest the WEDGE re writes On tor. Guest source wr external logic. interrupt nal-interruptsource logicwith thesamepe ware. •guest GIC_VLi_PENDfor software- to determine which local guestpending.interrupts are • GIC_VLi_MASK - for guest software todetermine which localguest interrupts are masked. • GIC_VLi_SMASKfor guest- software to set mask bitsfor local guest interrupts. • GIC_VLi_RMASK - for guest software toclear localmask bits for guest interrupts. • GIC_VLi_Compare - This allowsthe to guest software Apart from the WEDGE register, all of the above listed regi all of the above listed register, WEDGE the from Apart • currently no is - there GIC_SH_DUALn_m writing to the For guest contexttheuse of Count-Compartimer e interrupts, the global c (CC) and all guests cannot be used. Therefore, guests and all offset this guest counter specify each guest context. To context a for the guest are replicated • GIC_SH_TRIGn_m - to allow guest toset forEDGE to causing IPI other cores. •cu is - there GIC_SH_POLn_m expected and the root is Local section • GIC_SH_PENDn_m - todetermine which interruptsexternal pending.are • GIC_SH_MASKn_m - to determine which external interruptsmasked.are • GIC_SH_SMASKn_m- to set mask bits for external interrupts. • GIC_SH_RMASKn_m - to clear mask This allows guest This and allows root contexts in facilitatethis guest context interruptrouting, theCount-C To repli- register GIC_VL_COMPARE the also and registers GIC_VL_[PEND/MASK/SMASK/RMASK]_MAP isters cated for guest context. to write to allowed is not software guest the Note 7.3.4 Guest Mode Count- MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
. interrupts without interrupts register. In virtualized register. strictions for guest accesses for guest accesses strictions = 0), this GEN control bit is bitcontrolGEN 0), this = field. andthe interruptupdate con- VZE Description GNMI ode virtual address space. Within this Within virtual address space. ode GIC_VLi_[PEND/MASK/RMASK/ are read-only. Currently, the only reg- the only Currently, are read-only. sense to make them available to user- available to make them to sense em Programmer’s Guide, Revision 1.00 generated WatchDog generated WatchDog ved for future ved extensions. future for Reser GIC_VLi_WD_CONFIG GIC_VLi_WD_[MAP/CONFIG/COUNT/INITIAL] GIC_SH_CONFIG GIC_SH_CONFIG R Counter. Shared alias for GIC Read-only Type GEN = 1, there are further re 1, = GEN 1) if the root= softwareGEN sets = 1, then the guest context. The root may allow the guest to utilize this single this the guest to utilize allow may root The context. mode software can initialize = 1 and = 1 and VZE e Section Register Map Register Section e register: VZP Visible Section of the GIC Section are follows: calculated as Visible register. ftware is given direct access to them. to given direct access is ftware ds. These further restrictions are as follows, restrictions are as further ds. These so that it may be mapped to user-m call. The aliases The for these registers aliases call. that are read so often that it makes it often that so are read that fields are read-only 0 for guest. are read-only fields og timer, the guest may handle the guest the og timer, gatedfieldfurther is by MIPS64® I6500Multiprocessing Syst est and Root Interrupts est Root Interrupts and fieldwith values 0x0 and0x2 and notthe valueof when guest0x1. Thus GIC_SH_CONFIG GIC_SH_CONFIG WatchDog timer related registers related registers timer WatchDog DEBUG Name TYPE GIC_VLi_WD_MAP GIC_VLi_WD_CONFIG qualify accesses. qualify any GICregister the shared Counter registers. the ) GIC_SH_COUNTER = 1 and and MAP_TO_NMI VZP Table 7.5 Table Visibl User-Mode WAIT , WDRESET registers for guest context and guest so guest and guest context registers for GIC_SH_CONFIG - The SharedSection_Register_Physical_Address = GIC_baseaddress + = GIC_baseaddress SharedSection_Register_Physical_Address + Register_Offset UMVisible_Section_baseoffset - The guest writes to - The guest can only setthe writes this 3-bitfield, the is dropped LSB and for guest reads, returns 0.the LSB 0x0000 ( GIC Counter software is allowed to access software allowed to access the is When guest is allowed access to WatchD allowed access to guest is When related replicatedbitsare in facilitate this, the WatchDog root intervention.To SMASK] a don't care and is not used to don't care and is not a with timer WatchDog to access is allowed guest when Even However, in non-virtualized mode( non-virtualized in However, mode ( Notethat registerof is located1_0000 relativeattoanoffset base the GIC address. map are meant to be located in priv- located to be are meant map (VO) sections of the GIC register and VP-other Shared (SH), VP-local (VL), The ileged system virtual space, inaddress which only kernel In the GIC, a single WatchDog timer is present for the root the for present is timer WatchDog single a GIC, the In WatchDog timer bysetting thenewly added controlbit in theGEN WatchDog • to Guest has limited access of certain WatchDog timerrelatedregister fiel certain WatchDog of • to has limited access Guest ister aliased into this space is is this space aliased into ister User-Mode within the registers for the addresses The address space are aliases for GIC registers for space are aliases address mode programswithout requiring a system troller. allocated space is separate 64KB address A RegisterOffset Any OffsetsOther Reserved 7.3.5 Gu Timer (WD) Watchdog 150 7.4Section Visible User-Mode GIC
151 ry Floating-Point Floating-Point ry Floating Point Con- Floating sters that allow indirect sters ypes of FPU exceptions, rounding of FPU exceptions, ypes floating point exceptions, how to set the set the to how floatingexceptions,point IEEE Standard for Bina for Standard IEEE Uprovides twoadditional regi intinstructions128bitregis-of the lower32 bits use the between SIMD and FPU instructions (FPU uses only the uses only (FPU instructions FPU and SIMD between such as enabling selected t e following subsections are controlled by the controlled by are subsections e following how to enable the FPU, how to handle how EEE 754 compliant 3rdgeneration Floating Point Unit(FPU3) with SIMD that (FCSR). These include elements . Most. FPU instructions have a one-cycle throughput. All floating point denormalized inputoperands and trol and Status Register Status and trol FSCR The operation. a read-modify-write using updated are fields these Normally operation. and flush-to-zero mode, is read, the new valueis logically OR’d withthe existingintosingle a valueandvalue. merged The resultis written the FCSR. back to avoid having to use a read-modify-writesequence, theFP To updatesto the FCSR fields to be performedinsingle a write operation. The FPU programmableThe functionsdescribed in th The IEEE Standard 754-2008 defines the following:IEEE Standard The • Floating-point data types • Thearithmetic, basic comparison, and conversion operations • A computational model standardThe does not define specific processing nordoesresourcesitdefine aninstruction set. The FPU supportsThe fusedmultiply-adds as defined by the IEEE 754-2008, lower64-bits registers).of these Single precision floating po the use SIMD instructions register. bit of the 128 64 bits use the lower instructions point floating precision Double ter. entire 128bit register interpretedas multiple vector elements; 16 x 8-bit, 8 x 16-bit, 4 x 32-bit,and 2 x 64-bit vector elements. The I6500 core an optional I The features I6500 handlesall floatingpoint operationswithin the I6500Multiprocessing System.TheI6500core upcan issue to two to the FPU. cycle instructions per chapterprovides This informationon rounding mode,operation of the Flush-to-Zero (FS) function,anda programming example. Arithmetic resultsare fully supported in hardware. shared registers vector 128-bit thirty-two, contains FPU The 8.1.2 Floating Point Registers 8.1.1754 Standard IEEE MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 8.1 Overview Floating-Point Unit (FPU) Unit Floating-Point Chapter 8 Chapter
register. register. . Status of error once the of Table 8.1 is an alternative way to read and to read way an alternative is determine thetype Enables Flags RM em Programmer’s Guide, Revision 1.00 . the fieldsof FENR in a the single write. Hardware Cause on conditions are enabled. It provides kernel software It provides are enabled. conditions on ngle write operation. In this case the programmer would the programmer case In this ngle write operation. Figure8.1 Bit Meaning P1). To enable CP1, set the CU1 bit in the CP0 the in CU1 bit the set enable CP1, To P1). 2008 NAN (FEXR) located at CP1 Register 26, at (FEXR) located an alternative way to read and write way located alternative at CP1 register ENR) is an 28, ABS 2008 use the ‘Cause’ field in bits 17:12 to 17:12 in bits field use the ‘Cause’ ngle Hardwarewrite. would then updatedmovethese fields into theFCSR. MIPS64® I6500Multiprocessing Syst Figure 8.1Figure FCSR Format 0 1 1 EVZOU I VZOU I VZOU I a floating-pointattempt to execute Any is disabled. instruction1 a causes exception. S0 Table 8.1Table Definitions Field and Flag Enable, Cause, 252423 20191817161514131211109876543210 This bit exists only in the Cause field. bit Cause only in the This exists 0F would thenmove theseupdated fields into the FCSR. the exception type enables field, the rounding type enables modethe exception field, and the flush-to-zero field intheFCSR using a single write operation.In thethis case programmer would update #define C0_STATUSmfc0li C0_STATUS t0, $t12,0 or 0x20000000 t1, mtc0 t0 register to contents register CP0 Status //move 29 set with bit register into t1 value //load t1, t0 t0, C0_STATUS t0, 29 set bit with Status register CP0 t0 into //write into t0 result and copy and t1 of t0 OR contents //logically with the ability to check to see the type of error that occurred even though no exception type was enabled and no and enabledwas type exception no though even occurred that error of type see the to check to ability the with exception was taken. exception occurs. write and Flags fields the Cause of the FCSR using a si update the fields of the FEXR in a si FEXR update in a the fields of the (FCSR located at CP1 register 31) is used to set and monitorfloating 31) is used to set and register CP1 at located (FCSRRegister Status and Control FloatingPoint E Unimplemented Operation. This register contains three fields that This fields are used for the following register purposes. contains three • to enableup to 5 typesexceptions of in bits as described ‘Enables’ field 11:7 the Program in •when no excepti used is in bits 6:2 field Use the ‘Flags’ point exceptions. Theformat this registerof is shownin •the If ‘Enables’ fieldprogrammed, is The The Floating Point Unit is known as Coprocessor 1 (C known is Unit Point Floating The When this bit is cleared, Coprocessor is cleared, Coprocessor this bit When Coprocessor Unusable • The Floating Point Exceptions register Example Code Point Enable Floating • The Floating Point Enables Register (F Bit Name 31 152 8.3 a Floating Point Exception Setting 8.2Unit the Floating-Point Enabling
153 lt. In thesecaseslt.In rounded result is correctly signed according according signed correctly lues are equally near, the lues equally are near, en the Inexact Exception is sig- the en is delivered to the destination. the destination. to is delivered (continued) were the exponent range the range were exponent not enabled, the enabled, not result is defined for an operation on result efully definable resu efully red to the destination. . The RM . field is encoded as The follows. ting-point a quiet NaN. result ting-point is tude than the result. the than tude Figure 8.1 fault result is an infinity is result fault stination format’s largest finite number is exceeded exceeded is number finite largest format’s stination a tiny non-zero result is detected after rounding detected result after rounding is tiny non-zero a eld is set. Such an underflow condition observ- has no eld is condition Such an underflow set. When two representable va d floating-point result, floating-point d Meaning cant bit is zero (that even). (that is, bit is zero cant rounded result is delive rounded Bit Meaning but not greater in magni in but not greater exact bit in the Cause field is set. Cause bit in the exact that is, it differs from what would is, it differs that inexact an operation is result -- of ed if and only if an exact infinite exact only if an and if ed enabled, the overflowed rounded result result the overflowed rounded enabled, on is not enabled, the default floa default the enabled, is not on d result is exact or inexact. exact is result d xponent range and precision unbounded -- th unbounded precision and range xponent on is signaled if and only if there is no us no is there is signaled if and only if on e whose least signifi whose e Table 8.2 Table Definitions Modes Rounding able effect under under handling. default effect able Table 8.1Table Definitions Field and Flag Enable, Cause, finite operands. finite de enabled, the not is Exception Zero by Divide the When The Invalid Operation Excepti Invalid The performed. be to operation the for invalid are operands the Excepti Operation Invalid When the signal is Exception by Zero Divide The to the to operation. only if de the The Exception is signaled if and Overflow been rounde the by would have what magnitude in have been computed were both e been computed were both have naled. the enabled, is not Exception Inexact the When unbounded. is not Exception Overflow When the is set. Cause field bit in the Inexact the In addition, the Exception is signaled when Underflow If enabled, the rounde of whether regardless the handling, when default Underflow Exception exception i.e. is Under to the destination delivered and: • inexact, In If rounded result is the the •Flags fi the no bit in exact, rounded result is If the otherwise, if the rounded stated Unless Rounds the result to the value closest to, to, closest value the to result the Rounds result. the than less not but to, closest value the to result the Rounds result is rounded valu to the is rounded result Rounds the result to the nearest representable value. representable nearest the to result the Rounds I Inexact. ZDivide by Zero. Zero. by ZDivide VOperation. Invalid O Overflow. U Underflow. 1 zero. toward Round 2plus infinity. / towards positive Round 0even. to / to nearest ties Round To settherounding mode for floatingpoint operations, program To theRM field (bits1:0)in the Floating Point Control Registerlocated and (FCSR Status at CP1 register 31) shownin Bit Name RM Field Field RM Encoding MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 8.4the Rounding Mode Setting
Inexact Exception to be Inexact Exception em Programmer’s Guide, Revision 1.00 (FCSR located mod-at CP1register 31) the various bits of the FCSR as described in Sections in described of the FCSR as bits various the are set to 0, all exception types are enabled, the are ons except comparisons causes an comparisons causes ons except Meaning Figure8.1 fore rounding.fore Flushingtiny non-zeroof results and Under- causes Inexact MIPS64® I6500Multiprocessing Syst //Enables field = 5’b11111, Flags field = 0, and Rounding = 0, Flags field = 5’b11111, field //Enables = 1 //Mode ubnormal value and tiny non-zero result is replaced with zero of the same sign. In same sign. the of zero with result is replaced non-zero value and tiny ubnormal Table 8.2 Table Definitions Modes Rounding and Flags fields shown in fields shown Flags and Rounds the result to the value closest to, but not greater than the result. the than greater not but to, closest value the to result the Rounds signaled. flushed. #definemfc1li C1_FCSR C1_FCSR t0, $31 0x01000F81 t1, or t0 register to = 0, contents field register with Cause CP1 FCSR register //move into t1 value //load mtc1 t1, t0 t0, C1_FCSR t0, register CP1 FCSR the t0 into //write into t0 result and copy and t1 of t0 OR contents //logically flow Exceptions to be signaled reciprocals. approximate for except the all instructions, 3 / infinity. towards negative minus Round • For floating-point comparisons, theInexactException is not signaledwhen subnormal input operands are rounding mode is setto‘round towardszero’, and the FS bit set. is 10.4 (Exceptions),10.5 (Rounding Mode),and 10.6 (Flush-to-Zerobit). the Cause this example, In This section contains a programming example for programming for programming example programming a contains section This Floating Point Control and Status Register andStatus Floating the Pointin Control bit (FS) Zero to Flush The the ifies handlingof denormalized operands. s set, every input is Zero Flush to If addition: •be non-zero results are detected Tiny • Flushing of subnormal inputoperands in all instructi RM Field Field RM Encoding 154 8.6 Programming the Floating Point FCSR Register 8.5of the FS Bit Operation
- 155 TM ure that allow effi- ure MSA exception handling, MSA exception ation data format abbrevia- ation to map scalar floating pointfloating scalar map to n with leveraging generic n with ure, known as MSA (MIPS (MIPS MSA as known ure, and 64-bit integer, 16-and 32-bit fixed- and64-bit integer, to the MIPS architect the to as C or OpenCL, enabling fast and sim- and fast enabling OpenCL, or as C amming example, mbly amming language progr .B .H Abbreviation ) data format. e how to enable the MSA, how to enable the e e applications in conjunctio in applications e -bit floating-pointdata. 16-bit floating-point for- storage ent operands. One of the destin ent A architecture, including how including architecture, A de written manually in assembly language in order tobe the I6500 core, MSA implements 128-bitwide vector regis- ltiple-Data (SIMD) architect tionsto/from 32-bitfloating-point data. 32 vector registers of 8-, 16-, 32-, 32vectorregisters of 8-, 16-, ate compute-intensiv datamining, feature extraction in video,image andvideo processing, human- Byte, 8-bit Data Format Data A Control register (MSACSR) and asse (MSACSR) and register A Control ogramming concepts includ ogramming Halfword, 16-bit Halfword, dule adds more than 150 new instructions new instructions 150morethan adds dule supported within high-level languages such withinsupportedhigh-levellanguages Table 9.1 Table Abbreviations Format Data is appended to theinstruction name. Notethat the data format abbreviation is thesame vectorof operations. Table 9.1 Table 2008.All standard operationsare provided for 32-bit and 64 matis supported through conversioninstruc MSA instructions have 2- or 3-register, immediate, or elem immediate, 3-register, 2- or haveinstructions MSA compiler support. Applications such as computer interaction,and others, havesomebuilt-in data parallelism thatlends well itself toSIMD. easily SIMD instructions are The of each field in the MS description a and GNUcompiler support. MIPS®SIMDinstructionsThe on operate point, or 32- and 64-bit floating-pointdata elements. In ters sharedwith the64-bit wide floating-pointunit (FPU) registers. MSAThe floating-point implementationFloating-Pointisfor compliant withArithmetic 754theIEEE Standard tionsshown in utilized, the MSA is designed to acceler designed utilized, the MSA is This chapter describes theMIPS Single-Instruction-Mu mo SMA Architecture). The SIMD parallel processing cient MSAThe providesincreased system flexibilityby incorporating software-programmablea solution for handling or otherCODECs emerging functions notcovered byRather the than focusing on ce. devi dedicated in the hardware narrowly defined instructions that musthave optimized co ple developmentof new code, as well as leverage of existingcode. MS the of overview hardware a brief provides chapter This registers. Pr to MSA vector registers instructionsfloating-point and fixed-point, integer, all example, For type. data assumed instruction’s the of regardless operating on 32-bitelements use thesame word (.W in 9.1 Table 9.1.1 MSA Instruction Formats MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 9.1 of the SIMD Architecture Overview MIPS® SIMD Architecture (MSA) (MSA) SIMD Architecture MIPS® Chapter 9 Chapter
as follows: Table 9.1 Table d FPU instructions. SIMD instructions SIMD instructions. FPU d em Programmer’s Guide, Revision 1.00 .V .D .W (continued) Abbreviation r a completer a alllist of new SIMD instructions, e same clock speed as the CPU. The I6500 core can issue I6500 The same clock speed as the CPU. e stalls. This allows long-running SIMD operations to be par- operations SIMD long-running This allows stalls. on integer, fixed-point and floating-pointoninteger, data. Vector MIPS64® I6500Multiprocessing Syst 64® SIMD Architecture. Fo ector registers shared between SIMD an SIMD registers shared between ector ting-point, and fixed-point data. Word, 32-bit Word, Data Format Data Doubleword, 64-bit Doubleword, compare and branch instructions with no condition flag. MIPS Architecture for Programmers Volume IV-j; The MIPS64® SIMD Architecture The MIPS64® SIMDArchitecture IV-j; Volume Programmers for MIPSArchitecture Table 9.1 Table Abbreviations Format Data ’. In addition to Floating point instructions the Floating point Unit (FPU3) contains a full set of over 150 SIMD instruc- 150 of over setfull a (FPU3) contains pointUnit instructionsthe Floating Floatingpointadditionto In that are compliant with the MIPS tions The FPU contains thirty-two, 128-bit v 128-bit thirty-two, contains FPU The use the entire 128bit register interpretedas multiple vector elementsand relateto • 16 elements x 8-bits/element (.B) • 8 elements 16-bits/elementx (.H) • (.W) elements x 32-bits/element 4 • 2 elements x 64 bits/element (.D) • 1 (.V) x 128-bits element • Operationson absolute value operands. • Rounding and saturationoptions available. • Full precisionmultiply and multiply-add. •floa Conversionsbetween integer, •vector-level set of Complete • operations. (1D) and array (2D) shuffle Vector •load and store instructions for endian-independent operation. Typed operates at th and synthesizable is fully SIMD FPU plus The SIMD instructions enable: SIMD instructions •vector parallel Efficient arithmetic operations refer to document MD00868, ‘ Module up totwo instructionscycle per to the FPU. FPU containsThe two executionpipelinesSIMD instructfor ion execution.pipelines in parallel with These operate pipeline integer when the stall do not core and integer the tially masked by system stalland/or other integer unit instructions. optimizedFPU is The performance.for SIMD Most SIMD instructions have one cyclethroughput. 9.1.2 SIMD Instructions 156
157 0 LSB LSB [0] 5 0 [0] 61 [1] ar floating-pointunit (FPU) 11 [0] 32-bit), doubleword (64-bit). 23 32 31 LSB MSB [2] 73 [1] 84 [3] ers. If both MSA and the scal the MSA and ers. If both 34 , halfword, word(16-bit), ( 46 64 63 0 64 63 LSB MSB LSB MSB [4] 96 07 [2] [5] ector registers extend and share the 64-bit ector FPU registers. extend and share registers the show the vector registerlayoutelements for of all four data formats. 5 8 69 [1] 96 95 Figure 9.1 Figure x 8) (16 Elements Byte Register Vector MSA Figure 9.3 Figure x 32) (4 Elements Word Register MSA Vector LSB MSB Figure 9.2 Figure x 16) (8 Elements Halfword Register Vector MSA Figure 9.4 Figure x 64) (2 Elements Doubleword Register MSA Vector [6] 1 9 1 through Figure 9.4 21 [3] 1 [7] MSA vectorregistershaveMSA four data formats: byte(8-bit) are present, the 128-bit MSA v MSA the 128-bit are present, Figure9.1 The MSAThe operates on thirty-two 128-bit widevector regist 71 [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB 2 9.1.4 Registers of MSA Layout 9.1.3 Registers MSA Vector MSB MSB 1 2101121140998887776655444333221187 0 127120119112111104103969588878079727164635655484740393231242316158 127 127 MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
to
V 0 0 Figure 9.6 ementwith and Word value V Word Unpredictable = 0, …, 31, writes 0, …, 31, writes = to the el to to the floating-point r V V Figure9.5 = 0, …, 31, returns the value of value the returns 31, …, 0, = , where where , s. To facilitate register data shar- register data facilitate To s. r r 32 31 32 31 em Programmer’s Guide, Revision 1.00 where Vector Registers Vector Doubleword value V Doubleword r, = 0, …, 31, writes writes 31, …, 0, = r word element 0, and all remaining elements are remaining all and 0, word element Word value V Word Unpredictable after writing a 32-bit value , where = 0, …, 31, returns the value of the element with value …, 31, returns the = 0, r r r preserves . . r r r, dfloating-point registers are definedas follows: where 64 63 0 64 63 64 63 r, Registers to MSA ers are mapped on the MSA vector register vector MSA the mapped on are ers MIPS64® I6500Multiprocessing Syst to the high part of the floating-point registerfloating-point the of part high to the V shows thevector register and all remaining elements are UNPREDICTABLE. are UNPREDICTABLE. elements and all remaining Unpredictable Unpredictable . The element’s format is word32-bit format is for (single precisionfloating-point) read or . element’s The r r theto floating-point register V after writing 32-bita (single precisionfloating-point) and a 64-bit (double precision r tofloating-pointthe register Figure 9.7 V 96 95 96 95 Unpredictable Figure 9.5 Figure Register MSA Vector on the Effect Write FPU Word Figure 9.7 FPU High EffectWrite Word Register on the MSA Vector . Figure 9.6 Figure Register Vector MSA on the Effect Write FPU Doubleword r register UNPREDICTABLE. UNPREDICTABLE. the word element with index 1 in the vector register in 1 index with word element the floating-point) value the word element with index 1 in the vector register index 0 in the vector register show thevectorregister index 0 in the vector register double for 64-bit(double precisionfloating-point) read. Unpredictable Unpredictable •value write operation of 32-bit A • A write operation of value •register the floating-point of part the high from operation read 32-bit A The scalar floating-point unit (FPU) regist unit scalar floating-point The structions, the FPU is required to use 64-bit floating-point64-bit use to required FPU is the instructions, and vector instructions scalar floating-pointbetween ing registers operating 64-bitin mode. mappe the read operations for FPU/MSA and write The • A read operation fromthe floating-pointregister 9.1.5 Mapping Floating-Point of Scalar 127 127 127 158
159 MSADisabled the Config3.MSAP by the state of by t notis set causes a able access to the MSA instructions and instructions the MSA to access able cape as this functionality is already built in tothe part of the MIPS CodeScape. As such, it is not necessary it is not necessary part of the MIPS CodeScape. As such, enable the MSA block while writing a low-level support a low-level writing while the MSA block enable MSA is implemented by checkingthe MSAP bitis if set, ruction when MSAEn bi //and CU1 bits set CU1 bits //and 16, Select 5, bit 27) is used to en bit 5, Select 16, CP0 bitsregister mustbe programmed: . ehb Config5. in bit MSA enable //Set mfc0 C0_CONFIG5 v1, li or CFG5_MSAEN v0, mtc0 v1, v0 v1, C0_CONFIG5 v1, ehb v1 into register CP0 Config5 //move bit the MSAEN that sets into v0 value //load bit set MSAEN with CP0 Config5 result to out //write into v1 back result v0 and place v1 and //OR #include
. 2 1 0 of error once the of Table 9.2 lt. In thesecaseslt.In Flags RM enabled, the default float- the enabled, 7 6 led, the overflowed rounded the led, nd MSA Control Reg- and Status determine thetype were the exponent range the range were exponent em Programmer’s Guide, Revision 1.00 n is not enabled, the default result is default enabled, the not is n result is defined for an operation on is defined for an operation result efully definable resu efully Enables 12 11 stination format’s largest finite number is exceeded exceeded is number finite largest format’s stination Operation Exception is not Exception Operation on conditions are enabled. It provides kernel software It provides are enabled. conditions on rflow Exception not enab is Exception rflow d floating-point result, floating-point d . , CP1 ControlRegister31) a Bit Meaning using the CFCMSA and CTCMSA (Copy From and To Con- using the CFCMSA (Copyand CTCMSA Fromand To ) 32-bitis a of the read/writeoperation registerththe at controls EVZOU I VZOU I VZOU I FCSR ed if and only if an exact infinite exact only if an and if ed MSACSR MIPS64® I6500Multiprocessing Syst ng, i.e. when the Invalid ng, ng, i.e. when the Divide by Zero Exceptio the when i.e. ng, MSACSR on is signaled if and only if there is no us no is is signaled if and only if there on Figure 9.8Figure Format Register MSACSR read and write the MSACSR FS 0 Impl 0 NX Cause shows the format of the format shows the Table 9.2Table Definitions Field and Flag Enable, Cause, 25 24 23 22 21 20 19 18 17 layout. However, each serves a different functional a different serves each layout. However, register their purpose and related in closely ) are the operands are invalid for the operation to be performed. performed. be to operation the for invalid are operands the exception handli default Under This bit exists only in the Cause field. Cause bit only in the This exists Invalid Operation Excepti The an infinity correctly signed according to the operation. according infinity an correctly signed only if de the The Exception is signaled if and Overflow been rounde the by would have what magnitude in finite operands. finite handli default exception Under ing-point result is a quiet NaN. result ing-point signal is Exception by Zero Divide The unbounded. handling, when Ove i.e. the default exception Under is set. field Cause in the bit Inexact the addition, In destination. the to delivered is result Figure 9.8 0 with the ability to check to see the type of error that occurred even though no exception type was enabled and no and enabledwas type exception no though even occurred that error of type see the to check to ability the with exception was taken. exception occurs. 00000000 E Unimplemented Operation. ZDivide by Zero. Zero. by ZDivide V Operation. Invalid O Overflow. •when no excepti used is in bits 6:2 field Use the ‘Flags’ •the If ‘Enables’ fieldto programmed, is 17:12 in bits field use the ‘Cause’ This register contains three fields that used for the following This fields are purposes. register contains three • to enableup to 5 typesexceptions of in bits as described ‘Enables’ field 11:7 the Program in ister (MSACSR ister unit and can exist independently theof other. MSA unit. unit. MSA The kernelsoftware can trol register)MSA instructions. FloatingThe Point Control Register and Status ( The MSA RegisterThe Control and Status ( Bit Name 31 9.2.2 Setting Exception a MSA 160
161 MSA Control and Status Status and Control MSA rounded result is lues are equally near, the lues equally are near, en the Inexact Exception is sig- Inexact the en (continued) enabled, the rounded result is deliv- result the rounded enabled, not enabled, the enabled, not tude than the result. the than tude a tiny non-zero result is detected after rounding detected result after rounding is tiny non-zero a eld is set. Such an underflow condition observ- has no eld is Such an underflow condition set. When two representable va cant bit is zero (that even). (that is, bit is zero cant Bit Meaning but not greater in magni in but not greater exact bit in the Cause field is set. Cause bit in the exact that is, it differs from what would is, it differs that inexact an operation is -- result of when the Inexact Exception is not when d result is exact or inexact. exact is result d xponent range and precision unbounded -- th unbounded precision and range xponent . The RM field. encoded is as follows. for more information on MSA exception types. MSA exception on for more information e whose least signifi e for moreinformationfor CSR Register" the MSA ng on setting the rounding mode. for more informationfor more CSR Register" the MSA ng on programmingthe exception Table 9.3 Table 9.3 Table Definitions Modes Rounding ) shownin able effect under handling. default effect able Table 9.2Table Definitions Field and Flag Enable, Cause, ered to the destination. have been computed were both e been computed were both have naled. default exception handling, i.e. Under If enabled, the Exception is signaled when Underflow If enabled, the rounde of whether regardless the handling, when Underflow Exception default exception is i.e. Under to the destination delivered and: •inexact, In If result rounded is the the •Flags fi the no bit in exact, result is rounded If the otherwise, if the rounded stated Unless Rounds the result to the value closest to, to, closest value the to result the Rounds result. the than less not but to, closest value the to result the Rounds result. the than greater not but to, closest value the to result the Rounds result is rounded valu to the is rounded result Rounds the result to the nearest representable value. representable nearest the to result the Rounds MSACSR Section 9.2.6, "Programmi Section 9.2.6, "Programmi Section 9.3, "MSAExceptions" I Inexact. U Underflow. 1 zero. toward Round 3 / infinity. towards negative Round minus 2plus infinity. / towards positive Round 0even. to / to nearest ties Round Refer to Refer Register ( eld (bits 1:0) in the in the 1:0) (bits field RM the program operations, point for floating mode rounding the set To Refer to Refer types. to Refer Bit Name RM Field Field RM Encoding Meaning 9.2.3 Setting Mode the Rounding MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
. Inexact Exception to be Inexact Exception ) modifies the handling of denormal- em Programmer’s Guide, Revision 1.00 MSACSR e same format as the Cause field. The Flags bits Causefield. The Flags the same format as e are set to 0, all exception types are are enabled, the gister’s calculated results elements are set either to the gister’s ons except comparisons causes an comparisons causes ons except written floatingand the point exceptionsset the Cause bits Figure9.8 ockinnon-trapping floating point exception mode. Section 9.3.2 “MSA Non-TrappingExceptions” ed for that element in th ed fore rounding.fore Flushingtiny non-zeroof results causes Inexact and Under- Mode), and 11.6 (Flush-to-Zerobit).Mode), and 11.6 //move MSA CSR register contents to register t0 to register contents register MSA CSR //move 0, field = Flags 5’b11111, = field Enables = 0, //field set NX bit and = 1, Mode //Rounding t0 //into MIPS64® I6500Multiprocessing Syst ample for programming the various bits of the MSACSR as described in Sec- described as MSACSRthe variousbits of the for programming ample off). This field is encoded as follows: encoded as is This field off). for moreinformationfor CSR Register" the MSA ng on setting the FS bit. moreinformationfor CSR Register" the MSA ng on setting the NX bit. ubnormal value and tiny non-zero result is replaced with zero of the same sign. In same sign. the of zero with result is replaced non-zero value and tiny ubnormal and Flags fields shown in fields shown Flags and e MSA CSR Register Section 9.2.6, "Programmi Section 9.2.6, "Programmi signaled. flushed. cfcmsali $1 t0, or 0x01040F81 t1, Cause bit set, with FS register into t1 value //load t1, t0 t0, result and copy and t1 of t0 OR contents //logically flow Exceptions to be signaled reciprocals. approximate for except the all instructions, • For floating-point comparisons, theInexactException is not signaledwhen subnormal input operands are to Refer are updated for all floating-point operation with anIEEE exception condition that does notresult ina floating MSA (i.e., point the Enable bit is exception 0: Normal exception mode. 1: Non-trappingexception mode. to Refer For more information ontheNX bit, refer to tions 11.4 (Exceptions), 11.5 (Rounding (Exceptions), 11.5 tions11.4 the Cause this example, In rounding mode is setto‘round towardszero’, and the FS bit set. is This section contains a programming ex a contains section This Setting the NX bit MSA in the MSA CSR sets the bl ized operands. ized operands. s set, every input is Zero Flush to If addition: •be non-zero results are detected Tiny Innormal exception mode, the destination register is not and trap. Innon-trapping exception mode (NXbit set), the operationsthat would normallysignal floating point exceptions do notwrite thebits Cause and do not trap. Allthe destinationre if the operation would normally signalexception, an to signalingor, NaN values withthe least significant bits6 recording exception type detect the specific MSA Control and Status ( Register and Status MSAControl the in bit (FS) Zero to Flush The • Flushing of subnormal inputoperands inall instructi 9.2.6 Programmingth 9.2.5 Operation Bit of the NX 9.2.4 Operation the FS Bit of 162
163 n is either not n or with ExcCode with or and Flags fields of the the of fields and Flags e field has an additional field has e e common exception vector common e element in the MSA element vector in the al an exception according to exception uses the common exception and enable bits control excep- enable and element causes an exception element causes ng inprecise exception mode ssed instructio by the 6 bits have the same format as the format the same have 6 bits mmon exception vect exception mmon ster set to 0x0E. The exact reason for reason exact to 0x0E. The ster set emulation assistance. If type an exception emulation assistance. indicate Coprocessor 0. Coprocessor indicate . This exception uses th exception This . ure with the Cause, Enables, ure ect 5, bit 27) is not set or, when vector registers par- registers whenvector or, notset 27)is bit 5, ect MSA Floating Point exception MSA MSA Disabled exception MSA 0, bit 29) is set. This 29) is set. 0, bit case are at fault and the corre- on which elements 16,Select 3, bit 28) is not set, orthe if usable FPU , then the FPU is operati is the FPU , then enables determining which which determining enables ed byed theMSA floatingpoint instruction. Thisexception which would normally sign which would normally exception conditions. The Caus exception CE field set to 0 to the MSA Control and Status Register (MSACSR). Control and Status the MSA CTCMSA instructions attempt toread or write privileged MSA control enabled. This exception uses the co exception This enabled. set), if any MSA vector register acce vector any MSA set), if FCSR/MSACSR //write t0 into the MSA CSR register the into t0 //write Mnemonic Description ed due to a context switch context a to due ed NaN values, where the least significant values, NaN Table 9.4 Table Codes Exception precise indication in this each of the five IEEE each or with ExcCode field in Cause CP0 regi with or ation, used to trap for kernel software in the MIPS FPU/MSA architect the MIPS FPU/MSA in nt instruction. All elements nt instruction. All ception status flags, and cause the status exception implement IEEE bits The flag . 0x0e MSAFPE 0x15 MSADis ctcmsa $1 t0, operates in 32-bit12,Select mode;(CP Register Status.CU1 exception vector with ExcCodefieldCausein CP0 register set to 0x0A. field CP0 in Cause register setto 0x0Band registers without Coprocessor 0 access without Coprocessor 0 access registers with ExcCode field inCause CP0 register set to 0x15. taking thisexception inis the Cause bits of uses the common exception exception vect the common uses available or needs to be saved/restor or needs available titioning is enabled (i.e. MSAIR.WRP is enabled (i.e. titioning MSA providesMSA non-trapping a exception mode (bitthat NX) MSA instructions can generate the following exceptions: following the generate can instructions MSA • ReservedInstruction,if bitConfig3.MSAP (CP0 Register FPU exceptions are implemented FPU FCSR/MSACSR • CoprocessorUnusable, if CFCMSA or exception bit, Unimplemented Oper Unimplemented exception bit, the the Enables field of through is enabled for this type exception.of •Floating MSA Point, dataa dependent exceptionsignal caused the floating point exception. Innormal operation mode, floating point one vector exceptions signalleast are ed if at tion trapping.Each field a bithas for •16,Sel (CP0 Register Config5.MSAEnbit Disabled,if MSA enabled by the Enable bit. There is no There is bit. enabled by the Enable spondingexception causes. Theexception handlingroutine should set the non-trapping exceptionmode bit NX and MSA re-execute floating poi the to signaling bit-field are set the Enable 11 0x0b CPU Coprocessor exception unusable 14 1021 0x0a RIInstruction Reserved exception Exception CodeValue Decimal Hexadecimal 9.3.2 Exceptions MSA Non-Trapping 9.3.1 MSA Types Exception MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 9.3 MSA Exceptions
flags notare updated. Enable bit notis ement. The other ele- ement. Cause Flags after all bits are updated ns. If there are enabled excep- are ns. If there MSACSR operateson. assumedIt is EVZOU I em Programmer’s Guide, Revision 1.00 MSACSR detected for that that el for detected 6543210 Cause bits and setting the destination’s Cause bits andsetting thedestination’s MSACSR results.Regardless theNX of value, if a floating point Enable bit 0,is thefloating pointresult defaultis a value. oating point exceptionwill be taken, not even the always all elements the instruction the elements all Cause contains no enabled exceptio no enabled Cause contains executing the instruction. The instruction. executing the | c MIPS64® I6500Multiprocessing Syst Field Update Pseudocode Field Update MSACSR Cause | E /* Unimplemented (E) is always enabled */ enabled is always (E) Unimplemented | E /* Signaling NaN Bits NaN Signaling Cause ) to or the specific exception record exceptions ) Enable i.e. the corresponding MSACSR i.e. the and (enable & U) = 0 and (c & I) = 0 then (c & I) = 0 and & U) (enable and MSACSR
and (enable & O) = 0 then & O) = 0 (enable 0 and 0 Cause, a MSA floating-pointCause, exception willbe signaled and the Cause Update Pseudocode Update Figure 9.9 Figure 9.9 Figure Set is NX when Elements Faulting for Format Output c | I c ^ U (bit E is 0x20, O is 0x04, U is 0x02, and I is 0x01) and I is 0x02, 0x04, U O is E is 0x20, (bit exception Cause cleared bits are all before Cause d: exception disabled a case of used in be to value default e: a non-trapping set, i.e. of NX in case to be used value NaN signaling r: an exception without completed operation the if value result v: element to destination written to be value MSACSR Updated c:I bitfield O, U, E, V, Z, exception(s) element current if c = 0 then if c c */ exceptions all current Cause with MSACSR the update exceptions, No enabled /* MSACSR MSACSR Output MSACSR enable Input /* Set Inexact (I) when Overflow (O) is not enabled */ is not (O) Overflow (I) when Set Inexact /* (c & O) if endif */ is not enabled (U) Underflow when Underflow Clear Exact /* (c & U) if endif enable c & cause if cause = 0 then … changed and stillis used togenerate theappropriate default exception enabled, is not The followingThe pseudocode showstheprocess of updating the value. is invokedThis process element-by-element for Cause (see field Whenthenon-trapping exception mode bitNXset, no fl is mentswill beset to the calculated results on theirbased operands. enabled Unimplemented OperationException. Note thatbysetting the NX bit, the MSACSR MSACSR the processed elements have been and tionsin MSACSR 9.3.3 MSACSR Cause Register 164
165 interoperability between the betweeninteroperability ctions defined by MSA. The The MSA. by defined ctions support seamless mixingof scalar and is always enabled */ enabled is always ped instructions.data transfer as many of these operations as possible. In the process possible. In the process as many of these operations as */ the result gets destination ngle MSA instructions. the vector registers and instru and vector registers the for SIMD architectures is the is SIMD architectures for ) tibilities betweentheO32 andbase the ABI corresponding Cause Cause | c | E)) = 0 then /* Unimplemented (bit E 0x20) (bit /* Unimplemented = 0 then | E)) the base ABIs in the sense that existing binaries run unchanged on systems on run unchanged binariesexisting sense that in the base ABIs the | MSACSR | anslate directly in si in anslate directly Cause and the native vector data types. To types. To vector data the native and Enable Flags e MSA provides a rich of ty set provides a e MSA MSACSR
MSACSR & (MSACSR = 0 then
Cause NX r d ((e >> 6) << 6) | c 6) << 6) ((e >> */ is not written destination case */ exceptions for disabled value the default gets destination gets the signaling NaN value for non-trapping exception */ exception non-trapping for NaN value signaling gets the destination Cause Flags Update and Exception Pseudocode Signaling Exception and Update /* Exceptions will trap, update MSACSR Cause with all current exceptions, current with all Cause MSACSR update will trap, Exceptions /* MSACSR MSACSR Flags are not updated */ updated are not Flags MSACSR /* Operation completed successfully, completed Operation /* v destination enabled, are not exceptions Current /* v /* No trap on exceptions, element not recorded in MSACSR Cause, in MSACSR recorded not element exceptions, No trap on /* v Flags /* No enabled exceptions, update the MSACSR Flags with all exceptions */ all exceptions Flags with MSACSR the update exceptions, No enabled /* MSACSR SignalException(MSAFPE, MSACSR SignalException(MSAFPE, /* Trap on the exceptions recorded in MSACSR Cause, MSACSR in recorded the exceptions Trap on /* else endif */ are enabled exceptions Current /* if MSACSR else endif else if (MSACSR else endif supportingIn otherMSA. there words, are no incompa extended ABI. MSA extensions;MSA ABI Inparticular, • Do not change thedatabase ABI types layout / alignment MSA ABI extensions are compatible with are compatible ABI extensions MSA vector data typesoperations, th The O32 ABIs have been extended to allow efficient use of use efficient have been extended to allow ABIs O32 The The GNUThe C Compiler (GCC) supportfor SIMD operations onis based number a standard of pattern used fornames theinstruction should set implement generation.code Ideally, impor- most of the onewasinstruction patternsMSA definition,SIMDselection andGCC standardsupporting of the of objectives. these patterns tr Most tant MSACSR Another aspect related to efficient vector code compilation code vector to efficient related aspect Another types) data C (of language arrays scalar 9.4.1 MSA ABI MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 9.4 GNU Compiler Support MSA
no-msa. The SIMD ABIThe SIMD no-msa. can d by the -mmsa command line by the -mmsa command d em Programmer’s Guide, Revision 1.00 one,can be used to disable the parameter passing/ d (aka saved) status of thestatusaliasedd (aka of saved) floating-point regis- vector registers) is enable registers) vector a can be disabled using -m disabled be can a bled the functionat levelusing __attribute__() shownas ion for MSA must support 32 64-bit floatingregisterspoint support32 64-bit must MSA for ion bi option. In particular, twoSIMDABIs are defined: bioption. In particular, MSA ABI bydefault / and passed returnedby value without Avectors byvalue and returningMSA vector values. c stack re-alignment in this case. in this c stack re-alignment MIPS64® I6500Multiprocessing Syst theregisters. vector The O32permitsFR1 ABI use of 64-bit floatingpoint cessor symbols are defined for each option as follows: for each option cessor symbols are defined __attribute__((msa)) ters. below. below. • -mmsa •__attribute__((no_msa)) -mno-msa • -msimd-abi=none__attribute__((simd_abi_none)) • -msimd-abi=msa __attribute__((simd_abi_msa)) For convenience, pre-pro •__MSA__ -mmsa • calling convention base the - Use none • msa - Use the MSA calling convention(default) the same functionality could be enabled/disa Equivalently, be controlled by varying the valuegiven tothe -msimd-a option. A function compiledMSA is referredfor to as a MSAfunction. value. This is functionsbypassingvectorscalling convention for those a faster optionenables-mmsa the default, By achievedby usingtheregisters vector passing for MS A second MSA-relatedcommand line argument, -msimd-abi=n of conventions the calling types follow data vector all -msimd-abi=none, With registers. the vector in values returning the base ABI. a non-default that stating warning ABI an in results option -mmsa the without value by passed types use of vector The willABI be emitted. This warningcan be disabled byexplicitly passing the -msimd-abi=noneoption. It is illegal to use the -msimd-abi=msa optionwithout -mmsa. -mms option line command the by enabled functionality The • Do not introducenew callee-savedregisters (aka saved) •callee-save or temporary) (aka the call-clobbered Preserve any MSA flags results in a compilerwarning. extens ABI an hardware, MSA be compatible with the To and a stack size frame aligned to the of registers. Itis possible to adjust the stack alignment at runtime using an existing compiler mechanismcalled dynamic stack realignment. AnyABI thatdoesnot meetthe MSAstackalignment will therefore use dynamic stack re-alignment. 128-bit vector registers. How- For example, the 16-bytestackalignment of N32 andN64 ABIs is enough for MSA’s theO32must ABI performdynami ever, and instructions MSA defined the (using MSA for Compiling However, vector data types are considered part of the considered part are vector data types However, 9.4.1.1 ABI Requirements 9.4.1.2 Attributes Function and Line Options Command 166
167 Disable -mno-msa . GCC Table 9.5 or results are returned via vector reg- vector via are returned or results e callinge conventions MSA of and ared with the 64-bit wide floating-point wide 64-bit the with ared Enable -mfp64 -mhard-float -mfp64 32, and32, f24, f25,..., f30, f31N64. for For example,if e used to pass vector parameters. This falls back to the This falls back vector parameters. pass e used to lue and is compiled with - vectoror bya is returnsMSA value and dby non-MSA functions, i.e. a functionscompiled under th GAS (GNU Assembler)2.22.51 GCC 4.7.3. and The returned as specified by by the particular ABI. specified returned as enforce the compatibility of th the enforce -mno-msa -mmsa via vector registers w4 to w11 and vect via vector registers w4 tow11 ent release, MSA vector registers are sh release, ent GAS the aliasedcallee-saved floating-pointFR1, by the O32 specified registers as mbly directives to enable/disable MSA to are shown in mbly enable/disable directives -mhard-float nctionscompiled with -mmsa. vector mustregisters live and all be saved before callingfunction. a This temporary, Table 9.5 Table and Directives GNU MSA Options Enable Disable and -mmsa msa.set .set nomsa -mfp64 unit (FPU) registers. FPU, based on the fact that in the curr the based on FPU, command line options and asse line options command For functions withvariable arguments, no vector registers ar mmsacan be called onlyby fu withthe base ABI MSA disabled. MSAThe is supported by the GNUtool chain starting wi Anyfunction compiled with -msimd-abi=nonecan be calle The MSA vector registers are are MSA vector registers The ensures MSA functionscancallany other functionand compatibility with future MSA extensions. are passed vector parameters first 8 The w0.Floating-pointandister registers are passed passing schemeoriginalfrom variablethe particular argument ABI. need to preserve that compilers Note N32, andN64 ABIs:even f20, f22, f30 for..., O32FR1 andN ABIs. all under be preserved has to f30 register point floating aliased the used, is w30 register vector the a parameter value as by vector a MSA A function that takes •__NO_MSA__ -mno-msa • -msimd-abi=none__SIMD_ABI_NONE___ • -msimd-abi=msa __SIMD_ABI_MSA__ The GCCThe options 9.4.1.5 MSA GNU Options and Directives 9.4.1.4 Functions non-MSA MSA and Between Inter-calling 9.4.1.3 and Floating-Point Vector Register Usage for -mmsa and -msimd-abi=msa Command Line Command Options Directives Assembly MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
and Table 9.6 Table . >=, ~ __asm__ directive, by , > <=, , em Programmer’s Guide, Revision 1.00 !=, < ==, rators onvectordatarators types. Thelist of sup- >>, tor_size(16))) C Definition C Definition <<, __attribute__ ((vector_size(16))) __attribute__ , ; ((aligned(16))) __attribute__ , & | , __attribute__ ((aligned(16))); __attribute__ ^ , __attribute__ ((aligned(16))); __attribute__ ; ((aligned(16))) __attribute__ % and compare instructions: __attribute__ ((aligned(16))); __attribute__ , ; ((aligned(16))) __attribute__ __attribute__ ((vec __attribute__ , / precisionfloating-point vectors, as in: __attribute__ ((vector_size(16))) __attribute__ wu64_t * programmer either by the inline assembly the inline assembly either by programmer ; ((aligned(16))) __attribute__ __attribute__ ((vector_size(16))) __attribute__ __attribute__ ((aligned(16))); __attribute__ , ; ((aligned(16))) __attribute__ - ; ((aligned(16))) __attribute__ , wu8_t __attribute__ ((vector_size(16))) __attribute__ __attribute__ ((vector_size(16))) __attribute__ MIPS64® I6500Multiprocessing Syst __attribute__ ((vector_size(16))) __attribute__ wu32_t wi8_t __attribute__ ((vector_size(16))) __attribute__ wi64_t wf64_t wi16_t wi16_t __attribute__ ((vector_size(16))) __attribute__ wi32_t wordfloating-point add operators include: + typedef unsigned short wu16_t short unsigned typedef typedef unsigned long long unsigned long long typedef __attribute__ ((vector_size(16))) __attribute__ wf32_t float typedef double typedef Table 9.6 MSA in Supported Table Types Data Vector Integer GCC Table 9.7Table in MSA Supported Types Data Vector Floating-Point GCC . fadd.w $w3,$w0,$w1 # a is in $w3, b in $w0, c in $w1 in $w0, $w3, b is in a # $w3,$w0,$w1 fadd.w wi32_t t; wi32_t c; a, b, wf32_t b + c; a = b < c; t = compiles directly in MSA compiles MSA instructionsMSA are available to the C/C++ () intrinsics,msa_mnemonic when or usingmostthe of C/C++ ope ported vector C/C++ Table 9.7 The GCC integer and floating-point vector data types with generic MSA operation support are listed in are listed support operation MSA generic with types data vectorfloating-point and GCC integer The For example, adding or comparing two single- Vector Data Type Data Vector Vector Data Type Data Vector Vector of bytes signed of Vector signed typedef char Vector of signed halfwords signed of Vector short typedef Vector of unsigned bytes unsigned of Vector unsigned char typedef Vector of unsigned halfwords unsigned of Vector words signed of Vector int typedef Vector of unsigned words unsigned of Vector unsigned int typedef doublewords signed of Vector long long typedef double- unsigned of Vector words Vector of single precision Vector values floating-point Vector of double precision of double precision Vector values floating-point 168
169 , and . Figure 9.11 , and W8 after and execut- W8 e. temporaryare registers Figure 9.10 Figure 0 0 ed in vector registers W4 to W11. in registers vector W4 to W11. ed er sizes are shown in Table 9.8 are er sizes in assemblylanguage) based on thedata for- n vectors W5,n W6,vectors W7, . ws[n] = 0, 1 n ( sters are all caller-saved, i. sters are all caller-saved, = 0, …, 7 n = 0, …, 3 n n 15 …, = 0, ws Element Index identical source, target, and destination data types. and destination data identical target, source, 0 Figure 9.12 rmats and vector regist rmats E ove instructionstypeswith of different operands. 64 63 64 63 31 e initializede tothe word values shown in firsteight vector parameters pass are Figure 9.12Figure GPR 2 Value Source Byte Word Halfword Table 9.8 Table Values Index Element Valid is initialized as shown in have the resultingvalues of destinatio Figure 9.11 Figure W2 Values Vector Source abcd Figure 9.10 W1 Values Source Vector ABCD element in the vector register element Doubleword Data Format Data the stack pointer is always aligned to 16 bytes. pointer aligned to is always stack the th n 127 127 Figure 9.16 through fclt.w $w4,$w0,$w1 # t is in $w4 t is in # $w4,$w0,$w1 fclt.w . Valid element indexvaluesvarious for data fo Valid . df When compiled for the MSA, When not preserved between function calls. The calls. function preserved between not Assume that vector registers ar Assume W1 and W2 MSA instructions select the instructions select MSA Regardingthe vector parameterpassing conventions, regi MSA Regularinstructions MSA element-by-element operate with Figure 9.13 Figure thatgeneral-purpose R2 register ingthe following sequenceof word additions andm mat 9.4.3 Examples 9.4.2 Element Selection MSA Vector MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
): 0 0 0 0 0 Figure 9.17 em Programmer’s Guide, Revision 1.00 rating results on data formats twice as twice data formats results on rating c * C + d D + * C c * Value for ADDV.W Instruction for ADDV.W Value 64 63 64 63 64 63 64 63 64 63 and half the width,in i.e. word, this case. MIPS64® I6500Multiprocessing Syst //into $w5. The .w indicates at the 128-bit MSA registers MSA the 128-bit at The .w indicates $w5. //into words. 32-bit into four divided //are w6 $2 into register of GPR contents //replicate into w7 result move the //and a A * B + b * EEEE BBBB e on adjacent odd/even source elements, gene on adjacent e a + A + a + B b + C c + D d a + 17a + 17 b + 17 c + 17 d 127 127 127 127 127 Figure 9.14 Figure Instruction FILL.W for Value W6 Vector Destination Figure 9.13Figure W5 Vector Destination Figure 9.17Figure Instruction DOTP_S for W9 Value Vector Destination Figure 9.16 Figure Instruction SPLAT.W for Value W8 Vector Destination Figure 9.15 Figure ADDVI.W Instruction for Value W7 Vector Destination dotp_s.d $w9,$w1,$w2 dotp_s.d addv.w $w5,$w1,$w2addv.w move and $w2 $w1 and in operands two vector //add $w6,$2 fill.w $w7,$w1,17addvi.w $w8,$w2[2]splati.w into w1 17 Add immediate operand. immediate //vector w8 of all elements w2 into word 2 of //replicate Notethat the actualinstruction specifies data format.The data format the of .D (doubleword)as the destination’s being also signed inferred as is operands source Other MSA instructions operat Other MSA wide. The signeddoubleword dotproductis such an instructionDOTP_S (see 170
171 e processor is operating processor e ates to the I6500 core to the I6500 core to ates . Thenon-guest operating ot-mode exception and error exception and ot-mode Guests from their guest-mode equivalents. from operating modes canbereferred toas compatibility is retained for existing kernel kernel existing for retained is compatibility ) to determine whether th whether to determine ) and multiple DM bitisused along with ro Root ons, registers, and machine st machine registers, and ons, register sets for guest (or contexts)mode operation, Debug oduction to Root and Guest operating systems, modesand respectively, to distinguish them respectively, odes guest-kernel, guest-user and guest-supervisor modes. The guest mode tion of guest Operating Systems in a Systems in guest Operating tion the of execu for ualization Module allows n of virtualized systems. The Virtualization Module is designed to enable full virtu- full to enable is designed Module The Virtualization systems. of virtualized n ) and the Debug Mode bit ( bit Mode Debug the and ) . The. pre-existing kernel,andsupervisor user ERL root-supervisor and Status all times even when a guest is running. Backward when a even all times , root mode root EXL register contains the GM theGM (Guestregister contains This Mode) bit. root-user , Status mode newconsists of operating m GuestCtl0 fully virtualizedenvironment. This chapter provides an overviewof the VZ module, intr operation,excep- of Guesaddress translation, registert structurein Guest mode,software detection Virtualization, of tion handlingin Rootand Guest modeand interrupt handling,and overviewan Guestof debugmode. status bits ( bits status mode. root or mode guest in allowsthe separation between kernel,userand supervisormodes to be retained for a guest operating system running withina virtualmachine. The guest-kernel mode can handleinterrupts and exceptions,and managevirtual memory for guest-user mode processes. separationThe betweenrootmode and the limited-privilege guestmode allows root mode software to be infullcon- the machine at trol of mode knownis as root-kernel Guest software running in root mode. The The virtualizationThe module containsoperating a modes for one The Virtualization Moduledefines thefollowing elements: Virtualization The • Guest Operating Mode •CP0 set Partial (orregister Guest context)for Mode use • Registersfor Guest Mode control • Guest interruptsystem • features Detection of Virtualization providesModule separate Coprocessor0 Virtualization The whichphysically is Rootseparatefrom,anda subsetof, the Coprocessor0context. The Virtualization (VZ) Module new(VZ) set defines a of instructi Virtualization The implementatio the efficient mange Virt The systems. of operating alization 10.1.1 Rootand ModesGuest Operating MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 10.1 Overview Virtualization Chapter 10 Chapter
emulates all guest all emulates as a Virtual Machine Mon- Machine Virtual a as exceptions Guest-handled IRQs, ce-specific or board-specific ce-specific all times. When an operating an all times. When is running on a real machine is each user application, inter-process each user application, inter-process em Programmer’s Guide, Revision 1.00 guest-user guest-kernel each VM, and sharing resources between resources and sharing each VM, eret ode. TheHypervisorode. =1 CU0 ther than user applications. or. To ensure that it remains in control, the Hypervisor the in control, remains it ensure that To or. ure facilities, plus any devi plus ure facilities, rol of machine resources at rol of machine is intendedis allowto VM scheduling totake while place it becomes a ‘guest’ of the Hypervisor. All operationsper- it becomes a ‘guest’the of Hypervisor. , ivileged state, and ensures that the system behaves as the behaves system and ensures that ivileged state, erating system kernel. The hypervisor is responsible for man- for responsible is hypervisor The kernel. system erating eret hypcall, if Guest.Status exceptions Root-handledIRQs ze costs of context switching between VMs. of context switching ze costs t created and managed by theHypervisorconsists of thefullInstruction MIPS64® I6500Multiprocessing Syst ected virtual-memory environment for virtual-memory environment ected intaining the expected behavior intaining for the expected Hypercall exceptions Root-handled , which executes in the privileged m which executes , eret ns between operating modes. nts are full operating systems ra , thekernel, (or ‘supervisor’) typically a runs higherlevelat privilege of than user ack of the guest view of pr view the guest ack of IRQs, Exceptions Figure 10.1 Figure Modes Operating Between Transitions State root-user root-kernel eret IRQ, Exceptions shows the state transitio shows Reset itor (VMM) ‘Hypervisor’.or The Hypervisor is in full cont communications,and I/Odevice sharing.The hypervisor performs thesamebasic functions ina virtualized system- clie that the Hypervisor’s except environmen virtual machine execution The ent is a control knowna program elementkey software.is enabledThe by kernel is Virtualization always runs at a higher level of privilege than a guest op guest a than privilege of level higher runs at a always Architect Privileged Resource Architecture, including all Set system(OS) kernel run withinis a virtual machine (VM), Hypervis by the permitted be explicitly must guest a by formed to sensitive resources, ma aging access peripherals appears and associatedas to each guest if it It registers. operating system control. with full and exclusive enables Module full virtualization,and Virtualization The minimi real-time requirements, and to meeting Invirtualization, the guestoperating systemin operates unprivilegedmode. Allprivileged operations attempted by Hypervisor the traps back to the guest tr keeps privileged operations, multiple VMs. operating a system traditional In a prot The kernel provides applications. Figure 10.1 10.1.2 Introduction Hypervisor to the 172
173 ations of theguest kernel. theRoot TLBmaintain an to execute from its original location original its from execute to as described above. mberentries of be equalto the numberofin entries root TLB pages will likely result in better performance. better in result likelywill TLB pages root anslation to match the expect match the anslation to time. MIPS recommends that MIPS recommends time. anslation are performed are performed anslation ings. Thepagesizes used in the root-mode TLBmust be carefullyconsid- ation allows an unmodified guest kernel guest unmodified an allows ation root-mode whilesoftware, maximizingnumberthe guest-mode of TLB entries entriesfor itsown to use avoidcascading TLBevictions (thrashing). shows the outline of address translation in the Virtualization Module. shows the outlineof address translation in theVirtualization The Virtualization Modulein the I6500providesregister core separate CP0 setanda MMU for guest-modeexecu- Virtualization The tion.In guest mode twolevels trof address nu that the MMU,MIPS recommends For guest the TLB-based expected by the guest. Full address transl Full address guest. by the expected the root-context TLB used for Guest mapp for Guest the TLBroot-context used in memory, and allows the hypervisor manageto tr address in memory, control for sufficient allow ered to Larger entry. TLB root-mode each through mapped are which Both the guest and root MMU’s can be active at the same the same active at can be root MMU’s the guest and Both adequate amount of reserved TLB reserved amount of adequate Figure10.2 10.1.4 MMUConsiderations 10.1.3 EnablingGuest Mode Translations MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
Guest ASID l Guest Virtual l Guest Virtual GuestID = N GuestID processor 0 register set are processor Y Guest TLB Y ot register space and inaccessible in em Programmer’s Guide, Revision 1.00 Mapped? Guest CP0 Guest Exception? segmentation Guest exception N Y N ique non-zero GuestID. The GuestID value zero is GuestID The non-zero GuestID. ique l registers and can be accessed and only by privileged can be registers l means that a subset of the Co of the subset a that means Y MMU N enabled? ) represents a unique identifier forunique ) represents a Rootand al Guest? CP0 register is unique in the Ro Root exception Root RID RID Virtual Address (VA) Address Virtual MIPS64® I6500Multiprocessing Syst GuestCtl1 Guest Physical Address Physical Guest GuestID=N ignored ASID is Root GuestCtl1
or rtualization in the I6500 core in the I6500 rtualization ID N Y access to Guest TLB entries. to Guest access Y Figure 10.2 Figure Translation Address of Outline Root Virtual Address Root ASID GuestID=0 Root TLB is anoptimization,is designed to minimize TLBinvalidation overhead on a virtualmachine con- ddress (PA) ddress GuestCtl1 N
Mapped? Root CP0 Root Exception? segmentation Physical A N text switch Root and simplify text physically replicated for use by the Guest Operating System. replicated for use physically In the I6500 core, Coprocessor 0 (CP0)the In system contro contains instructions. The presence of vi The presence of instructions. The ‘GuestID’ field ( ‘GuestID’ The Guest mode segmentation controlsandthe guest mode ontherootmode MMU have noaddressspace. effect ace is identified by a un by a identified is ace address sp Guest’s spaces. Each Address guest mode. GuestID reserved for Root address space. The space. address reserved for Root 10.1.6 in Root and Guest Mode CP0 Structure 10.1.5 Guest ID 174
175 describes CP0 describes Mode Debug Root-User rnal interrupt han- Root-Kernel Guest-Kernel UNDEFINED Root-Supervisor Table 10.2 Table KSU 11 UNPREDICTABLE 0110 Guest-Supervisor Guest-User Status translation and exte translation EXL Don’t care Don’t the minimum hypervisor intervention, intervention, minimum hypervisor the 1000 care Don’t Description l the guest context. l Guest ot Coprocessor presence of 0 are active. The Status for animmediate for switch between root guest and ERL Don’t care Don’t Don’t care Don’t guest mode behavior. mode behavior. guest 1 0 are used toenter exitor an operating mode. Don’t care Don’t Status Guest ID Guest Offset for guest timer value timer for guest Offset Controls Virtual Interrupts Virtual Extension to GuestCtl0 Don’t care Don’t GM lization Module to contro lization Don’t care Don’t GuestCtl0 ch to/from memory. Simultaneously accesses to the guest guest and root Coproces- the accesses Simultaneously to ch memory. to/from ileged code accesses to execute with with to execute ileged code accesses KSU ssor 0 (CP0) registers registers allows 0 (CP0) ssor 11 10 01 Don’t care Don’t 1 Status Table 10.1 Table Modes Debug and Root Guest, EXL tion, both the guest Coprocessor 0 and the ro 0 and Coprocessor both the guest tion, 0000Don’t care 1 0000Don’t Root Status Table 10.2 Table Module Virtualization by the Introduced Registers CP0 ERL 1 0 11 4 GuestCtl0Ext 12 7 GTOffset 121010 6 4 GuestCtl0 5 GuestCtl1 GuestCtl2 thedescribes how thevarious CP0fields register Number Sel Register Name Register Don’t care Don’t Status DM Coprocessor 0 registers are added by the Virtua Coprocessor twosimultaneously activeCoprocessor 0 contextsModule. is fundamental The operationto the theVirtualization of of two sets of Coproce these presence a context swit without requiring modes sor guest-kernel priv allows 0 registers timekeeping, address that key root-mode machine such as systems and ensures dling continuetowithout operate majorchanges duringguest execution. Table 10.1 Module. Refer to Chapter this2 of registers manualintroducedmoreinformation. for bytheVirtualization During guest mode execu guest mode During 0 1 10.1.7 New CP0 Registers Debug MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
16 Config3 context, and for a guest and for a guest context, R1 Write Reset State Read/ 0 ate of the VZ bit in the in VZ bit of the ate em Programmer’s Guide, Revision 1.00 ode access to the guest CP0 guest CP0 the to access ode Description implemented by checking the st checking the by implemented VZ = 1), and GuestID is supported, then explicit invalid TLB entry entry TLB invalid explicit then supported, is GuestID 1), and = ll to root mode. ll VZ Invalidate Flush Invalidate Description Config3 ented. This bit indicates whether the Virtualiza- the whether indicates bit This ented. w instructions for root m instructions for root w Hypercall - Hypercall ca Guest TLB Invalidate Guest TLB Guest Read Global Invalidate Guest Invalidate Guest TLB Global TLB Guest Guest TLB Probe Move to Guest CP0 Move Doubleword Guest CP0 to Move Move from Move Guest CP0 Write Random to Guest TLB Write Write Guest TLBWrite Doubleword from Guest CP0 Move MIPS64® I6500Multiprocessing Syst d. This bit is always 1 for the I6500 core. the always 1 for This bit is d. Figure 10.3 Figure Format Register Config3 of Virtualization odule not implemented odule is odule implemented Table 10.4Table Field Descriptions for Config3 Register Instruction tion Module implemente tion is 0: Virtualization m 0: Virtualization m 1: Virtualization Table 10.3 Table Module Virtualization by the Introduced Instructions CP0 describes CP0Module. instructionsintroduced by Virtualization the DMTGC0 TLBGINV TLBGINVF TLBGP TLBGR TLBGWI TLBGWR DMFGC0 GINVGT MFGC0 MTGC0 HYPCALL 23 implem Module Virtualization CP0 register. If Virtualization is supported ( supported is Virtualization If register. CP0 Software can determine if the Virtualization Module is Module Virtualization the if can determine Software The Virtualization Module introduces ne introduces Module Virtualization The to make a call into root mode - a ‘hypervisor call’. mode - a ‘hypervisor root into call to make a Table 10.3 support(EHINV) is requiredin order Guestfor a to be able to detectinvalid entries in the GuestTLB. 10.1.8 New CP0 Instructions Name Bit(s) 31 30 29 28 27 26 25 24 23 22 VZ 176 10.2Detection Software
177 =1, GM e state which must e ation, instruction Root.GuestCtl0 ed guest features within Coprocessor t, and then against the root CP0 con- root the t, and then against ese registers, such as TLB entries and entries TLB as such registers, ese it is theentirevisiblit is ftware can access the guest Coprocessor guest Coprocessor the access ftware can udes address transl address udes r accesses and breakpoints. r accesses =0) and =0) DM =0)) =0) then ting anERET instruction when ine can be used to test whether processor is in guest- EXL EXL s and Guest mode operation the other. The software visi- andGuests mode operationthe other. subset of thecomplete root Coprocessor 0 is implemented. =0) and =0. themselves, but also the physical resources which are shared are shared which resources physical the also butthemselves, DM DM lidity checks, coprocesso checks, lidity Root.Debug e root Coprocessor 0. Root mode so mode 0. Root root Coprocessor e itch context from one guest to another, another, guest to itch one context from ich can trigger an exception. This incl This ich exception. can trigger an ring Guest mode is by execu by mode is Guest ring =0 and =0 the GPRs, FPRs and Hi/Lo registers. =0) and (Root.Status =0) and =0) and (Root.Status =0) and =1) and not ((Root.Debug =1) and not ERL =0) or =0) ERL ERL =1) and (Root.Debug =1) and GM GM GM Root.Status =1, ) then return(true) return(false) return(true) return(false) (Root.Status ((GuestCtl0 (GuestCtl0 (Root.Status EXL else endif else endif if (GuestCtl0 if ( endsub endsub subroutine IsGuestMode() IsGuestMode() : subroutine subroutine IsRootMode() : IsRootMode() subroutine 0, and emulate guest-modeif required can to0, accesses disabledor unimplement The 0. guestCoprocessor 0 is partiallypopulated - only a The recommended method of ente recommended method The Root.Status be saved and restored, not solely the replicated registers replicated the not solely and restored, saved be contex guest CP0 the tested against are first guest operations guest mode, all In text. An‘operation’ is any process wh between Root and Guest, such as and between Root followingThe subroutine can be used to test whetherprocessor is in root-mode. Root mode operation uses one set of Coprocessor 0 register Coprocessor of set one uses operation mode Root th via is accessed which state and any registers of these state is the contents ble Segmentation Controlconfigurations. ForHypervisor a sw tosave, restore or instruction va data, for fetches, memory accesses to th no access has software Guest mode Guest mode operation determinedis as follows. This subrout mode. 10.3.2 Guest Mode Operation 10.3.1 Root Operation Mode MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 10.3 Operation Modes Of
t mode operates in its own its in operates t mode for the I6500 Virtualization Module. Virtualization the I6500 for em Programmer’s Guide, Revision 1.00 , it has full access to all resources that are that access to all resources full it has , =0. Otherwise GuestID =0. Otherwise MMU RAD leveladdress translation invoked.are Theisprocess translation process translation the Root context, while Gues Root context, while the ASID ID =4) then // TLB type MT sections describethe subroutinescalled. AddressDecode(vAddr, pLevel) AddressDecode(vAddr, MIPS64® I6500Multiprocessing Syst Guest.TLBLookup(asid, GuestID, addr, IorD, LorS) addr, IorD, GuestID, Guest.TLBLookup(asid, Guest.OtherMMULookup(addr, CCA, LorS, pLevel) LorS, CCA, Guest.OtherMMULookup(addr, =0) =0) then MT RAD =1 or Config =1. in Debug Mode is running If the processor MT DM ignored asid Guest.EntryHi asid (addr, CCA) (addr, # MMU=None case is undefined case # MMU=None UNDEFINED use LorS. BAT will or BAT. type, FMT MMU # Other CCA) (addr, GuestID GuestCtl1 GuestID if (mapped) then endif if (Config else if (Config else endif CCA) addr, (mapped, // This is a Guest Address translation Guest Address This is a // translation Address Guest Physical -> Virtual step 1: Guest // if (GuestCtl0 Root.Debug // Initialization. if GuestCtl0 is only applicable GuestID // translation. address of in process (not applicable) is ignored // GuestID if (IsGuestMode()) then * vAddr* Address - Virtual IorD* LorS* or DATA - INSTRUCTION type - Access pLevel* or STORE - LOAD type KERNEL - Access USER, SUPER, level - - Privilege * * Outputs pAddr* address - physical CCA* * mapped) when (valid attribute cache - functions See called Exceptions: * context. or root guest Called from * */ subroutine AddressTranslation(vAddr, IorD, LorS, pLevel) IorD, LorS, AddressTranslation(vAddr, subroutine /* Inputs available to Root Kernel Mode operation. DebugRoot Mode, Modeand ModemutuallyGuest are exclusive. givenAt any time,the processor canonly bein theone modes.Noteof three thatDebug mode operates in unique context. described in top-downorder - subsequent Segmentation, TLB lookups,hardware TLB refill and second- The followingpseudocode describes the complete address For processors that implementOCI debug,the processoroperating is indebug privilegedexecution mode(Debug Mode) when 10.3.3 Debug Mode 178 10.4 Pseudocode Address Translation
179 =0 and =0 and EXL =0, EXL,ERL !=0 and !Instruction) !=0 and =00 and Root.Status =00 RID KSU RID is non-zero,Root.Status is RID =0 and GuestCtl1 DM =1 and Root.Status =1 and AddressDecode(vAddr, pLevel) AddressDecode(vAddr, ASID =0) DRG RAD ASID =1,GuestCtl1 =0, then guest entry ASID is global in Root TLB. in Root is global ASID entry then guest =0, GuestID 0 GuestID GuestCtl1 GuestID DRG RAD =0, then all root kernel data accesses are mapped and root are mapped accesses data kernel all root =0, then =0 and Debug =0 and (GuestCtl0 DM ERL vAddr endif endif if (Instruction or (!drg_valid)) if (Instruction else endif GuestCtl0 (mapped, addr, CCA) addr, (mapped, addr pAddr mapped mapped addr LorS) addr, IorD, GuestID, Root.TLBLookup(asid, CCA) (pAddr, asid Root.EntryHi asid Root Exception Exception Root context guest in initiated Root exception This is a // TLB exceptions. all This includes // does not as guest not included, exception Error Address Segment map // map. segment lookup root // endif Exception Guest for Execute-Inhibit Invalid, Refill, include may TLB exceptions // for Data. Read-Inhibit Modified, Invalid, Refill, Instruction, // Error include Address may exceptions related map Guest segment // else endif if (!mapped) then (GuestCtl0 if else if (drg_valid) if (drg_valid) then endif Exception Root Root context. in exceptions related Segment and all TLB Includes // Error an Address root-kernel,then is not by access and If drg_valid, // is caused. exception // Root.TLBLookup(asid, GuestID, addr, IorD, LorS) IorD, addr, GuestID, Root.TLBLookup(asid, pAddr if (exception) endif translation Root Address This is a // translation Address Physical -> Root Root Virtual // // If GuestCtl0 endif if (exception) endif translation Address Root Physical -> Physical step 2: Guest // // if Root.Status // and Debug // H/W must set G=1 for guest entry for TLBWI and TLBWR. for TLBWI entry for guest set G=1 H/W must // Root.EntryHi asid guest. for were the access as if set G=1 must ignored.H/W SegCtl is // drg_valid endif if (exception) endif (pAddr,CCA) return else else end MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
s are omitted for are omitted s Complete operation N All exception and All exception mode software). el em Programmer’s Guide, Revision 1.00 odes (supervisor mode Y Root CP0 Root exception? el through the root kernel tocomplete the opera- root-kernel handler slation rules defined by the root CP0 context are applied, are context CP0 root the by defined rules slation d, and resulting exceptions are taken in guest mode by the by guest mode taken in are exceptions and resulting d, root-kernel N Y root-user Guest CP0Guest exception? SegmentLookup(vAddr, pLevel) SegmentLookup(vAddr, pLevel) LegacyDecode(, context exception,the nextlayer to be crossedis therootCP0 context (con- MIPS64® I6500Multiprocessing Syst est contextCP0 (controlled byguest-kern in Root and Guest Mode and Guest Root in guest-kernel handler ) then guest-kernel SC Figure 10.4 Figure Mode Guest and Root Handling in Exception guest-user , an operation executed in guest-user mode must must trav mode guest-user executed in , an operation (mapped, addr, CCA) addr, (mapped, // optional Segmentation Control based address decode address based Control Segmentation optional // CCA) addr, (mapped, exceptions are handled in each of the shows operating the how m Operation starting point Operation starting # Determine whether address is mapped address whether # Determine attribute cache and address physical obtain if unmapped, # - if (Config3 else endif CCA) addr, (mapped, return subroutine AddressDecode(vAddr, pLevel) : pLevel) AddressDecode(vAddr, subroutine endsub Figure 10.4 Exceptions are handled in themode whosecontext triggered the exception. An exception triggered bythe guest CP0 mode. root in handled is context CP0 context is handled in guestroot the mode. An exception by triggere d Figure10.4 In clarity). tion. first layer The tobethegucrossed is are applie context CP0 the guest by defined rules translation guest kernel handler. theIf operationdoesnot triggerguest- a tran and exception All software). mode root-kernel by trolled and resulting exceptions takenin root modeby the root kernel handler shown.as 180 10.5 Exception Handling
181 cal TLB while the guest index TLB cal such, the VTLB must accom- the VTLB such,
) RID RID RID RID RID RID RID RID ID ID ID ID ID ID ID RID RID RID RID RID RID RID GuestCtl1 GuestCtl1 GuestCtl1 GuestCtl1 GuestCtl1 GuestCtl1 /GuestCtl1 ID GuestID GuestCtl1 GuestCtl1 GuestCtl1 GuestCtl1 GuestCtl1 GuestCtl1 and guest. The I6500 core contains a TLB structure that TLB structure a contains core The I6500 guest. and else GuestCtl1 else GuestCtl1 else GuestCtl1 else GuestCtl1 else GuestCtl1 else GuestCtl1 else GuestCtl1 om the bottom of the physi of the bottom the om (GuestCtl1 if RootMode then RootMode if if RootMode then RootMode if if RootMode then RootMode if if RootMode then RootMode if if RootMode then RootMode if if RootMode then RootMode if if RootMode then GuestCtl1 RootMode if bit. However, access of guestto notCoprocessor 0 is qualifiedbit. However, not shared with root. not shared CU1 Status must first be permitted by the guest context by the permitted be first 1 Unit) Point must (the Floating and guest in a sharedand structure. TLBP TLBR GINVT TLBWI TLBGP TLBGR TLBWR Table 10.5 Table TLB Instructions by Use GuestID TLBINV GINVGT GuestCtl1 TLBGWI TLBGWR TLBINVF TLBGINV as Coprocessor 0 state is 0 Coprocessor as TLBGINVF TLB Operation CU0 Status thespecifies association of GuestID with TLBinstructions. For supportinginformation, refer to Section bit, andthen by the rootcontext CU1 . 10.1.8 Table 10.5 (Fixed page size TLB). As size TLB) and FTLB (Fixed page size page VTLB (Variable incorporates a modate wired entries for bothroot fr increases the root index implementation, TLB shared a In The I6500 core shares a common physical TLB amongst root TLB amongst physical common core shares a I6500 The For example, an access For anto Coprocessor example, Status by root context increases from the top of the physical TLB. the top This isfrom toincreases avoid overlap of root and guestwired entries. On theother 10.5.1.1 Root and Guest Access to the Shared TLB 10.5.1 Rootand Guest Shared TLB Operation MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
Config4 field to guest con- guest and instructions. Guest MMUExtDef Config1 instructions. in the guest CP0 context is CP0 context guest the in st and root TLB operations operations root TLB and st rvisoris required to initial- drestore, thehypervisor is n, as is the case for any case for the is n, as MTGC0 relyby rootthe context.CP0 TLBGWR and are present in the root context. are present in the root ch events can be generated as a by- events can be generated as ch Guest.Config4 ination of the guest CP0 context and context CP0 the guest of ination and access to a privileged feature triggers access to a em Programmer’s Guide, Revision 1.00 written. Since the entries allocated for MFGC0 exception handler. The saved state and the The saved state and exception handler. KScratch2 registers determine which features are active features registers determine which and and guest, root software must be careful not to allocate careful and guest, root softwarebe must exception occurs. Su exception ual boot a of Guest, the hype e. On a Guest context save an save Guest context On a e. eatures. Access to features with eatures. the enti machine is controlled theinitial writablestate of Guest context registers. On e bottom of the FTLB. Both gue Both FTLB. the of bottom e KScratch1 eventsthe guest frompopulating all remaining non root- The Root may deconfigure one or more guest CP0 registers more CP0orguest one deconfigureRootmay The Guest.Config7 TLBGP, TLBGR, TLBGWI TLBGP, through register controls whether a guest whether a register controls ops processing instructions, saves sufficient state to resume the interrupted the interrupted resume to state sufficient saves instructions, processing ops tries for guest. The Root then reads the guest. The Root for tries rootmode by using theroot-only the machine is controlled by the comb the the machine is controlled by MIPS64® I6500Multiprocessing Syst size extension fields need to be MMU GuestCtl0 number wiredof entries to itself,and thenwrites theguest Guest.Config0 Config4 ceptionError mode,or andstarts a software itialization and Control and itialization ster Management ster When in guest mode, the behaviorof themode, guest in When required to preserve and re-initializethe Guest state. For virt determine whichof the guest text. the root CP0 context.When in root mode, the behaviorof f optional of a base set plus consists context CP0 guest The guest use also includes nonwired entries shared by bothroot guest configurationthat is read-only to guest but writeable byroot. the as known is This by the guest. use for registers CP0 of partialset a providesModule Virtualization The all remainingnon entriesroot-wiredtothe guest. Thispr wired entries withownits guest-wired entries, leavingnofor non root-wiredentries entries. Rootsoftware should not change guest MMU configuration while the guestis in operatio duringguest modeexecution. The TLB contents can be accessed by using the root-only the using by can be accessed TLB contents Normal execution of instructions can be interrupted when an execution of instructions Normal hand, the root and guest indices to the FTLB grow from th from the FTLB grow to indices and guest root the hand, must interpret the TLB index accordingly. the accordingly. TLB index interpret must This ensures thathypervisorexception handlers have an adequate number of scratch registers tosave and restore all general purpose registers in use by theguest. an exception. Guest be accessedCP0 registers can from Rootcontext software (hypervisor) is requiredtomanage power-up, theinitial power-up, state defaults to thehardware reset stat ize the Guest state equivalent to the hardware reset state. to the hardware equivalent state Guest the ize by writing tothe guest configuration registers. Modulerequires that scratch registers Virtualization The controlled fromrootmode. The productof instruction execution(e.g., an integer overflow caused by an add instructionorTLB miss a caused by a not event an by or mode), user from MTC0 (e.g. instruction privileged a use to attempt illegal an byinstruction), load directlyrelatedto instruction executionanexternal (e.g., interrupt). st exception occurs, the processor an When instruction stream, enters Ex instruction stream, The RootThe allocates the appropriate related fields to set the available VTLB en VTLB the available related to set fields 10.5.1.5 CP0RegisterIn 10.5.1.3 CP0RegisterAllocation 10.5.1.2 Wired Regi 10.5.1.4 CP0RegisterAccess 182 10.6 Exceptions
183 GuestCtl0 registers, excep- registers, not enabled in root in enabled not . rootmode. External inter- Guest.Config Section 10.6.2 ode. If an interrupt is interrupt an If ode. mode switch is performed after the excep- mode register, exceptionsand resulting fromregister, context can be handled entirely within guest be entirely within guest handled can context esent and enabled by the by and enabled esent r, Cache Error are taken in Cache Error are taken r, d in the guest CP0 context, the interrupt is taken in guest in taken is interrupt the context, CP0 guest the in d t-modeCP0 context and then by root mode CP0context oughthe root-modetaken TLB are in rootmode. Root.GuestCtl0 sulting fromthe root-modeCP0 context (including whose CP0 state triggered the exception whose achine state to be saved to either the root or guest state to be saved machine allows This is saved. e tion, and the current state of the pro- the of state the current and exception, of both the type of function a are est-mode operation be checked first against the guest CP0 context, and then then and context, the guest CP0 first against checked be operation est-mode 0 context, and if enabled are taken in root m taken are enabled if and context, 0 during guest mode execution, any required ntext. Exceptions resulting from theguest CP0 Root Guest Guest Root tionstriggeredby those features are takenin guest mode. address translationguest of memorythr accesses ctx ctx ctx ctx ctx accesses, breakpoints and so forth. accesses, • Exceptions resultingfrom control bits set in the # Booleans, indicating source of exception: source indicating # Booleans, ## root_async # root_sync# guest_asyncexception context root - Asynchronous # guest_sync Root.Status.EXL, or set Root.Status.ERL context to root directed # Exceptions root context by triggered guest context exception by triggered - Synchronous exception - Asynchronous root mode. in the handler executes the processor that # meaning guest context by triggered exception - Synchronous conditions of exception # Ordering if (root_async) then then (guest_async) elsif then (guest_sync) elsif then (root_sync) elsif •the guest context are pr in features architecture When • coprocessor which memory Thisexceptions can accesses, be generated - for includes all operations mode withoutroot-mode intervention.Exceptions re The Virtualization Moduleadds new rules for the Virtualization processingThe of exception conditions detectedduring guest-mode execution. gu every that model’ requires ‘onion The co CP0 the root against address of the software exception handler exceptionsoftware the of address cessor. permissions) requirea root mode (hypervisor) handler. Duringguest modeexecution, the modein whichanexception taken is is determined by thefollowing: • Guest-mode operationsmust first be permitted bygues Asynchronous exceptions Reset, NMI, Memorysuch as Erro rupts are received by the root CP the by are received rupts mode and is bypassed to the guest CP0 context, and is enable and is context, the guest CP0 to bypassed is and mode mode. an exception is detected When detected and before any machine stat is tion exception the and allows to be handledcontexts, in theproper mode. alsoSee • Exceptionstaken in the mode are always 10.6.1 Exceptions in Guest Mode MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
, refer to a virtualrefer to a address GuestCtl0, Root.EPC tion was triggered by root- by triggered was tion BadVPN2 address that caused one of the fol- one of the caused that address de execution, the handler executes in executes execution, the handler de is ideally the Guest Physical Address is ideally the Guest Physical Address em Programmer’s Guide, Revision 1.00 ddress (GVA) unmapped by the Guest MMU Guest the by unmapped (GVA) ddress BadVPN2 is the Guest Physical Address being accessed Guest the is Root.Context . and BadVPN2 BadVPN2 ion through the guestTLB if it is in a mapped regionof sters. The registers affected are The registers affected sters. Root.Context spective of whether the excep the spective of whether not available for write to root context, then root context, available for write to not and Root.BadVAddr Root.Context Root.Context and and MIPS64® I6500Multiprocessing Syst sult of a root TLB access during guest-mo access during TLB root of a sult Root.BadVAddr xceptions xceptions Mode from Guest the guest context. A Guest Virtual A Virtual context. A Guest guest the Root.Cause , Root.BadVAddr ate is storedinto root CP0 regi after an exception, both after must indicate this. must null Root.EntryHi , register is a read-only register that captures the most recent virtual register read-only a register is GExcCode ctx ctx BadVAddr else endif by the guest. by the that ensures This process (GPA) presented to the root TLB by TLB by root the to presented (GPA) perspective. the root’s from GPA a is considered is is mapped by theGuestMMU,the GPA yet a GVA If root mode,andexception st GuestCtl0 in The value stored memory. The GPA presented to the root TLB is the result of TLB translat is the result root the to presented GPA The When an exception is triggered as a re a triggered as is an exception When Root.BadVAddr The The faulting address value stored into faulting address value stored The which immediatelyis irre usableby a root-mode handler, mode or guest-mode execution. lowing exceptions. lowing •Modified Addresserror • TLB Refill • TLB Invalid •TLB • TLB ExecuteInhibit • TLB Read Inhibit 10.6.3 Guest TLB Initiated Root Exception 10.6.2 Faulting Address for E 184
185 Root Root Root Root Root Root Guest mode Taken in Taken Reset Type Debug Debug Debug Synchronous Synchronous Asynchronous Root Asynchronous Guest Asynchronous Asynchronous Asynchronous Asynchronous Root Asynchronous Guest Asynchronous Root Asynchronous Asynchronous or Synchronous lowest. The table also lists new new lists also The table lowest. mode in which mode in is recommended recommended is Guest EXL Guest wasone so that one can single-step that one can so TLBinstruction mustcause a B. It is It recommended that the B. ite, probe). It ite, the processor. the guest (second step) address transla- (second step) address guest relative priority of each, to priority highest of relative ons to break on illegal allow detected by the processor. the detected by a guest address translation (first guest translation a address and root TLB (write, and operation root TLB d. Prioritized above other exceptions, other exceptions, above Prioritized d. or was asserted. DINT) or eak condition was asserted. was condition eak Description deferred deferred because deferred because EXL was one when the was because EXL deferred upt occurred. upt break was condition asserted. Prioritized break al was asserted to the al processor s asserted to theprocessor Table 10.6 Table of Exceptions Priority Root, or Root TLB related. related. TLB or Root Root, A Root watch exception, exception, Root watch A exceptionwas detected, was asserted after EXLwent to zero. A in guest watch may occur exception deferred root A root enabled interrupt occurred. interrupt A enabled root when the exception was detected, was asserted after EXL went to went EXL after asserted was detected, was exception the when zero. instruction fetch excepti above instruction addresses. instruction The Cold Reset The sign Cold into interrupt (or other asynchronous) handlers. into asynchronous) (or other interrupt including asynchronous including exceptions, asynchronous This can only occur as part of a part occur as only can This root address translation, tion, A be synchronous. Machine-Check Check. Machine synchronous related. TLB Guest part of can only occur as This operation (wr and guest TLB step), guest occurring simultaneous a than higher prioritized it is case interrupt. The signal NMI asserted was to TL or root probe) whether for guest An imprecise debug data br An data imprecise debug An internal inconsistency was be A instruction must synchronous. TLB the that Machine-Check Machine Check. a synchronous cause A debug interrupt (DbgBrk interrupt A (DbgBrk debug A enabled guest interr A A Guest watch exception, The Reset wa signal lists all possible possible and the exceptions, all lists exception conditions introduced by the Virtualization Module, andto whethera switch defines root mode is requiredexception conditionsintroduced by theVirtualization before handling eachexception. Table 10.6 Exception 10.6.4 ExceptionPriority Deferred Watch Debug Instruction Break Instruction Debug instruction A debug Debug Interrupt Debug Debug StepSingle Debug occurre Single Step Debug A Machine Check Deferred Watch Nonmaskable Interrupt Interrupt Nonmaskable (NMI) Imprecise Debug Data Imprecise Break Interrupt Interrupt Reset Soft ResetSoft MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
Root Root Root Root Root Root Guest mode Taken in Taken or Type Debug Hypervisor Synchronous Synchronous Synchronous Current Synchronous Guest Synchronous Guest Synchronous Synchronous Root Synchronous Guest Synchronous Asynchronous em Programmer’s Guide, Revision 1.00 ception raised is exceptions to allow exceptions . s detected on an instruction instruction an on detected s n be taken. Reserved Instruc- be taken. Reserved n instruction fetch instruction a Reserved Instruction Excep- Instruction a Reserved loaded into PC. loaded Reserved Instruction Redirect is Instruction Reserved st context TLB entry mapping the TLB context st Refer to ‘Watch Registers’ - Registers’ to ‘Watch Refer on fetch exceptions to allow watch allow to fetch exceptions on valid Root TLB entry which had which valid Root TLB entry oot TLB entry mapping the address the address TLB entry mapping oot Section 10.8 on an instruction fetch. on Description otherwise follow standard rules of prior- follow otherwise ion was executed. ion was =1, this root-mode ex =1, ddress match detected an ddress was on instruc- RI MIPS64® I6500Multiprocessing Syst above instruction fetch instruction above t of this processing. t ruction addresses. ruction Table 10.6 Table of Exceptions Priority GuestCtl0 context watch address match wa watch address match context A guest-mode instruction triggers A instruction guest-mode When tion. A Guest TLB miss occurred on an A occurred an Guest TLB miss on A occurred Root TLB miss This can occur due to a Root or Guest translation. can occur due This fetch. an instruction referenced by to a Root or Guest translation. can occur due This The valid bit was zero in the gue the in was zero bit valid The by instruction referenced an address fetch. R in the zero was bit valid The the bitXI set. matched a An fetch instruction the bitXI set. to a Root or Guest translation. can occur due This fetch. on an instruction occurred A error cache on instruction an fetch. occurred A error bus taken as a side-effec taken before the guest-mode exception ca the exception guest-mode before Exception processing tion context - itization a given within fetch. Prioritized above instructi above Prioritized fetch. illegal instruction addresses. on 10.8. Section A watch guest-context a tion Prioritized fetch. watch on watch illegal inst Registers’ - to ‘Watch Refer A non-word-aligned was address A non-word-aligned A SDBBP instruct A debug Exception Guest Reserved Instruc- Reserved Guest tion Redirect TLB Refill - Instruction - Instruction TLB Refill fetch TLB Invalid - Instruction - Instruction TLB Invalid fetch TLB Execute-inhibit matched fetch An a valid Guest TLB instruction had which entry Cache - Error Instruction fetch Bus - Error Instruction fetch SDBBP Watch - Instruction fetch Instruction - Watch root A Address Error - Instruc- Address fetch tion 186
187 Root Root Root Root Root Root Root Guest Guest mode Taken in Taken Type Debug Hypervisor Hypervisor Hypervisor Hypervisor Synchronous Current Synchronous Synchronous Current Synchronous Root Synchronous Synchronous Synchronous Synchronous Root Synchronous Synchronous EXL/TS EXL/TS . Status MSAEn was not allowed was fer to ‘Watch fer to ‘Watch fer to ‘Watch Config5 re (address match only) or a or only) match (address re ss to a coprocessor was permit- to a coprocessor ss initiated change to certain CP0 to certain change initiated est or Root address translation, or Root address est tch was detected on the address was on address tch detected the leted because it it because leted disabled. If exceptions occur on on occur exceptions If disabled. condition asserted. match) was ta addresses. Re ta addresses. Re ptions to allow break on illegal illegal on break to allow ptions Reserved Instruction Exception. Instruction Reserved Guest address translation, or a translation, address Guest st-mode could not be completed could st-mode not the required resources by the required the detected by the processor. the detected by bits, but denied by bits, ocessorUnusable, MSA disabled Prioritized above Prioritized data fetch excep- above Prioritized data fetch excep- rdware initiated set of initiated rdware ruction was executed. ruction Description CU1-2 resources, or was illegal: Coprocessor Unus- illegal: or was resources, address match was detected on the address address on the detected was match address , but denied by Root. bits. Table 10.6 Table of Exceptions Priority MSAEn CU1-2 Section 10.8. Section 10.8. Section Guest.Status . e debug data break on load/sto data break debug e Config5 RootTLBrelated. the same instruction, the Copr the instruction, same the access to the required required to the access MSA able, Reserved Instruction, over the take priority Exception Acce guest. unusable - Coprocessor the ted by An could not be comp instruction occurred MSAdisabled guest.Access- to the MSA wasunit permittedby Guest. exception. 2 point, coprocessor floating breakpoint, system call, Root.Status Guest TLB related. related. TLB Guest a of part can only occur as This TLBP/TLBWI executed in guest-mode An internal inconsistency was in gue executing An instruction because itwas denied access to Root.GuestCtl0 register. This can only occur as part a Gu part of can only occur as This root-mode. in executed a TLBP/TLBWI/TLBGP/TLBGWI or A hypercall A HYPCALL inst execution, a software guest During occurred. fields register guest a ha During execution, data addresses. data Prioritized above data fetch exce above Prioritized store. a load or referenced by data break on store (address+data break on store data illegal to allow watch on da tions A ma context address guest watch store. a load or referenced by illegal to allow watch on da tions Registers’ - Registers’ - Registers’ Exception Instruction Validity Instruction Validity Exceptions Machine Check Execution Exception Execution Debug Data BreakPrecise trap, Integer overflow, occurred: exception An instruction-based precis A Guest Privileged Sensi- Privileged Guest Exception Instruction tive Hypercall Software Field- Guest Change Field- Hardware Guest Change Watch - access Data - Watch A watch root context MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
Root Root Root Root Root Root mode Taken in Taken ion. These exceptions exceptions ion. These These exceptions have These or Type Debug re to enter Debug Mode, even in Mode, even to enter Debug re Synchronous Guest Synchronous Synchronous Current Synchronous Guest Synchronous Guest Synchronous Guest Synchronous ways be placed in a running state. running be placed in a ways Asynchronous em Programmer’s Guide, Revision 1.00 explains the characteristics of each of explains the characteristics to instruction to execut to instruction execution. instruction to Table10.7 onous and synchronous. These always exceptions Characteristics s+data match only) s+data data reference guarantee that the processor can al processor guarantee that the last because all aspectsall of the because last rea switch to root mode. st TLB entry mapping the address mapping the entry TLB st ng root TLB entry found, was and root TLB entry ng oot TLB entry was found, but the oot entry found, TLB was that occurs asynchronously asynchronously occurs that Description in order to do data match. in order a matching guest TLB entry was found, and was found, matching guest TLB entry a MIPS64® I6500Multiprocessing Syst break on load (addres break on load ed on a load or store or on a load ed to root to mode. occurred on occurred a data access. on ed on a load store or referenceon data load ed a a matching guest TLB entry was found, but the entry was found, matching guest TLB a t-type exception that occurs asynchronously asynchronously exception that occurs t-type Table 10.6 Table of Exceptions Priority describes thetype exception.of Table 10.7 Table Characteristics Type Exception require a switch require other exceptions because of the desi to other with respect high priority very exceptions, both presence other the asynchr of always have the highest priority to always requi always exceptions These An unaligned address, or an address that was inaccessible in the the in inaccessible was that or an address address, An unaligned instruc- store load or a referenced, mode by was processor current tion. A root TLB miss occurred on occurred A a data access. miss on root TLB to a Root or Guest translation. can occur due This valid (V) was valid bit zero. On r a data access, matching a (V) was valid bit zero. to a Root or Guest translation. can occur due This set. was bit RI the matchi On a a data read access, set. was bit RI the to a Root or Guest translation. can occur due This the gue in zero was bit dirty The referenced by a store instruction mapping the address entry root TLB bit zero in the The was dirty a store instruction.referenced by to a Root or Guest translation. can occur due This datafetch must complete condition was asserted. Prioritized asserted. was condition exception type. Table 10.6 column of Table “Type” The Exception ExceptionType Asynchronous ResetAsynchronous DebugAsynchronous a rese Denotes exception a debug Denotes Address error - Data Address access TLB Refill - TLB Data accessRefill miss A TLB guest TLB Invalid- Dataaccess On a data access, TLB Read-Inhibitaccess, read a data On TLB Modified - Data access Cache - accessError Data A occurr error cache Bus - Error Data accessDebug Data BreakPrecise occurr A error bus A precise data debug 188
189 obtained VEIC nd is reported nd pre- is reported precisely reported precisely Config3 and ions require always a exception condition is VS exceptions with each other. In other. exceptions with each the presence of other exceptions. other exceptions. of presence the =1 (as appropriate) before=1 any(as appropriate) IntCtl ction execution, a , execution, and is ERL st value supply the appropriate for BEV rdware and Hypercall. Field Change instruction execution which requires hyper- which requires execution instruction Status , Root.Status at any time. When an at EXL e second way. These except second e way. =1 or =1 Status Characteristics , EXL ere the exception was detected. ere isor exceptions Guest PrivilegedSensitive Instruction, is a relative priority of synchronous of priority relative is a ons, they are either the lowest the they are either lowest ons, instructi occurring ons between as ecisely with respect to the instruction that caused the exception. exception. the caused that instruction to the respect with ecisely EBase be handled switching modes. be without tion that occurs as tion a of instru result rea switch to root mode. rea switch to root mode. to allow entry to Debug Mode, even in Mode, to Debug allow entry to instruction execution. These excep- execution. to instruction asynchronously that occurs ception Root.Status e condition requires a switch to root mode, the switch is made before any before is made switch the mode, to root switch a requires condition e , as describedin, thefollowingas pseudo-code. that occurs as a result of guest-mode occurs as a result that ses a guestexitses a toroot,mu hardware Guest Guest Change,Ha Software Field all exception state is stored into root CP0 context, regardless of whether the pro- the regardless of whether context, CP0 root into state is stored exception all fined in the base architecture. fined in the GExcCode “GE”| guest modeatthe point wh Table 10.7 Table Characteristics Type Exception
mined from thevalues of tion,control can be returnedto root mode GuestCtl0 occurs exception that as a result other instruction any of Denotes These exceptions always requi always exceptions These visor intervention. It is reported pr intervention. visor Denotes any other type of ex type other any Denotes These exceptions always requi always exceptions These with respect to the instruction that caused the exception. These exceptions tend to be prioritized below below prioritized be to tend exceptions These exception. the caused that instruction the to respect with of but exceptions, there types other cases, these exceptions some can priority relative to the previous instruction, or the highest priority relative to the next instruction. The The instruction. next to the relative priority highest the or instruction, previous the to relative priority them in th considers above the table of ordering to root mode. switch cisely with respect to the instruction that caused the exception. These exceptions are prioritized above above prioritized are exceptions These exception. the caused that instruction to the respect with cisely synchronous exceptions other tions are shown with higher priority than synchronous exceptions mainly for notational convenience. If convenience. notational mainly for exceptions priority than synchronous higher shown with are tions one of excepti thinks asynchronous ExcCode and ExcCode Root.Cause if guestif exception is (GPSI or GSFC or GHFC or HCor GRR or IMP) then fromthe context in which the exception is handled. GeneralThe Exception entrypoint usedhypervfor new is Guest Redirect, Reserved Instruction In the case of a guest exception which cau which a guest exception of the case In The vector location is deter vector location The execu guest mode During Root.Cause Exception vector locations are as de Exception vector locations detected during guest mode execution and th guest during detected affected. exception CP0 statecontext is not a result, in the guest As is saved. exception state switchThe torootmode is achieved by setting Refer to the Exceptions chapter for more information on these more exceptions. these information on to the Exceptions chapter for Refer other state is saved. This ensures that that ensures This saved. state is other executing cessor in root or was ExceptionType 10.6.7 Guest Exception Code in Root Context 10.6.6Hypervisor Exceptions Synchronousand Synchronous 10.6.5 Locations Exception Vector Synchronous Synchronous Hypervisor an exception Denotes Synchronous Debugexcep an debug debug Denotes Asynchronous MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
em Programmer’s Guide, Revision 1.00 ecution. An interrupt source enabledin source interruptAn ecution. or “HC” or “GRR” or “IMP” or “HC” or “GRR” or exts todetermine whenan interrupt should be taken. An rrupt.Guestscannot disable root mode interrupts. “GPA” “GPA” or GVA” “GPA” “GPA” or “GVA” “GPA” or “GVA” “GPA” or “GVA”
“MOD” “TLBL” “TLBXI” “TLBS” or “TLBL” or “TLBS” “TLBRI” MIPS64® I6500Multiprocessing Syst ways active, even during guest mode ex active, even during guest ways GExcCode “UNDEFINED” “GPSI” or “GSFC” or “GHFC” or “GSFC” or “GPSI”
GExcCode GExcCode GExcCode GExcCode
= 0) then = baseline “ExcCode” ExcCode ExcCode ExcCode ExcCode ExcCode IEC
GExcCode GExcCode ExcCode Root.Cause Root.Cause Root.Cause Root.GuestCtl0 Root.GuestCtl0 Root.GuestCtl0 # loading of GPA for both TLB-Refill andTLB-Invalid recommended. is # loadingof GPA Root.GuestCtl0 Root.GuestCtl0 Root.Cause Root.Cause Root.PageGrain shows the howvirtualized interrupts are managed in theI6500core. if ( if elseif (TLB Execute-Inhibit) else endif Root.Cause Root.GuestCtl0 Root.GuestCtl0 endif elseif guest exceptionis(RootTLB-Refill or TLB-Invalid) Standard interruptused bybothrulesare root Standard and guestcont interruptenabled in therootcontext is taken in root mode.Aninterrupt maskedby root and enabledin the guest con- textis taken in guest mode. Rootinterrupts take priority over guest interrupts. Figure10.5 the root context always results in a root-mode inte a root-mode the results root context always in The Virtualization Moduleprovides virtualized a interrupt systemfor theguest. Virtualization The al is system root context interrupt The elseif guestelseif exception is (Root TLB-Execute_Inhibit or TLB-Read_Inhibit) elseifModified) is (TLB guest exception else 190 10.7 Interrupts
191 IPTI =1) PIP[n] Guest.IntCtl . register, or direct direct or register, GuestCtl0 N VS via IntCtl No action IPPCI IP[n] or Y IV if implemented. Guest.Cause IntCtl IRQ? PIP Cause Cause Guest Guest handler propriate and if both Root Guest use , Guest. ces are combined such that both meth- such ces are combined interrupts are not affected by the by affected are not interrupts BEV GuestCtl0 or of or this field is controlled fromthe root upt source indicatedupt source by the Status Timer, etc. fieldnon-EICin mode,or hardware capturea of Pending VIP nges to theguest interrupt systemstatususing thefield- Y ample, innon-EIC interruptmode,if an is pin(HW[5:0]) , whether non-EICEIC or provides thefollowing capabili- system. Interrupt sour Interrupt system. N Root GuestCtl2 Pass? ys applied to the interr the to applied ys (e.g., Timer interrupts, Software interrupts) interrupts,Software (e.g., Timer No action No registers. Direct assignment is ap is Direct assignment registers. field. Similarly, software Guest Similarly, field. N om therootcontext, enabled by PIP Cause pin to be visible to the Guest, possibly removing Root intervention capability. pin to be visibletotheGuest,possibly removing Rootintervention capability. Y in EIC mode. IRQ? and Root can assert IRQ by IRQ assert can Root write to pendingfield GRIPL Roothandler GuestCtl0 set by software write to by software set Status guestfield is the source of interrupts. The behavi GuestCtl2 Timer, etc. Figure 10.5 Figure l Module Virtualization the in Handling Interrupt Pending RIPL/IP field, and are always applied to theinterruptand are always field, source indicatedby PIP Guest.Cause guest interruptin External Sources • context guest the within generated Interrupts • Rootasserted interrupts, causes all the interrupt sources on that causes RootIf Software needs toguarantee Root intervention capabilityon an interrupt thenthat interruptshould not be Guest. visible to directly Innon-EIC mode, theguest timer interruptis alwa Software should enabledirect interruptassignment only when root andguest agree on theinterpretation of interrupt the in fields pending/enable context. Two methods can be used to trigger guest interrupts - a root-mode write to the to write - a root-mode interrupts guest trigger to used be can methods Two context. assignmentreal interruptof signal to theguest interrupt ods can be used. and related interrupts are availableTimers in both guestandrootcontexts. setofThe pending interrupts seen by theguest contextthe is combination (logicalof: OR) • External interrupts passed through fr The A virtualization-based external interrupt delivery system GuestCtl0 ties: Root must assign interrupts to Guest with caution. For ex For caution. with Guest to interrupts assign must Root sharedbymultiple interrupt sources, thenenabling visibilitydirect guest (in Guest field and is not affected by the field and is not affected changeexceptions which result fromguest initiatedchanges to fields EIC mode,or if both use non-EIC mode.Root can track cha MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
The other- PIP. PIP. , , fol- , , Root vIP vIP IP[n+2] (Pending Inter- PIP PIP GuestCtl2 GuestCtl2 and GuestCtl0 and vIP vIP Guest.Cause ementation. The term HW is The term HW ementation. GuestCtl0 ]=0)) vIP[n] set earlier. earlier. set em Programmer’s Guide, Revision 1.00 either by device activity or protected device either activity or by IP method to deliver interruptsto guest. so used by Rootto inject a virtual interrupt Cause which may be problematic since other interrupts other since problematic be may which IP ual drivers. TheRoot injects an interrupt into the Guest ) or ) (MTC0[GuestCtl2 . atively referred to as IRQ in other sections of the Module.the of sectionsotherin ativelyreferred to as IRQ cansubsequently clear theinterrupt writingby 0 to
handling in a recommended impl a recommended in handling It HC[n] . Guest.Cause IP[n+2] vIP withroot-mode servicingof external interrupt. withroot-mode toguest hand-off by writing to handling is described in relation to GuestCtl2 relation in described is handling IP thenHW[n] visibleis to guest context through GuestCtl2 , rrupt Interrupts.delivery system Root canalso provides supportfor Virtual Root.Cause interrupts, thenrootshould use this MIPS64® I6500Multiprocessing Syst and in so doingtoa trap Root,causes =1 ent wayfor Root to save and restore interrupt state of a Guest,aninterrupt if 1 0 ]=1)
Root.Cause PIP[n]
visible toguest context rootcontextor is dependenton vIP[n] and vIP[n] vIP[n] is discussed below. IP IP HC (Interrupt Pending, Virtual). Thismethod is al (Interrupt Pending, Virtual). GuestCtl0 GuestCtl2 vIP[n] GuestCtl2 GuestCtl2 =0, but Root needs to transfer the external interrupt to Guest, then it must write to a software visible a software visible write to must it then Guest, to external interrupt the transfer to needs Root but =0, Guest.Cause Handling: . PIP[n] vIP, vIP, vIP vIP else if ((Deassertion ofHW[n] and GuestCtl2 if (MTC0[ if endif GuestCtl2 lowed servicingby guest of external interrupt. rootrequiresIf visibility into guest Hardware deliversinterrupt to guest context without root intervention,followed byguest servicing external of interrupt. The interrupt is notvisible torootas root madehas the choice to assign to guest. Hardware deliversinterrupt to root context, Hardware Hardware interruptdelivers to root context, GuestCtl0 into guest context. It is also a conveni had beeninjected byRoot, butneeds tobepreserved context across switches.In the absence of GuestCtl2 If This section provides a detailed description of non-EIC of non-EIC description detailed a provides section This altern source. HW is an external interrupt represent to used HW set interruptis a of pinscommon to both root and guestcontext. is Whether an external interrupt could also be present. GuestCtl2 3. Guest assignmentof InterruptExternal without Root Intervention. inte enabled external A virtualized MIPS simulate a guest interruptbywriting 1 to memory access. Root memory may then clear guest access. writing the to interrupt by Virtual Interrupt capability can be used to support guest virt guest support to be used can capability Interrupt Virtual Guest fields the interrupt, context. The rupt Pass-through).If would need to derive the equivalent of vIP by reading reading by vIP of equivalent the derive to need would 2. Guest assignmentof External Interruptwith Root Intervention. 1.Interrupt. External of assignment Root register, register, application GuestCtl2of GuestCtl2 wise it is visible to root context through 10.7.1.1 Handling Interrupt Non-EIC 10.7.1 External Interrupts 192
193 is 0 then 0 then is HC to be cleared. ), and one for the IP[n+2] ) to be cleared, thus to be cleared, RIPL . The guest associated The guest . GuestCtl2 specific source by clear- by source specific EID vIP[n] 1, then the deassertion of deassertion then the 1, IP[n+2] =1), two =1), interrupt priority-
. Hardware clear capability is is capability Hardware clear . is VEIC Root.Cause HC Root.Cause If a bitIf a of
))) vector number to the core. vector number GuestCtl1 gnals are combined in an implementa- an in are combined gnals the field is writeable or preset the writeable to 1. field is or GuestCtl2 Root.Cause HC[n] assignment externalof interrupts and GuestCtl2 ble interrupts for thatinterruptsforble ) or GuestCtl2 ) or Guest.Config3 to be cleared. to should notcause vIP PIP[n] If a bitIf a of
field. and GuestCtl2 vIP [n] vIP =0, the assumptionis that is nothere external interrupt pportedinthe implementation. becauseThis is theEIC onsiblefor combining internal and external sourcesinto a tly there is no capability to distinguish between the two is tly no there RIPL by hardware is,as derived or from theEIC input. A Gues- bus. Thus the GuestID for the root interruptThus for the the bus. GuestID bus maybe non- is fixed - it is either a vec- fixed EIC is the from accept core can lized vIP[n] GuestCtl2 HC[n] causes corresponding tobethiscleared. In case, itis the responsibility rootsoft- of is reset. is thiscapability toinject interruptsinto Guestcontext for guest
. providesthemeans to roottodistinguish software between the cal virtualized EIC source a cal virtualized EIC source Cause vIP vIP ID GuestCtl2 HC vIP[n] vIP[n] estinterrupt buses as per the following rules: GuestCtl2 or (GuestCtl2 or ). The root and guest timer interrupt si interrupttimer guest root and The ). GuestCtl2 GuestCtl2 GuestCtl1 at can be detected by the presence of presence by the can be detected at to transfer an external interruptHW[n] for guest servicing. Inthis scenario, vIP [n] . [n] vIP GuestCtl2 tcontext serves two purposes - root s are supported.Thiss capabilityare exists if RIPL PIP[n] ((HW[n] and GuestCtl0 and ((HW[n] =
GuestCtl2 ways causes the associated causes ways GuestCtl0 ned, the type of vector a virtua of vectortype the ned, e transfer. Otherwise, Root would have to disa to havewould Root Otherwise, transfer. e Guest.Cause n makes EIC mode available indicated(as by IP[n+2] IP[n+2] Onthe other hand, Rootcan use . is assertedis in both cases described. CSS is also sent on each of the Root and Guest of the Root each also sent on is number), and EICSS or (offset the interrupt Vector PL, =1 and theassertion of IM[n] Handling: Handling: is providedto controlhow IP[n+2] IP[n+2] IP IP (HW[n] and !( (HW[n]
HC[n] HC Root.Cause = Guest.Cause Root.Status The EIC shouldThe assign interrupts to root and gu tor number or offset but never both. This is because curren but never offset tor number or types, intentionally so. Itis recommended that a typi zero. The GuestID for a guestGuestIDfor zero. The interrupt taken inrootmode must be registeredin can alsosendcan an interrupt for guest on the rootinterrupt interrupt buses. The Vector fromtheeitherEIC is utilized interruptbuses. TheVector tID accompanies onlythe rootproviding bus, GuestID is su In the architecture as defi as architecture the In Guest.Cause two. Root softwarethis facility can use GuestCtl2 virtual device drivers, as an e.g. In this case, In this an e.g. as device drivers, virtual Virtual interrupt handling is an option th is an option handlinginterrupt Virtual InEIC mode,the external interruptcontroller (EIC) resp is singleinterrupt-priority level, whichin appears the tion-dependent way with external inputs toproducethe root and guest interruptpriority levels. RI addition to In ing transparently affecting th affecting transparently In summary, interrupt injection in gues Insummary, injectionof virtualinterrupts to Guest. GuestCtl2 Guest.Cause Root.Cause tiedto the injected interrupt, and thus assertion of levelsignals mustbegenerated within root context the onefor the EIC - (affecting with the guestbusis by defaultequal to GuestCtl2 guest context (affecting context (affecting guest the deassertion HW[n] doesof notcause related interruptsexternal al ware toclear by writing to 0 When an implementatio When also an option, virtualeven if interrupt 10.7.1.2 EICInterrupt Handling MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
to the EIC. EIC. the to
ID , the other for guest. the other for guest. , GuestCtl1 context, followedbywritecontext,a detects a change detects in RIPL on a active guest is posted on the is posted guest active command for the EIC. The EIC for the command the requested interruptpriority level changes and when it is visible to it and when the changes is visible em Programmer’s Guide, Revision 1.00 ID can enable guest mode operation. If an EIC If operation. guest mode enable can GuestCtl1 nt on the root interrupt bus. An interrupt for the res- the interruptfor Aninterruptbus. root the on nt terruptbus, then animplementation thecoreof is andthus be presented on root interruptbusbythe EIC. ftware programs the EIC to EIC to the guestinterruptthebus.softwareprograms If then save and restore guest restore and save then to avoidthe above mentioned race. On a guest context t vector, depending on whether the EIC provides a vector a vector the EIC provides whether dependingon vector, t An interrupt for theformerly ot context whenever hardware ot context whenever . This is equivalent to a STOP to equivalent is . This ID 0x200 EIC_vectorOffset EIC_vectorOffset 0x200 0x200 + (EIC_vectorNumber x (IntCtl.VS|| 0b00000)) GuestCtl1 MIPS64® I6500Multiprocessing Syst send interruptsto guest context by setting r the delay between r when the the delay . Once the write is complete, root software root Once the write is complete, . rootcontext, twointerrupt different vectorone for root s are used, ID vectorOffset vectorOffset vectorOffset vectorOffset vectorOffset vectorOffset vectorOffset vectorOffset ector number (vectorNumber). ector Hardware shouldHardware not stall theinterrupt until entersthe processor guest mode. . IPL GuestCtl1 endif else //GuestIDis non-zero endif // relative(GuestID=0) EIC providesif 0x200to an offset else //GuestIDis non-zero if (GuestID=0) if Config3.VEIC=1 &&IntCtl.VS!=0 && Cause.IV=1&& Status.BEV=0 endif else // EIC provides vectorOffset if (EIC providesif vectorNumber) send an interrupt for a non-resident guestonthe guest in notrequired torespond to this interrupt. ident mayguest alsobe senton the root interruptbus. A guest interruptwhileisprocessorin therootmode can cause an interrupt immediatelyunless masked by Root.Status And interrupt for a non-resident guest must always be se be always mustnon-resident guest a interrupt forAnd •onsent be residentguest can a interrupt for an Only •guestinterrupt requiresroot a intervention, If EIC. the rootinterruptbus thenbe presented on by theit mu st • Rootinterrupts mustalwaystaken be contextin root endif offset (vectorOffset) orv offset EIC_modeif EIC_mode EIC_mode the respective interrupt buses from the EIC. It is possible for an EIC implementation to have active interrupts on both oninterrupts active have to for an EIC implementation possible is It EIC. the from buses interruptrespective the In thisbus. case the root interruptis always higherpriority thenthe guest interrupt. For of in the case an interrupt Hardware is able todistinguish between the two by checking the GuestID onthe root interrupt bus. Thefollowing generatesinterruphardwarehowpseudo-code describesthe switch, mustroot software first write 0 to EIC to avoidspurious a interrupt fornon-resident a guestfrom beingsenton guestthe interrupt bus. processorThe and EIC are requiredto implement a protocol recognizes this as a stall and does not a stall as recognizes this can software thecore. Rootinterrupt guestbusto the 0 on to of new GuestID to new of implementationandrootsoftware followthis recommendation,then thisprevents lossof an interrupt postedto the guest interruptbuswhile rootis switching guest context. Root interrupt bus. interrupt Root An EIC mode interruptis generated in eitherguest or ro An implementation must account fo An implementation To allow the EIC to distinguish between resident and non-resident guests, the core must send guests, the core must and non-resident resident between EIC to distinguish the allow To 194
195 is GRIPL
ss is disabled in is disabled ss EIC when the inter- EIC when GuestCtl2 providing if the interrupt on the on the interrupt if ESS EICSS cause a loss of an interrupt. cause d on this bus. Hardware can this bus. d on ion. There maybe some arbi- e root ERET instruction causes root ERET e tCtl1ID. notIf theyare equal, then a STOP command on interface to on command a STOP root or guest context. If interrupt ser- interrupt If context. or guest root Root.SRSCtl guest context. If a return to root mode root If a return to guest context. appropriately. If acce If appropriately. Guest.SRSCtl ot been received on context after having SS and RIPL storage in root CP0 state and is SS to to rrupt was received on the root interrupt bus, received on the root interrupt was rrupt into guest CP0 context on guest entry. intocontextCP0 on guest guest entry. CU[2:1] EICSS EICSS ed to the EIC as this may the EIC as this may to ed mode and hardware detects that detects and hardware mode Saving the fields as root CP0 register allows for nesting for nesting allows register CP0 root as fields the Saving re may execute whatever software sequence it needs to. it needs execute software whatever sequence may re on of preventing hardware transfer by clearing the receive not interrupt was , then the , root ERET then instruct g guestby a interrupt providing GuestCtl2GRIPL is non- GuestCtl2 Root.Status changea to guestmode. In themeanwhile, another root iggeredcontext,in rootthen the use thesefieldsof does not iced in guest context, then th then guest context, in iced ID , and and GuestCtl2 , root software must first insert first must root software , ID RIPL eans, and must be saved/restored if necessary. if be saved/restored and must eans, providing GuestCtl2GRIPLis non-zero. GuestCtl1 GRIPL GRIPL . Otherwise, hardware forces use of hardware Otherwise, . because processor is in root mode. d ERET instruction where EIC can respond withan interrupt on guestbus, e the interrupt is transferred from ro is transferred interrupt e the would non-zerorootinjection.be case a of value for the GuestCtl1 ndler must compare GuestCtl1EID to Gues GuestCtl1EID to must compare ndler returned to the an is acknowledgement returned d implementation, EICSS ntext. The root ERET instruction causes a transfer to guest mode (when to root mode even if there was a change in was root mode even if there to Guest.Cause GuestCtl2 where the root interrupt bus Vector, EIC where the root interruptbus Vector, GRIPL to to erwrite the fields on the bus. fields on the bus. the erwrite D are equal,D save and restorethen is notneeded.Interrupt servicing may either con- . Once quiescent, root softwa . when guest the processor enters on the guest interrupt bus as guest interrupt bus the on is received on the root interrupt bus, hardware must always send an acknowledgement on received is ID an interrupt into guest context after the inte an GRIPL Root.SRSCtl e not protected by any m by not protected e GuestCtl2 GuestCtl2, GuestCtl1 GuestCtl2 is non-zero. Root software thus has the opti non-zero. Root software is before guest entry. , and not transfer back , GRIPL GRIPL EPC interrupt can occur which can ov occur which can can interrupt interrupts. of nesting supports thus and fields, these of of optimizes the transfer Hardware is required, thentheinstruction HYPERCALL mustbe used. register, CP0 root The typical EIC-base in a required because rupttriggered.is If aninterruptis initially for the guest tr executed to effect is until the root ERET instruction occur determine this because determine this EIC by writing0 to Hardware writes This is followedThis is bya newwrite of to GuestID Access toCOP1Access FPR and COP2 may be protectedsetting root interruptbus is for any guest. wher the scenario guest interrupt in The the root interruptbus is caused GuestCtl2 root injects case where the In GuestCtl2 return acknowledgementsare not two that ensure must hardware Once inguest mode, the guestinterrupt handler completeswith instruction.an ERET The guest continues execution its from zero. As described above,any for inchange interrupt is for non-resident guest, and interrupt servicing may either continue in continue either may servicinginterrupt and guest, for non-resident is interrupt etc) follow- (CP0, GPRs state guest resident the save first must the handler then context, guest in continue is to vicing co ingbyrestore a guest’s of the new GuestCtl0GM=1), followed by a guest interrupt GuestCtl1EIDIf and GuestCtl1I serv be to is interrupt If the context. or guest rootin tinue changea to guestmode (when GuestCtl0GM=1), followin an interrupt where the case In If the If interrupt is for guest, then theha hardware should guestroot,contextbyinto interrupt was injected the case where thein bus.interruptBut root the on send an acknowledgement not non-zero. trary delaybetween write of GuestID an buthardware does nottrigger an interrupt use mustinterrupt root A s the appropriate exception (Coprocessor Unusable in root con- root in Unusable (Coprocessor exception appropriate the causes and guest in disabled is also it then context,root ar Hi/Lo registers text). MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
) PIP[5:0] terrupts. Hence the value value Hence the terrupts. on a read is generatedfrom read on a eudocode example. The result The example. eudocode RIPL / IP em Programmer’s Guide, Revision 1.00 field and is the value value used to determine the is field and Guest.Cause RIPL / IP rectly assigned external in external rectly assigned is source of interrupt. source is as shown in the following ps following the in shown as Guest.Cause ) GRIPL OR (irq[7:2] AND Root.GuestCtl0 AND OR (irq[7:2] IP[1:0] GRIPL is however preserved. is however vIP[5:0] IP/RIPL is not supported, then root writes Guest.Cause.IP writes root then not supported, is MIPS64® I6500Multiprocessing Syst and from the status of di of from the status and IP[1:0] IP[1:0] vIP[5:0] vIP is incorporated in EIC. is incorporated GRIPL = 1) and 1) = =1) =1) G2 G2 = 0)) then = 0)) does not apply in EIC mode. in EIC not apply does != 0) and != 0) VEIC VEIC =0) = 1) and IP[1:0] IP[1:0] PT VS BEV PIP GRIPL GRIPL IV HW[5:0] GuestCtl2 Root_HW_VIP[5:0] Root.GuestCtl2 EICGuestLevel GuestCtl2 # if GuestCtl2 # if # root software injects interrupts. injects software # root r in a the write captures H/W context. in guest interrupt inject # to Root_HW_VIP. called register # shadow r r irq << 2) OR Guest.Cause 2) OR irq << irq irq irq GuestCtl2 else # h/w must clear if GuestCtl2 if must clear # h/w # All interrupts processed first by root. by first processed interrupts # All if (GuestCtl0 endif supported. passthrough interrupt # Guest if (GuestCtl0 - FDCI is only visible in root context. in root visible is only - FDCI (Guest.Cause else r (Guest.IntCtl # State of Guest.Cause of # State # Guest in non-EIC mode in # Guest enabled. passthrough if guest in factored interrupts External # - if implemented here, applied interrupts Internal # - root. by injection interrupt guest for support Includes # - irq[7:2] if (GuestCtl0 endif # Guest.Cause else (Guest.Status # Guest in EIC mode in # Guest GuestCtl0 # - signal EICGuestLevel in the sources guest interrupt include EIC must # - # if implemented. PCI and IP1, IP0 TI, Guest’s includes - This mode. in EIC required GuestCtl2 # - if (EICGuestLevel > GuestCtl2 else # Returns: # Non-EIC -# EIC IP7..0. : GuestInterruptPending() subroutine + IP1..0 << 2) (RIPL if ((Guest.Config3 whether a guest interrupt is taken.valueis whetherNotea guest interruptreturned that thefrom the valueoriginally written by the root writtenby the root maynot be equaltothe valueback. read The interrupt pending value seen by the guest is calculated is the guest by value seen interrupt pending The valuecan be read by root)the guest (and the from the 10.7.2 Derivation of Guest.Cause 196
197 . This . Compare Compare is allowed is allowed is is written by IP[IPTI] TI TI ) Compare Cause in non-EIC mode or PIP[5:0] IM and Guest and Guest ) Status IPTI Count and indirectly Guest and . bleto the guest. TI that is set when Guest.Cause that is set ) TI TI Cause IPPCI . Once Root transitionsto guest mode,then guest if there are are if multiplethere guests in operation.Otherwise,if . As per baseline MIPS architecture, a write to architecture, MIPS per baseline As . IP[IPTI] Section 10.7.2 TI Cause Cause IP[1:0] or “Other External and Internal interrupts”. and Internal External or “Other thas beenswitchedmaintained out, butby root, its virtual trig-is timer, TI ng() is subsequentlyqualified by Guest and Guest 1 0 is in root mode, then a match on Guest on match a then mode, root in is TI before entering guest modethe for guest. Guest would takea timer interrupt, TI TI ]=1) TI Cause TI Cause is a hardware shadowa hardware is copyof Guest.Cause TI TI and Internalinterrupts” is defined in r OR (PCIEvent << Guest.IntCtl << OR (PCIEvent r Root_HW_VIP[5:0] OR (irq[7:2] AND Root.GuestCtl0 AND (irq[7:2] OR Root_HW_VIP[5:0] r << 2 r << Guest.IntCtl OR (GuestTimerInterrupt r OR Guest.Cause r options are availa interrupt options registers indicate which Root.Guest.Cause Guest.Cause , which would then clear Guest would then clear which , = Root.Guest.Cause Root.Guest.Cause r
Config in EIC mode, as per the base architecture. . else endif IP[IPTI] IPL TI Compare if (MTGC0[ if r else if ((MTC0[Guest.Compare])) endif endif r r r Cause Status Cause endif return(r) endsub clears Root. Guest. timer interruptcan be signaled inguest mode. TI: Guest of Injection Root Rootmaintaining a virtualtimera guest for is recommended there is only one guest, but the processor guest, but the processor one only is there Guest where “Other External where Rootmay inject timera interrupt inguest context by setting Guest The value by GuestInterruptPendi returned The in an implementationto setGuest may happen under the scenario where a gues scenario where a happen under the may Guest set would Root gered. Fields in Guest Fields in Guest where Root.Guest.Causewhere clear Guest clear 10.7.3 Interrupts Timer MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
Perf- is is and . PCI UNPRE- PCI as follows: registers but is registers but 2 or as 3. PC and Root EC Cause PerfCnt(N+1) registersin RootCP0 tializes guest context. guest tializes register pair(s). These These pair(s). register ed, the encodings of encodings ed, the PCI WatchLo WatchLo Config1 y Watch register support, or support, register Watch y PerfCnt Guest.Cause Cause WatchLo WatchLo and = 1. = to indicate to register interruptmasksand WR and EC[1] em Programmer’s Guide, Revision 1.00 WatchHi Status =1. If virtually shar tly managesthe performance counters, Config1 WatchHi PC performance counter interrupt by clearing the by clearing interrupt performance counter Guest access when it ini when Guest access est via Guest context t. A Guest may have direct access to virtual perfor- to virtual direct access have may Guest A t. PerfCnt(N+1) Config1 emented in the guest context, access in access is the guest context, emented to a guestto a is not dynamic- once established initial after ounter register. Root soft- Root register. performancecounter access to a Guest enabled context enabled , IE Otherwise, counter overflow sets Guest. counter overflow sets Otherwise, a GPSI Exception. PerfCnt = 1 and in Guest if Guest Guest if 1 and in = doesnot requiretheability to read/write fields takenis fromthe current Root or Guestcontext. nce counters in theGu should returnroot WR M EXL MIPS64® I6500Multiprocessing Syst lt) context, that context independen context lt) context, that and as such for duration of guest. en remain as the allotment must Config1 PerfCnt(N) access does not cause does not access pairs are allocated to guest, then guest read of the last M bit must return 0. Guest bit M last of the then guest read guest, pairs are allocated to K, S, U, counter. Similarly Root may clear a guest Similarly counter. oot and Guest. Root typically configures the typically configures and Guest. Root oot PerfCnt =0, then performance counters are unimpl are counters then performance =0, contexts. by root and guest performance are virtually counters shared the =1, register PerfCnt . PC PC . Status fieldis Root only virtualization controlandis not visible to the Guest. are set by hardware on counter overflow. overflow. counter by hardware on are set
IP[IPPCI] register(s) are never implemented in the Guest contex in the are never implemented register(s) EC Config1 Config1 as 0 or 1 cause a GPSI Exception to be raised on raised be to Exception GPSI a or 1 cause 0 as use of use interrupt behavior is solelygoverned by EC IP[IPPCI] Cause PerfCnt DICTABLE PerfCnt pairs assigned toGuest in this mannermust be a contiguo Itis range, us starting fromthe least significant pair. context to Guest. Read of guest context Read of to Guest. Alternatively, an implementation mayoptiona llychoose to assign a subsetAlternatively, thetotal of PerfCnt If assigned to Guest then Guest assigned to Guest If manceregistersundercounterrootsoftware management when Guest. Software may choose to assign all performance counters to Guest or Root, but not both. This is the recommended pol- the recommended is This both. not but Root, Guest or to counters all performance to assign choose may Software icy R for sharing between generically referred to as “Watch” registers. registers. “Watch” to as generically referred The ware may choose to configure performance counters for legal Guest access by encodingby may choose to configureaccess ware legal countersGuest performance for registers are present in registers Rootare present if Root • Guest The Root and Guest Watchpoint debug support is provided by Coprocessor 0 Coprocessor by provided is support debug Watchpoint and Guest Root PerfCnt PerfCnt Cause PerfCnt Rootcan configure the definition performaof further assumed that the allotment performanceof counters Cnt GPSI), th (which caused guest access Root (defau to Guest or Once assigned including interrupts.if the performanceenabledE.g., counters are for Root, then Root ownedby guest.If all A virtualized implementation may choose to provide no Watch register support, Root-onl support,register Watch no provide to virtualizedimplementationchoose may A handling applies to both registersupport. Virtualized Rootand Guest Watch enable. most-significant bit of the counter. Thus, Root most-significantbitthecounter. of ormanceto inject a perf counter needs interrupt Root software intoGuest context,If itsettingmustthe do so by most- of the significantbit • Guest 10.7.4 Performance Counter Interrupts 198 10.8Debug Support Watchpoint
= WR WR 199 WR - Config1 None Root Watch Watch Config1 Exception - ers under Guest control. If under Guest ers = 1), then Root and Guest and = 1), then Root None , and an MFC0 will return 0s return and an MFC0 will , Watch Guest Match WR [1:0] 2inwrites this configura- WM 0s on MFC0. If Guest 0s to determinewhether virtual register pair is assigned to Guest, is pair register Exception on on Exception WM WR GPSI exception. Root may choose to may choose GPSI exception. Root [1:0], will write 0, defaulting to RVA [1:0], will defaultingwrite 0, to RVA are enabled for Guest watch. A Guest for are enabled Config1 present. WM WatchHi port provided. port WatchHi Config1 [0] determines whether Rootis watching = 0) allows for Root Watch of Root Virtual of Root Virtual allows= 0) Rootfor Watch WM - Virtual Guest Watch sup- Guest Watch Virtual WatchHi WR None GPSI e enabled for Rootor Guest watch. Referring to Access an MTC0 and return and MTC0 an ss of a sharedregist pair of WatchHi Config1 Guest Exception on on Exception Guest gisters. Rootemulation of Guest watchwouldregisters C0 cannot modify C0 [1].Root R/W State R/W Function R/W (Root) R/W return to the guest instruction following themove. WM = 0, thennowatch= pairs register = 1 and Guest . conveys what support is available to Guest. available to is what support . conveys [1]=0 then a Guest access results in a results Guest access then a [1]=0 WR WR t Watch present registers are (Guest t Watch ap to Root. In sharing mode, once a watch ap WR The I6500 will no-op will The I6500 Table 10.9 Table Control Watch WatchHi Reserved WM Function rmally except a MT a except rmally Root Watch RVA Watch Root Software can test R/W state of can test R/WGuest state Software Value Guest Watch GVA Guest Watch Config1 Config1 Config1 WR Table 10.8 Table Support Watchpoint Guest WatchHi 01 R Rregisters. NoGuest Watch registers Watch Guest 0/1 R (Guest) Config1
, Guestif WM[1:0] = 1, then selected Root Watch register pairs ar 1, then= selected RootWatch 11 00 10 Guest Root WR , the state of Guest Guest of state , the Table 10.9 WatchHi WM. , this is determined by Root
Config1 WR WatchHi Table10.8 1 01 1 X0RVA Watch Root UNPREDICTABLE None access is treated as UNPREDICTABLE. access RVA or GPA. Root Watch of GPA is optional. A write of 1 to Root Root to 1 of write A optional. is GPA of Watch Root GPA. or RVA Table 10.9 = 1, then a Guest access is treated no access is treated a Guest 1, then = IfGuest In Guest withoutcan setupregisters Root intervention. Referring to There is no supportRootfor emulation Guestwatch of re that read and write tr every require guest Guest Watch registers are supported. Guest Watch assign thispairregister to Guest at this point, or 0/1). This feature is optional.Thisfeature is 0/1).Root Root-only Watch registers (Root registers Root-only Watch Addresses (RVA). If both RootandGues Addresses (RVA). for watch. of 3 A write toRoot underGuestIf control, Guest can only watchGVA. Watch operates independently. operates independently. Watch (Guest registers Watch Root via Watch Guest virtual for also allows definition Debug Virtualization The tion, defaulting to GVA watch. Root can take away privilege from Guest at any time by writing to Root Watch regis- watch. Rootcantakeaway privilegefrom Guestat anytime bywriting toRoot Watch tion,defaulting to GVA on acce not take an exception does thus Root access The ters. under Rootcontrol with Root Config1
Value (in R/W State) Guest MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
10.1.8 Reference Section Debug Technical Technical Debug Debug Technical Technical Debug Reference Manual Reference Manual = 0) = is, events occurring when events is, = 1))
DM DM MIPS On-Chip Instrumentation MIPS MIPS On-Chip Instrumentation MIPS ged execution modes; kernel, cessor is running in debug privileged is cessor em Programmer’s Guide, Revision 1.00 Root.Debug Root.Debug the Root context. the Root = 0 and and 0 = = 1 or
ERL ERL not in guest mode. not in guest Root That intervention events. se a GPSI exception. a GPSI se are used to transfer data est, privile there are three est, step process is required - to step the provided to ini- instructions root context - TLBGP, TLBGR, TLBGR, TLBGP, - context root st use the Virtualization Module use the Virtualization st estCP0 context. When accessing 0 context and guest TLB, and to and guest TLB, and 0 context Debug mode, it has full access to has it full mode, Debug pipeline. in the processor ions Root.Status Root.Status data between the root and guest and data between the root that are available in that CP0 context and guest CP0 context. CP0 and guest CP0 context e to Root-Kernel to Root-Kernel mode e operation. Description clusive with Debug mode. When in mode. Debug with clusive lication to the Virtualization Module. licationtothe Virtualization = 1 or = 1 =1), the processor is processor =1), the
ere are four; kernel, supervisor, user anddebug. kernel,supervisor, are four; ere = 0 and DM EXL access to debug facilities. When the pro When to debug facilities. access MIPS64® I6500Multiprocessing Syst EXL est access does not cau does est access Debug Root.Status Root.Status bug tools tools access general purpose bug registers (GPRs) and coproces- to Root, Guest or but not both. This is the recommendedpolicysharingbetween for Root and tiate guest TLB operations from the from guest TLB operations tiate all resources that are availabl are that resources all context. root the by determined sor instruct registers by executing mu CP0 context guest the to Access to transfer provided instructions contexts MTGC0 and MFGC0. - Accesses to theguest usemust TLB operations These TLBGWR. TLBGWI, between guest and the gu the TLB TLB in mode, a two- the debug guest root the to/from data transfer When the processor is running in the is When processor running guest CP the to/from data transfer Debug mode ( mode Debug = 1 and = 1 and 1 = ( , The debug privileged execution mode exists in the root context. A processor supporting virtualiza-supportingprocessor A context. the root exists in mode execution privileged The debug , GM GM WatchLo Table 10.10Table Module Virtualization to Application and Features Debug lists debug features and their app and lists debug features and Table 10.1 Table Feature Debug modeDebug is ex mutually mode Guest Root.GuestCtl0 Root.GuestCtl0 There facilityis no Guestfor to watch addressesrelatedto the following equation true:is ( The Virtualization Module provides full Virtualization The execution full accessmode, it has to all resources per As Guest watchenabled is strictlyin guest modedefinedby as the equation: ( The I6500 supports virtual sharing betweenRoot andGuest. Root As such, maysoftware choose toassign all WatchHi Guest. If assigned to Guest then Gu assigned to Guest Guest. If tion operates in two contexts, Root and Guest. Within Gu tionin operates two contexts, RootandGuest.Within and inRoot context, th andsupervisor user, Table 10.10 Debug (dseg)Segment is map memory the in Debug mode, the is running When processor Access to guest CP0 contextAccess De 200 10.9 Mode and Debug Features Guest
201 10.6.4 Section 10.8 Section Reference Section Refer Refer to guest software. debug are of root part the con- In both cases, the excep- cases, the both In e pro- Guest is optionally ve during mode execution, guest during ve re breakpoints of type Syn- breakpoints are re Description kpoints to be used to used to be kpoints e of watch-point from th of from watch-point e mented, hardware breakpoints hardware mented, vided. tions are handled in Debug mode. handled in Debug are tions Exceptions resulting from hardwa Exceptions Debug. Debug or Asynchronous chronous text. root remains acti The context hardware brea allowing Table 10.10Table Module Virtualization to Application and Features Debug Feature Watch registersWatch for us Support Hardware BreakpointsHardware Whenimple MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 em Programmer’s Guide, Revision 1.00 MIPS64® I6500Multiprocessing Syst 202
203 . Table 11.1 C). There is one SAARI reg- There C). index into the SAAR reg- SAAR the into index gister to access the associated block. the associated to access gister determines whether the DSPRAM is whether the determines or other module is being accessed. module is being other or . is There core. one SAAR registerper validate access. No other tag array. other tag access. No validate P0 Register 9, Select 6) Register Index. Provides an read Communication Unit (IT read invariant format to facilitate access to the DSPRAM as shown in as shown to the DSPRAM access to facilitate VP and provides an index value that index value provides an VP and ister to indicate whether the DSPRAM the to indicate whether ister There one VP. is per SAARI register size block the as well as located, be SAARI registers use the same SAAR re same SAAR the registers use SAARI RegisterIndex SAARI— (C cache to minimize access latency. latency. to minimize access cache ead/write in byte ead/write ECC/noneon 32 bitgranularity) ) is checked against base and range ) to is checked against base and these register is shown below. register is shown these ing twonewCP0 registers. Table 11.1 Table DSPRAM Module the Accessing for Used Registers CP0 9 6 SAARIAddress Access Special 9 7 SAAR will DSP the where address the base Stores Register. Access Address Special The SAARIThe register is instantiated per- accessed, or another block is accessed such as the Inter-Th as such accessed is block or another accessed, multiple This means that per VP. ister Two new Coprocessor 0 registers have been added have been added 0 registers Coprocessor new Two The DSPRAM modulefollowingthe features:has • 16 Bytewide data pathboth for read and write operations • Data (parity/ be protected can •multi-cycle One or latencyr for • Multi-threaded design, so the blocking of onethread may notblock other thread •(RPA physical address Root The optional Data Scratch Pad RAM (DSPRAM) block provides a general scratch pad RAM used for temporary stor- temporary for scratch pad RAM used general a providesblock Scratch Pad RAM (DSPRAM) Data optional The age of data. The DSPRAMprovidesconnection a to on-chip ormemory memory-mapped registers,which are data the L1 with in parallel accessed the of address base The etc.) KB, 256 KB, (128 size 2 of power any to set be can but RAM size is 64 KB, default The DSPRAMin memory set us is for each of bit assignments The Number Sel RegisterName Description Register 11.1.1.1 Address Access Special 11.1.1 New CP0 Registers MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 11.1 Overview Data RAM Pad Scratch Data Chapter 11 Chapter
1 0 0 0 0 TARGET SIZE EN R 6 5 65 0 R Communication unit (ITC) unit Communication R/W Read/Write ResetState Read/ Write Reset State size of the DSPRAM block. block. DSPRAM the of size Reserved is encoded as 2^SIZE to indicate the indicate to encoded as 2^SIZE is em Programmer’s Guide, Revision 1.00 sses. Once thisinformation pro-is 12 11 s between the Inter-Thread between the s moreinformationfor on howthe SAAR register is for more informationmore for on howthis register is used. block is accessed. If blockis the value set accessed. to0x00, is ITC the the DSPRAM. This field storedis in bits 43:12 theof d by the SAAR register. by the d SAAR register. intoeitherthe SAAR0_ITCor SAAR1_DSPRAMhardware stores the base address address the and base stores the size of theDSPRAM is 2^17,128 or KBytes. itten as zero. Reads are undefined. are Reads zero. as itten — SAARSelect 7) (CP0 Register 9, Description itten as zero. Reads are undefined. are as zero. Reads itten ADDR[47:16] Description MIPS64® I6500Multiprocessing Syst register enables DSPRAM ITC acce / the default DSPRAM size is 2^16, or 64 KBytes. Similarly, a value of 0x11 a value of 0x11 the defaultDSPRAM 2^16, size is or 64KBytes.Similarly, Reserved codes the size of the DSPRAM. This field This DSPRAM. the of the size codes TARGET field that select TARGET ogic block ogic to be accesse Figure 11.2Figure Format Register SAAR Figure 11.1Figure Format Register SAARI bits be wr should Register Register Programming Sequence Register Sequence Register Programming Table 11.2 Table SAARI Register for Descriptions Field Table 11.3Table SAAR Register for ons Descripti Field for more information onthesetwo hardware registers. 44 43 This field is encoded as follows: is encoded field This ITC 0x00: DSPRAM 0x01: 0x03F: Reserved - 0x02 values will be dropped. to reserved Writes 63:44be wr bits should This Reserved. 5:0l the between Selects 31:6 This Reserved. Reserved The 64-bit SAAR register is instantiated per-core and instantiated per-core is 64-bit SAAR register The used. Refer to Refer the sectionentitled and the DSPRAM. If and thevaluetheDSPRAM. 0x01, to is set the DSPRAM 32-bitThe ADDR[47:16] field indicates the base address of SAAR register. en register of this field SIZE 5-bit The to corresponding is 0x10, value the default For example, KBytes. is 64 field for this The default DSPRAM. of the size that means 16. This of decimal value a that 17, meaning value of decimal to a corresponds An ENABLE bitlocated inbit 0 of this grammed intothe CP0SAAR, itis moved byhardware ET field described above.to Refer the sectionentitled registers dependingon the programmingof TARG SAARI the DSPRAM Accessing the block is accessed. block is to Refer the sectionentitled Each SAARI register contains a 6-bit a contains SAARI register Each Name Bit(s) 11.1.1.2 Address Access Register Special Reserved Name Bit(s) TARGET Reserved 63 31 204
205 0 0 R R/W 0 R/W 0x10 R/W e. The read/write access to e. The Read/Write ResetState aligned to the size of access (i.e. 4 of access size aligned to the (continued) wever, since the DSPRAM is a 1-way set 1-way DSPRAM is a the since wever, to trigger on a cache error exception. When exception. cache error on a to trigger is preset at build time. build at preset is requests for load instructions can be issued to the issued be for load instructions can requests ng CP0 registers have been modified as shown have below. as been modified registers ng CP0 was detected.was Encoding 0x8of this field was addedto structions are non-speculativ s alignment can cause anaddress (i.e. s error exception fer to fer the I6500 CP0 Register information.moredocument for e upper 48 KB of address would not KB upper 48 e the base physical address for the loca- the for address physical the base itten as zero. Reads are undefined. are Reads zero. as itten Description ZE field should be 0x10. field should ZE register provides details about the error. The remaining bitsof register provides CacheErr aboutdetails theerror. ded as 2^SIZE bytes. This bytes. 2^SIZE as ded instruction to the DSPRAM must be instruction to the DSPRAM must 0 Registers — Error Reporting (CP0 Register 26, Select 0) cate the array where the error where the the array cate ndicate the the error occurred. Ho way where ndicate register, thefollowing fields are described.Note thatonly those register, bits thathave changed register, bit the DSPRAM 31 is used to enable register, tion of the DSPRAM in memory. The address must be at least 64 KB- 64 least be at must address The in memory. DSPRAM the of tion aligned = PA[47:16]). (ADDR[47:16] For a 64 For KB the memory SI The actual sizetheof device size canbe set to a smallerthan KB, but 64 if example, For be 64 KB. must window address of the size minimum the 16 KB, th occupies only memory the be used. be current value the current of bit. Table 11.3Table Register SAAR for Descriptions Field 0 the gives A read DSPRAM accesses. allow to set be must bit enable This 5:1 Enco device. the Sizeof 11:6be wr bits should This Reserved. 43:12Address. This field Base specifies indicate a DSPRAM error. DSPRAM error. indicate a associative memory, this field is not used. field is not this memory, associative • Bits 21:20 usedare to i are defined here. If notdefined, the field(s) behavethe same as inprevious generationcores.Refer to the I6500 CP0 Registersdocument for more information. • Bits 29:26 usedare to indi this bit is set and an error occurs, the CP0 occurs, set and an error bit is this behavethisregister the same as in previous cores. Re IntheI6500 CP0 CacheErr The DSPRAM is accessed by Load and Store instructions. Read instructions. and Store Load by DSPRAM is accessed The IntheI6500 CP0 ErrCtl for store in requests Write module speculatively. DSPRAM To accommodate error reporting by the DSPRAM, two existi accommodate error reporting To the 16DSPRAM is Bytes (128 bits) wide for data. GINV*,CACHE,LL/SC variants, The andPREF instruc nottions are supportedon the address space of the the load/store of DSPRAM. The address bytes, 8 bytes, or 16bytes). Anyviolation of the addres unalignedloads/stores to DSPRAM are notsupported). The SYNC instruction will enforce ordering of DSPRAM stores. and loads EN SIZE Name Bit(s) 11.1.2.20) Select 27, Register (CP0 — Error CacheErr Cache 11.1.2.1 Error — ErrCtl Control Reserved 11.1.2to Existing CP Changes ADDR[47:16] MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 11.2 Interface DSPRAM Software
AARregister with the on the programming of the on the programming 0_ITC register is dedicated to the dedicated to register is 0_ITC em Programmer’s Guide, Revision 1.00 Special Address Access Register (SAAR) Register Access Address Special ftware programs the S the programs ftware er is setto 0x00,programs kernel software theSAAR DSPRAM register is dedicated to the DSPRAM.These dedicated register is DSPRAM AM, thereby setting the base address and thethesize of gister per core, and one SAARI register per VP. This means This means per VP. register one SAARI and per core, gister accessed by hardware depends depends by hardware accessed then uses this informationtoprogram the internal . Thisfigure. 2-VP shows a implementation. MIPS64® I6500Multiprocessing Syst of the ITC block.uses ITC this theinformationHardware of to program the internal accessed using two CP0 registers; the registers; two CP0 using accessed ) located at CP0 (Reg 9, Sel 6). 9, Sel (Reg at CP0 (SAARI) located Access Register Index Address Special e two SAAR registers per core. The SAAR The core. per SAAR registers e two registers per core dependingregisters on the numberofinstantiated. VP's Figure 11.3 Figure DSRPAM the Accessing Figure 11.3 Which register is visible. dedicated to the ITC block. to the dedicated theSAARI register tois set 0x01,kernel so Inter-Thread Communication (ITC) unit,Inter-Thread and the SAAR1_ registers are NOT software two SAARIdescribedregister as in addressbase and size of the DSPRAM block. Hardware SAAR1_DSPRAMregister that is dedicated to theDSPR block. DSPRAM SAARI the field of CP0 regist when the TARGET Conversely, size register with the base address and SAAR0_ITC register thatis that there multiple SAARI can be that ar perspective, there a hardware From located at CP0located Sel at the (Reg 9, 7), and re SAAR one is perspective, there software kernel a From When the TARGET field of the TARGET When As mentioned above, the DSPRAM is DSPRAM the above, mentioned As 11.3.1 Register Programming Sequence 206 11.3the DSPRAM Accessing
207 by VPanother at any time. ster. Therefore, if one VP one if Therefore, ster. ove if it is different from theitdefaultove different if is t of the other. Therefore, if one VP Therefore, of the other. t fields of the SAAR, the programming the SAAR, the programming of fields DSPRAM mustadhere to thefollowing lue of to indicate a DSPRAM0x01 lue access. wever, if VP1 sets the base address at a different if VP1 sets thebase address at a different wever, rmationcan be overwritten SAAR can write to the regi es, this field need not be programmed. be this not field need es, register to enable DSPRAM accesses. DSPRAM enable register to re (i.e. by operating system software if Virtualization is not implemented or or implemented is not Virtualization software if systemoperating by (i.e. re the DSPRAM in the ADDR[47:16] field of the CP0 SAAR register. This This theDSPRAM in theADDR[47:16] fieldof the CP0 SAAR register. k and set the address, size, and enable address, size, and and set the k \\DSPRAM in the core. As such, accesses to the As such, accesses core. in the followingassembly language code, alongwith anexample transfer of data: dicate the size of the DSPRAM as described ab DSPRAM as described the size of dicate the of the CP0 SAARI register with a va with register CP0 SAARI of the ent, each VP can access the DSPRAM independen access the DSPRAM each VP can ent, zation implemented).is \\is stored to DSPRAM address 82000 address to DSPRAM stored \\is #define c0_SAARI $9,6 c0_SAARI #define $9,7 c0_SAAR #define target as the DSPRAM to select bit 0 \\Set t0, 000000001 li DSPRAM select of 1 to a value with register SAARI \\Write t0, c0_SAARI mtc0 enable to 64K; set size to 80000; address base \\Set t1, 0000000080000021 dli t1 of register contents with register SAAR \\Write t1, c0_SAAR dmtc0 to DSPRAM be transferred value to data \\load t0, 5555AAAA5555AAAA dli from 2000 is offset t1; this into of 82000 address \\load t1, 0000000000082000 dli 80000 of base address the Data = 0; offset t1; address in to the address in t0 the data \\Store t0, 0(t1) sd sets the base address for the for DSPRAM.theaddress sets base Notethat thisfieldresidesin bits 43:12 of the register. KByt 64 of 64 KBytes. If the size is value For VP0example, in the code above, places the baseDSPRAM example at a 0x80000 of ofwith a size 64K, so Ho the DSPRAM resides from0x80000 0x8FFFFin memory. - value, 0xA0000,such as then thelocation of theDSPRAM will be moved. sets the base address and size for the DSPRAM, that info that for the DSPRAM, size address and the base sets tents of the CP0SAARregister to either the SAAR0_ITCSAAR1_DSPRAM or hardware registers. by hypervisorif Virtuali stores datato a location in the DSPRAM,at any time. thatVP by another data can be overwritten The DSPRAM is shared across all VP's across all DSPRAM is shared The 3.the ProgramSIZE field to in sequence as follows:is 1. field the TARGET Program 2. location of address the base Program For example, to select the DSPRAM bloc example, to select For Itis incumbent upon software toensure that these conditions do not occur. 4.CP0 SAAR bit in the the ENABLE Set 5.softwa privileged the by done is This constraints: 1. The SAARI register must be programmed so thathardware knows tomove beforethecon- the SAAR register, 2.are pres multiple VP's If These steps can be represented by the by can be represented steps These 3.VP per core, each only one SAAR register is Since there 11.3.2 Programming Constraints MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 em Programmer’s Guide, Revision 1.00 MIPS64® I6500Multiprocessing Syst 208
209 . started by the con- started by Table 12.1 Cells configuredcan be to types appear as a single a single appear as types index into the SAAR reg- SAAR the into index The ITU memory region is a fixed is memory region The ITU on between threads. It is achieved achieved is It threads. on between ovides an alternative to Linked-Load/ ovides d if necessary and re necessary d if r block is being accessed. There is one block r . is There core. one SAAR registerper storage cells. Both cell Both storage cells. store instructions. numberofinstructions extra required toperform them Register Index. Provides an eading by utilizing gatingGating storage. storage is used formation and associated data. and associated formation mixof singleelement cellsand multi-element FIFO cells. d to facilitate access to the ITU as shown to in the ITU as access to facilitate d uration based on customer requirements. customer on based uration TU) is is configurationa TU) optionthat pr ister to indicate whether the ITU or othe to indicate whether ister SAARI per VP. register size block the as well as located, be multi-element FIFOdata eby allowing Inter-thread communicati allowing Inter-thread eby or store request can be precisely aborte request can be precisely or store ) is checked against base and range to validate access. validate range to ) is checked against base and these registers is as follows. as registers is these Table 12.1 Table Module ITU the Accessing for Used Registers CP0 9 7 SAAR ITU will the where address the base Stores Register. Access Address Special 9 6 SAARIAddress Access Special size of size 128KBytes. Each cell contains tag state in made ITU up of cells. is The cells, or storage element data be single addressable memorylocation, and the ITU can contain a IP config during configured cells are The trolling operating system. accessed through load and is memory mapped and ITU is The through Load and Store requests which maythrough Loadbe blocked and Store until thestateof locationthe storage changes, allowing a given. A blocked load to be response Two new Coprocessor have been adde 0 registers Coprocessor new Two Store-Conditional synchronizationStore-Conditional for fine grained multithr ther to execution streams, synchronize The ITU module providesthe following features: • 64-bitdata path •8 Byte 4 read or and write operations • Eliminates spinlocking encountered withthe LL/SC instructions • Provides support for semaphore typeswhich reduces the •(RPA physical address Root The Inter-thread Communication Unit (I Communication Inter-thread The The bit assignments for each of bit assignments The Number Sel RegisterName Description Register 12.1.1 New CP0 Registers MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 12.1 Overview Inter-Thread Communication Unit Communication Inter-Thread Chapter 12 Chapter
0 0 TARGET for more informa-morefor 65 0 R of the SAAR.SIZE field of the SAAR.SIZE R/W Read/ Write Reset State ses. Once this information is pro- Once ses. em Programmer’s Guide, Revision 1.00 ng accessed. If the SARRI.TARGET field is SARRI.TARGET If the accessed. ng ich is the ich ITU module. is Accessing the ITU Module Accessing eld is encoded as 2^SIZE to indicate the size size indicate the 2^SIZE to as is encoded eld P0 Register 9, Select 6) Register Select 9, P0 e ITU. Thisfielde is ITU. stored in bits 43:12 of the SAAR Since there is one SAARI register per VP, this this means VP, per one register SAARI Since there is for moreinformation for on howthis register is used. formore information on howthe SARRI register is a value of 0x11, whichcorresponds a defaultto size of value a 0x11, of des an index value that determines whether the ITU is that determines an value index des Ublockis accessed. If the valueis set to 0x01, the to either the SAAR0_ITUSAAR1_DSPRAM or hardware indicating the DSPRAM, a read DSPRAM, a indicating the h corresponds to a decimal value of 17. This means that thethath decimal correspondsvalue17.This means to ofa d by the SAAR register. by the d SAAR register. this 0x00, field is wh nd theaddressstores base andof size the ITUblock. itten as zero. Reads are undefined. are as zero. Reads itten SAAR register to access the associated block. the to access SAAR register Description MIPS64® I6500Multiprocessing Syst Reserved is register DSPRAMenables is ITU acces / Register Index Register — (C SAARI field depends on which module is bei is which module on depends field it TARGET field that selects between the Inter-Thread Communicationfieldthat selectsbetween theInter-Thread Unit it TARGET ogic block ogic to be accesse Figure 12.1Figure SAARIRegister Format bits be wr should Register Register Programming Sequence Register Sequence Register Programming register encodes the size of the ITU. This fi of This the ITU. the size register encodes Table 12.2 Table Register SAARI for Descriptions Field This field is encoded as follows: is encoded field This ITU (default) 0x00: DSPRAM 0x01: 0x03F: Reserved - 0x02 values will be dropped. to reserved Writes 5:0l the between Selects 31:6 This Reserved. of the The defaultof ITU. for this fieldis 128 KBytes,whic default ITUsize is 2^17, 128or KBytes. default value for the SIZE that Note indicating0, thea read ofITU, fieldyields the SAAR.SIZE field1, is if theSARRI.TARGET 128KBytes.However, field described above. These registers are indirectly fielddescribedabove. These registers registerdepending on the programming ofthe SAARI.TARGET entitled Refer to the section through the CP0 SAAR register. accessible The 64-bit SAAR register is instantiated per-core a instantiated per-core is 64-bit SAAR register The 32-bitThe ADDR[47:16] field indicates the base address of th register. 5-bitThe SIZE field of this grammed intothe CP0SAAR, it is moved in by hardware tion. to Refer the sectionentitled used. The 32-bit SAARI register is instantiated per-VP and provi per-VP instantiated register is 32-bit SAARI The the same registers use multiple SAARI that to Refer sectionthe entitled yieldsa ofvalue 0x10,which corresponds to a defaultof size 64 KBytes. bit located 0 of th An in ENABLE bit accessed, or another block is accessed such as the DSPRAM. such as accessed is another block or accessed, SAARI register contains a 6-b Each (ITU) and theDSPRAM.thevalue If to set 0x00,is theIT for The default value accessed. is block DSPRAM 12.1.1.27) 9, Select — SAAR (CP0 Register Register Address Access Special 12.1.1.1 Access Address Special Name Bit(s) TARGET Reserved 31 210
211 0 . Note 1 0 EXEC 0 0 0 0 0 0 0 0 ERROR_ 1 SIZE EN Table 12.6 PARITY ERROR_ R R RConfig IP R R R R/W 6 5 R/W R/W 0x11 R/W AXI Read/ Write Reset State Read/Write ResetState ERROR_ 3 2 is memory mapped. memory is Reserved when PA[6:3] a contains when PA[6:3] 13 12 8 7 at least 128 KB- Section 12.2.5. Section formation and the about configuration ITU formation Description address must be address ions for SAARions Register s out the out cell addressing bys virtually cell 0, but be accessed can the base physical address for the loca- the for address physical the base 0 of the ITU using cell view 0xF as described in 0xF using cell view of the ITU 0 itten as zero. Reads are undefined. zero. itten Reads as are undefined. zero. itten Reads as itten as zero. Reads are undefined. zero. itten Reads as itten as zero. Reads are undefined. are Reads zero. as itten access to cell 0. 0. to cell access Description Description ADDR[47:17] 16 15 11 10 d contains the number of cells configured in the in the cells configured of contains number d Figure 12.3 Figure Format Register ICR0 Figure 12.2Figure SAAR Register Format ITU. This register This register of the ITU. operation for the global controls value of 0xF during value an It is not physically of part is It not is implementation dependent. CELL_NUM Reserved BLK_GRAIN Reserved Table 12.5 Table FieldDescriptions for ICR0Register Table 12.3 Table Field Descript 44 43 ITU. Maximum number of cells is 32. ITU. number Maximum replicating the cells, giving multiple addresses to access the same cell. cell. same the access to addresses multiple giving cells, the replicating of by mapping individual or groups access control This to allow cell is in examples the to Refer pages. different across cells tion of the ITU block in memory. The The memory. in block ITU the of tion aligned (ADDR[47:17] = PA[47:17]). aligned = PA[47:17]). (ADDR[47:17] For KB, the SIZE field should be 0x11. 128 For rent value of the bit. rent the value of 24 23 Table 12.4Table ITU Module the Accessing for Used Registers CM3 ICR0 Contains in 0. register Control ITU 0cur- the gives A read accesses. ITU allow to set be must bit enable This 7:3wr This bits should be Reserved. 5:1bytes. 2^SIZE Sizeas the device. Encoded of 10:8 This field spread granularity. Block 12:6are Reads undefined. zero. be written as bits should This Reserved. 15:11wr This bits should be Reserved. 23:16 fiel This number. Cell 63:24wr This bits should be Reserved. 63:44be wr bits should This Reserved. 43:13 Address. This field Base specifies Register Name Reserved Reserved This register can be modified when accessing cell This register can be modified when accessing that the total number of cells number of the total that EN SIZE Name Bit(s) Name Bit(s) Reserved Reserved Reserved Reserved Reserved 12.1.2Control Register ITU CELL_NUM BLK_GRAIN ADDR[47:16] 63 63 MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
es theFIFO depth, R/W1 0 R/W1 0 R/W1 0 Cell
Read/ Write Reset State 3 2 1 0
Tag
Storage
Entry Entry Entry Entry
State
em Programmer’s Guide, Revision 1.00 FIFO FIFO FIFO FIFO (continued) Cell element ngle-element cell. In a 4-entry FIFO as ‐ state information includ state information Multi g cell types, view, state, and indexing. state, view, cell types, g y 0ofSubsequent y the FIFO. the cause writes data to be shifted te an error the bus. Software on AXI an error te te an execution error during an access access an an execution error during te set clear error. this bit to the Data
cate a parity error occurred when occurred error a parity cate Cell Description bitdata value and associatedstate information. Multi-element FIFO data MIPS64® I6500Multiprocessing Syst ry cells. Two cell types are supported; cell Two ry cells. l structure, includin l Cell
64-bit data values in a FIFO format. The FIFO format. a values in 64-bit data FO cell is accessed in the same manner as a si as a same manner accessed in the cell is FO Tag
Storage
Data Figure 12.4 Single- and Multi-Element CellsStorage
, a write operation writes to entr to , a write operation writes State must set this bit to clear the error. the clear to bit this set must accessing theITU module. Software mustset this bit to clearthe error. to the to ITU module. Software must
FIFO data storage cells FIFO Cell Table 12.5 Table ICR0 Register for Descriptions Field Cell element ‐ 2 This bit is set by hardware to indica 1 This bit is set by hardware to indi 0indica to hardware bit is set by This Figure12.4 Single shownin through in thethe entries On entryread firstFIFO. written operation, a the to theFIFO is read out first. The memoITU consists of a series of •storage cells data Single-element • Multi-element This section describes the ITU cel describes This section contain a 64- storage cells element Single storage cells contains multiple contains storage cells full/empty indication,and read pointerto indicate whichentry in the isFIFO being read. multi-element that FI a Note Name Bit(s) 12.2.1Types ITU Cell ERROR_AXI ERROR_EXC ERROR_PARITY 212 12.2 ITU Cell Structure
213 ITU CellAddressing l. operationThe exact is e requesting thread. requesting e undefined when using this view. using P/V view. All views are legal All views are view. P/V using ad thehead of theFIFO. Bypass l information. l hardware for queue messaging sup- pass value threads a single between effect on cell state/control informa- cell state/control on effect will block the thread. requesting block will Description Cell Views for more information. Description empty cell blocks th empty cell blocks ailable stored value. ailable full state of the target cel target full state of the of views is described in the following above. these Each tion undefined is when usingtion. instruction of the SC Operation this view. if it is on completion, flag, empty cell set the will request Load A av last the returning cell to a full request Store A is cell the if completion, on flag, full cell set the will request Store A value. last possible after storing the full the of SC instruction Operation is Table 12.6 Table the physical address. toRefer the section entitled In the multi-entry FIFO cell type a single memory mapped word contains word contains mapped memory single a type cell FIFO multi-entry the In allowing FIFO, a in entries multiple of number the on depending neither or full be empty, can FIFO The port. onto the queue. entries pushed already multi-entry on P/V views not allowed Note, type are FIFO cells.theIn a read will operation re view, Bypass tail. the overwrite will stores In the single entry cell type a single memory mapped word contains a mapped word contains a single memory cell type entry the In single can be used to This entry. single counter event an as or E/F view using single entry cells. for for a definition of E/F and P/V. a definitionfor andP/V. of E/F Table 12.7Table CellViews . Refer theto . section entitled Nostate/contro of cell Store or Load Nono of cell data, Store or Load 2 1 type of can be accessed cell Each in only type accessed. ITU is address when the Table 12.6 Table Table 12.6 Table E/F try E/F E/F try E/F Bypass P/V try P/V Table 12.6 Table Type Cell by Supported Cell Views Control Control Cell View E/F synchronized E/F synchronized P/V synchronized P/V Bypass Control 0001 0010synchronized E/F YesLoad request to an A 0000 Cell Type Single Entry Addr[6:3] CellView Blocking for more information. Referto table. viewThe cell is indicated in bits 6:3 of The cell can operate in any of the views listed listed the views in any of cell can operate The The ITU The supports numerouskinds of cell operations, including celldataupdate, cell state update,and load/store blocking/nonblocking semphore requests based on the empty/ embedded into bits 6:3 of the physical the 6:3 embedded of bits into in as shown cell views certain Multi-entry FIFOMulti-entry Bypass 1.= Empty/Full E/F 2. (increment) P/V = Probeer (try)/Verhoog 12.2.2 CellViews MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
be cleared as part of the initial- the of part as cleared be initial- the of part as cleared be em Programmer’s Guide, Revision 1.00 undefined when using this view. undefined when using this view. ons referencing the E/F Try view Try the E/F ons referencing ll not affect cell state. omic post decrement (Decre- by 1. based on whether the ITU store suc- ITU store the whether based on atomic post decrement by 1. cell will fail, returning a value of 0. of value a returning fail, will cell Description not affect cell state. not affect cell state. cell value is not 0 ) will block if the if cell value is 0. block will A Load request, which fails, wi which Load fails, A request, silently. fail will it block, not will cell to a full request Store A state. cell affect not will fails, which request, Store A instructi Conditional) (Store SC failure or success indicate will ceeds fails.or value; cell of bits significant least 16 the return will request Load A extended, and causes zero an block. will never request Store A by 1 increment and an write request's data ignored is Store A occurs. turates 16 bits (0xFFFF) sa at increment request's Store A will requests Load/Store state bits should empty and full The P/V semaphore use. for ization the of SC instruction Operation is value; cell of bits significant least 16 the return will request Load A zero extended, causesand an at occurs if ment only block. will never request Store A by 1 increment and an write request's data ignored is Store A occurs. turates 16 bits (0xFFFF) sa at increment request's Store A will requests Load/Store state bits should empty and full The P/V semaphore use. for ization the of SC instruction Operation is A Load request reads from Load ICR0 register. A the request reads ICR0 register. the to writes request Store A Table 12.7Table CellViews MIPS64® I6500Multiprocessing Syst Noblock. Load never request A will NoLoad A request to an empty E/F/try P/V try 1111 ICR Register No(ICR0) access register control ITU 0011 0100 P/V synchronized YesLoad A request 0101 Addr[6:3] CellView Blocking 0110 - 1110 0110 Reserved No view. Behaves Bypass same as the the 214
215 0 0 1 - 1 3 - (Multi-element) (Single-element) . The state cell . R0 RConfig Value IP R RConfig Value IP RConfig Value IP R/W 0 Type Reset Table 12.7 Table e will be returned returned be will e encoded follows: as encoded , where n is the value in this field. field. in this value is the n where , e even FIFO entry. In this configura- In this entry. FIFO even e igured as multi-element with an 8- n oldest whose valu oldest entry pends on the of the pends size FIFO_RD_PTR pointer depends on the state of the depends on the pointer Description ew when PA[6:3]) = 0001 as described in described = 0001 as when PA[6:3]) ew ts 29:28. This field is 29:28. This field ts Table 12.8 Table Cell State ion 20 bit is reserved. ta (single-entry cell type) cell (single-entry ta = 1 entry = 2 entries = 4 entries = 8 entries 0 1 2 3 field. See below Notethat single-element cells this field isalways 0. Indicates that the cell FIFO depth is 2 Indicates that cell FIFO depth the 01: 2 01: 2 10: 11: 2 This means that he FIFO can be encoded as follows: as encoded be can FIFO he that means This 2 00: 1 = multi-entry FIFO multi-entry 1 = FIFO FIFO (multi-entry in the of entries number maximum the contains Cell type) cell Bit 18: Used when the cell is configured as single-element, or as a multi-ele- single-element, as configured is cell the when Used 18: Bit 18 the odd FIFO bit selects logic 0 on A with a 2-entry FIFO. cell ment th 18 selects bit on and a logic 1 entry, bits tion 20:19 are reserved. 4-entry a with multi-element as is configured cell the when Used 19:18: Bits configurat In this FIFO. 20:18. Bits Used when cell is conf the entry FIFO. on the next read. The of this size on next the read. bi field in FIFO_DEPTH R de field this of size The Reserved. FIFO_RD_PTR Indicatesthe pointer value for the address that is organized as accessed follows.using a 48-bitThe ITU is physical addressis organized that The cell state can be accessed in the Control accessed vi in the state can be The cell providesthefollowing information. 1 Full Cell valid da contains 0 Empty Cell no contains valid data. R/W 1 12.2.4Cell Addressing ITU 12.2.3 Cell State 18 17 FIFO_TYPEcell entry 0 = single 16:2 R Reserved. R 0 Bits Field 19:18 20:18 27:19 27:20 27:21 29:28 FIFO_DEPTH 63:30 R Reserved. MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
3 2 1 0 3 2 1 0 . . Cell View Cell Offset . 7 6 7 6 Table 12.7 em Programmer’s Guide, Revision 1.00 FO cells. The value configured in the value configured in The FO cells. Figure12.6 Table 12.7 ss bits are required to access these 32 cells, the these 32 cells, to access bits are required ss Cell Index Cell e always between the upper and 0. Bit 2 is used to select e always GRAIN described as field in the following subsections. cells are used, there are no all are 32 cells care. Since are used, there :12 are don’t Don’t Care Don’t Index Cell View Cell Offset , the cell index fallssomewherewithin bits15:7 physi-of the ds of the ICR0 register register ICR0 the e CELL_NUMof and BLK_GRAINfields 16 15 16 15 12 11 ts43:12 of. the CP0 SAAR register12.1.1.2 described in Section mmedinto theBLK_GRAIN field is zero. Figure 12.5 MIPS64® I6500Multiprocessing Syst into 16 single-element cells and 16 FI 16 and cells 16 single-element into dress No Index Shift and InvalidCells No NoIndex Shift Figure 12.5 Figure Format Cell Addressing ITU ITU Base Address Base ITU ITU Base Ad , the cell index starts at PA[7]. Since 5 addre PA[7]. at index , starts the cell Figure 12.6 Example 1: 32 Cells with No Index Shift Section shown12.1.2. As in , the cell state is accessed when PA[6:3] = 0001 described= as in , whenthe cell state is accessed PA[6:3] 48 47 48 47 Figure 12.5 Figure withinbits 15:7isindicated of by the state the BLK_ lower 32-bitwords. Reserved Reserved Figure 12.7 The CellThe Index is derived frominformation stored in th in described as cal address. The exact location depends on the programming of these fields. on the programming location depends exact The cal address. The addressdividedThe is into followingthe fields: •Address: Base ITU Thisfield is takenfrom bi • CellcellIndex:The thesize of indexvaries dependingon the numberofTheposition cells. of thecell index •as in of described the cell views one This field encodes View: Cell • Each cell is 64-bits wide.In this field bits1:0 Offset: ar Cell Index would reside at PA[11:7]. In thiscase, bits15 CellIndex would reside at PA[11:7]. as shown would in be organized invalidcells. The physicaladdress PA[63:0] In this example the 32 cells are divided In As shown in CELL_NUM field is 32 (0x20).The valueprogra In 63 63 12.2.5.1 Example 1: 32 Cells with 12.2.5 Cell Indexing Examples 216
217 d containsvalue a of 3 2 1 0 . CellView Offset Table 12.7 FO cells. The value configured in the value configured in The FO cells. VA Index
Cells 9 8 7 6
Tag
Structure
Cells ITC .
State 1
Element Cell Index Cell
lls with 2-bit Index Shift withlls 2-bit Shift Index 14 are don’t care. Bits 8:7 (VA Index) used to mapcan be care. Bits 8:7(VA 14 are don’t FIFO our. In this example there are noinvalid this there example In cells. Thephysical our. Cell Multi_Element ndex Shift and No Invalid Cells and No Invalid ndex Shift Single‐ Care Don’t Don’t Figure 12.8 Example mmedinto theBLK_GRAIN field is two. 16 15 14 13 Bit Index Shift and No Invalid Cells Invalid No and Shift Index Bit to the left 2 bits. Since 5 address bits are required to access these 32 cells, the access to required are bits address 5 Since the left 2 bits. to into 16 single-element cells and 16 FI 16 and cells 16 single-element into 0x1F 0x00 0x0F 0x10
= = = =
ITU Base ITU Address , the cell index starts at PA[7]. In this example BLK_GRAINtheIn this fiel PA[7]. at index starts , the cell PA[11:7] PA[11:7] PA[11:7] PA[11:7] Figure 12.8 Example 1: 32 Ce Figure12.7 Cells with I 32 No 48 47 , the cell state is accessed when PA[6:3] = 0001 described= as in , the cell state is accessed when PA[6:3] Figure 12.5 Figure Reserved Figure 12.9 63 address PA[63:0] would shownas be organized in address PA[63:0] 0x2, causing the cell index to be shifted be to cell index the causing 0x2, bitsIn thiscase, 15: CellIndex would reside at PA[13:9]. the ITUtomultiple virtual addresses, in thiscase up to f In As shown in In this example the 32 cells are divided In CELL_NUM field is 32 (0x20).The valueprogra 12.2.5.2 Example 2: 32 Cells with 2- MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
. d containsvalue a of 3 2 1 0 to map the ITU to multiple ITU to multiple the map to ss bits are required to access to access bits are required ss Table 12.7 nvalid cells. The physical address The physical cells. nvalid em Programmer’s Guide, Revision 1.00 7 6 cells and 10 FIFO cells. The value pro- The FIFO cells. 10 and cells
Cells
Tag Structure
Cells
ITC 11 10 is case, bits 10:7 can be used be can case, bits 10:7 is State
Element 2:
‐ FIFO Cell memory space. Since 5 addre Since 5 memory space. value programmed into the BLK_GRAIN field is four. valueprogrammed into theBLK_GRAIN fieldfour. is . Multi_Element ndex Shift and No Invalid Cells Invalid No and Shift ndex ere are 20 valid cells and 12 i and 12 are 20 valid cells ere Single Example 16 15 sed when PA[6:3] = 0001 as described in described 0001 as = sed when PA[6:3] Figure12.10 MIPS64® I6500Multiprocessing Syst 4-Bit Index Shift and Invalid Cells Index Shift 4-Bit 0x1F 0x00 0x0F 0x10
= = = =
ITUBase Address Cell Index Index VA CellView Offset , the cell index starts at PA[7]. In this example BLK_GRAINtheIn this fiel PA[7]. at index starts , the cell PA[13:9] PA[13:9] PA[13:9] PA[13:9] Figure 12.10 4-bit Index Shift with 1: 20 Cells Example Figure12.9 Cells 32 2-bit I with 48 47 Figure 12.5 Figure Reserved 63 these 20 cells, the Cell Index would reside at PA[15:11]. In th In reside at PA[15:11]. would Index the Cell 20 cells, these th example this 16. In to case up address, in this virtual at are divided into 10 single-element 10 single-element into that are divided 20 cells are this example there In grammed intothe CELL_NUM field 20is (0x14). The As shown in 0x4, causing the cell index to be shifted tothe left 4 bits. Even thoughonly required,20cellsare the number of memory locations allocated mustbeon powerof 2, whicha this still required to access are bits that 5 address means PA[63:0] would be organized wouldas shown beorganized in PA[63:0] In the diagram below, the cell state is acces diagram below, the In 12.2.5.3 Example 2: 20 Cells with 218
219
structions are non-specula- are structions tiated. the sectionRefer to 0_ITU register is dedicated to the to dedicated register is 0_ITU ARI register per VP. This means that that means This VP. per ARI register re depends on the programming of the programming of depends on the re tes). Any violation of bytes). or 8 bytes 4 (i.e. ss behavior is undefined. behavior
ddress (PA) matches that in the in matches that (PA) ddress Special Address Access Register (SAAR) Register Access Address Special Cells
ecuted independent of the core's CP0 core's ecuted independent of the ted on the address space of the ITU. The address ITU. The address the of space address on the ted ligned loads/stores totheITU are not supported). Tag Structure
e translated address. e Cells
Cells
ITC the number of VP's instan of the number State
Element 3: ‐
DSPRAM register is dedicated to the DSPRAM. These FIFO Cell Invalid Multi_Element Single Example associated with th associated other views, other SC pass/fail views, structions are not suppor are structions ess error exception (i.e. una error exception ess ) located at CP0 (Reg 9, Sel 6). 9, Sel (Reg at CP0 (SAARI) located Access Register Index Address Special sed using two CP0 registers; the CP0 registers; sed using two e two SAAR registers per core. The SAAR The core. SAAR registers per e two 0x1F 0x14 one SAAR register per core, and one SA and core, one per SAAR register ys uncached. When the physical a ys uncached. 0x13 0x00 0x09 0x0A
e. Which register is accessed by hardwa register e. is Which ======
for more information. the ITU module is via a 64-bit wide data path. 64-bit module wide is via a ITU the e SAAR0_ITU address match overwrites and The SAAR0_ITU address uncached. access is then the field, to the ITU must be aligned to the size of acce size aligned to the be must ITU the to ructions referencing the ITU space are ex ITU the ructions referencing viewis used, the SC instruction indicatessuccess or failure depending onwhetherthe ITU PA[15:12] PA[15:12] PA[15:12] PA[15:12] PA[15:12] PA[15:12] Figure 12.11and Invalid Cells Cells Shift with4-bit Index 20 E/F try ITU Software Interface ITU store succeeds or fails due to the Full state. In the Full state. fails due to or succeeds store The CACHE, GINV*, PREF, and SYNCI in and SYNCI PREF, GINV*, CACHE, The instruction load/store the of can addr cause an alignment the address Cache Coherency Attributes (CCA) that may be As mentioned above, the ITU is acces As mentioned tive. The read/write access tive. to The read/write access the core, ITU accesses are alwa From canthere be multiple SAARI registers per dependingcore on entitled ns. Write requests for store in (ST) instructio ns. Write accessed by Load (LD) and Store The ITU is located at CP0located at Sel (Reg 9, 7), and the there is perspective, a software From LLAddr.LLbit. If If LLAddr.LLbit. Store (SC) inst Conditional Store SAAR0_ITU.ADDR[47:16] Communicationunit, Inter-Thread (ITU) and the SAAR1_ visibl software registers are not two From a hardware perspective, there ar perspective, there a hardware From MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 12.4 Accessing the ITU Module 12.3 Interface ITU Software
register that is dedicated register ster with the base address and size address base the with ster em Programmer’s Guide, Revision 1.00 fields of theSAAR, the programming 47:16] field of the CP0 SAAR register. This sets the This register. SAARtheCP0 47:16] fieldof rectly accessed using the SAAR reg- SAAR using the accessed indirectly are registers these of Both . 0x00, software programs the SAAR regi SAAR programs the software 0x00, e CP0 SAARI register is set to 0x01, software programs the SAAR register SAAR the programs software0x01, set to is register SAARI CP0 e MIPS64® I6500Multiprocessing Syst and set the address, size, and enable and set the address, size, and Figure 12.12 Figure address and the size of the ITU block. of the ITU and the size address Figure 12.12Figure ITU the Accessing of the CP0 SAARI register with a valueof ITU access. 0x00 to indicate an with register CP0 SAARI of the is used to access the memory. is the used to access base addressbase for the ITU module. Notethat thisfieldresides in bits43:12 of the register. Notethat the ITUmodule a fixedis size of 128As a result,KB. fieldalways theSIZE contains value a of 0x11 and neednot be programmed. 3. ITU accesses. enable CP0 SAAR register to bit in the the ENABLE Set When the SAARI.TARGET field is set to SAARI.TARGET the When SAAR0_ITU internal the informationprogramto uses this then Hardware ITU block. the of to theITU, thereby setting thebase field of th when the TARGET Conversely, with the base address and size of theDSPRAM block. Ha rdware uses thisinformation to program theinternal register that SAAR1_DSPRAM For example, to select the ITU block sequence is as follows: 1. field the TARGET Program 2.ADDR[the addresslocationof the ITU in base the Program SAARI.TARGET field as described described as field SAARI.TARGET ister described above. This concept is shown for a 2-VP 2-VP core. for a is shown This concept above. described ister 12.4.1 Register SequenceProgramming 220
221 value,such as 0xA0000, ster. Therefore, if one VP one if Therefore, ster. to the following constraints: to the ree error bits that ree are used by error bits se address at a different a different address at se transactions.thetransactionof theSIZE field As such, SAAR can write to the regi example, in VP at any time. For another overwritten by operating system software if Virtualization is notimple- ifoperatingsystemsoftware Virtualization e valuee thisfieldof value, is anyotherhardware the sets bit is not set, the ITU is not present in the system. the in present not is ITU the set, not is bit sses to the ITU must adhere must the ITU to sses the AXI bus. The ITU only The AXI bus. occurs the on an error re when , the ICR0 register contains th , the e ITU at a base of 0x40000at ITU 128K,e size of a with sothe ITU resides from \\ from the base address of 40000 base address the \\ from followingassembly language code, alongwith anexample transfer of data: \\is stored to ITU address 42000 to ITU address stored \\is #define c0_SAARI $9,6 c0_SAARI #define $9,7 c0_SAAR #define t0, 000000000 li t0, c0_SAARI mtc0 ITU enable to 128K; set size to 40000; address base \\Set t1, 0000000040000031 dli t1, c0_SAAR dmtc0 the target as ITU 0 to select bit \\Clear ITU 0 to select a value of with register SAARI \\Write t0, 5555AAAA5555AAAA dli ITU to be transferred value to data \\load t1, 0000000000042000 dli 2000 offset is t1; this of 42000 into address \\load Data = 0; offset t1; address in to the address in t0 the data \\Store t0, 0(t1) sd t1 register of with contents register SAAR \\Write mented or by hypervisor if Virtualization is implemented). mentedby or hypervisor Virtualization if sets the base address for the ITU, that information can be the base address for the ITU, that information can sets the VP0code example above, places th 0x40000 - 0x5FFFF in memory. However, if VP1 sets the ba However, 0x40000 - 0x5FFFF in memory. the the moved. will be ITU location of then The ERROR_AXI bit in the ICR0 register is set by hardwa is in the register ICR0ERROR_AXI bit The supports32- and 64-bit transactions. Itdoes notsupport burst These steps can be represented by the by can be represented steps These As shown in the section entitled ITU Control Registerthe section As shown in musttobe equal[64bit]. either 3'b010 If th [32bit] or3'b011 The ITU is shared across all VP's in the core. As such, acce As in the core. VP's all across shared The ITU is ICR0.ERROR_AXI bit. 5. Programmingisdoneprivileged bythe by (i.e. software 4.If the EN the SAAR register. of contents Read back the 1. The SAARI register must be programmed before the SAAR register. 2.VP per core, each only one SAAR register is Since there Itis incumbent upon software toensure that these conditions do not occur. hardware toreport the following error types. •bus AXI error •error Parity • Execution error 12.5.1Bus Error AXI 12.4.2 Programming Constraints MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 12.5 ITU Error Reporting
= 0xF) to a cell = d cell address d cell address This range is only is range This execution error, causing execution error, waysa power 2 regard-of to an invali request (PA[6:3] (PA[6:3] request both setor both cleared. ing invalidoccurs: accesses em Programmer’s Guide, Revision 1.00 lid cell address range. address cell lid l 0) will generate an an generate will 0) l The cell address range is al is range cell address The when the either of follow the ICR0.ERROR_EXECbit. For more information,to refer ess variesess based on theICR0.BLK_GRAIN fieldand the num- when cell does not the E and have both F cleared. does cell when ity checkedwhen their data is received. gister (any cell except cel gister (any cell except MIPS64® I6500Multiprocessing Syst accessed only in cell 0. As such, any ICR view any ICR such, only in cell 0. As accessed less of how many cells are configured. many cells of how less of the inva part is the cell address range space within remaining address The range, response an error is returnedandhardware sets Example 2: 20 Cellswith 4-BitIndexShift and Invalid Cells Invalid ICR0 Register Access the ITU, the ICR0 register can be In If a normal request is made If a normal of 2. not a power of when cells is the total number accessed •address Invalid •access ICR0 register Invalid Invalid Address decode the cell addr used to bits of address range The of cells configured based on theber ICR0.CELL_NUM field. address which has no correspondingICR re hardware toset theICR0.ERROR_EXEC bit.Note thatsoftware willsee this condition Busas a Error. • toa multi-element Loador On E/F Store FIFO cell when E flags itsand F bothcell has set. • to a multi-element FIFO cell Store P/V or Load On any Inaddition, the ERROR_EXEC bit set is byhardware The ERROR_EXECThe is bitset under theany of following conditions: •flags the either E and F to a single-element en cell, wh On a E/F Load or Store • a cell single-element to or Store Load a P/V On The ERROR_PARITY access the to bit in the ICR0 an during error occurs a by parity hardware when register is set ERROR_PARITY The transactions are even-par ITU module. Write 12.5.3 ExecutionError 12.5.2 Parity Error 222
223 ltiple threads in C) for all four threads. for C) Simultaneous Multithread- Simultaneous s are used to store the dou- slated to a Guest Physical orms instruction address translation, address translation, instruction orms the larger Variable TLB (VTLB) and (VTLB) TLB Variable larger the ter (PC) ter for that thread. Thispair of eading that executes mu that executes eading the VP. Conversely, if there are four VPs, if Conversely, the VP. ructions in a round-robin manner. ructions ina round-robinmanner. Each VP contains a complete system state (Gen- state Each a completeVP contains system shared Instruction Cache (I Cache Instruction shared exception model). In has its exception addition, each thread model). resolves all data and resource conflicts and manages pre- manages resource conflicts and and all data resolves ssue machine, allowing up to two threads to execute in a in execute to threads allowing up to two machine, ssue . The I6500 MPS implements The I6500 . ical address (RPA). The ITLB The address (RPA). ical n Virtual Address (IVA) is tran is (IVA) Address Virtual n can be fetched, decoded, issued, executed, andgraduated in ies dependsies onthenumber VPs of implemented. threads. This ITLBs are backed up by backed are ITLBs This threads. tches instructions from a instructionsfrom tches ion TLB (ITLB) structure. The ITLB perf ITLB The structure. TLB (ITLB) ion thread) in a cycle, using a program coun a cycle, using in thread) B mappings, interrupt and B mappings, interrupt tion Unit(EXU). The IFU fetches inst e shared between all of VPs. the between all e shared em (MPS) incorporates hardware multithr (MPS) incorporates hardware em multiple threads in parallel every cycle. Inaddition,every instructions multiple threads in parallel fromdifferent ear to be run in parallel. This functionality is performed entirely in hardware and does and hardware inperformed entirelyfunctionality is This parallel. in run be to ear , the instructions are issued and graduated in order. and issued are , the instructions one VP, all entries of the ITLB are used by the ITLB of entries all one VP, read is referred to as a Virtual Processor Processor (VP). read is referred to as a Virtual ble translation tominimize thenumber entriesof andmoreimportantly improve performance by doing thedouble cycle. translation in a single translated instructions are passed to theThe ExecutionUnit (EXU), whichis responsible decoding,for issuing, exe- the EXU In addition, graduating the instructions. and cuting cise exceptions. In the I6500 exceptions. In cise there are 18 ITLB entries that ar ITLB entries are 18 there InInstructioorderto support virtualization, the thread’s to Root is translated Phys the and GPA then (GPA) Address Itfetches twoinstructions single(for a instructions are sent to the Execu instructions the are sent to Instruct shared a manages also IFU The amongst complete independence allowing Fixed TLB (FTLB). The number of shared ITLB entr ITLB shared of number The (FTLB). TLB Fixed •= 6 entries 1 VP • 2 VPs = 12 entries • 4 VPs = 18 entries For example, if thereonly is such a way that the threads app way that the threads a such notrequire control.any software Hencethis chapteron is lyintended to providean overview multithreadingof and howitimplemented is in theI6500 MPS. th the I6500, each In TL MSA registers, and eral, CP0, FP, ownsystem debug, resetand various bootand exception vectors,and memory coherency. There are multiple typesof multithreadingimplementations The I6500 Instruction Fetch Unit (IFU) fe Fetch Unit (IFU) I6500 Instruction The The I6500 Multiprocessing Syst Multiprocessing The I6500 can execute ing, where the core threads canexecute same timeat the in thesame pipeline stage. This allowsmaximum for throughput and minimiza- is a dual-i The I6500 execution. hardware during of idle tion parallel. singlepipeline In the I6500,stage. allthreads (up to 4) MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 13.1 Instruction Flow Multithreading Chapter 13 Chapter
execution, each instruc- execution, multipleloads and stores r instruction from the same the from instruction r to a Guest Physical Address Address Physical a Guest to it becomesvisible toother data address translation, allowingtranslation, address data In other words, data stored by one In ta cache to perform loads and stores perform cache to ta lability and dependencies.data It is are available to issue, the EXU uses a the issue, are available to em Programmer’s Guide, Revision 1.00 TLB (VTLB)and Variable the larger units. During its During units. ed by the VP. Conversely, if there are four if there are Conversely, the VP. ed by (up to) four threads and determines which and threads to) four (up e thread in a e cycle, but thread in ss (RPA). The DTLBs operate much like the ITLBs to the operate much like The DTLBs (RPA). ss le instructions (>2) instructions le antiated on a per-VP basis. The 512 dual-entry Fixed TLB dual-entryFixed basis. The 512 a per-VP onantiated exactly the same point that l Address (DVA) is translated (DVA) l Address ruction completes, but an earlie an ruction completes, but ies dependsies onthenumber VPs of implemented. which eliminates most of the cache conflicts. most of which eliminates (DTLB) structure. The DTLB performs performs The DTLB structure. (DTLB) The shared DTLB is backed up by DTLB up is backed The shared load or a store for a singl store or for a a load -Store Unit (LSU) manages a shared da manages Unit (LSU) -Store entification and instruction order. This allows the proper instruction toorder entificationand instructionorder. MIPS64® I6500Multiprocessing Syst ciated cache line (for cacheable accesses). ciated are ready to issue based on resource avai based to issue are ready e shared the between all of four VPs. to a Root Physical addre to a , they are executed in one of the functional one of the in , executed they are the top two instructions from each of the each of two from instructions the top r threads in the same core at the same in threads r one VP, all eight entries of the DTLB are us the DTLB eight entries of all one VP, thread has notthread has graduated, thecompleted instructionremainin s the graduation queueto maintainin-order completion. Each of the threads operate independently, except to share some common resources. However, there are times when common resources. However, some to share except of operate independently, the threads Each MIPS R6 Instruction The manner. controlled very accessedin a being is make sure the system to needs processor the Like the IFU mentioned above, the Load Every cycle, the EXU decodes EXU decodes the cycle, Every two (of the possibletwo(of the eight)instructions capableof issuinginstructions from any of the four thehence SimultaneoustermVPs, Multithreading (SMT). Note multip If thatthe I6500 always issues instructions in order. policyfair issue allto makeget sure threads equal representation. are issued instructions Once the tionis appropriately tagged for thread id be maintained at graduation (completion) time.If an inst for all threads. The LSU also performs a also for The all LSU threads. from differing threads can be queued up to access the data cache. to access queued up be threads can differing from maintain cache coherency between threads. The data received to stores in the order and loads LSU processes The cache, associative 4-way set as organized cache is shared Data TLB a manages LSU also The (GPA) and then the GPA is translated the GPA and then (GPA) •= 8 entries 1 VP • 2 = 14 entries VPs • 4 = 20 entries VPs For only example, if there is (FTLB)shared between all VPs. is Data Virtua Intoorder support virtualization, the thread’s perform a double translation in a single cycle. Data by onestored thread does not becomevisible toother threads until the store instructionhas graduated and the has obtained ownership of the asso core complete independence amongst threads. complete entr ITLB shared of number The (FTLB). TLB Fixed that ar entries 20 DTLB are VPs, there (VTLB) is inst TLB dual-entryVariable 16 the addition, In visible to othe thread becomes the system. in cores starvation between and threads to prevent (such as buffers) shared resources allocation data of manages The I6500 that all threads can make forward progress. ensure 224 13.3 Thread Management 13.2 Flow Data
225 formationlost is e instructions allow a thread, e operat- instructions read is suspended, hence the system read hence the is suspended, her threads to achieve that goal. her threads to achieve There is no loss of information for the resumed thread. thread. resumed the for information of loss no is There (Overflow, TLB AsynchronousMiss, etc.), Interrupts (Overflow, be re-enabled via the EVP EVP the via re-enabled suspended can be e, threads the read can be reset to reboot, while the other threads are the other threads to reboot, while can be reset read f. DVPf. privilegedis a instruction onlyand is available to stem timercontinues to countwhile a th end or resume resume theexecutionend or of ot erating mode. appropriat When erating instruction. The only visible effect might be the sy be the might only visible effect The Since eachthread has a completely independentexception model, one thread cannotblock anotherthread. This inde- pendent exceptionmodel includes: Synchronous Exceptions (Int, DebugNMI, etc.), Exceptions (DIint), andReset. A th completely unaffected. The EVP instruction re-enables execution in all other threads. in all other execution re-enables instruction EVP The ing in privileged state, to to susp in state, privileged ing in allinstruction execution suspends DVP other threads. For theThe suspendedstate in threads, no thread can be restarted exactly where they left of and the op Kernel (Hypervisor) Root (Hypervisor)operatingKernel Root toavailable onlyis andinstructionprivileged is a Thischanged. timingcouldbe mode. instructions to manage threads. Thes threads. manage to instructions specialized Architecture (ISA) includes Set 13.3.2 Processor (EVP) Instruction Enable Virtual 13.3.1 (DVP) Instruction Processor Virtual Disable MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 13.4 Independent Exception Model em Programmer’s Guide, Revision 1.00 MIPS64® I6500Multiprocessing Syst 226
227 ssors (VP)per core or mul- single-clustercore. two or four Virtual Proce two Virtual or four ese are connected by a Regis- These data is gathered. debug h nonCodescape MIPS probes, debugtools, SDKsanddoc- rs (VPs)a insystem. The DBU providesseveral functions implemented in a typical in a implemented ide comprehensive debugging and performance-monitoringdebugging comprehensive ide of the interface debuggingand external environment todebugrequired MIPS On-Chip Instrumentation (OCI) debug system for multi-coredesigns. Please shows the OCI system as OCI system the shows Figure 14.1 to assist debugging. There is one DBU per cluster of cores or Virtual Processo There is one DBUofVirtual per cluster cores or capabilitiesfor multi-core be can where there processor designs MIPSThe Debug OCI Systemcomprises dedicated a on-chip module called the DebugUnit and various on-chip resources from whic debug have dedicated that components This chapter provides a brief overview brief chapter provides a This the MIPS processors that incorporate refer to thefollowing communitypages link for informatio umentation: https://www.mips.com/develop/tools/ prov to developed been has system OCI debug MIPS The ter Bus (RRB). Bus ter tiple cluster. cores per 14.1.1 Debug Unit (DBU) MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 14.1 Overview Debug System OCI MIPS On-Chip Instrumentation On-Chip MIPS Chapter 14 Chapter
em Programmer’s Guide, Revision 1.00 MIPS64® I6500Multiprocessing Syst Figure 14.1 OCI System Block Diagram 228
229 iguration registers iguration ers reside in the DBU and in ers reside by the VP when running in in running VP when the by via the coherence manager via (RRB) using a packet-based a using (RRB) s for Fast Debug Channels. ch as breakpoint conf as ch abled on-chip debug controller or emulator transac- or emulator controller debug on-chip abled . The JTAG TAP data regist data TAP JTAG The . ite these registers indirectly theseregisters ite e processor in debug mode only. It contains the com- indebugprocessor e mode only. monitor code and contains the memory mapped area, devices on the Register BusRegister on the devices gment, dmseg, and is accessed and is dmseg, gment, e DBU during normal and debug mode execution. normal and e DBU during control logic and configuration registers. s that are mapped to debug resources su resources debug to are mapped that s eakpoints are shared between all VPs. are shared eakpoints ed by dmxseg in DBU RAM. DBU in dmxseg by ed allow read/write requests tothe VPs being debugged viadebug monitorcode. Debug monitor code is loadedinto RAMin the DBUandschedules debugcommands to theVPs via the Register Bus. A dedicated block of RAM intheDBU thathoststhe debug debug modeand when a debugcontains the FIFO probe is attached.Thisalso RAM dmxseg. Dmxseg is a mapped to the VPs debug memory se memory debug VPs the to mapped is a Dmxseg dmxseg. A memory mapped area of main memory, accessible from th accessible A memory mapped area of main memory, bined dmseganddrseg areas. is probe a debug when mode debug in running when core the by accessed is of dseg that memorysegment debug The area is mirror This attached. register includes that dseg of region A samplingand wr and DBUread VP and the canregisters.The Each VP Each has its ownindependent breakpoint tor interface. debug probe allowsconnection to a JTAG TAP A serialJTAG th accessed Drseg from registers can be (CM). An APB Slave Port in the DBU provides connection to an APB en connection DBU provides Slave Port in the APB An protocol. The I6500 The MPS implementsI6500 8 instruction 4triggers,lowerofthe which have rangetriggering and theupper4have equality/mask, and 4 data triggers.Br The DBU connects to VPs and other cluster-level coherent to cluster-level VPs and other DBU connects The 14.1.1.3 Debug Monitor 14.1.1.4 RAM 14.1.4.2 Dseg 14.1.4.3 Dmseg 14.1.4.4 Drseg 14.1.4.1Controller Breakpoint 14.1.1.2TAP JTAG 14.1.1.1 APBSlave Port 14.1.4 PerCore/VP Resources 14.1.3 Number of Breakpoints 14.1.2 Register Bus MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00
the debug process. For es signals to put VPs into to put signals es em Programmer’s Guide, Revision 1.00 rious aspects of the CM, the coherence the of the CM, aspects rious can be used to aid in used to be can ous aspects of a VP's debug features. a VP's of aspects ous a cluster and or core provid a cluster for the DBU, CM and VPs; registers for determiningthe CMTrace functionality that CMTrace ainsthe following coherentdevices. and clock CM.power up and gating of the MIPS64® I6500Multiprocessing Syst are used toare used configure and controlva ion PDtrace Specification ers that facilitate and configure vari configure and that facilitate ers nce Manager) (v3) (v3) Manager) nce Power Controller) Controller) Power Interrupt Controller) Interrupt CP0 contains specific regist contains specific CP0 more information, refer to the document entitled; MIPS On-Chip Instrumentat For more information onMIPSthedebug the OCI system,refer to documententitled; Manual Reference Technical Debug Instrumentation; On-Chip MIPS and MPS also contains PDTrace The I6500 DebugThe GIC also providesMode. debug mode status monitoring and controlsdebug team assignments for syn- chronousstop/go of multiple VPs. This handlesthedistribution of interrupts between the VPs in The I6500 Multiprocessing System cont System Multiprocessing The I6500 Connects coherent devices to the Coherence Manager. Coherence to the coherent devices Connects Controlsthe global ordering of requests and responses devices.across core state of each VPs power and clock rate; power and clock each VPs state of of memory mapped registers that A set counters. CM performance scheme and An optional block of custom registers thatcanbe used to control systemlevel functions. Providesstop/run signalsVPs; for resetoccurred signals 14.1.4.5 CP0Registers 14.1.5.2 CPC(Cluster 14.1.5.1 GIC (Global 14.1.5.6 IOCU(I/O Coherence Unit) 14.1.5.3 Registers) GCR Configuration (Global 14.1.5.4Registers) Global Configuration (Custom - CGCR 14.1.5.5- (Cohere CM 14.1.5Devices Coherence 230 14.2 More Information
231 MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 em Programmer’s Guide, Revision 1.00 MIPS64® I6500Multiprocessing Syst 232
233 the document since its last its since document the Description t indicate significant changes in indicate significant t s thatthanare more one revisionold. itial version of I6500 Multi-Cluster Programmers Guide Programmers Multi-Cluster itial of version I6500 01.00 March 201729, In Revision Date Change bars (vertical lines) in the margins of this documen this of margins the in lines) (vertical bars Change release.removedare Change bars for change MIPS64® I6500 Multiprocessing System Programmer’s Guide, Revision 1.00 Appendix A Appendix History Revision em Programmer’s Guide, Revision 1.00 www.wavecomp.ai MIPS64® I6500Multiprocessing Syst Copyright © Wave Computing, Inc. All rights reserved. 234