EC 413 Computer Organization

Introduction to Memory

Prof. Michel A. Kinsy

Department of Electrical & Computer Engineering Computer Organization v4 § Our fifth view of computer organization: The modern digital computer has three major functional hardware units: CPU, Main Memory and Input/Output (I/O) Units

Memory I/O Devices Processor

0

ADD ADD 1 4 Shift left 1 PCSrc ALUOp Branch MemRead Control MemtoReg Unit MemWrite ALUSrc

Instr[31-21] RegWrite Device Device Overflow

Instr[19-15] Read Addr 1 zero Read … Instr[24-20] Data 1 100 #1 Read Addr 2 #n Read Inst[31-0] Result PC Register File ALU Address 0 Instr[11-7] Read 0 Write Addr Read Data Data 2 1 Write Data 1 17 Write Data Address

Sign ALU Extend Control 12| 20 32 114 Instr[30, 14-12] 2 Control Bus Address Bus Data Bus

Department of Electrical & Computer Engineering Processor- Memory Gap § Performance gap: CPU (55% each year) vs. DRAM (7% each year) § Processor operations take of the order of 1 ns § Memory access requires 10s or even 100s of ns § Each instruction executed involves at least one memory access 10 6

Processor 10 3

Relative performance Relative Memory

1 1980 1990 2000 2010 Calendar year Department of Electrical & Computer Engineering Memory Organization § Memory is organized and accessed in ways to hide this gap Reg

L1 $

Ln $

Main Memory

Secondary Memory

Department of Electrical & Computer Engineering Memory Organization § Memory is organized and accessed in ways to hide this gap Reg 4-8 bytes (word) L1 $ 8-32 bytes (block) Ln $ 1 to 4 blocks Main Memory 1,024+ bytes (disk sector = page) Secondary Memory

Department of Electrical & Computer Engineering Memory Organization § The fastest memories are expensive and thus not very large Capacity Access Time Cost (per GB) 100s B ns $Millions Reg 4-8 bytes (word) 10s KB few ns $100s Ks L1 $ 8-32 bytes (block) MBs 10s ns $10s Ks Ln $ 1 to 4 blocks 100s MB 100s ns $1000s Main Memory 1,024+ bytes (disk sector = page) 10s GB 10s ms $10s Secondary Memory

Department of Electrical & Computer Engineering Computer Organization v5 § Our sixth view of computer organization § A fast memory can help bridge the CPU-memory gap § The fastest memories are expensive and thus not very large

On-Chip Components Control Cache Instr Secondary Datapath RegFile Second Level Main Memory Memory (Disk) Cache

Data Cache ALU (SRAM) (DRAM)

Department of Electrical & Computer Engineering Memory Technology § Random Access Memory (RAM) § Any byte of memory can be accessed without touching the preceding bytes § RAM is the most common type of memory found in computers and other digital devices § There are two main types of RAM § DRAM (Dynamic Random Access Memory) § Needs to be “refreshed” regularly (~ every 8 ms) § 1% to 2% of the active cycles of the DRAM § Used for Main Memory § SRAM (Static Random Access Memory)

Department of Electrical & Computer Engineering Memory Technology § Random Access Memory (RAM) § Any byte of memory can be accessed without touching the preceding bytes § RAM is the most common type of memory found in computers and other digital devices § There are two main types of RAM § DRAM (Dynamic Random Access Memory) § SRAM (Static Random Access Memory) § Content will last until power turned off § Low density (6 transistor cells), high power, expensive, fast § Used for caches

Department of Electrical & Computer Engineering Memory Technology § Single-transistor DRAM cell is considerably simpler than SRAM cell § This leads to dense, high-capacity DRAM memory chips

Word line Word line Vcc

Pass transistor

Capacitor Compl. Bit Bit bit line line line (a) DRAM cell (b) Typical SRAM cell DRAM Cell SRAM Cell

Department of Electrical & Computer Engineering RAM Organization § One memory row holds a block of data, so the column address selects the requested bit or word from that block § RAS or Row Access Strobe triggering row decoder § CAS or Column Access Strobe triggering column selector 21 Address

Chip select SRAM 16 Output enable 2M x 16 Dout[15-0] Write enable

Din[15-0] 16 Department of Electrical & Computer Engineering RAM Organization § One memory row holds a block of data, so the column address selects the requested bit or word from that block bit (data) lines

R o Each intersection represents a w 6-T SRAM cell or a 1-T DRAM cell

D e RAM Cell c Array o d e word (row) line r

Column Selector & column row I/O Circuits address address

data bit or word Department of Electrical & Computer Engineering RAM Organization § Latency: Time to access one word § Access time: time between the request and when the data is available (or written) § Cycle time: time between requests § Usually cycle time > access time § Bandwidth: How much data from the memory can be supplied to the processor per unit time § Width of the data channel * The rate at which it can be used

Department of Electrical & Computer Engineering DRAM Packaging § DIMM (Dual Inline Memory Module) contains multiple chips arranged in “ranks” § Each rank has clock/control/address signals connected in parallel (sometimes need buffers to drive signals to all chips), and data pins work together to return wide word § A modern DIMM usually has one or two ranks (occasionally 4 if high capacity)

Department of Electrical & Computer Engineering DRAM Packaging § DIMM (Dual Inline Memory Module) contains multiple chips arranged in “ranks”

Department of Electrical & Computer Engineering Disk Memory Basics § Hard disk drive (HDD), hard disk, hard drive is the dominant secondary storage device in computer systems

Typically 2 - 8 cm

Department of Electrical & Computer Engineering Disk Memory Basics § Hard disk drive (HDD), hard disk, hard drive is the dominant secondary storage device in computer systems 2. Disk rotation until the desired sector arrives under the head: 3. Disk rotation until sector Rotational latency (0-10s ms) has passed under the head: Data transfer time (< 1 ms) 1. Head movement from current position 2 to desired cylinder: 1 Seek time (0-10s ms) 3 Sector

Rotation Department of Electrical & Computer Engineering Disk Memory Basics § Solid-State Drive (SSD) uses integrated circuits and has no moving mechanical components § Low latency § Low power § Solid state reliability § Widening application range § Embedded devices § Desktop and laptop PC § Server and supercomputer

Department of Electrical & Computer Engineering Memory Organization On-chip

CPU

Cache

25 cycles

Bus 25 cycles

25 cycles

25 cycles Memory

Department of Electrical & Computer Engineering Memory Organization On-chip

CPU

25 cycles Cache 25 cycles 25 cycles 25 cycles Bus

Memory Memory Memory Memory Bank 0 Bank 1 Bank 2 Bank 3 Interleaved Memory Department of Electrical & Computer Engineering Intel Core i7 Organization

Department of Electrical & Computer Engineering Intel Haswell

Department of Electrical & Computer Engineering Next Class § Exam II Lectures L09 – L16

Department of Electrical & Computer Engineering