CALIFORNIA STATE UNIVERSITY, NORTHRIDGE RAM-DISK a Thesis

Home , Bank switching, Floppy disk, Hard disk drive

CALIFORNIA STATE UNIVERSITY, NORTHRIDGE

RAM-DISK

A thesis submitted in partial satisfaction of the requirements for the degree of Master of Science in

Engineering

Chung Ting Ho

May, 1984 The Thesis of Chung Ting Ho is approved :

Pr . John T. Jo , Cha1r

California State University, Northridge

ii TABLE OF CONTENTS

Page

Abstract : vi

Chapter 1 DESIGN PHILOSOPHY AND THEORY 1

1.1 Overview l

1.2 : Design Background 4

1.3 Design Goal and Theory 7

Chapter 2 THEORY OF OPERATION 10

2.1 : System Monitor 10

2.2 : Operating System 12

2.3 : Custom Basic I/0 System for RAM-Disk 18

2.4 Description of The Block Diagram 22

Chapter 3 CIRCUIT DESCRIPTION 27

3.1 4146 Memory Chip 27

3.2 Z80A CPU 30

3.3 Detailed Circuit Description 34

3.4 Power Supply 41

Chapter 4 SOFTWARE DESCRIPTION 43

4.1 Self-Test Program 43

4.2 : Forrnating The RAM-Disk 44

4.3 : Custom Basic Input/Output System 45

Chapter 5 EVALUATION AND CONCLUSION 48

5.1 User Interface 48

5.2 : Performance Evaluation 49

5.3 : Conclusion and Comment 51

iii References 53

Appendix A CIRCUIT SCHEMATICS 54

Appendix B IC LISTING AND POWER REQUIREMENTS 58 Appendix c : SELF-TEST PROGRAM LISTING 59 Appendix D FORMATING PROGRAM LISTING 65 Appendix E MOVE PROGRAM LISTING 66

Appendix F CUSTOM BIOS DRIVE A PROGRAM LISTING 67

Appendix G CUSTOM BIOS DRIVE E PROGRAM LISTING 78

Figure 1 A MICRO-COMPUTER SYSTEM 1

Figure 2 A MOTHER-DAUGHTER RAM-DISK BOARD 8

Figure 3 : RAM-DISK BLOCK DIAGRAM 23

Figure 4 RAM-DISK INTERFACE FUNCTIONAL BLOCK DIAGRAM 26

Figure 5 4164 DYNAMIC RAM READ CYCLE TIMING 28

Figure 6 : 4164 DYNAMIC RAM WRITE CYCLE TIMING 29

Figure 7 4164 DYNAMIC RAM REFRESH CYCLE TIMING 30

Figure 8 ~ Z80 INSTRUCTION OPCODE FETCH TIMING 31

Figure 9 Z80 256-CYCLE REFRESH CONVERSION DIAGRAM 32

Figure 10 Z80 INPUT AND OUTPUT CYCLES TIMING 34

Figure 11 RAM-DISK COMPOSITE TIMING 39

Figure 12 MOVE PROGRAM FUNCTIONAL DIAGRAM 47

Table 1 RELATIONSHIP BETWEEN BLS, BSH AND BLM 16

Table 2 RELATIONSHIP BETWEEN BLS, MAXIMUM DISK SIZE AND EXTEND MASK 16

Table 3 RELATIONSHIP BETWEEN BLS, DIRECTORY ENTRY AND ALO, ALl 17

iv " '

Table 4 : RAM-DISK PARAMETER HEADER 20

Table 5 : RAM-DISK PARAMETER BLOCK 21

Table 6 : RAM-DISK BENCH MARK TEST so

v ABSTRACT

RAM-DISK

CHUNG T. HO

Master of Science in Engineering

Microcomputers are found in all areas of modern society. They have become the basic tools for word processing and data file management. A floppy disk drive is necessary for both long term file storage and on-line data support. Since the floppy disk drive is mainly a mechanical device, it is inherently slow. To improve the microcomputer's run-time efficiency, an alternate form of on-line data support is proposed.

A RAM-disk is a block of solid state memory. When integrated into the microcomputer system, it functions just like a floppy disk. THE RAM-disk is completely transparent to the user. It is accessed in the same manner as a floppy disk, but its response speed is ten to twenty

vi times faster than a floppy disk drive.

The RAM-disk has 256K bytes of storage capacity. To simplify the hardware design, it is subdivided into eight tracks with 256 sectors per track and 128 bytes per sector.

Several programs were created to integrate the RAM disk with computer. A format program is to initialize the

RAM-disk. Two custom BIOS programs are to integrate the

RAM-disk into either drive 'A' or drive 'E' of the computer system. Once the RAM-disk is formated and integrated into the system it is accessed as either drive

'A' or drive 'E' of the system.

vii CHAPTER 1

DESIGN PHILOSOPHY AND THEORY

1.1 OVERVIEW In today's business and hobby world the micro-computer has become increasingly popular. The usual time consuming and laborious chores such as personal financing, inventory control and accounting can be taken over by a micro- computer which performs with much higher precision and greater speed. There are hundreds of different microcomputers on the market now, and there are just as many application software packages available. A micro-computer system generally consists of a CPU unit, a display such as

TV screen or CRT monitor, a keyboard, a printer and at least one 5-1/4 or 8 inch floppy disk drive.

: CRT . : PRINTER . . ------: CPU :------: UNIT :------. . : 'KEYBOARD . : DIS'K DRIVES :

FIGURE 1 A MICRO-COMPUTER SYSTEM

The CPU unit includes the micro processor, timing circuitry, I/O control and on-line memory. For most 8-bit micro-processors such as the Z80, I8080 and M6502, there

1 2

are only 16 memory address bits available, which limits the maximum addressable on-line memory to 64k bytes. After the memory space reserved for the system monitor and the operating system software is subtracted, there are less than 60K bytes of memory available for the application program and data. In the early days of micro-computer history, very rarely would a program exceed 16K bytes in length, but as more software development tools became available, many complicated programs were developed. Application programs such as high level language compilers, spread sheet programs and word processor programs are extremely large and can not fit into the available memory space in its entirety. Therefore, they are broken down into smaller pieces as overlays. These overlays are stored in an off line mass storage device such as a floppy disk. As the program is being executed, each overlay is swapped in and out of the on-line memory as they are needed. It is the same with the data base programs. It is not unusual to have inventory data, accounting data or graphic data which are too large for the on-line memory space. They are broken down into smaller pieces so they can be loaded into the memory as they are processed by the computer. As the program becomes more complicated the more overlays it must create. For example, 'QUAD' a sophisticated business software which can perform inventory control, customer mailing list, payroll and many 3

other accounting functions has 17 overlays and the whole program takes 242K bytes of memory. To run such a program the overlays are swapped in and out of memory constantly, and the disk drive is being accessed almost continuously. In the past few years the floppy disk drive has became a vital part of any computer system for both long term program storage or run time program support such as over lays or library funtions storage. The floppy disk drive is interfaced to the CPU through a disk controller chip.

The disk controller takes the CPU's parallel data bits and shifts them out serially to the disk drive during a disk write operation. Likewise, it shifts in the serial disk data bits and passes them to the CPU as 8-bit parallel data during a read operation. Due to this serial data link, the floppy disk data transfer rate is inherently slow and is limited to about 30 kilo-bytes per second. When the disk files are accessed randomly, there is an additional delay associated with the movement of the read/write arm, load/unload of the head and settling time.

For a typical disk drive, the average random access time is 91 milli-seconds plus the head loading time of 35 milli-seconds. It takes 1.126 seconds to read a 30 kilo- byte long file from the disk if the file occupied one contiguous block on the disk. If the same file is broken up into 30 blocks of one kilo-bytes each, then the transfer time increases to 4.78 seconds. 4

A disk drive requires three levels of power supplies, a plus five volts for the TTL circuitry, a plus 24 volts for the stepping motor and 120 volts AC for the rotation motor.

1.2 DESIGN BACKGROUND In the past two to three years, several alternate forms of data storage methods have been developed to overcome the micro-computer's limitation of on-line memory space and slow floppy disk interface. One is the hard disk drive system such as Winchester disk drive. The hard disk technology has just been introduced into micro computer systems in the past two years. A typical Winchester hard disk drive has between one and twenty mega-bytes of storage capacity. It is generally used as an off-line storage device. Its data transmission rate is several times faster than a floppy disk drive, but the cost of a hard disk drive system and its controller electronics is usually higher than most people care to pay for it. Another method to increase on-line storage is done with the bank-switching memory. Bank switching is to have two or more banks of solid state memory. Each bank has the same storage capacity and can be switched in or out of the computer address range by some predetermined bits of a dedicated I/O port. A long program can be loaded into several consecutive banks of memory. During execution, the appropriate program segment is accessed by 5

the computer as each memory bank is addressed. The bank switching method has all the advantages of a solid state memory such as speed and reliability, and it can be expanded to more than two thousand banks of 64K bytes each. The disadvantages of the bank switching are that it requires special software to operate and it is difficult to implement as an add on feature. The third option of increasing on-line memory is the ram-disk. A ram-disk is also called a disk emulator which is a block of solid state memory which communicates with the CPU just like a normal floppy disk drive. The ram-disk also has all the speed and reliability of a solid state device. It has practically no limitation on capacity expansion and since it emulates a regular floppy disk drive, there is no special software required to operate it. With the availability of VLSI memory chips, the cost of a ram-disk is becoming compatable with a floppy disk drive.

In the past year the ram-disk has become increasingly popular, and there are half a dozen computer peripheral companies marketing different versions of the ram-disk. Basically, there are three approaches to a ram-disk design. The first method is to put the ram-disk in place of a floppy disk drive so that the disk controller will treat the ram-disk as a normal floppy disk drive. All the communication between the computer and the ram-disk is still in a serial path, but the disk seek time and data access time will be virtually zero. This approach 6

requires no special software or hardware modification to the computer but since the data is still in serial link, the solid state memory speed has not been taken advantage of. The second approach of ram-disk design is geared toward a specific standard data bus system such as SlOO or STD data bus structures. This ram-disk design is simpler than the previous approach because the ram-disk has access to all the necessary data bus, address bus and timing signals that it requires for interface. It communicates with the CPU in parallel transmissions, therefore it is at least twice as fast as the serial transmission ram-disk. The one draw back of this data bus approach is that each design can only operate with the particular bus structure which it is designed for and it is not interchangeable between two different computers. The third design is most popular, although it is more complicated than the data bus approach. This design is to use two or three of the computer's input/output parallel ports to communicate between the computer and the ram disk. One port is dedicated for data input/output, one port is used for ram-disk address output and the third port is used for the timing and control signals. This I/0 port design has the advantages of parallel data communication, interchangeability between different types of computers, and unlike the data bus approach, the I/O 7

ram-disk can be placed at a reasonable distance away from the computer as a separate unit. Both the data bus and

I/O ram-disk design are commercially available now and they range in price from one thousand to four thousand dollars with memory capacity from 250K bytes to one mega bytes respectively.

1.3 DESIGN GOAL AND THEORY

The above three ram-disk designs have some flaws, they all assume the computers have either the proper data bus structure or necessary I/O ports available for interfacing. With the new VLSI technology available today, many computers have gone to the single board design. All the computer functions, timing, control and memory reside in a single piece of printed circuit board which completely eliminates the need for a bus structure, and they have very limited I/O port capability other than those ports reserved for peripheral devices. In light of these hardware limitations, I came up with a different approach called the mother-daughter board ram-disk.

The mother-board is the computer board with its CPU chip removed. A forty-pin ribbon connector is inserted into the computer board's CPU socket, the other end of the ribbon cable is connected to the ram-disk daughter board, and the CPU chip which has been removed from the computer board is inserted on the ram-disk board. 8

. COMPUTER . . RAM-DISK : BOARD BOARD . . . . . : . ----- : CPU : . . : . . . . :------: ------: . .:------

: ----=4~0_-""""P"""'I"""N-....-R=I;;..:;B=B;;..;;;O=N..;...... ;C=A...::;;B=L=E=----:

FIGURE 2 A MOTHER-DAUGHTER RAM-DISK BOARD

On the ram-disk board, all the CPU signals are buffered, and all the communications to the computer board are directed through the ribbon cable. Also, all the necessary signals for the ram-disk are picked up from the buffer outputs. The daughter-board ram-disk has a parallel data communication with the CPU that makes it one of the fastest ram-disks. Since it interfaces directly with the CPU chip, it is computer independent which means the same design can be used with any micro-computer that has the same type of CPU. Another advantage of the daughter-board ram-disk is the simple design. With the currently available integrated circuits, the cost of a

256K bytes board is less than half of a commercially compatible ram-disk.

The ram-disk designed here has 256K bytes of storage capacity which is compatible to a single-side, single- density, 8-inch floppy disk. This capacity allows the entire floppy disk data to be copied onto the ram-disk and 9 any program however long can be executed entirely from the ram-disk. The design is also transparent to both the user, software and hardware. The programmer can access the ram-disk as if it is a normal floppy disk drive. Any program can run with the ram-disk without alteration. Most importantly, the computer's performance does not deteriorate because of the relocation of the CPU chip. The ram-disk is mapped into the CPU's I/0 address space. Since eighteen address lines are required to address 256K bytes of memory, the ram-disk addresses are outputed to three ports and a bidirectional fourth port is used for the data read and write.

I chose the 'BIG BOARD' as the target computer to which the ram-disk will be integrated with. The 'BIG BOARD' is a single board computer with a four-mega HZ Z80-A central processor. The board was designed by

'Furgason' and marketed by 'Digital Research Group' of Texas as a kit. The reasons for which I picked the 'BIG BOARD' are because it runs on a zao central processor which has built in dynamic memory support that makes dynamic memory implementation much easier, and because the 'BIG BOARD' represents a typical single board computer. It has 64K bytes of on-line memory and has all the desirable functions and capabilities of any computer system, but it has only two parallel I/O ports and no externally accessable data bus. These features make it an ideal candidate for daughter-board ram-disk implementation. CHAPTER 2 THEORY OF OPERATION Before we discuss the functions of the ram-disk hardware and software in depth, we will first look into the organization of the 'BIG BOARD' computer. In this chapter, the system's built-in software, the system monitor and the computer's operating system software are examined. Then the custom software and the description of the block diagram are presented in the second half of this chapter.

2.1 SYSTEM MONITOR Any computer, however small, must have some built-in software to initialize the hardware when the computer is first powered up. This piece of software is generally refered to as 'SYSTEM MONITOR', for the 'BIG BOARD' computer. The system monitor resides in a PROM and it is 2K bytes long. The monitor program is automatically loaded into the top 2K location of the RAM when the CPU is reset by either a power up reset or a manual reset. The monitor provides two essential functions for the system. It is the interface between the hardware and the software, and it has all the routines that initialize and control all the basic system input/output functions. The basic I/O functions include the driving routines of the floppy disk controller. The I/O driver portions of the monitor are always active even when the operating system such as

10 11

CP/M has control of the computer. The 'BIG BOARD' is equipped with a Western Digital 1771 disk controller chip which is capable of handling up to four 8-inch Shugart compatible floppy disk drives. The monitor software provides a set of subroutine entry points to the user for disk I/O interfacing. The basic functions available are; drive select, restore, seek track, read sector and write sector routines. To select a disk drive for future operation, the user program simply calls up the drive select routine and passes the desired drive number as a parameter to the drive select routine. The desired disk track can be sought in a similar manner by calling up the seek track monitor routine, then a sector read or sector write operation can be performed by invoking the sector read and sector write routine respectively. The data transfer between the floppy disk and the CPU memory is done in blocks of 128 bytes since each disk sector is 128 bytes long. To perform a data transfer of a large file, the seek track and sector read/write routines are accessed repeatly until the entire file is transferred. When the disk driver routines are invoked, a built-in software/hardware timer is triggered. The timer provides a delay to allow the disk to finish its mechanical movements before the actual read/write operation is performed. 12

2.2 OPERATING SYSTEM

An operating system is a monitor control program for the micro-computer system. It is the interface between the application program and computer's custom system monitor. It also provides a file management system for both the disk storage and dynamic file access and allocation within the CPU's memory space.

The 'BIG BOARD' has CP/M 2.2 as its operating system.

CP/M is a fully developed single console disk operating system. It supports a text editor, I8080 assembler and debug subsystems.

One distinct part of CP/M is the BIOS, the hardware dependent Basic Input/Output System. The BIOS provides the primitive operation to access the disk drive and other standard peripherals. The operating system can be tailored to any particular hardware environment by patching this portion of the CP/M.

All disk-dependent portions of the CP/M are placed in a BIOS-resident "parameter block" which describe the particular characteristics of the disk subsystem used with

CP/M. In general, each disk drive has an associated 16- byte disk parameter header (DPH) which contains information about the disk drive and provides a scratch pad area for certain disk operating system operations.

The format of the disk parameter header for each drive is shown below 13

DISK PARAMETER HEADER

: XLT : 0000 : 0000 : 0000 : DIRBUF : DPB : CVS : ALV :

16b 16b 16b 16b 16b 16b 16b 16b where each element is a 16-bit value. The meaning of each DPH elements is ; XLT - Address of the logical to physical translation vector. If used for this particular drive, or the value 0000 hex is used if no translation takes place. The translation vector provides a skew factor from the logical to physical disk sector address. The disk controller can not read/write the disk data fast enough if the data were recorded in consecutive physical sectors, The translation vector is to translate the logical consecutive sector adddress into the physical interlacing sector address. In general, for a disk drive rotating at 60 HZ rate, a skew factor of 6 is used. Therefore, it takes 6 disk revolutions to read one entire track. 0000 - Scratchpad area. DIRBUF- Address of a 128 byte scratchpad area for disk directory operation. All the disk parameter headers address the same buffer area. DPB - Address of a disk parameter block for this drive. Disks with the same characteristics address the same DPB. 14

CSV - Address of a scratchpad area for software check

in the operating system. Each disk drive points

to a different CSV address.

ALV - Address of a scratchpad area to keep disk allocation information for the operating system. This address is different for each DPH.

The CP/M is capable of supporting up to 16 disk drives, and the DPH's are arranged in a table with the

first row corresponding to drive 0, and the last row

corresponding to drive 'n-1' , where 'n' is an integer in the range 1 to 16. The DPH table appears as

DISK PARAMETER HEADER

: XLT : 0000 : 0000 : 0000 : DIRBUF : DPB : CVS : ALV : : XLT : 0000 : 0000 : 0000 : DIRBUF : DPB : CVS : ALV : (and so forth through) : XLT : 0000 : 0000 : 0000 : DIRBUF : DPB : CVS : ALV :

The translation vector tables are located somewhere

else in the BIOS. The drives with the same skew factor share the same translation vector table.

Another important table which characterizes each disk drive is the disk parameter block (DPB). Any number of disk drives with the same character can share the same DPB. A DPB takes the general form : 15

DISK PARAMETER BLOCK

:SPT :BSH :BLM :EXM :DSM :DRM :ALO :ALl :CKS :OFF : 16b 8b 8b 8b 16b 16b 8b 8b 16b 16b where each parameter is a 8-bit or 16-bit value as indicated. SPT - The total number of sectors per track. For an IBM standard floppy disk it is 26 sectors per track.

BSH - The data allocation block shift factor, determined by the data block allocation size. BLM - The block mask constant, also determined by the data block allocation size. EXM - The extent mask, determined by the data block allocation size and the number of disk blocks. DSM Determines the total storage capacity of the disk drive. DRM - Determines the total number of directory entries of this disk drive. ALO,ALl-determine the reserved directory blocks. CKS The size of the directory check vector. OFF - The number of reserved tracks at the beginning of the disk.

In the CP/M manual, several tables are provided to help determine each parameter value of the DPB. These tables are duplicated below. 16

The values of BSH and BLM are determined by the data block allocation size as in table I :

TABLE I

Relationship between allocation block size, block shift constant and block mask constant.

BLS BSH BLM

1,024 3 7 2,048 4 15 4,096 5 31 8,192 6 63 16,384 7 127

The data block allocation size is the minimum data size per each disk file transfer. In other words, the disk space is allocated to a file in BLS bytes blocks. For a

CP/M single-side, single-density, IBM format disk, the data allocation size is 1K bytes. From the first row of table I it shows the values of BSH and BLM are 3 and 7 respectively.

The value of EXM depends upon both BLS and DSM value as shown below in table II :

TABLE II

Relationship between allocation block size, maximum disk size and extend mask.

BLS DSK<256 DSK>255

1,024 0 N/A 2,048 1 0 4,096 3 1 8,192 7 3 16,384 15 7 17

The value of DSM is the maximum number of the data blocks supported by the disk drive. The product of BLS times DSM is the total number of bytes can be held in the disk drive, not including the reserved operating system tracks. Again, a single-side, single-density, IBM format disk has a storage capacity of 242 K bytes. From table II, The DSM value is 0. The DRM entry is one less than the total number of directory entries. The CP/M can support a maximum of 64 directory entries, therefore the value for DRM is 63.

The two values ALO and ALl can be considered as one 16-bit string as below :

ALO ALl . :------: : : ...... 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 where each bit position (starting bit 00) reserves a 1K byte data block for directory entry. Each directory entry occupies 32 bytes, resulting in the following table.

TABLE III Relationship between allocation block size, directory entry and ALO, ALl.

BLS DIRECTORY ENTRIES

1,024 32 * # bits 2,048 64 * # bits 4,096 128 * # bits 8,192 256 * # bits 16,384 512 * # bits 18

For an allocation block of 1,024 bytes and 64 directory entries, it requires 2 reserved data blocks or 2 bits position in ALO for directory entries, that is ALO = CO hex and ALl = 00 hex. The CKS value is determined as follows : if the disk drive media is removable such as a floppy disk, then CKS = (DRM + 1)/4 = (63 + 1)/4 = 16. If the media is fixed, then CKS = 0. Finally, the OFF field determines the number of physical tracks which are reserved for the operating system. These tracks are skipped during a seek track operation. In CP/M environment track 0 and track 1 are reserved for the operating system, therefore OFF = 2.

From the above tables and calculations we can code a disk parameter block for an IBM format, single-side, single-density disk with 242K bytes of storage capacity as

DISK PARAMETER BLOCK

:SPT :BSH :BLM :EXM :DSM :DRM :ALO :ALl :CKS :OFF : : 26 : 3 : 7 : 0 :242 : 63 :COh :OOh : 16 : 2 :

2.3 CUSTOM BASIC I/0 SYSTEM FOR RAM-DISK A standard IBM format disk has 77 tracks, 26 sectors per track and 128 bytes per sector. Track 0 and track 1 are reserved for the operating system. Another 2K bytes are reserved for directory entries. This leaves user 19

247,552 bytes of free space, or 242 allocation blocks of lK bytes each, a total of 242K bytes of useable storage space.

For a ram-disk to emulate a floppy disk it is also divided into tracks, sectors and bytes. The operating system can access any file on the ram-disk by specifying a track number and a sector number just as it would with any floppy disk drive. The track and sector numbers that are sent to the ram-disk are dynamically translated into the physical ram address by the ram-disk decoding hardware.

Therefore, it is completely transparent to the operating system.

To efficiently use the memory and decoding circuitry, the ram-disk is configured a little differently from the floppy disk. The 256K bytes of ram-disk are divided into

8 tracks, 256 sectors per track and 128 bytes per sector.

Since the ram-disk memory is volatile and it must always boot-up through a floppy disk drive, no tracks are reserved for the operating system. A standard 2K bytes are reserved for the 64 directory entries. The total useable storage space for the ram-disk is :

128 byte/sector * 256 sector/track * 8 track - 2048 byte

= 26,0096 bytes or 254 alloction blocks of lK bytes each.

These specifications are reflected in the disk parameter header and the disk parameter block for the ram- 20

disk of the BIOS section. Recall that each disk drive must have its own disk parameter header and disk drives with the same physical characteristics can share the same disk parameter block. For the ram-disk, both a new disk parameter header and a new disk parameter block are generated, and they are listed as below :

TABLE IV

Ram-disk Parameter Header ram-disk allocation buffer <------. ram-disk software check buffer <------. address of the ram-disk parameter block <-. . . common disk directory buffer <--...... : 0000: 0000: 0000: 0000: DIRBUF: RAMBLK: CHK4: ALL4: . .: scratchpad area for system internal use :--> indicates no translation vector reqired

The only difference between the ram-disk parameter header and a floppy disk parameter header is the lack of a translation vector table pointer for the ram-disk. Since the ram-disk is operating in the real time speed of the

CPU, no memory interlacing is required. This character gives us the first glimpse of the speed advantage of a ram-disk over a floppy disk drive.

The disk parameter block shows more distinct 21

characteristics of the ram-disk as described in the table below :

TABLE V

Ram-disk Parameter Block no reserved track for operating system <------. . no directory check vector <------. 2 reserved directory blocks <------.----. . . . . 64 directory entries <------...... : SPT: BSH: BLM: EXM: DSM: DRM: ALO: ALl: CKS: OFF: ...... --> 255 blocks of storage . . . . . ------> extent mask constant . . . block mask constant . . ------> .: ------> block shift constant ------> 256 sectors per track

There are four parameters in table V that have changed from a floppy disk parameter block. Those are SPT, DSM,

CKS and OFF. All these parameters reflect the distinct characteristics of a ram-disk. By patching table IV and table V into the BIOS portion of the operating system it enables the CP/M to control the files and data flow of the ram-disk.

Now we have specified the characteristics of the ram- disk. There is one more important patch to the BIOS. A standard CP/M is programmmed to handle four disk drives. 22

If the ram-disk is integrated into the system as the fifth drive, the BIOS must be altered so it will recognize all five drives. The ram-disk file address is generated by the CP/M file manager in the same way as a floppy disk file, but the files are accessed in a different manner. Recall in section 2.1, a floppy disk file is accessed through system monitor by calling seek track, seek sector and sector read/write monitor subroutines. The monitor routines will issure a series of commands to the disk controller for proper disk operations. The ram-disk is not interfaced through the disk controller. Instead, it is interfaced through the I/O structure of the CPU. For example, to access a particular track of the ram-disk, the desired track number would be passed to an I/O port address instead of passing it to the seek track routine in the monitor. The BIOS portion of the CP/M must be patched so it can recognize the different calling sequence between the ram-disk and a floppy disk.

2.4 DESCRIPTION OF THE BLOCK DIAGRAM There are three distinct parts to the ram-disk hardware design; the interface, the decode and the RAM block. The block diagram and their associate major functions are shown in figure 3. The heart of ram-disk is the memory block, which consists of 32 dynamic RAMs. Each RAM is a 64K by 1 memory cell. The 32 RAMs are arranged in a 4 by 8 array to "23

D0 - D7 D0 - D7 INTERFACE IBUFFER I· 1 A16,Al7 BANK r--RAS0 256K X 8 TRACK r--RASl DECODE r--RAS2 RAM BLOCK LATCH r--RAS3 ---- T RFSH T i CAS R/W A15 SECTOR ADDRESS AB - A14 LATCH MUX 1-- ~ ROW/CA0 ROW/CA7 1' MUXC A0 - A7 A7 BYTE ROW A0 - A6 LATCH MUX A0 - A7 I REFRESH CONTROL CONTROL CAS & RFSH BUS LOGIC RD CONTROL WR MUXC

FIGURE 3 : RAM-DISK BLOCK DIAGRAM 24

achieve the 256K by 8 memory capacity. The RAMs are MOS type chips. A MOS to TTL bidirectional, tri-state buffer

is used for interfacing the RAM data bus to the TTL data bus. The memory read/write strobe, RAM address strobe and all the address lines are also buffered before they are distributed to all the RAM chips.

The decoding circuitry is the most complex portion of the design. Its major functions are listed below :

1) address mapping The 3-bit track address, 8-bit sector address and 7-bit byte address are mapped into a

2-bit bank select, 8-bit row address and 8-bit column address for the memory block. There are a total of 18

address lines for 256k bytes addressing capability. 2) refereshing address - The dynamic RAM requires

periodic refreshing. Its 8-bit refreshing address is generated by the decoding circuitry.

3) address multiplexing - The 8-bit refreshing address is first multiplexed with the 8-bit row address, then the

8-bit multiplexer output is multiplexed with the 8-bit column address to produce an 8-bit row/column address.

4) generate all the strobe, timing signals and multiplexer select signals.

5) synchronize the CPU and ram-disk operations, since the 'BIG BOARD' and the ram disk each has its own 20M HZ

clock running asynchronously. To avoid a race condition a wide margin was designed into the ram-disk timing. A

detailed timing analysis will be presented in the next 25

chapter. The interface can be broken down into smaller functional blocks as shown in figure 4. The Z80's control and timing signals and the address bus is buffered and distributed to both the ram-disk address latches and the computer board. The ram-disk address latches include the

'byte' address latch, the memory refresh address latch and the port address decoder. The CPU's data bus is buffered by two sets of bidirectional tri-state buffers. One set of buffer outputs go to the computer board via the ribbon cable and the other set of buffered outputs are routed to various points on the ram-disk board.

The clock input to the Z80 CPU is sensitive to both level and rise and fall times. The clock voltage should be no greater than +0.45 volts for a low level and no less than vee - 0.6 volts for a high level. Additionally, the rise and fall times for the waveform should be no greater than 30 nano-seconds, according to the device specifications. A clock driver is included in the interface section to deliver the proper voltages and rise/fall times. 26

D0 - D7 CLOCK TRACK# B TRACKS C> ITA15 - Al7 BUFFER

RAM- ~ Z80 ~ DISK ~ SECTOR# CPU PORT 256 SECTORS DECODE !--- A7 - A14 1- f---< IT ~ AB - A14

BUFFER I BYTE BYTE # LATCH 128 BYTES sel A0 - A6 [> DATA BUS 00 - D7 IOREQ CONTROL Ml BUFFER RFSH

Figure 4 : Ram-Disk Interface Functional Block Diagram CHAPTER 3

CIRCUIT DESCRIPTION

In the first half of this chapter the major components of the circuitry are discussed. Then the detailed circuit description and critical timing analysis are presented in the second half of the chapter.

3.1 4164 MEMORY CHIP

The 4164 is a 64K dynamic random-access memory chip, organized as a 65,536 words of 1 bit each. It requires a single five volt power supply and all inputs and outputs are TTL level compatible. Chips with two hundred nano second access time are chosen for this application.

Sixteen address bits are required to decode one of

64K bit storage cell locations. Eight row-address bits are set up on the input pins AO thru A7 and latched onto the chip by the row-address strobe (RAS). Then the eight column-address bits are set up on the input pins AO thru

A7 and latched on to the chip by the column-address strobe (CAS).

The read/write function is controlled by the WRITE input. A low-signal on this pin while both RAS and CAS are low will latch the data presented on the data input pin into the storage cell selected by the column address and row address decode.

Data-in can be driven from a standard TTL signal, data-out is tri-state buffered. Data-out is the same

27 28

polarity as data-in. During a read cycle the output is in the high-impedance state until the CAS is brought low.

The output goes active within 135 nano-seconds after CAS becomes low.

As for all dynamic RAMs, the 4164 requires a periodic refresh operation to retain data, and the refresh should be performed at least every four milli-seconds. A complete refresh sequence is performed by strobing each of the 256 row address (AO thru A7) with RAS. The CAS is to remain high during the refresh sequence.

The read, write and refresh cycle timing diagrams are shown in figure 5, 6 and 7, respectively,

r·~------lc(td)------"1111

~ rl I I ... lw(Rll-----i.,...,. ::: ~....,.,.' ______.~..,': ;\.... ___ _ _.., )ooe-tr lo-. tcLRH--.. lo-f-tw(RHl-I!Oof 1 I ,...._ 'ALCL ., "4 1 wiCL~ ~ fCHAL --lloj ,... I 'RLCH-901 I I : I I -..I !.t-'tt :i ~~------~J?r~,~,~-----i\____~, "-f r-J'tu(RAl : j ~ lw(CHl---, I ,...... 'hiRLCAI I .,j I I 'hCAAI--t )14 H- I I : I 1 I ~ '•uiCAl I I Vrw , ' ~~,.....,.."?r':..-x-..,..-,,.....,... ,------AO·A7 Vn.

I I ::~ &o9v~~w I I '«<91:£~~ 00 l 1""1--'•ICI~ I I lf.eiotlt-----i..,Jaol '

FIGURE 5 : 4164 DYNAMIC RAM READ CYCLE TIMING (source Texas Instrument MOS Memory data book) 29

~------~(W)------~

RAS

CAS

AO·A7

FIGURE 6 : 4164 DYNAMIC RAM WRITE CYCLE TIMING (source : Texas Instrument MOS Memory data book) 30

f------'clrdl-----.-.l

VtH ------'--,_ 1-1--lw(Rll--.,.1 :'?f= !=l ------::.~ VtL :J' I ~'--- ! I I r---'wtRHI--i --...l r-- ,, I I I I ::~ ~ ~?~·i C~R~ YXX>'v\if : I I 1 I r-- htRAI ~ r- lauiRAJ~ I

AO-A7 ::: ··:"""'Xx;...... tJo-iN...,..:r ...... eA...... :E. ..-~.,....,.= ~ ROW :»~

:;~ x)(XXX:xXX>JJ<)

VoH Q VoL ------HI-Z ------

FIGURE 7 : 4164 DYNAMIC RAM REFRESH TIMING (source : Texas Instrument MOS Memory data book)

3.2 Z80A CPU The Z80A-CPU is a four mega-HZ central processor unit. It has a 16-bit address bus and a 8-bit bidirectional data bus. The general operation of the Z80A-CPU will not be presented here. Only some unique features of the Z80A that are pertinent to the ram-disk design will be discussed in this section. 31

The Z80A-CPU has a built-in transparent dynamic memory refresh support. It has a 7-bit refresh address register which is automatically incremented, and placed on the lower 7-bit of the address bus after each instruction fetch cycle. This seven bit address is used as a refresh address to the dynamic RAM, together with RFSH and MREQ signals a memory refresh cycle can be performed. The timing diagram of a instruction fetch and refresh strobe is shown in figure 8.

------MICvete-----11

T1 T2 T3 t 4

ifti

WAiT

RFSH

FIGURE 8 Z80 INSTRUCTION OPCODE FETCH TIMING (source Zilog Z80 CPU technical manual)

Recall from the previous section that 4164 dynamic

RAM requires an 8-bit refresh address (256-cycle refresh), but Z80 only provides a 7-bit refresh address (128-cycle refresh). The eighth refresh address bit is generated by the ram-disk decode hardware as shown in figure 9. 32

A7 ------~ t---___.... JIODAESS 7 TO MUL TIPlEXEA

1-0F·2 Z!OSIGNALS SELECT OAT~ SELECTOR :j: SYSTEM SIGNALS 1A 2A

FIGURE 9 : Z80 256 CYCLE REFRESH CONVERSION (source Zilog Z80 CPU technical manual)

The address 7 of the multiplexer output along with AO thru A6 from the Z80's refresh register are used for the dynamic RAM refresh row-address during a refresh cycle. The Z80 CPU refreshes the memory more frequently than is necessary to meet the four milli-second ROW refresh requirement. Under worst case conditions, no more than 19 clock states will separate two opcode fetch cycles (the EX(SP),HL instruction is representative of the longest time between opcode fetches). Assuming this worst case period between opcode fetches, the refresh period of a 4 M-HZ is 1216 micro-second for a 256 cycle refresh. This is about four times the required refresh speed of a 4164 dynamic RAM • The ram-disk is I/O mapped. All the communictions between the ram-disk and the CPU is via the INPUT and OUTPUT operations. Here, we will take a closer look of two particular I/O instructions. 33

IN r,(C) : The I/O port addressed by the contents of

the C register is read and the results

are loaded into the register r.

The register C supplies AO thru A7 of the

address bus and the contents of register

B appears on AS thru Al5 of the address

bus.

OUT (C),r: The contents of register r is loaded into

the I/O port addressed by the contents of register c.

The register C supplies AO thru A7 of the

address bus and the contents of register

B appears on AS thru A15 of the address

bus. In both instructions the port address in register c appears on the lower eight bits of the address bus and the contents of register B is dumped on the upper eight bits of the address bus. In the ram-disk software the register

B is used as the byte counter. During an I/O operation,

AS thru Al4 of the address bus is loaded into a byte address latch to address the 12S bytes of each sector.

This eliminates the need of a hardware byte address counter. Each I/O operation takes three micro-second for a four-mega HZ CPU, therefore, the ram-disk data transfer rate is about 330 kilo-bytes per second. The timing diagram of the ZSO input, output instruction cycles are 34

shown in figure 10.

AO ~ A7

I ORO -+---.;-, l I ~-+----"-----' ~----~ r-+--- \. , } Rud 1 j I Cvcle OATA aus -T~---+i---+-i---+-~ ~Gr---:-!--

~:•i =t====r=== r :n:=·r===:r-::..-::..-=.

/ 'Nrote I I ' · JCf

FIGURE 10 : Z80 INPUT AND OUTPUT CYCLES TIMING (source : Zilog Z80 CPU technical manual)

3.3 DETAILED CIRCUIT DESCRIPTION

In this section the design details are discussed in depthe The complete schematics are attached in appendix

A. All the IC reference designations are referred to on the schematics.

The Z80 has eight status output signals, and each of them is buffered by 'A2', 74LS244, before they are sent out to the 40-pin ribbon connector and the ram-disk decode circuitry. There are also five status input signals to the CPU. They are also buffered by a 74LS244 chip, I B2', before they reach CPU input pins. The 'RESET' is the only

input status signal that is used by the ram-disk. 'RESET' together with CPU's 'M1' signal form 'MlR' (IC F3, 74LS08) which is used to reset the ram-disk I/0 port decoder, C3. The sixteen address bits generated by the CPU are buffered with 'AS' and 'A6' (both are 74LS244). The 35

buffered address bits are distributed to both the ram-disk and the 'BIG BOARD' computer. The address · lines A8 through Al4 are used for the ram-disk byte address and they are latched into IC-'C2' (74LS374). To simplify the decoding circuitry, the byte address is latched in each time there is an I/O operation, although the ram-disk will not respond to these address changes unless the ram-disk data port is being enabled. The 8-bit bidirectional data bus from the CPU is wired into two seperate bidirectional tri-state buffers, 'B5' and 'B6'. The 'B5' controls the data flow between the CPU and the ram-disk. It isolates the ram-disk data bus from the CPU bus when the 'BIG BOARD' is being accessed by the CPU. In contrast, 'B6' isolates the 'BIG BOARD' data bus when the CPU is accessing the ram-disk. The ram-disk data buffer is enabled by the signal 'RAMDISK' which is generated from the decoder circuitry.

The same signal disables the 'BIG BOARD' data buffer. The directional control of 'B5' is the 'OR'ed output of

'IOREQ' and 'RD' of the CPU status signals. To meet the Z80 clock requirement, a transistor clock driver is employed. The clock generated on the 'BIG BOARD' is double buffered to preserve the phase, and a

2N2907 PNP type transistor is used for the output section of the clock driver. If the 'F2' pin 2 and pin 3 are at

TTL low state, the 220 OHM and 1.2K OHM resister provides 36 a forward bias to the transistor's BASE-EMITTER junction and causes the transistor to go into saturation. That brings the COLLECTOR voltage close to vee, which is in phase with the 'F2' output, pin 1. If the 'F2' pin 2 and pin 3 is at a TTL high state, the transistor is operating at the cutoff region. Then the output of 'F2', pin 1, sinks the COLLECTOR terminal to the ground level. The 33 pico-farad capacitor is there to reduce the ringing of the COLLECTOR waveform by slowing down the transistor's BASE switching speed. This clock drive circuitry works extremely well for this type of aplication. It produced a clock that swings from 0.2 volts to +4.9 volts. The ringing is less than 0.15 volts with a rise and fall time of less than ten nano-seconds. A Z80A-PIO is used to latch in the ram-disk's track and sector address. It is very simple to interface a PIO chip with Z80-CPU because most signals can take directly off the CPU buffer as show by 'C1'. The PIO has two 8-bit parallel ports, port A is used to latch the 3-bit track number and port B is used to latch the 8-bit sector number. Both port A and port B are initialized to be output ports. Their status ports reside in address 85 hex and 87 hex respectively. The data port A resides in address 84 hex and data port B resides in port 86 hex. The 7-bit byte address, 8-bit sector address and the 3-bit track address were labelled as DISKAO through DISKA17. DISKA16 and DISKA17 are decoded by 'F4', 74138, 37

to produce four RAM bank-select lines as in Sheet 3 of the schematics. The DISKA8 through DISKA15 are RAM column addresses and DISKAO thru DISKA7 are RAM row addresses. The eighth refresh address bit is generated by '03', 74393, a two stage binary counter. The counter is cleared by a CPU reset, and each refresh cycle bumps up the count by one. For every 128 refresh cycles, the MSB of the dual counter changes state once. This counter output is implemented as the eighth bit of the refresh address. The eight row address, eight column address and the eight refresh address are multiplexed together to form one set of eight bit address that goes to the eight address input pins of the dynamic memory chip. The multiplexing is accomplished with four 74157 ( quad two to one multiplexers) , 'A9', 'A10', 'Al2' and 'A13'. Two of the multiplexers 'A9' and 'AlO' are used to select either refresh address AOB through A7B or DISKAO through DISKA7 as the row address, and the remaining two multiplexers

'A12' and 'Al3' are used to multiplex row and column addresses to the memory chips. During a normal ram-disk read/write cycle, the signal 'RFSH' is inactive, and DISKAO thru DISKA7 are selected as the row address by 'A9' and 'A10'. The select signal for 'A12' and 'Al3' is generated by the shift register '05',

74164. This chip not only controls the internal ram-disk timing, it also synchronizes the ram-disk operations to 38 the CPU timing cycles. The 74164 is driven by a twenty- mega HZ local clock and it is enabled by the ram-disk data port enable signal. When the 74164 is not enabled, all its outputs are at logical low state {been cleared), and the multiplexers 'A12' and 'A13' pass the row address to their outputs. Both inputs to the shift register are pulled up to positive five volts. When enabled, its eight outputs, starting with the LSB, will change from a logical low to a logical high, one at a time at 50 nano-second intervals. Approximately 50 nano-second to 100 nano- second after the shift register is enabled {the timing skew depends on the synchronization shift between the local oscillator and the decoded CPU signal 'DATACE'), the

'QB' output of the shift register becomes a logical high. This output signal together with the IOREQ and bank-select multiplexer 'F4' output generates a RAS strobe to a selected bank of RAMs. Exactly 100 nano-seconds after

'QB' became a logical one (about 55 nano-seconds after RAS strobe became active), the 'QD' output pin of the shift register goes to a logical one, and the multiplexers 'A12' and 'A13' switch their outputs to the column address.

Another 50 nano-seconds later, the 'QE' output of '05' (shift register) also becomes a logical one. This output is used as the CAS strobe. One hundred nano-seconds after CAS strobe became active, the 'QG' output of 'D5' goes to a logical one, and this output is 'AND' with the CPU's 'WRITE' strobe to generate the 'DISKWRITE' strobe. A 39

SYSTEM CLOCK A0 - A7 ===:x ______P~O~R~T--A~D~D~RE~S~S~------~X~------IOREQ

DATA BUS ------~

WAIT

RAMDISK

RAS

DATACE

MUXC

CAS

A0 - A6 ------J><~~D~I~S~K~A~D~D~R~E~S~S~A0~-~A~6~------A7 - A17 DISK ADDRESS A7 - A17

Figure 11 : Ram-Disk Composite Timing Diagram 40

detailed timing diagram of the ram-disk read/write cycle is included in figure 11.

During a refresh cycle, the select pins of the first two multiplexers 'A9' and 'A10' are held low by the refresh strobe, and the refresh address is selected to tQeir outputs. The select pins of the second pair multiplexers are also held low, because shift register 'DS' has been cleared by the refresh strobe, and the refresh addresses are passed through to the RAM address input pins. The refresh strobe is 'OR'ed with 'MEMRQ' to generate four RAS strobes. Recall that RAS is the only strobe that is required for a memory refresh cycle, and all four banks of memory chips are refreshed at the same time.

The regular TTL multiplexers instead of the low power Schottky were used for 'A12' and 'A13' for their higher current sinking capabilitiese Each output of the 'A12' and 'A13' has a serial 33 OHM resistor to reduce the transient voltage noise spikes on the address lines. The ram-disk I/0 port address is decoded by 'C3', a 74138 chip. The track address is loaded into port 84 hex, the sector adress is loaded into port 86 hex and the data port is 80 hex. When either the data-port or address-port has been accessed, the signal 'RAMDISK' becomes active.

This signal is used to enable the bidirectional data buffer between the ram-disk and the CPU data bus.

The final section of the circuit description is the 41

memory block. There are thirty-two dynamic RAMs arranged in four banks of eight chips each. All the RAM address inputs are wired in parallel. The specification of the 4164 shows that each input pin draws ten micro-amps, and thirty-two inputs draw a maximum of 320 micro-amps, which is well within the drive capability of a 74157 multiplexer chip. All the CAS pins are also tied together. Four RAS lines are distributed to four banks. The data-in and data-out pins of four banks are tied together to form an eight bit wide data bus. The data bus is buffered by 'A7' and 'All', two 8216 MOS to TTL bidirectional data buffers, and the data flow direction of the buffers is controlled by the 'RD' signal from the CPU.

3.4 POWER SUPPLY

The ram-disk requires one positive five volts supply. All the TTL and memory chips can work from +4.5 volts to +5.5 volts DC power supply, but Z80A-CPU and Z80A-PIO can only tolerate a five percent voltage deviation, therefore the power supply must be regulated to within 4.75 volts to 5.25 volts DC under full load. To keep the ground potential difference between the 'BIG BOARD' computer and the ram-disk to a minimum, the following steps were taken :

1) Both the computer board and the ram-disk power was

taken from the same supply, and off the same power

distribution bus. 42

2) Heavy gauge wires were used for the power supply.

3) A ground jumper wire was connected between the two

boards, and the Z80 ground pin was connected to the

ground planes of both boards.

The 4164 dynamic RAM draws 25 milli-amps operating current and 3.5 milli-amps stand-by current, and the current requirement of the other ICs is shown in the Appendix B. The theoretical worst current demand is calculated to be 2.2 AMPS, however, the average current demand of the ram-disk were measured to be 1.5 amps.

As in any digital circuitry, the logical level switching can produce large current spikes on the power supply line. This phenomenon is especially true for the dynamic RAM. The current demand of a dynamic RAM increases by more than seven hundred percent each time the

RAM chip is accessed for a read/write or refresh operations. To reduce these current spikes, a .1 micro farad filter capacitor is placed between the +5 volt and ground supply pins of each chip, two 10 micro-farad capacitors are placed on the top and bottom of each column of chips and two 100 micro-farad capacitors are placed at where the +5 volt and ground supply enter the board. In addition to the capacitors, a bread board with a good ground-plane is chosen for the ram-disk. CHAPTER 4

SOFTWARE DESCRIPTION Several programs were written for the ram-disk application, one self-test program, one formatting program and two custom 'Basic Input/Output' programs. Each of these programs is discussed in the following sections.

4.1 SELF-TEST PROGRAM The self-test program was developed to trouble shoot the 256R byte dynamic RAMs. This program was originally written to bring up the ram-disk. After the ram-disk was operational, some modifications were made to the program and transformed it into a complete diagnostical RAM testing program.

This program tests all the memory cells extensively. Every byte of the memory is tested with 256 different data patterns, and every 128 bytes are tested as one group. The program first loads the 128 bytes under test with an incremental data pattern, such as 00 hex in the first byte, 01 hex in the second byte and so forth. After all

128 bytes memory are loaded, the RAMs are read back to confirm if the data was correctly stored. If all 128 bytes checked out to be correct, then a new data pattern is loaded into the same group by adding one to each of the previous patterns. This sequence is repeated 256 times for every 128 bytes of memory and every location of the

RAM-block must go through this procedure to pass the test.

43 44

For one complete test pass, each memory location is

written into and read back 256 times. There are 256K

bytes of memory in the ram-disk, therefore, more than 67 million read and write operations are performed by the CPU

for one test pass. It takes 22 minutes and 38 seconds to

run this program once. During the test, the track number and the sector number that is under test is displayed on the CRT monitor. After one complete pass, the program will

repeat the test until it is terminated by the programmer.

If any memory location failed the test, the CRT screen will display the track, sector and byte address that

failed the test along with the test data and failed data.

The listing of this program is attached in appendix c. This program can be executed without any ram-disk initialization and it will overwrite the ram-disk data with the test patterns.

4.2 FORMATTING THE RAM DISK

Each time after the power up, the ram-disk memory

contains meaningless, random zeros and ones, just like a newly coated floppy disk. Before a new floppy disk can be used, it must be formatted first, which means the track address and sector address are written to the disk, and the file directory space are cleared. For a ram-disk, the track and sector addresses are defined by the hardware, and only the file directory needs to be initialized.

The ram-disk is always initialized as a blank disk, 45

and the CP/M operating system recognizes an empty disk by reading all 'F5'hex from its directory entry. Recall from chapter two, in the 'disk parameter block' section, the ram-disk was defined to have a maximum of 64 directory entries. The CP/M requires 32 bytes allocation for each directory entry, therefore a total of 2048 bytes are reserved for the disk directory. This information is also defined in the 'disk parameter block' by two parameters

'ALO' and 'ALl'.

The reserved disk directory space is located in the beginning of the disk. For the ram-disk it is track 0, sector 0 through sector 15. The format program simply writes 'F5 hex' into the first 16 sectors of track 0 to initialize the ram-disk. A listing of the format program is attached in the appendix D.

4.3 CUSTOM BASIC INPUT/OUTPUT SYSTEM

Several additions and alterations were made to the standard CP/M 'Basic Input/Output System'. A new 'disk parameter block' and 'disk parameter header' for the ram disk were added. The total disk drive number was changed from four to five disk drives. Since the ram-disk is accessed differently from a floppy disk drive, a new read routine and write routine were added to the BIOS too.

Two versions of the custom BIOS were created. In the first configuration, the ram-disk is drive five of the computer system, but most application programs assign 9 ' 46

drive one as the default drive. During program execution, all the data and overlays are sought from the default drive only, and after program execution, the default drive

is always selected by the operating system. In order to utilize the ram-disk more efficiently, the second version of the custom BIOS assigns the ram-disk as the drive one, and the four floppy disk drives as drive two through drive five.

When the computer system is booted up, the standard

CP/M BIOS is always loaded into the reserved computer RAM area. For 'BIG BOARD' the BIOS starts in memory location

E800 hex and has 2K bytes reserved spaces. To implement the ram-disk, the custom BIOS must over-write the standard

BIOS. The BIOS is not an executable program, therefore, a

'MOVE' program was written to move the custom BIOS over the reserved BIOS locations. The operation of the 'MOVE' program is shown in figure 12.

A listing of the MOVE program and both custom BIOS are attached in the appendix E, F AND G. 47

100 hex 'MOVE' PROGRAM 200 hex

CUSTOM BIOS

600 hex

~------+------~'~------~, E801ZJ hex STANDARD BIOS

~----~~, ~------~ EC00 hex

FIGURE 12 : THE 'MOVE' PROGRAM WRITE THE CUSTOM BIOS OVER THE STANDARD BIOS SPACES CHAPTER 5

EVALUATION AND CONCLUSION In this chapter the user interface, the ram-disk performance evaluation and some comments are presented.

5.1 USER INTERFACE The user interface includes the installation of the ram-disk and the ram-disk boot up into the system. The

installation is a one-time only operation. It involves two power supply wires, one ground jumper and one 40-pin ribbon cable. The power supply plugs into the terminals that are soldered on the ram-disk board. The ground

jumper clips on any ground lead of the 'BIG BOARD' computer and the ribbon cable connects between IC-'Al' of the ram-disk board and the CPU socket of the computer board. The Z80A-CPU is removed from the computer board and

inserted into IC-'A3' of the ram-disk board. The software integration must be repeated each time the power is cycled. After the computer is powered up and the CP/M has been booted into the system, the ram-disk formating program 'NFORMAT' should be executed. 'NFORMAT' should be executed only once after each power up. This program initializes the ram-disk directory, and if it is executed after some programs have been loaded into the ram-disk, the entire disk files would be lost. Next, one of the programs 'ABIOS' or 'EBIOS' must be executed. 'ABIOS' configures the ram-disk as drive one

48 49

and 'EBIOS' configures the ram-disk as drive five. After the configuration program has been executed, the ram-disk is ready to respond to the operation commands. But before any program can be executed from the ram-disk, the programs must be copied into its memory.

The file copy operation can be done with standard CP/M command 'PIP'. Either an entire disk file or few selected files can be copied into the ram-disk. Before the computer is powered down, all the files that have been altered must be copied back onto the floppy disk for long term storage.

If a 'system reset' occurred during the operation, the program 'ABIOS' or 'EBIOS' must be executed to re configure the ram-disk. As long as the 'NFORMAT' is not executed and the power supply is not interrupted, the ram disk will preserve all its files.

5.2 PERFORMANCE EVALUATION The greatest advantage of a ram-disk is the data transfer speed. It takes three micro-seconds for a four mega-HZ CPU to execute an input or an output instruction, which means the ram-disk has a data transfer rate of greater than 330 K bytes per second. That is more than ten times the transfer rate of a floppy disk drive which has a data transfer rate of 30 K bytes per second.

Several bench mark programs were tested to compare the execution speed between the floppy disk and the ram- 50 disk. Although the ram-disk transfer rate is ten times that of a floppy disk, it does not mean that the program execution time can be reduced to one tenth when it is loaded from the ram-disk. A good bench mark program should have extensive disk access, or a very short program, for which the program execution time is negligible and most of the run time was spent on disk access.

TABLE VI Ram-disk Bench Mark Test

I BENCH TEST I RAM DISK I FLOPPY DISK I I FILES I RUN TIME (SEC) I RUN TIME {SEC) I I------I------I------I I Word Star I 3 I 14 I I------I------I------I I Status I 1 I 8 I I------I------I------I I Directory I 1 I 8 I I------I------I------I I Assemble I I I I RAM test file I 11 I 46 I I------I------I------I I Copy File I I I I Thesis2.doc I 3 I 32 I

For longer programs such as WORDSTAR, ASSEMBLER or game programs such as ADVENTURE, the computer run time is also improved significantly with the ram-disk. The computer responds to the user command almost instantaneously.

So far the ram-disk has been operating with the 'BIG BOARD' for more than one-hundred hours and it has 51

performed flawlessly. It is important to have a good ground connection between the ram-disk and the computer board, otherwise the CPU may hang up and only can be recovered by recycling the power supply.

The time it takes to initialize the ram-disk is the total execution time for the 'NFORMAT', 'ABIOS' and disk files transfer. The execution time for 'NFORMAT' is one second and for the 'ABIOS' is two seconds. It takes two minutes and 44 seconds to copy an entire floppy disk into the ram-disk. In contrast, a floppy to floppy files transfer take six minutes and 21 seconds. The total initialization time for the RAM-disk is less than three minutes.

5.3 CONCLUSION AND COMMENT

Overall, the ram-disk satisfied all the design requirements. It reduced the file access time to one- tenth. It is reliable and has 254 K bytes of usable storage capacity. To make initialization less bothersome, the most often used programs should be combined into one floppy disk, and one copy command can transfer them into the ram-disk together.

To interface the ram-disk with computers other than the 'BIG BOARD', the hardware interface remain the same.

The same ram-disk design should work as long as the computer satisfied the following requirements : 52

1) The computer must have a Z80 or Z80A CPU.

2) The computer operates with a CP/M operating system.

3) The I/O ports 80 hex through 84 hex are not used by the computer system.

The ribbon cable for this design is limited to four inches long due to the data propagation delay of the cable. In future designs, the CPU and the buffers should be placed in the computer end of the ribbon cable. This modification will allow the cable to extend to a few feet in length.

When the 256 K by one dynamic RAM becomes available next year, the ram-disk can expand into one-mega byte capacity with minor hardware and software changes. This will enable the ram-disk to handle even the most sophisticated data base programs in the market today along with all the data files in the ram-disk. 53

REFERENCES

1. Zilog, Inc., "Z80-CPU Technical Manual," Zilog, 1977.

Cupertino, California.

2. Zilog, Inc., "Z80-PIO Technical Manual," Zilog, 1978.

Cupertino, California.

3. Digital Research, "CP/M User Manual," Digital Research,

1980~ Pacific Grove, California.

4. Texas Instruments, "MOS Memory Data Book," Texas

Instrument, 1982, pp.39-54. Dallas, Texas.

5. Digital Research Computer, "Big Board User Manual,"

J. B. Ferguson, Russel Smith, 1980. Garland, Texas. ---:;--=-----:-:--:-----:-----,------~----...... ,.-,------~------~------,

54 CAMBION 714-1115-01 30 25 20 15 10 5

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . 0 0 0 0 0 c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 c 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 !r:Jt !r:Jt I I I ·1 I I I I I 0 0 0 0, c 0 0 0 0 d 0 0 ic 0 0 i 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 "' "'0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ~0 0 0 0 0 0 c. ; 0 0 0 0 0 0 c i 0 0 0 0 0 0 0 0 I 0 g g g g 0 0 ~ ~ ~ ~ ~ ~ I ~ ~ ~ ~· ~ ~ ~ ~ 0 0 0 0 0 0 o•o ofo o•o o o ofo o o o

0 d 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

• ~BBB88888BB888BBB8BBB8888BB8888888B 8 8 8 8 8 8 8 8 8 !I 8 8 8 8 8 8 8 8 II 8 8 8 8 8 8 II 8 8~8 II 8 8 8 II 8 ft 118888888811&&1181188!888!8888118.1181188811 ft 888888888888888888881188888888888888

RAMDISK BOARD ID I REV A r ___ _ ~-~-n 1 -I 1 "r A i 55

F3 .. I niR-L 10 71LS08 IS 7,.LS244 18 z ...... AI~ A15 4 ~ 16 AI 14 4 AH 6 ...... Al3 ,.._L...J 12 AIRI:E •II ... 9 A12 .. 1 I All ~ 7 13 AID ZtLDtK IS' .... ~5 ISl-L A9 7 -~ 3 1:1: AI 81 B2 .. l ...3 QO 2 OJ&KAO 4 DO 5 B2 Ill Ql DI&KAl J 6 74LS244,_., Al5 ~ D2 74LS374 Q2 DJ&KA2 2 ' 18 11 8 Q3 9 - D3 DJ&KA3 4 -" .U4 f-4..--.3 13 12 .. 16 Al3 1M 04 DI&KA4 6 ., ...... 14 li 2 14 IS CLOCK Al2 ~ C2 Q5 DI&KA5 8 ., __ I 16 1 -~- All D6 DJ&KR6 1 II 9 40 18 .. 19 .uo .., Q7 I 13 ~ 7 39 D1a C> A9 38 I 15 ~ II AIT AI M 17 ..~ 3 74LS244 - BU&REQ '11 2 18 & Al'3'r IJ R1 ii B2 36 4 ~ 16 A3 - A& JOREQ-L 13 04 .... 12 ... Ale: 35 6 __., 14 AI ~7tso4 11 lli AS - 34 8 ~ 12 AI ZL R&T M" .... 34 A4 ID. INT 33 II 9 AI f-ir A3 13 ...... ,t:::..l 7 R3 L1 11n1 32 AI~ R2 - fl. 31 15 .... ,_j82 5 .u Alht: AI fl. 30 17 ,_..t:: 3 .RI 30 280 NJ '-=-- AD 74LS244 B2 13 8i 18 ...... 2 Zl BU&ACK D7 I 16 ::t. .. 4 10 14 ...... 6 ~ ftRED D& 9 RD ~ I 12 ~ 8 7 -Ll IIR 04 I 9 ...... II IOREQ D3 8 - I 1 ~- 13 2 12 l8a-.. ... ftl D2 5 IS RF&H Dl ~ 3 L:ll-.,., 17 I HALT ·oo JL 81 B2 - ~ 18 D78 3 ~~~1 17 D&B 4 IS L1 5 74LS2E~. 15 058 - D4B 6 85 -~ 14 038 7 13 028 HALT-L :~~s- 12 D18 RF&H-L II DDB n1-L lDRED-L DIA a IIR-L RD-L il ftREQ-L

AI """"i3 2 01 rJ_ NOT US ED ~ AI~BIIB. ... 17 01 3 A7 3 Al-jij- 06 A& f-!- NOT US ED 4 fl. -~ 16 06 38 r-74LS2E ;, Al'9"'"" 05 05 AS ~ NOT US ED 5 15 AI'""]""- Q.4 39 04 NOT U& ED 40 A4 P.i: 6 115 ~- 14 Al----r- 03 03 A3 7 13 Al~ I 13 02 02 Cl A2 14 DI&KRn TRACK 8 ~~8-12 AI~ 20 01 01 I! A1 15 DI6KR1& ADORE&& 9 II .AI-jt- DO DO AD DI&KRIS r- DIR '-'-'-- 8 6 18 - !i RIB _ _2_ A/B &EL A ROY AORTA .READY ROB C/0 &EL A &lB ,!£. woe 34 ADDRE&&CE-L 4 CHiP El B'l DI&KA14 37:. 33 ftl-L ftl 86 32 DI&KAU C5 JIIRD-L 36: IDRQ 85 DI&KA12 31 DI&KRU &EtTDR 1211 5 3 C5 14 RD-L -.--Jit RD 84 30 12 280-PID B3 Dl&KA1D ADDRESS 1 ) D2 II 29 220 OHft E 'JI: 82 .... DJ&KR9 99 ~F J 16_... 13 741.S3ilf -- --- 56

7 . +SV

C4 lK •F 2 llA r+4 I It QB Z B oc ~ ,..,.4 D5 llD 3 E2 8 CLK OE rW----- CRS-H 74l.S04 74164 or r412 00 4 IJI 5 ~c~ r!l 6 __, DRTRCE-L IIRROISK 4 rz ...... 517:soo IOOrf= El 6 74LS02 5' E2 ~6 RFSH-L 15 '74Lso4 RZB I YO DRTRCE-L ~ 2 A 14 -= R38 B VI ROORESSCE-l A48 3 C Y2 >lt 71138 Y3 >¥.- ·c3 Y4 :>;\!- nJR-L 6 Gl Y5 4 ~9 . IOREQ-l G2A Y6 5 G2B Y7 :>-'-~ . 6 R78 5 04 I 74LS04

12~E3 ll 13174LSOO

9 ~8 RST-L E2 'J4LS04 18 2 82 74LS244 8 4 16 2 A8 15 OISKNR-L 14 82 ID~ ~ 4 2 I 16 2 lA 4 ~ 7:4'L504 3UHn .--.1- !NR 108 lA IY 5 IY ROW/CR7 74LS244 IDC -+ R6B 5 2A 2A I 4 II A9 II Al2 7 2 Al~.. l5 ICP IDO _L_ RSB 3A 2Y ..l.___j 3A 2Y ROW/CR6 ~---•o 14 14 '.~ 74L504 71393 R4B. 4A . 3 4A 3 Al4 14 DISKR7 3 18 3Y DISKRIS IB 3Y 9 ROW/CAS .__!L 2D~ -!!- 6• 9 I I 6 '-~~ DISKRB DISKRI4 2YR 03 ~ .J9.. 10 2B 71157 12 10 2B 74157 12 4 Al4 13 2QC DISKRS 38 4Y 015KR13 38 4Y rvv ROW/CR4 -+8 13 13 ~ 2CP 2 DISKR4 48 DJSKR12 48 33 OHn _._ro 5 5 6 5 G 6 74LS04 4 ) ~4LS -11 -11 - -

/ I I E3 ,..., 3 3 2 74LSOO . 2 ) .. l 4 2 4 5· Al4 12 ~ R3B 2 lA IY lA IY 3 - 5 RDW/CR3 RZB 5 2A .3 RRSD-l AIO II 2A 7 6 Al1 II ~74LSOO AlB II .JA All 14 3A 2Y f.L-J 14 2Y RDW/CRZ 74LSOO ROB 4A 4A ~ 3 3 ' 7 DISKR3 IB 3Y 9 DISKAll IB 9 ~~ 10. 6 I I 6 3Y ROW/CRI ~ ~6 DliC1_1 nlt~:IUliJ ntt:.K.D.1n 711 - I "' ,... 57 g g g g g g g g ' A7 A7 A7 A7 A7 A7 A7 A7 13 13 13 13 13 -- 13 13 13 AS AS AS AS AS It, Ar. Ar. 10 10 10 10 10 10 10 10 AS AS AS AS AS AS AS II II II II II II AS II II A1 A1 A1 A1 A4 A1 A4 12 12 12 12 12 12 A4 12 12 A3 f1 A3 E8 AJ E9 A3 EIO AJ 012 A3 013 A3 014 6 6 6 6 6 on A3 6 6 A2 A2 A2 A2 A2 6 A2 A2 7 7 7 7 A2 7 7 AI AI 7 AI AI AI 7 AI AI 5 5 5 5 5 AI 5 5 AO 4164 AO "1164 AO 4164 5 AO 4164 AO 4164 AD 4164 AO 4164 AO 4164 3 w 3 w 3 w 3 w 3 w 3 w 3 w 3 w CAS CAS CAS CAS CAS CAS CAS CAS ·, ---lfC RAS ~ RAS ~ RAS -4< RAS r---!fC RAS r-lfC RAS 4 RAS ~ RAS ___.1_ ___.1_ _]_ ___.1_ ___.1_ _]_ Dl 00 JL ,---1.. Dl 00 ,JL Dl 00 r!L Dl 00 JL Dl 00 JL Dl 00 ...!L ,---1.. 01 00 JL Dl 00 ,JL

g g g g 9 9 9 9 A7 A7 A7 A7 A7 A7 A7 A7 13 13 13 13 13 13 13 13 AS A6 A6 A6 Ali A6 Ar. A6 10 10 10 10 10 10 10 10 AS AS AS AS AS AS AS AS II II II II II II II II A1 A1 A1 A1 A1 A4 A4 12 12 12 12 12 12 A1 12 12' A3 07 A3 08 A3 09 A3 DID A3 011 012 A3 013 A3 014 6 6 6 6 6 A3 6 6 A2 A2 A2 A2 6 A2 A2 7 7 7 7 7 1.2 A2 7 7 AI AI AI AI 7 AI AI 5 5 5 5 AI AI 5 5 AD "1164 AO 4164 AO 416-t AO 116-t s AD 41S-t 5 AO 4164 AO 1161 AO 1161 3 w 3 w 3 w 3 w 3 w 3 w 3 w 3 w CAS CAS CAS y< CAS CAS CAS CAS CAS 4< RAS 4 RAS f--lf= RAS RAS ---'iC RAS ---'iC RAS ~ RAS ~ RAS ~ Dl 00 ~ ._1... Dl DO ~ ~ Dl DO ~ ~ Dl 00 ~ ~ 01 00 Ji.... ~ Dl 00 c.JL, ~ 01 DO JL. ._1.. Dl DO ~

g g g g 9 9 9 9 A7 A7 A7 A7 A7 A7 A7 A7 13 13 13 13 13 13 13 13 A6 AS AS A6 AS- AS AS A6 10 10 10 10 10 10 10 10 AS AS AS AS AS AS AS AS II II II II II II II II A1 A1 A1 A1 A4 A1 A1 A4 12 12 12 12 12 12 12 12 A3 C7 A3 C8 A3 C9 A3 CIO Cll Cl3 A3 CI-t 6 6 6 6 A3 A3 cti 6 A3 6 A2 A2 A2 A2 6 6 A2 A2 A2 7 7 7 7 A2 7 7 7 AI AI 7 AI AI AI 5 AI 5 AI AI 5 5 s AO 4161 AO 1164 s AO 1164 AO 1164 5 AO 1164 5 AO "1164 AO 116"1 AO 416-t 3 w 3 w 3 w 3 w 3 w 3 w 3 w 3 w CAS CAS CAS Wf( CAS CAS CAS CAS CAS - 4 -4< RAS ~ RAS ~ RAS RAS ~ RAS ~ RAS ~ RAS ---'iC RAS ~ Dl 00 ~ ~ Dl 00 JL. ~ 01 00 JL. ~ 01 00 JL. ~ 01 DO JL. ~ Dl 00 ~ ~ 01 DO JL. ....,1... 01 00 JL. i g 9 9 9 9 9 g 9 A7 A7 lo7 A7 A7 A7 A7 A7 13 13 13 13 13 13 13 13 i AS AS A6 A6 A6 AS A6 A6 10 10 10 10 10 10 10 10 AS AS AS AS AS II II II II ·II AS II AS II AS II A1 A1 A1 A1 A-t A4 A1 A4 12 12 12 12 12 12 12 12 i A3 87 A3 B8 A3 89 A3 810 A3 811 A3 812 A3 813 A3 BI-t 6 6 6 6 6 6 6 I A2 A2 A2 s A2 A2 A2 A2 A2 7 7 7 7 7 7 7 7 AI AI AI AI AI AI AI AI s 5 5 5 5 5 5 AD 4164 AO 4164 AO 1164 s AO 4164 AO 416-t AO 416"1 AO 1164 AO 4164 3 w 3 w 3 w 3 w 3 w 3 w 3 w 3 w CAS CAS CAS ~~ C'AS CAS CAS y< CAS us 4 RAS ---'iC RAS 4 RAS RAS 4< RAS 4< RAS RAS ---'iC RAS ~ 01 DO rJi.-., ~ 01 DO JL. ._1... Dl 00 JL. ~_L Dl DO JL. ~ 01 DO JL. ....,1... 01 00 ~ ._1.. 01 DO rlL ....,1... 01 DO ~

,--

RRSD-L RDN/CR7 - RASH ROW/CRS RRS2-L ROW/CAS RRS3-L ROW/CA4 4 ROW/CA3 4 ... 2 ""\. 3 2 3 ROW/CR2 ~ 038 078 7 ROW/CAl A7 6 '-'--f..5 ""All 6 DISKWR-L ROW/CAD s DZB 068 9 9 II 8216 10 II 821S iO 018 058 12 12 14 "\ 13 I"' 13 ,,...2 I AS 16 DOD 048 CAS I 04 OlEN CS . OlEN"" CS 71LS04 33 OHn RAMDISK !!! !!! MEMORY 471 • 71LS04 1- 1- RO-L ID I I REV A 58

APPENDIX B IC LISTING AND POWER REQUIREMENT

IC PART : NUMBER : MAX. CURRENT : TOTAL POWER NUMBER : REQUIRED : PER CHIP REQUIRED

Z80-CPU 1 . 200 rnA 200 rnA Z80-PIO 1 100 rnA . 100 rnA

74LS244 4 54 rnA 216 rnA

74LS245 2 . 95 rnA 190 rnA 74LS374 . 1 40 rnA 40 rnA

74LS04 2 6.6 rnA . 13.2 rnA 74LS08 . 1 8.8 rnA 8.8 rnA

74LS32 1 22 rnA : 22 rnA

74LS02 1 5.4 rnA 5.4 rnA

74164 1 54 rnA 54 rnA

74LSOO 3 4.4 rnA 13.2 rnA

74138 2 10 rnA 20 rnA

74393 . 1 . 64 rnA 64 rnA

74157 4 48 rnA 192 rnA

8216 2 130 rnA 260 rnA 4164 . 32 25 rnA 800 rnA ======MAXIMUM CURRENT REQUIREMENT : 2200 milli-AMPS 59

APPENDIX C RAM-DISK SELF TEST PROGRAM LISTING ;* ------·------* ,•* ------RAMO DISK SELF TEST PROGRAM ------* •*, * ,•* - CHUNG T. HO - MARCH 15, 1983 ;*------** ORG 100H

CR EQU OOOODH ;ASCII LF EQU OOOOAH ;ASCII EOT EQU 00004H ;ASCII BASE EQU OFF77H ;CRT BASE LINE # STORAGE KBDRD EQU OF46DH ;KEYBOARD DATA READ KBDST EQU OF431H ;KEYBOARD STATUS CHECK SCROLL EQU 0001CH ;CRT SCROLL REGISTER PORT CURSOR EQU OFF73H ;CURSOR LOCATION POINTER CRTOUT EQU OF520H ;MONITOR DISPLAY ROUTINE PASS EQU 01002H ;NUMBER OF TEST PASSES TRACK EQU OlOOOH ;TRACK # STORAGE SECTOR EQU OlOOlH ;SECTOR # STORAGE TRKPORT EQU 00084H ;TRACK PORT ADDRESS SECPORT EQU 00086H ;SECTOR PORT ADDRESS PNEXT EQU OF3ECH ;MONITOR MESSAGE ROUTINE DATPORT EQU OOOSOH ;DATA PORT ADDRESS

., ;INITIALIZE STACK POINTER .,

LD SP,02000H

., ;SET UP PIO PORT A AND PORT B AS OUTpUT PORTS .,

LD A, OFH OUT (85H) ,A OUT (87H) ,A ., ;INITIALIZE TRACK # AND SECTOR #

LD A, 00 LD (TRACK),A LD (SECTOR),A LD {PASS) ,A 60 p •

., ;NOW CLEAR THE cRT SCREEN .,

LD A,OOlAH ;REG. A HAS (CONTROL-Z) CALL CRTOUT ;CALL CRT WRITE ROUTINE ., ;WRITE 'RAMDISK MEMORY SELF TEST' ON THE SCREEN .,

CALL PNEXT DEFB CR DEFB LF DEFM 'RAMDISK MEMORY SELF TEST' DEFB CR DEFB LF DEFB LF DEFB EOT ., ;OUTPUT TRACK #

DSKLOOP LD A,(PASS) ;BEGINING OF THE DISK ADD A,Ol LD (PASS) ,A ;NUMBER OF TEST PASSES LD A,OO LD (TRACK) ,A ;ALWAYS START ON TRACK 0 TRKLOOP LD A, (TRACK) LD C,TRKPORT OUT (C) ,A ;SELECT TRACK ADDRESS ., ;OUTPUT SECTOR NUMBER

SECLOOP LD A, (SECTOR) LD C,SECPORT OUT (C) ,A ;SELECT SECTOR ADDRESS

;OUTPUT THE CURRENT TEST STATUS ON THE SCREEN

LD HL,WRITSEC ;PASS WRITSEC ADDRESS CALL CONVERT ;CONVERt HEX NUMBER TO LD A, (TRACK) ; DECIMAL ASCII LD HL,WRITTRK ;PASS WRITTRK ADDRESS CALL CONVERT LD A, (PASS) LD HL,WRITPAS CALL CONVERT 61 9 '

CALL PNEXT ;CALL CRT WRITE ROUTINE

DEFM 'TESTING TRACK # I WRITTRK DEFS 3 DEFM SECTOR # I WRITSEC DEFS 3 DEFM ***** PASS WRITPAS DEFS 3 DEFM ****' DEFB cR DEFB EOT

;INITIALIZE REGISTER E WITH TEST DATA OOHEX ., LD E,OO

;THERE ARE 8 TRACKS PER DISK, 256 SECTORS PER TRACK AND ;128 BYTES PER SECTOR, THAT MAKES 128 X 256 x 8 = 256 K ;BYTES PER RAMDISK. DUE tO THE SPECIAL HARDWARE DESIGN, .;REGISTER B MUST ALWAYS HOLD THE BYTE ADDRESS. LOAD ;REGISTER B WITH BYTE ADDRESS .,

BYTLOOP LD B,l28

;START OUTPUT TEST DATA .,

LD A,E LD C,DATPORT WRLOOP OUT (c) ,A ;OUTPUT DATA INTO RAM INC A ;NEW DATA DEC B ;NEXT BYTE LOCATION JR NZ,WRLOOP ;IF NOT END OF SECTOR ; CONTINUE ..... CALL KBDST ;CHECK FOR KEYBOARD INPUT OR A ;CHECK IF THERE IS INPUT JR Z,CHKPASS ;IF NO INPUT, START CHECK PASS PUSH HL ;SAVE HL REGISTER PAIR CALL KBDRD ;INPUT KEYBOARD DATA AND 07FH ;ZERO 7TH BIT CP 'C'-64 ;sEE IF INPUT = CONTROL-C JP Z,ENDTEST ;IF CONTROL-C, EXIT ., ;FINISHED SECTOR LOAD, START CHECK PASS .r

CHKPASS LD B, 128 62

LD A,E ;REG. A HAS THE S/B DATA RDLOOP IN H, (C) ;INPUT DATA FROM RAM CP H ;CHECR IF READ BACK DATA ; IS CORRECT ? JP NZ,ERROR ;IF INCORRECT, GO TO ERROR ROUTINE. INC A ;NEW S/B DaTA DEC B ;NEXT BYTE LOCATION JR NZ,RDLOOP ;CONTINUE CHECK PASS INC E ;CHANGE BASE DATA JR NZ,BYTLOOP ;IF NOT END OF SECTOR TEST, ; CONTINUE. LD A, (SECTOR) INC A ;INCREMENT SECTOR NUMBER LD (SECTOR) ,A ;STORE NEXT SECTOR ADDRESS OR A ;CHECK FOR END OF TRACK JR Z,NXTTRK ;If END,GO TEST NEXT TRACK LD (SECTOR) ,A ;OTHERWISE CONTINUE TEST JP SECLOOP SAME TRACK, NEXT SECTOR

NXTTRR LD A, (TRACK) ;CHECK TRACK NUMBER INC A ;IF ALL 8 TRACKS ARE CP 8 TESTED, THEN REPEAT JR Z,NXTDSK ENTIRE TEST. LD (TRACK) ,A ;OTHERWISE CONTINUE ON JP TRI

NXTDSR LD A,OO LD (TRAcK) ,A ;START ON TRACK 0 AGAIN JP DSI

;THIS SUBROUTINE CONVERTS THE HEX NUMBER IN REGISTER A TO ;DECIMAL ASCII NUMBERS AND WRITES THE RESULT INTO THE ;MEMORY WHOSE ADDRESS IS PASSED IN REGISTER PAIR HL.

CONVERT PUSh BC LD B,O ;INITIALIZE REG. B LD (HL), 20H ;FILL IN WITH BLANK INC HL LD (HL),20H ;FILL IN WITH BLANK INC HL ;HL REG. PAIR PoiNT TO THE LD (HL),20H BOTTOM OF THE RESERVED DATA SPACE LOOP! SUB 10 ;START CONVERTION JR C,ENDl INC B ;REG. B HAS THE QUOTIENT JR LOOP! ENOl ADD A,lO ;REG. A HAS THE REMAINDER ADD A, 30H ;ADD 30H TO CHANGE HEX TO LD (HL),A ASCII DEC HL 63

LD A,B OR A ;CHECK FOR THE END OF CONVERTION JR Z,ENDCNVT ;IF QUOTIENT = 0, END CONVERT ION LD B,O ;OTHERWISE COMPUTE FOR JR LOOPl NEXT DIGIT ENDCNVT POP BC RET

; ;THIS SUBROUTINE CONVERTS HEX DATA TO ASCII DATA FOR ;DISPLAY. THE DATA IS PASSED INTO SUBROUTINE BY REGISTER A ;,AFTER CONVERTION THE ASCII DATA IS WRITTEN INTO THE ;RESErVED SPACE WHOSE ADDRESS IS PASSED BY HL REGISTER ;PAIR.

ASCII PUSH BC ;SAVE REG. BC ;REG. C IS NIBLE COUNTER INC HL ;HL POINT TO THE BOTTOM ;OF RESERVED DATA SPACE LD c,o ;SET NIBLE COUNTER TO 0 LD B,A ;BACK UP DATA IN REG. B CNVT AND OOOOllllB ;CONVERT 4 BITS AT A TIME CP 10 ;CHECK IF REG. A HAS A ; NUMBER JR NC,LETTER ;IF NO CARRY, IT HAS A ; LETTER ADD A,30H ;ADD 30H TO CONVERT NUMBER JR NIBLE ;GO CONVERT NEXT 4 BITS LETTER ADD A, 37H ;ADD 37H TO CONVERT LETTER NIBLE LD (HL) ,A ;STORE THE ASCII RESULT DEC HL ;HL POINT TO NEXT SPACE BIT o,c ;CHECK COUNTER rEGISTER JR NZ,NOMORE ;CHECK FOR END OF CONVERT LD A,B ;IF NOT END, CONTINUE NEXT SRL A NIBLE. SRL A SRL A SRL A LD C, 1 JR CNVT NO MORE POP BC RET

ERROR LD (SB) ,A ;TEMPERORY SAVE THE DATA LD A,H LD (BADDAT), A LD A, (SB) ;PASS DATA IN REG. A FOR CONVERTION LD HL,SB ;PASS SHOULD BE DATA ADDRESS 64

CALL ASCII ;CONVERT HEX DATA TO ASCII ; DATA LD A, {TRACK) LD HL,BADTRK CALL CONVERT ;CONVERT TRACK TO DECIMAL LD A, (SECTOR) DATA LD HL,BADSEC CALL CONVERT ;CONVERT SECTOR TO DECIMAL LD A,B DATA AND OlllllllB ;ONLY 7 LSB ARE REQUIRED LD HL,BADBYT CALL CONVERT ;CONVERT BYTE TO DECIMALL LD A, (BADDAT) ASCII LD HL,BADDAT ;PASS BAD DATA ADDRESS CALl ASCII ;CONVERT BAD DATA TO ASCII ; FOR DISPLAY CALL PNEXT ;OUTPUT ERROR MESSAGE

DEFB CR DEFB LF DEFB LF DEFM 'RAM TEST FAILED ..••. ' DEFB CR DEFB LF DEFB LF DEFM 'FAILED TRACK # ' BADTRK DEFS 3 DEFM SECTOR # ' BADSEC DEFS 3 DEFM BYTE # ' BADBYT DEFS 3 DEFB CR DEFB LF DEFB LF DEFM 'FAILED DATA : ' BADDAT DEFS 2 DEFM SHOULD BE : ' SB DEFS 2 DEFB CR DEFB LF DEFB EOT

ENDTEST RST 00

END 65

APPENDIX D : RAM-DISK FORMATING PROGRAM LISTING

,•*------* ,•* * •*, THIS PROGRAM FORMATS THE RAM DISK .•.• * ,•* * •*, Chung T. Ho --JUNE,19,1983-- * ,•* * •*------*, ;THE RAM-DISK IS FORMATED BY WRITING 'E5' HEX INTO THE ;FIRST 2048 BYTES OF TRACK ZERO.

ORG 00100H

LD A,OFH OUT {85H) ,A OUT {87H) ,A ;SELECT PIO PORT A AND B AS OUTPUT PORTS LD A,O OUT (84H), A ;SELECT TRACK 0

LD D, 0 LOOP1 LD C,86H OUT (C) ,D ;SELECT SECTOR # LD B, 128

LD A,OE5H LD C,80H LOOP2 OUT (C) ,A ;LOAD FIRST 16 PAGES WITH ; 'E5' HEX DJNZ LOOP2 ;LOOP UNTIL FINISHED 128 BYTES INC D BIT 4,0 JP Z,LOOP1 ;LOOP UNTIL FINISHED 16 ; PAGES RET

END 66

APPENDIX E CUSTOM BASIC I/0 MOVE PROGRAM LISTING ;*------* ,•* * •*, THIS PROGRAM MOVES THE CUSTOM BIOS.COM PROGRAM * ,•* TO THE ADDRESS OE800H AND INITIALIZE THE RAM * •*, DISK PIO CONTROLLER To BE OUTPUT PORTS * ,•* * •*, Chung T. Ho --JUNE,l9,1983-- * ,•* * ;*------* ORG lOOH ., ;DEFINE TRACK AND SECTOR PORTS STATUS PORT ADDRESSES

TRKSTAT EQU 00085H ;TRACK STATUS PORT ADDRESS SECSTAT EQU 00087H ;SECTOR PORT ADDRESS ., ;OUTPUT COMMAND WORD OF HEX TO THE PIO STATUS PORT WILL ; INITIALIZE THE PIO AS OUTPUT PORTS .,

LD A,OFH ;LOAD COMMAND WORD OUT (TRRSTAT),A ;OUTPUT TO TRACK STATUS OUT (SECSTAT) ,A ;OUTPUT TO SECTOR STATUS

;THE CUSTOM BIOS PROGRAM STARTING LOCATION IS 200 HEX AND ; THE DESTINATION LOCATIOn START IN OE800 HEX, THE BIOS PROGRAM LENGTH IS 2 K BYTES • .,

LD HL,00200H ;LOAD BEGIN ADDRESS LD DE,OE800H ;LOAD DESTINATION ADDRESS LD BC,0800H ;MOVE 8 PAGES OF 256 BYTES LDIR ;REPEAT UNTIL FINISHED

RST 00 ;BACK TO BDOS

END 67

APPENDIX F RAM DISK CUSTOM BIOS DRIVE A PROGRAM LISTING

•********************************************************, ,•* * ,~* CUSTOM BIOS FOR CP/M VERSION 2.2 * •*, * •*, Russell Smith 7-0ctober-1980 * ,•* * •*, -- MODIFIED FOR RAM DISK ON DRIVE A * •*, * ,•* Chung T. Ho 26-JUNE-1983 * ,•* * •********************************************************, ., MSIZE EQU 60 ;MEMORY CAPACITY IN KBYTES MONITR EQU OFOOOH ;BASE OF SYSTEM MONITOR ., ., CP/M REFERENCE CONSTANTS

BIAS EQU .RES.((MSIZE-20)*1024)-200H CCP EQU .RES.3400H+BIAS BOOS EQU .RES.CCP+806H CBIOS EQU .RES.CCP+1600H ., ., ORG CBIOS ., JP BOOT ;STANDARD jUMP TABLE TO BVECTR: JP WBOOT ;THE SUBROUTINES OF CBIOS SVECTR: JP CONST IVECTR: JP CON IN OVECTR: JP CONOUT JP CONOUT ;LIST DEVICE VECTOR JP CONOUT ;PUNCH DEVICE VECTOR JP CON IN ;READER DEVICE VECTOR JP HOME JP SELECT JP SEEK JP SETSEC JP SETPTR JP READ JP WRITE JP CONST ;LIST DEVICE sTATUS VECTOR JP TRANS ., ., ., BOOT: XOR A LD ( 0003H) , A ;RESET IOBYTE TO ZEROS LD HL,SIGNON CALL PMSG ;PRINT SIGNON MESSAGE 68

JR GOCPM ., ., WBOOT: LD SP,STACk LD C, 1 CALL SELECT ;SELECT UNIT 1 OF FLOPPY ; DRIVE CALL HOME ;SEEK TRACK ZERO LD HL,.RES.3400H+BIAS LD BC,OD02H CALL RDLoOP ;READ EVEN SECTORS ON LD HL, .RES.3480H+BIAS ; TRACK 0 LD BC,OC03H CALL RDLOOP ;READ ODD SECTORS ON LD C,l TRACK 0 CALL SEEK ;SeEK TO TRACK 1 JR NZ,BOMB LD HL,.RES.4080H+BIAS LD BC,OAOlH CALL RDLOOP ; READ ODD SECTORS ON TRK 1 LD HL,.RES.4100H+BIAS LD BC,0902H CALL RDLOOP ;READ EVEN SECTOR ON TRK 1 GOCPM: LD A,OC3H ;STORE JUMP VECTORS IN RAM LD (OOH),A LD HL,CBIOS+3 ;JUMP TO CBIOS WARM BOOT LD (OlH), HL ; AT 00 HEX LD (05H),A LD HL,BDOS ;JUMP TO BOOS GOES AT 05H LD ( 06H), HL LD (38H),A LD HL,MONITR ;JUMP TO MONTR GOES AT 38H LD (39H), HL LD BC,0080H CALL SETPTR ;MAkE DISK BUFFER=0080H LD C,O JP CCP ., ., RDLOOP: LD ( POINTR) , HL ;STORE ADDR. PASSED IN HL LD A,C LD (SECTOR) ,A ;STORE SECT# PASSED IN C PUSH HL PUSH BC cALL READ ;READ THE SPECIFIED SECTOR POP BC POP HL JR NZ,BOMB INC H ;BUMP LOAD ADDRESS BY 256 INC c INC c ;BUMP SECTOR# BY 2 DjNZ RDLOOP RET 69

., ., BOMB: LD HL,DEAD CALL PMSG LOOP: JP LOOP

DEAD: DEFB CR DEFB LF DEFM 'cannot boot CP/M $' ., .r ., CONST: JP MONITR+6 ;MONITOR CONSOLE STATUS ROUTINE

CONIN: CALL MONITR+9 ;MONITOR CONSOLE INPUT AND 7FH ;ZERO OUT BIT 7 RET ., CONOUT: LD A,C JP MONITR+12 ;MONITOR CONSOLE OUTPUT ROUTINE ., ., .r ,•******************************************************** ,•* * •*, DISK I/0 SUBROUTINES FOR CP/M CBIOS * •*, * •********************************************************, .r ., SECTOR TRANSLATE TABLE FOR STANDARD 1 IN 6 INTERLEAVE FACTOR ., SECTAB: DEFB 1 DEFB 7 DEFB 13 DEFB 19 DEFB 25 DEFB 5 DEFB 11 DEFB 17 DEFB 23 DEFB 3 DEFB 9 DEFB 15 DEFB 21 DEFB 2 DEFB 8 DEFB 14 DEFB 20 70

DEFB 26 DEFB 6 DEFB 12 DEFB 18 DEFB 24 DEFB 4 DEFB 10 DEFB 16 DEFB 22 ., ; DISK PARAMETER BLOCK FOR STANDARD 8" FLOPPY ., DPBLK: DEFW 26 ;SECTORS PER TRACK DEFB 3 ;BLOCK SHIFT CONST. DEFB 7 ;BLOCK MASK CONST. DEFB 0 ;EXTENT MASK CONST. DEFW 242 ;MAX BLOCK# DEFW 63 ;MAX DIRECTORY ENTRY# DEFB 11000000B ;ALLOCATION MASK MSB DEFB OOOOOOOOB ; ' ' LSB DEFW 16 ;CHECK SIZE DEFW 2 ;RESERVED TRACKS ., ; DISK PARaMETER BLOCK FOR RAM DISK ., RMBLK: DEFW 256 ;SECTORS PER TRACK DEFB 3 ;BLOCK SHIFT CONST. DEFB 7 ;BLOCK MASK CONST. DEFB 0 ;EXTENT MASK CONST. DEFW 255 ;MAX BLOCK NUMBER. DEFW 63 ;MAX DIRECTORY ENTRY DEFB 11000000B ;ALLOCATION MASK MSB DEFB OOOOOOOOB ;" " LSB DEFW 16 ;CHECK SIZE DEFW 0 ;RESERVED TRACKS ., ; DISK PARAMETER HEADER FOR RAM DISK ., DPHTAB: DEFW OOOOH ;DPH FOR RAM DISK DEFW OOOOH DEFW OOOOH DEFW OOOOH DEFW DIRBUF DEFW RMBLK DEFW CHK4 DEFW ALL4 ,. ; DISK PARAMETER HEADERS FOR A 4 DISK SYSTEM ., DEFW SECTAB ;DPH FOR UNIT 1 DEFW OOOOH 71

DEFW OOOOH DEFW OOOOH DEFW DIRBUF DEFW DPBLK DEFW CHKO DEFW ALLO

DEFW SECTAB ~DPH FOR UNIT 2 DEFW OOOOH DEFW OOOOH DEFW OOOOH DEFW DIRBUF DEFW DPBLK DEFW CHKl DEFW ALLl

DEFW SECTAB ;DPH FOR UNIT 3 DEFW OOOOH DEFW OOOOH DEFW OOOOH DEFW DIRBUF DEFW DPBLK DEFW CHK2 DEFW ALL2

DEFW SECTAB ;dPH FOR UNIT 4 DEFW OOOOH DEFW OOOOH DEFW OOOOH DEFW DIRBUF DEFW DPBLK DEFW CHK3 DEFW ALL3 ., ., SETSEC: LD A,C LD (SECTOR) ,A ;STORE SECTOR NUMBER pASS- RET ; ED VIA BC .,

TRANS: EX DE,HL LD A, (UNIT) CP 0 ~CHECK FOR RAM DISK JR NZ,TRANSLA ;IF NOT RAM DISK, GO DO ., TRANSLATION PUSH BC ;IF RAM DISK, MOVE BC INTO HL REG. PAIR AND RETURN POP HL WITHOUT TRANSLATION RET

TRANSLA ADD HL,BC ;ADD TRANSLaTION TABLE LD L, (HL) ADDRESS PASSED IN DE TO SECTOR # IN BC REG. 72

LD H,O ;LOOKUP PHYSICAL SECTOR RET NUMBER AND RETURN IT IN HL REG. PAIR ,.

SETPTR: LD ( POINTR) , BC ;STORE DATA POINTER PASSED RET ; VIA BC ., ., SELECT: LD HL,O ;PREP TO CHECK FOR MAX LD A,C DriVE UNIT # CP 5 RET NC ;RETURN WITH HL=O IF C > 4 LD {UNIT), A ;STORE C AS NEW DRIVE UNIT LD L,A NUMBER ADD HL,HL ADD HL,HL ADD HL,HL ADD HL,HL ;MULTIPLY UNIT# BY 16 LD DE,DPHTAB ADD HL,DE ;ADD START ADDRESS OF DHP PUSH HL BLOCK CP 0 ;CHECK FOR RAM DISK JR Z,SELRAM ;IF RAMDISK, NO CHANGE DEC A ;OTHERWISE DECREMENT A SELRAM LD C,A ;LOAD C WITH DISK DRIVE # LD B,O ;LOAD B WITH SEEK SPEED CALL MONITR+27 ;CALL SELECT ROUTINE IN POP HL ; MONITOR RET z ;EXIT IF SELECTED OK LD c, 1 CALL REPORT JR NZ,SEL2 ;JUMP IF COMMAND ABORTED LD A, {UNIT) ;ElSE TRY TO SELECT THE LD C,A DRIVE AGAIN JR SELECT

SEL2: LD HL,O ;DISABLE FURTHER BIOS RET CALLS BY INDICATING ., SELECT ERRoR TO BOOS

; HOME: XOR A LD {TRACK) ,A OUT (84H), A LD A, (UNIT) ;CHECK FOR RAM DISK CP 0 ;IF NOT RAM DISK, CALL CALL NZ,MONITR+30 MONITOR HOME ROUTINE ; FOR FLOPPY RET z ;RETURN IF ALL WENT WELL LD C,2 CALL REPORT 73

JR Z,HOME ;RE-TRY HOME IF ERROR RET INDICATED ., ., SEEK: LD A,C ;GET TRACK # FROM C LD {TRACK) ,A OUT {84H), A LD A, {UNIT) CP 0 ;CHECK FOR RAM DISK CALL NZ,MONITR+33 ;CALL SEEK ROUTINE RET z ;EXIT IF NO ERRORS LD C,2 INDICATED CALL REPORT ;REPORT SEEK ERROR TO CONSOLE RET NZ ;RETURN PERMANENT ERROR UNLESS RE-TRY REQUEST LD A, {TRACK) IS INDICATED LD C,A JR SEEK

READ: LD A, {UNIT) CP 0 ;CHECK FOR RAM DISK JR NZ,READF ;BRANCH IF FLOPPY

LD A, (TRACK) OUT (84H) ,A ;OUTPUT TRACK TO RAM DISK LD A, (SECTOR) OUT (86H), A ;OUTPUT SECTOR LD HL, {POINTR) LD B, 128 ;128 BYTE SEcTOR LD C,80H ;DATA PORT INIR ;TRANSFER DATA SUB A ;A SUCCESSFUL READ??? RET

READF: LD HL, (POINTR) LD A, (SECTOR) LD C,A CaLL MONITR+36 ;CALL READ ROUTINE RET z ;RETURN IF NO ERRORS LD C,3 ;INDICATE READ ERROR TO HANDLER CALL REPORT ;REPORT DISK ERROR TO CONSOLE JR Z,READF ;RE-TRY READ IF INDICATED RET ., ,. ., WRITE: LD A,(UNIT) CP 0 ;CHECK FOR RAM DISK 74

JR NZ,WRITEF ;BRANCH IF FLOPPY

LD A, (TRACK) OUT (84H), A ;OUPUT TRACK TO RAM DISK LD A, (SECTOR) OUT (86H) ,A ;OUPUT SECTOR LD HL, (POINTR) LD B, 128 LD C,80H ;DATA PORT NXTBYT LD A, (HL) OUT (C) ,A ;OUTPUT DATA TO RAM DISK DEC B ;NEXT RAM DISK ADDRESS JR Z,XYZ ;EXIT IF END OF SECTOR INC HL ;OTHERWISE, NEXT BYTE JR NXTBYT ;CONTINUE OUTPUT XYZ SUB A ;ASSUME A SUCCESS? RET

WRITEF: LD HL, (POINTR) LD A, {SECTOR) LD C,A CALL MONITR+39 ;CALL WRITE ROUTINE RET z ;RETURN IF NO ERRORS LD C,4 ;INDICATE WRITE ERROR TO ; HANDLER CALL REPORT ;REPORT DISK ERROR TO CONSOLE JR Z,WRITEF ;RE-TRY WRITE IF INTIICATED RET ;ELSE RETURN PERMANENT ., ERROR ., REPORT: LD (FLAGS) ,A ;STORE 1771 I/0 STATUS LD A,C FLAGS LD (CLASS) ,A ;STORE COMMAND CLASS OF LD HL,DSKMSG ERROR CALL PMSG ;PRINT OUT START OF DEC HL MESSAGE LD A, (CLASS) LD B,A REP!: CALL SKIP ;SKIP TO NEXT '$' IN DJNZ REPl STRING @ HL CALL PMSG ;PRINT STRING NOW POINTED LD HL,ERRMSG ; TO BY HL CALL PMSG ;PRINT 'error' AFTER TYPE LD A, (FLAGS) RLA ;TEST FIRST FOR DRIVE-NOT JR C,REP8 READY ERROR AND JUMP IF THAT IS THE PROBLEM LD E,A ;GET REMAINING 1771 ERROR LD HL,RWERRS BITS INTO E LD A,{CLASS) CP 3 ;DETERMINE IF SELECT/SEEK JR NC,REP2 OF R/W ERROR 75

LD HL,SKERRS ;POINT HL TO PROPER SET OF REP2: lD B,S MESSAGES RES O,D REP4: SLA E ;SHIFT OUT A 1771 STATUS JR NC,REPS ; REGISTER BIT LD C , ' , ' BIT O,D CALL NZ,OVECTR ;PRINT COMMA BeTWEEN STRINGS IF D = 1 CALL PMSG ;THEN PRINT ERROR MESSAGE @ HL SET 0 ,D ;FLAG THAT A STRING WAS JR REP6 ; PriNTED

REPS: CALL SKIP ;SKIP TO NEXT STRING @ HL RES O,D ;FLAG THAT A STRING WAS ; SKIPPED REP6: DJNZ REP4 ;REPEAT FOR ALL 5 POSSIBLE LD HL,TSMSG ERRORS CALL PMSG ;PRINT TRACK/SECTOR# LD A, (TRACK) HEADER CALL PUT2HX ;PRINT TRACK# IN HEX LD c, 'I' CALL OVECTR LD A, (SECTOR) CAlL PUT2HX REP7: LD A, 1 OR A ;RETURN PERM ERROR RET INDICATION IN REG. A ., REPS: LD HL,RDYMSG CALL PMSG ;PRINT DISK-NOT-READY MESSAGE AND WAIT FOR CALL IVECTR CONSOLE INPUT CP 'C'-64 JR Z,REP7 XOR A ;RETURN A=O IF SOMETHING RET OTHER THAN CONTROL-C ; WAS TYPED AT THE CONSOLE ., SKIP: PUSH BC ;SAVE BC LD B,255 LD A, '$' CPIR ;SCAN MEMORY FOR '$' POP BC RET ., ., CHARACTER STRiNG OUTPUT ROUTINE. PRINTS ASCII DATA ; POINTED TO BY HL UNTIL A DOLLAR SIGN IS ENCOUNTERED

PMSG: LD A, (HL) ;HL POINTS TO ASCII STRING 76

CP '$' INC HL RET z LD C,A ;PRINT CHARACTER IF NOT CALL OVECTR ; DOLLAR SIGN JR PMSG

.r PUT2HX: PUSH AF RRA RRA RRA RRA CALL PUTNIB POP AF PUTNIB: AND 000011118 ADD A,90H DAA ADC A,40H DAA LD C,A CALL OVECTR ;PRINT A HEX-ASCII CHARAC. RET .r .,

LF EQU OAH ;LINE FEED CR EQU ODH ;CARRIAGE RETuRN

DSI

ERRMSG: DEFM 'error $'

RDYMSG: DEFM 'drive not ready -$'

RWERRS: DEFM 'write protected$' DEFM 'write fault$' DEFM 'record not found$' DEFM 'bad ere$' DEFM 'data overrun$' 77

TSMSG: DEFM trk/sect = $' SIGNON: DEFB CR DEFB LF DEFM '20k CP/M version 2.2' CRLF: DEFB CR DEFB LF . DEFB ' $' .,I UNIT: DEfS 1 TRACK: DEFS 1 SECTOR: DEFS 1 POINTR: DEFS 2 FLAGS: DEFS 1 CLASS: DEFS 1 DEFS 32 STACK: DEFS 1 ;LOCAL STACK FOR WARM BOOT ., •********************************************************, ,•* * •*, DISK I/0 BUFFERS FOR BOOS FILE HANDLER * •*, * •********************************************************, ., ., ., DIRBUF: DEFS 128 ;SCRATCH DIRECTORY BUFFER ., ALLO: DEFS 32 ;UNIT 0 ALLOCATION BUFFER CHKO: DEFS 16 ;UNIT 0 CHECK VECTOR ALL1: DEFS 32 ;UNIT 1 ALLOCATION VECTOR CHKl: DEFS 16 ;UNIT 1 CHEcK VECTOR ALL2: DEFS 32 ;UNIT 2 ALLOCATION VECTOR CHK2: DEFS 16 ;UNIT 2 CHECK VECTOR ALL3: DEFS 32 ;UNIT 3 ALLOCATION VECTOR CHK3: DEFS 16 ;UNIT 3 CHECK VECTOR ALL4: DEFS 32 ;RAM DISK ALLOCATION VECT. CHK4: DEFS 16 ;RAM DISK CHECK VECTOR ., ., END 78

APPENDIX G : RAM DISK CUSTOM BIOS DRIVE E PROGRAM LISTING

•********************************************************• •*• * •*• CUSTOM BIOS FOR CP/M VERSION 2.2 * •*, * •*• Russell Smith 7-0ctober-1980 * ,•* * •*• -- MODIFIED FOR RAM DISK ON DRIVE E : * •*, * •*, Chung T. Ho 19-JUNE-1983 * •*, * •********************************************************, ., ., MSIZE EQU 60 ;MEMORY CAPACITY IN KBYTES MONITR EQU OFOOOH ;BASE OF SYSTEM MONITOR ., CP/M REFERENCE CONSTANTS ., BIAS EQU .RES.((MSIZE-20)*1024)-200H CCP EQU .RES.3400H+BIAS BOOS EQU .RES.CCP+806H CBIOS. EQU .RES.CCP+1600H .• I

ORG CBIOS ., JP BOOT ;STANDARD JUMP TABLE TO BVECTR: JP WBOOT ;THE SUBROUTINES OF CBIOS SVECTR: JP CONST IVECTR: JP CON IN OVECTR: JP CONOUT JP CONOUT ;LIST DEVICE VECTOR JP CONOUT ;PUNCH DEVICE VECTOR JP CON IN ;READER DEVICE VECTOR JP HOME JP SELECT JP SEEK JP SETSEC JP SETPTR JP READ JP WRITE JP CONST ;LIST DEVICE STATUS VECTOR . JP TRANS .,• ., BOOT: XOR A LD (0003H),A ;RESET IOBYTE TO ZEROS LD HL,SIGNON 79

CALL PMSG ;PRINT SIGNON MESSAGE JR GOCPM ., WBOOT: LD SP,STACK LD C,O CALL SELECT ;SELECT UNIT 0 CALL HOME ;SEEK TRACK ZERO LD HL,.RES.3400H+BIAS LD BC,OD02H CALL RDLOOP ;READ EVEN SECTORS ON LD HL,.RES.3480H+BIAS TRACK 0 LD BC,OC03H CALL RDLOOP ;READ ODD SECTORS ON LD C,1 ; TRACK 0 CALL SEEK ;SEEK TO TRACK 1 JR NZ,BOMB LD HL,.RES.4080H+BIAS LD BC,OA01H CALL RDLOOP ; READ ODD SECTORS ON TRK 1 LD HL,.RES.4100H+BIAS LD BC,0902H CALL RDLOOP ;READ EVEN SECTOR ON TRK 1 GOCPM: LD A,OC3H ;STORE JUMP VECTORS IN RAM LD (OOH) ,A LD HL,CBIOS+3 ;JUMP TO CBIOS WARM BOOT LD ( 01H), HL AT 00 HEX LD ( 05H), A LD HL,BDOS ;JUMP TO BOOS GOES AT 05H LD (06H) ,HL LD (38H),A LD HL,MONITR ;JUMP TO MONTR GOES AT 38H LD ( 39H), HL LD BC,0080H CALL SETPTR ;MAKE DISK BUFFER=0080H LD C,O JP CCP ., RDLOOP: LD (POINTR) ,HL ;STORE ADDR. PASSED IN HL LD A,C LD (SECTOR) ,A ;STORE SECT# PASSED IN C PUSH HL PUSH BC CALL READ ;READ THE SPECIFIED SECTOR POP BC POP HL JR NZ,BOMB INC H ;BUMP LOAD ADDRESS BY 256 INC c INC c ;BUMP SECTOR# BY 2 DJNZ RDLOOP RET 80

., ., BOMB: LD HL,DEAD CALL PMSG LOOP: JP LOOP

DEAD: DEFB CR DEFB LF DEFM 'cannot boot CP/M $' ., .,

CONST: JP MONITR+6 ;MONITOR CONSOLE STATUS ,. ROUTINE ., CONIN: CALL MONITR+9 ;MONITOR CONSOLE INPUT AND 7FH ;ZERO OUT BIT 7 RET ., CONOUT: LD A,C JP MONITR+12 ;MONITOR CONSOLE OUTPUT ROUTINE ., ., •********************************************************, ,•* * ,•* DISK I/0 SUBROUTINES FOR CP/M CBIOS * ,•* * •********************************************************, ., ., ,. SECTOR TRANSLATE TABLE FOR STANDARD 1 IN 6 INTERLEAVE FACTOR ., SECTAB: DEFB 1 DEFB 7 DEFB 13 DEFB 19 DEFB 25 DEFB 5 DEFB 11 DEFB 17 DEFB 23 DEFB 3 DEFB 9 DEFB 15 DEFB 21 DEFB 2 DEFB 8 DEFB 14 DEFB 20 81

DEFB 26 DEFB 6 DEFB 12 DEFB 18 DEFB 24 DEFB 4 DEFB 10 DEFB 16 DEFB 22 ., ; DISK PARAMETER BLOCK FOR STANDARD 8" FLOPPY ., DPBLK: DEFW 26 ;SECTORS PER TRACK DEFB 3 ;BLOCK SHIFT CONST. DEFB 7 ;BLOCK MASK CONST. DEFB 0 ;EXTENT MASK CONST. DEFW 242 ;MAX BLOCK# DEFW 63 ;MAX DIRECTORY ENTRY# DEFB 11000000B ;ALLOCATION MASK MSB DEFB OOOOOOOOB ; ' ' LSB DEFW 16 ;CHECK SIZE DEFW 2 ;RESERVED TRACKS ., ., DISK PARAMETER BLOCK FOR RAM DISK ., RMBLK: DEFW 256 ;SECTORS PER TRACK DEFB 3 ;BLOCK SHIFT CONST. DEFB 7 ;BLOCK MASK CONST. DEFB 0 ;EXTENT MASK CONST. DEFW 255 ;MAX BLOCK NUMBER. DEFW 63 ;MAX DIRECTORY ENTRY DEFB 11000000B ;ALLOCATION MASK MSB DEFB OOOOOOOOB ; " " LSB DEFW 16 ;CHECK SIZE DEFW 0 ;RESERVED TRACKS ., ; DISK PARAMETER HEADERS FOR A 4 DISK SYSTEM ., DPHTAB: DEFW SECTAB ;DPH FOR UNIT 0 DEFW OOOOH DEFW OOOOH DEFW OOOOH DEFW DIRBUF DEFW DPBLK DEFW CHKO DEFW ALLO

DEFW SECTAB ;DPH FOR UNIT 1 DEFW OOOOH DEFW OOOOH DEFW OOOOH DEFW DIRBUF 82 i' .

DEFW DPBLK DEFW CHKl DEFW ALLl

DEFW SECTAB ;DPH FOR UNIT 2 DEFW OOOOH DEFW OOOOH DEFW OOOOH DEFW DIRBUF DEFW DPBLK DEFW CHK2 DEFW ALL2

DEFW SECTAB ;DPH FOR UNIT 3 DEFW OOOOH DEFW OOOOH DEFW OOOOH DEFW DIRBUF DEFW DPBLK DEFW CHK3 DEFW ALL3

DISK PARAMETER HEADER FOR RAM DISK ., DEFW OOOOH ;DPH FOR RAM DISK DEFW OOOOH DEFW OOOOH DEFW OOOOH DEFW DIRBUF DEFW RMBLK DEFW CHK4 DEFW ALL4 ; ., SETSEC: LD A,C LD (SECTOR) ,A ;STORE SECTOR NUMBER RET PASSED VIA BC

TRANS: EX DE,HL LD A, (UNIT) CP 4 ;CHECK FOR RAM DISK JR NZ,TRANSLA ;IF NOT RAM DISK, GO DO TRANSLATION PUSH BC ;IF RAM DISK, MOVE BC INTO POP HL HL REG. PAIR AND RETURN RET WITHOUT TRANSLATION

TRANSLA ADD HL,BC ;ADD TRANSLATION TABLE LD L, (HL) ADDRESS PASSED IN DE TO ; SECTOR # IN BC REG. 83

LD H, 0 ;LOOKUP PHYSICAL SECTOR RET NUMBER AND RETURN IT ., IN HL REG. PAIR ., SETPTR: LD ( POINTR) , BC ;STORE DATA POINTER PASSED RET ; VIA BC ,. ., SELECT: LD HL,O ;PREP TO CHECK FOR MAX LD A,C ; DRIVE UNIT # CP 5 RET NC ;RETURN WITH HL=O IF C > 4 LD (UNIT),A ;STORE C AS NEW DRIVE UNIT LD L,A NUMBER ADD HL,HL ADD HL,HL ADD HL,HL ADD HL,HL ;MULTIPLY UNIT# BY 16 LD DE,DPHTAB ADD HL,DE ;ADD START ADDRESS OF DHP PUSH HL BLOCK LD C,A ;LOAD C WITH DISK DRIVE # LD B,O ;LOAD B WITH SEEK SPEED CALL MONITR+27 ;CALL SELECT ROUTINE IN POP HL MONITOR RET z ;EXIT IF SELECTED OK LD c, 1 CALL REPORT JR NZ,SEL2 ;JUMP IF COMMAND ABORTED LD A, (UNIT) ;ELSE TRY TO SELECT THE LD C,A ; DRIVE AGAIN JR SELECT

SEL2: LD HL,O ;DISABLE FURTHER BIOS RET CALLS BY INDICATING ., SELECT ERROR TO BOOS ; ; HOME: XOR A LD (TRACK) ,A OUT (84H), A LD A, (UNIT) ;CHECK FOR RAM DISK CP 4 CALL NZ,MONITR+30 ;CALL MONITOR HOME ROUTINE FOR FLOPPY RET z ;RETURN IF ALL WENT WELL LD C,2 CALL REPORT JR Z,HOME ;RE-TRY HOME IF ERROR RET INDICATED ., ., 84

SEEK: LD A,C ;GET TRACK # FROM C LD (TRACK) ,A OUT (84H) ,A LD A,(UNIT) CP 4 ;CHECK FOR RAM DISK CALL NZ,MONITR+33 ;CALL SEEK ROUTINE RET z ;EXIT IF NO ERRORS LD C,2 INDICATED CALL REPORT ;REPORT SEEK ERROR TO CONSOLE RET NZ ;RETURN PERMANENT ERROR LD A, (TRACK) UNLESS RE-TRY REQUEST LD C,A IS INDICATED JR SEEK ., .,

READ: LD A, (UNIT) CP 4 ;CHECK FOR RAM DISK JR NZ,READF ;BRANCH IF FLOPPY

LD A, (TRACK) OUT (84H), A ;OUTPUT TRACK TO RAM DISK LD A, (SECTOR) OUT (86H) ,A ;OUTPUT SECTOR LD HL, (POINTR) LD B, 128 ;128 BYTE SECTOR LD C,80H ;DATA PORT INIR ;TRANSFER DATA SUB A ;A SUCCESSFUL READ??? RET

READF: LD HL, (POINTR) LD A, (SECTOR) LD C,A CALL MONITR+36 ;CALL READ MONITOR ROUTINE RET z ;RETURN IF NO ERRORS LD C,3 ;INDICATE READ ERROR TO HANDLER CALL REPORT ;REPORT DISK ERROR TO CONSOLE JR Z,READF ;RE-TRY READ IF INDICATED RET ., ., WRITE: LD A, (UNIT) CP 4 ;CHECK FOR RAM DISK JR NZ,WRITEF ;BRANCH IF FLOPPY

LD A, (TRACK) OUT (84H), A ;OUPUT TRACK TO RAM DISK LD A, (SECTOR) 85

OUT (86H) ,A ;OUPUT SECTOR LD HL, (POINTR) LD B, 128 LD C,80H ;DATA PORT NXTBYT LD A, (HL) OUT (C) ,A ;OUTPUT DATA TO RAM DISK DEC B ;NEXT RAM DISK ADDRESS JR Z,XYZ ;EXIT IF END OF SECTOR INC HL ;OTHERWISE, NEXT BYTE JR NXTBYT ;CONTINUE OUTPUT XYZ SUB A ;ASSUME A SUCCESS? RET

WRITEF: LD HL, (POINTR) LD A,(SECTOR) LD C,A CALL MONITR+39 ;CALL WRITE ROUTINE RET z ;RETURN IF NO ERRORS LD C,4 ;INDICATE WRITE ERROR TO HANDLER CALL REPORT ;REPORT DISK ERROR TO CONSOLE JR Z,WRITEF ;RE-TRY WRITE IF INDICATED RET ;ELSE RETURN PERMANENT ., ; ERROR ., REPORT: LD (FLAGS) ,A ;STORE 1771 I/0 STATUS LD A,C FLAGS LD (CLASS),A ;STORE COMMAND CLASS OF LD HL,DSKMSG ERROR CALL PMSG ;PRINT OUT START OF DEC HL MESSAGE LD A, (CLASS) LD B,A REP1: CALL SKIP ;SKIP TO NEXT '$' IN DJNZ REP1 STRING @ HL CALL PMSG ;PRINT STRING NOW POINTED LD HL,ERRMSG ; TO BY HL CALL PMSG ;PRINT 'error' AFTER TYPE LD A, {FLAGS) RLA ;TEST FIRST FOR DRIVE-NOT READY ERROR AND JUMP IF JR C,REP8 THAT IS THE PROBLEM LD E,A ;GET REMAINING 1771 ERROR LD HL,RWERRS BITS INTO E LD A, (CLASS) CP 3 ;DETERMINE IF SELECT/SEEK JR NC,REP2 OF R/W ERROR LD HL,SKERRS ;POINT HL TO PROPER SET OF REP2: LD B,5 MESSAGES RES 0 ,D REP4: SLA E ;SHIFT OUT A 1771 STATUS JR NC,REP5 REGISTER BIT 86

LD C , 1 , 1 BIT O,D CALL NZ,OVECTR ;PRINT COMMA BETWEEN STRINGS IF D = 1 CALL PMSG ;THEN PRINT ERROR MESSAGE @ HL SET 0 ,D ;FLAG THAT A STRING WAS JR REP6 PRINTED

REPS: CALL SKIP ;SKIP TO NEXT STRING @ HL RES 0,0 ;FLAG THAT A STRING WAS ; SKIPPED REP6: DJNZ REP4 ;REPEAT FOR ALL 5 POSSIBLE LD HL,TSMSG ERRORS CALL PMSG ;PRINT TRACK/SECTOR# HEADER LD A, (TRACK) CALL PUT2HX ;PRINT TRACK# IN HEX LD C, 1/1 CALL OVECTR LD A, (SECTOR) CALL PUT2HX REP7: LD A,l OR A ;RETURN PERM ERROR RET INDICATION IN A ., REP8: LD HL,RDYMSG CALL PMSG ;PRINT DISK-NOT-READY CALL IVECTR MESSAGE AND WAIT FOR CP 1 C'-64 CONSOLE INPUT JR Z,REP7 XOR A ;RETURN A=O IF SOMETHING RET ; OTHER THAN CONTROL-C ; WAS TPED AT THE CONSOLE ., SKIP: PUSH BC ;SAVE BC LD B,255 LD A, '$' CPIR ;SCAN MEMORY FOR '$ 1 POP BC RET ., ., ; CHARACTER STRING OUTPUT ROUTINE. PRINTS ASCII DATA POINTED TO BY HL UNTIL A DOLLAR SIGN IS ENCOUNTERED

PMSG: LD A, (HL) ;HL POINTS TO ASCII STRING CP '$ t INC HL RET z LD C,A ;PRINT CHARACTER IF NOT CALL OVECTR ; DOLLAR SIGN JR PMSG 87

., PUT2HX: PUSH AF RRA RRA RRA RRA CALL PUTNIB POP AF PUTNIB: AND OOOOllllB ADD A,90H DAA ADC A,40H DAA LD C,A CALL OVECTR ;PRINT A HEX-ASCII CHARAC. RET .,

LF EQU OAH ;LINE FEED CR EQU ODH ;CARRIAGE RETURN DSKMSG: DEFB CR DEFB LF DEFM 'bios $' DEFM 'select $' DEFM 'seek $' DEFM 'read $' DEFM 'write $' ERRMSG: DEFM 'error $'

SKERRS: DEFM I$! DEFM I$! DEFM 'cannot seek$' DEFM 'bad ere$' DEFM 'cannot restore$' RDYMSG: DEFM 'drive not ready -$'

RWERRS: DEFM 'write protected$' DEFM 'write fault$' DEFM 'record not found$' DEFM 'bad ere$' DEFM 'data overrun$' TSMSG: DEFM trk/sect = $' SIGNON: DEFB CR DEFB LF DEFM '20k CP/M version 2.2' CRLF: DEFB CR 88

DEFB LF DEFB '$' ., UNIT: DEFS 1 TRACK: DEFS 1 SECTOR: DEFS 1 POINTR: DEFS 2 FLAGS: DEFS 1 CLASS: DEFS 1 DEFS 32 STACK: DEFS 1 ;LOCAL STACK FOR WARM BOOT ., •********************************************************, •*, * •*, DISK I/0 BUFFERS FOR BOOS FILE HANDLER * •*, * •********************************************************, ., ., ., DIRBUF: DEFS 128 ;SCRATCH DIRECTORY BUFFER ., ALLO: DEFS 32 ;UNIT 0 ALLOCATION BUFFER CHKO: DEFS 16 ;UNIT 0 CHECK VECTOR ALL1: DEFS 32 ;UNIT 1 ALLOCATION VECTOR CHK1: DEFS 16 ;UNIT 1 CHECK VECTOR ALL2: DEFS 32 ;UNIT 2 ALLOCATION VECTOR CHK2: DEFS 16 ;UNIT 2 CHECK VECTOR ALL3: DEFS 32 ;UNIT 3 ALLOCATION VECTOR CHK3: DEFS 16 ;UNIT 3 CHECK VECTOR ALL4: DEFS 32 ;RAM DISK ALLOCATION VECT. CHK4: DEFS 16 ;RAM DISK CHECK VECTOR ., ., ., END