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Z80 Bank-Switching Scheme An101

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Z80 Bank-Switching Scheme An101 Z80 BANK-SWITCHING SCHEME AN101 1. INTRODUCTION 1. Scope: This Application Note gives a description of a circuit design allowing the classic Z80 microproces- sor to access expanded memory, beyond the 64K bytes made readily available by its 16 address lines, A0 through A15. 2. Z80 microprocessor: Though it has been over 20 years since the introduction of the Z80, this family of microprocessors still finds application in new designs. This is because the Z80 is still cost-effective for many 8-bit applications; because many users have a large library of tested code for the Z80; and because the parts are readily available from several manufacturers, easing supply concerns that apply to sole-sourced processors. 3. Applicable chips: This Application Note applies to the classic Z80 microprocessor. It can also be applied to the newer Z84C15, which comprises a Z80 CPU, a clock generator, four Z80 CTC channels, two Z80 SIO channels, DMA, chip select signals, and glue logic in a 100-pin quad flat pack. However this external bank-switching circuitry is not necessary for members of the Z80180 family, which have a built-in MMU (memory management unit) on-chip. 2. DESIGN GOALS 1. Program memory: We wanted to expand program memory space to 128K bytes for our application. We needed to support in-circuit reprogramming, so we chose the AMD 29F010 flash memory device. This +5 volt part does not require a +12 volt power supply for programming. After the flash chip is initially programmed at the factory with the bootstrap loader and the current application code, it can later be reprogrammed in the field over the RS-232 serial port. 2. RAM memory: Our communications application needed 512K bytes of RAM, mostly to support storage of long messages. The circuit diagram here shows a fully static 512K byte SRAM. (We have also used a 512K-byte pseudostatic RAM, but that is not shown here.) 3. Software interface: We wanted to ease the bank-switching software burden on the programmers. 4. Cost: We did not want to add lots of cost. We used readily available ICs. 3. SCHEMATIC DIAGRAM A circuit diagram for the bank-switching logic and the two memory ICs is shown below. 2101 OXFORD ROAD PHONE FAX INTERNET DES PLAINES, IL 60018-1919 USA 847.803.6860 847.803.6870 www.siliconengines-ltd.com Z80 BANK-SWITCHING SCHEME SCHEMATIC DIAGRAM Z80 BANK SWITCHING SCHEME MEMORY BANK CONTROL BS3 1 U3A BS7 1 U4A 3 RAMA14 3 RAMA18 U1A 2 2 D[0..7] 74HCT273 74HCT08 74HCT08 D7 18 19 BS7 8D 8Q D6 17 16 BS6 7D 7Q D5 14 15 BS5 BS2 4 U3B BS6 4 U4B 6D 6Q D4 13 12 BS4 6 ROMA16 6 RAMA17 5D 5Q D3 8 9 BS3 5 5 4D 4Q D2 7 6 BS2 74HCT08 74HCT08 3D 3Q D1 4 5 BS1 2D 2Q D0 3 2 BS0 1D 1Q BS1 10 U3C BS5 9 U4C 11 8 ROMA15 8 RAMA16 /BANK CLK 1 9 10 /RESET CLR 74HCT08 74HCT08 U2A BS0 13 U3D BS4 13 U4D 74HCT139 11 ROMA14 11 RAMA15 1 7 /MREQ G Y3 12 12 6 Y2 74HCT08 74HCT08 3 5 /RAMCE B Y1 2 4 /ROMCE A Y0 A15 A14 D[0..7] PROGRAM MEMORY RAM MEMORY 128K BYTES FLASH 512K BYTES SRAM U5A U6A 29F010 512K SRAM RAMA18 1 21 D7 A18 D7 ROMA16 2 21 D7 RAMA17 30 20 D6 A16 D7 A17 D6 ROMA15 3 20 D6 RAMA16 2 19 D5 A15 D6 A16 D5 ROMA14 29 19 D5 RAMA15 31 18 D4 A14 D5 A15 D4 A13 28 18 D4 RAMA14 3 17 D3 A13 D4 A14 D3 A12 4 17 D3 A13 28 15 D2 A12 D3 A13 D2 A11 25 15 D2 A12 4 14 D1 A11 D2 A12 D1 A10 23 14 D1 A11 25 13 D0 A10 D1 A11 D0 A9 26 13 D0 A10 23 A9 D0 A10 A8 27 A9 26 A8 A9 A7 5 A8 27 A7 A8 A6 6 A7 5 A6 A7 A5 7 A6 6 A5 A6 A4 8 A5 7 A4 A5 A3 9 A4 8 A3 A4 A2 10 A3 9 A2 A3 A1 11 A2 10 A1 A2 A0 12 A1 11 A0 A1 A0 12 A0 /ROMCE 22 CE 24 /RAMCE 22 /RD OE CE 31 /RD 24 U2B /WR PGM/WR OE 1 30 /WR 29 74HCT139 VPP NC WE VCC 15 9 G Y3 10 Y2 13 11 B Y1 14 12 A Y0 A[0..15] VCC 20 16 14 14 32 32 U1B U2C U3E U4E U5B U6B 74HCT273 74HCT139 74HCT08 74HCT08 29F010 SRAM DIP20 C1 DIP16 C2 DIP14 C3 DIP14 C4 DIP32 C5 DIP32 C6 0.1 uF 0.1 uF 0.1 uF 0.1 uF 0.1 uF 0.1 uF 8 7 7 10 16 16 AN101 PAGE 2 Z80 BANK-SWITCHING SCHEME CIRCUIT DESCRIPTION 4. CIRCUIT DESCRIPTION 1. Chip select decoder: One half of a 74HCT139 decoder serves to select ROM versus RAM. When A15 is high, RAM is selected; when A15 is low, ROM is selected. A15 is gated with /MREQ to assure that the memory chips are enabled only when the bus access is for memory, and only when the address lines are stable. 2. Bank switch latch: A 74HCT273 eight-bit latch serves as the bank switch latch. The user outputs bank switch information with a Z80 OUT instruction, which generates the output strobe /BANK. Typically a 74HCT138 or similar part (not shown in this schematic) will be used to generate this and other needed I/O strobes. At power-on, the /RESET signal resets all the bank switches to zero. 3. Eight AND gates: The latched bank switch output signals, BS0 through BS7, are connected to one input of each of eight 74HCT08 AND gates. The outputs of these gates are used to generate extra address lines for the ROM and RAM chips—three for the ROM, and five for the RAM. 4. A14 gating: Each of the eight 74HCT08 AND gates has its other input tied to Z80 address line A14. When A14 is high, the extra address lines will follow the values latched in the 74HCT273 bank switch latch. When A14 is low, the extra address lines will all be set low, regardless of the values latched in the bank switch latch. However the last values stored in the bank switch latch remain there, ready for the next access to a bank-switched memory area. 5. PAL option: The logic shown here could be embedded in a PAL to save PC board space. 5. MEMORY MAP 1. Four memory areas: Because of the way A14 is gated into the 74HCT08 inputs, the Z80 memory space has been divided into four areas, as shown below: AREA CHIP ADDRESS A15 A14 FUNCTION MEMORY SIZE 3 RAM C000-FFFF 1 1 BANK-SWITCHED RAM 31 BANKS, EACH 16K BYTES 2 RAM 8000-BFFF 1 0 BASE RAM 16K BYTES 1 ROM 4000-7FFF 0 1 BANK-SWITCHED ROM 7 BANKS, EACH 16K BYTES 0 ROM 0000-3FFF 0 0 BASE ROM 16K BYTES 2. ROM space: ROM occupies the low half of memory, from 0000 hex to 7FFF hex. 3. RAM space: RAM occupies higher memory, from 8000 hex to FFFF hex. 6. SOFTWARE NOTES 1. Area 2, Base RAM: The Base RAM area, containing addresses 8000-BFFF, will always be accessible no matter what setting has been stored in the bank-switch latch. The program stack should be assigned within this area, as well as any other temporary information that needs to be accessible from many parts of the software. 2. Area 0, Base ROM: The Base ROM area, containing addresses 0000-3FFF, will always be accessible regardless of the bank switch latch. The power-on start-up program must be stored at 0000 H, as usual for the Z80. The Z80 RESTART instruction vectors will automatically be located in Area 0. The Z80 interrupt vectors should also be stored in Area 0, so that they will always be accessible. AN101 PAGE 3 Z80 BANK-SWITCHING SCHEME SOFTWARE NOTES 3. Area 3, Bank-Switched RAM: Bank-switched RAM can now be used to provide additional RAM storage. In a communications application, for example, these banks serve as expanded buffers for incoming and outgoing messages. If the software uses these 31 banks for dedicated purposes like this, it is relatively straightforward to keep the RAM bank-switching straight. As an applications example, we are now receiving a long message, and bank switch bits [BS7..BS3] are set to [01000], meaning that we are storing data into the sixteenth 16K bank in RAM. During the receive process, SIO interrupts are continually being received. Each interrupt requires use of the program stack, and probably of some temporary RAM variables as well, all of which are in the Base RAM area. The bank-switching hardware takes care of accessing these RAM resources, without having to change the RAM bank-switch setting whenever there is an interrupt. 4. Area 1, Bank-Switched ROM: The seven switched ROM banks in Area 1 are typically used to store specific software tasks. In our systems we usually use a multi-tasking software executive that controls a number of independent jobs. Control passes from one job to another in round-robin fashion. Each ROM bank in Area 1 contains one or more jobs. Jobs typically do not overlap from one ROM bank to another. The multi-tasking executive is housed in Area 0, Common ROM, and when the executive turns on each job is succession, it also sets the ROM bank switch bits [BS2..BS0] to the appropriate values for the job being started.
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