IE1204 Digital Design

F11: Programmable Logic, VHDL for Sequential Circuits

Masoumeh (Azin) Ebrahimi ([email protected])

Elena Dubrova ([email protected]) KTH / ICT / ES This lecture

• BV pp. 98-118, 418-426, 507-519

IE1204 Digital Design, Autumn2015 2 Programmable Logic Devices

• Programmable logic devices (PLDs) were introduced in the 1970s • They are based on a structure with an AND-OR array that makes it easy to implement a sum-of-products expression

IE1204 Digital Design, Autumn2015 3 Structure of a PLD

x1 x2 xn

Input buffers and inverters

x1 x1 xn xn

P1

AND plane OR plane Pk

f1 fm

IE1204 Digital Design, Autumn2015 4 (PLA)

x1 x2 x3 • Both AND and OR arrays are programmable OR P1 plane

f1=x1x2+x1x3+x1x2x3 P2 f =x x +x x x +x x 2 1 2 1 2 3 1 3 P3

P4

AND plane f1 f2

IE1204 Digital Design, Autumn2015 5 (PAL)

x1 x2 x3 • Only the AND array is programmable

P1 f =x x x +x x x 1 1 2 3 1 2 3 f1 P2 f2=x1x2+x1x2x3

P3

f2 P4

AND plane

IE1204 Digital Design, Autumn2015 6 Combinatorial and register outputs

• In earlier PLDs there were – combinatorial outputs – register outputs (outputs with a flip-flop) • For each circuit the number of combinational and register outputs was fixed • To increase flexibility, macrocells were introduced – one can choose if an output is combinatorial or has a flip-flop

IE1204 Digital Design, Autumn2015 7 Macrocells in a PLD x1 x2 x3 Select P1 Enable f P2 1 P3 f2 f P4 1 Flip-flop

D Q A programmable can be Clock used to select the type of output

To AND plane

IE1204 Digital Design, Autumn2015 8 Programming of PLDs

IE1204 Digital Design, Autumn2015 9 Complex PLD's (CPLD)

• PLDs were quite small (PALCE 22V10 had 10 flip-flops) • To program larger functions, structures consisting of several PLD-like blocks were developed called Complex PLD (CPLD)

IE1204 Digital Design, Autumn2015 10 CPLD Structure k I / c O o l b b PAL-like PAL-like l o O

block block c / I k

Interconnection wires k I / c O o l b b PAL-like PAL-like l o O

block block c / I k

IE1204 Digital Design, Autumn2015 11 Programming of CPLDs via the JTAG interface • Modern CPLDs (and FPGAs) can be programmed by downloading circuit description (programming information) via a cable • Download usually uses a standard port called JTAG port (Joint Test Action Group)

IE1204 Digital Design, Autumn2015 12 Programming via the JTAG port

You can program the chips when they are soldered to the circuit board - using the (a) CPLD in a Quad Flat Pack (QFP) package you can select which chip you To want to program through the JTAG port

Printed circuit board

(b) JTAG programming

IE1204 Digital Design, Autumn2015 13 Field Programmable Gate Arrays

• CPLDs are based on the AND-OR array • It is difficult to make really large functions using CPLDs • FPGAs use a different concept based on logic blocks

IE1204 Digital Design, Autumn2015 14 Structure of an FPGA

IE1204 Digital Design, Autumn2015 15 Look-up-tables (LUT)

A LUT with n inputs can Programmable 0/1 realize all 1 cells combinational functions with up to n inputs. 0/1 0 The usual size of LUT 1 in an FPGA is n = 4 f 0/1 0 1

0/1 0

x2 x1 Two-input LUT

IE1204 Digital Design, Autumn2015 16 in a FPGA

• A logic block in an FPGA often consists of a LUT, a flip-flop and a multiplexer to select register output Select

Out Flip-flop In1 In2 LUT D Q In3 Clock

IE1204 Digital Design, Autumn2015 17 Programming the LUT's and the connection matrix in an FPGA

x f • Blue cross: switch 3 is programmed • Black cross: switch

is not programmed x1

x1 0 x2 0 0 f 1 f 0 1 0 2 x x x f=f1+f2 2 2 1 3 0

f=x1x2+x2x3

f 1 0 1 f 1 f 2 1

IE1204 Digital Design, Autumn2015 18 DE2 University Board

• DE2 Board – Cyclone II EP2C35 FPGA (Datorteknik- course) – 4 Mbytes of flash memory – 512 Kbytes of static RAM – 8 Mbytes of SDRAM – Several I/O-Devices – 50 MHz oscillator

IE1204 Digital Design, Autumn2015 19 Cyclone II Logic Element

IE1204 Digital Design, Autumn2015 20 Cyclone II Family

(3) Total Number of 18x18 Multipliers DE2

IE1204 Digital Design, Autumn2015 21 III Family

DE3 Board

IE1204 Digital Design, Autumn2015 22 Multiple processors can be implemented on an FPGA

• Nine II is a so-called 'soft-

' (32-bit) that Nios II can be implemented on ’s FPGAs • Today's FPGAs are so large that multiple Nios II processors can fit on a single FPGA chip Very powerful multiprocessor systems can be created on an FPGA!

IE1204 Digital Design, Autumn2015 23 ASICs

• An ASIC (Application Specific ) is a circuit which is manufactured at a semiconductor factory • In a full custom integrated circuit, the entire circuit is customized • In an ASIC, some design steps have already been made to reduce design time and cost • There are several types of ASICs: – ASICs – ASIC

IE1204 Digital Design, Autumn2015 24 ASICs: Gate Array

• In a gate array ASIC, gates (or transistors) are already on silicon

IE1204 Digital Design, Autumn2015 25 ASICs: Gate Array

f • We only need 1 to create the x links between 1 the inputs and

outputs of x2 gates

x3

IE1204 Digital Design, Autumn2015 26 ASICs: Standard Cells

• A standard cell can for example be AND, OR, Invert, XOR, XNOR, buffer, or a storage function as flipflop or latch.

IE1204 Digital Design, Autumn2015 27 Comparison FPGA, Gate Array, Standard Cell

Initial Cost Cost per part Performance Fabrication Time

FPGA Low High Low Short

Gate Array (ASIC) Standard Cell High Low High Long (ASIC)

IE1204 Digital Design, Autumn2015 28 Design Trade-Offs

Design Time Full Custom

Standard Cell

Gate Array

Programmable Logic Microprocessor

Performance

IE1204 Digital Design, Autumn2015 29 VHDL: Sequential circuits

IE1204 Digital Design, Autumn2015 30 Moore machine

State

NEXT STATE STATE REGISTER OUTPUT DECODER DECODER Input Output signals signals

Clk

• In a Moore-type machine output signals depend only on the current state

IE1204 Digital Design, Autumn2015 31 How to model a state machine in VHDL? • In a Moore machine, we have three blocks – Next state decoder – Output decoder – State register • These blocks are executed in parallel

IE1204 Digital Design, Autumn2015 32 Quick question

• Which is represented by the following VHDL code?

IE1204 Digital Design, Autumn2015 33 Quick question

• Which logic gate is represented by the following VHDL code?

IE1204 Digital Design, Autumn2015 34 Processes in VHDL

• A architecture in VHDL can contain multiple processes • Processes are executed in parallel • A process is written as a sequential program

IE1204 Digital Design, Autumn2015 35 Moore-machine processes

• For a Moore machine, we create three processes – Next state decoder – Output decoder – State register

IE1204 Digital Design, Autumn2015 36 Internal signals

• Moore machine contains internal signals for – Current state – Next state • These signals are declared in the architecture description

IE1204 Digital Design, Autumn2015 37 Bottle dispenser vending machine in VHDL

• We use bottle dispenser vending machine as an example • We describe its system controller in VHDL

COIN_PRESENT DROP GT_1_EURO DROP_READY DROP BOTTLE

COIN EQ_1_EURO SYSTEM RECEIVER LT_1_EURO CONTROL

DEC_ACC RETURN_10_CENT

CLR_ACC CHANGER_READY COIN RETURN

IE1204 Digital Design, Autumn2015 38 Vending Machine: Flow diagram

Reset

No Coin registered?

Yes

Total <1 € Total? Total = 1 € Total> € 1

Eject Return bottle 10 Cent

Reset Decrease sum sum

IE1204 Digital Design, Autumn2015 39 Vending Machine: State diagram

COIN_PRESENT (a) 000 • The state diagram COIN_PRESENT contains all information COIN_PRESENT (b) required to generate an 001 implementation COIN_PRESENT LT_I_EURO (c) • Assumption: D flip-flops 011 GT_I_EURO are used as state EQ_I_EURO register DROP CHANGER READY (d) (f) READY • 7 states: 3 flip-flops are DROP 110 100 RETURN_10_CENT needed DROP READY CHANGER_READY The state variable order is (e) (g) ABC, i.e. state (c) is 111 101 A = 0, B = 1,C = 1 CLR_ACC DEC_ACC

IE1204 Digital Design, Autumn2015 40 Vending Machine: Logic design

Next state Output Input-signals decoder Flip-flops decoder Output-signals (Combination (Combination al circuit) al circuit) Clk ? ? COIN_PRESENT DA A D LT_I_EURO DROP EQ_I_EURO RETURN_I0_CENT GT_I_EURO DB B DROP_READY Next D Output CHANGER_READY State Decoder CLR_ACC Decoder A DEC_ACC DC C B D C Clk

At next step, we develop the logic for the next state (DA, DB, DC) and outputs

IE1204 Digital Design, Autumn2015 41 Decoder: Next state - DA

COIN_PRESENT (a) DA AB 000 00 01 11 10 COIN_PRESENT

COIN_PRESENT 0 0 - 1 1 (b) C 001 1 0 (=) + (>) 0 0 COIN_PRESENT LT_I_EURO (c) (=) : EQ_1_EURO 011 (>) : GT_1_EURO EQ_I_EURO GT_I_EURO

DROP CHANGER READY (d) (f) READY DROP 110 100 RETURN_10_CENT

DROP READY CHANGER_READY (e) (g) 111 101 DA = AB(EQ) + AB(GT) + AC CLR_ACC DEC_ACC

IE1204 Digital Design, Autumn2015 42 Decoder: Next state - DB

COIN_PRESENT (a) DB AB 000 00 01 11 10 COIN_PRESENT

COIN_PRESENT 0 0 - 1 0 (b) C 001 1 CP (=) 0 1 COIN_PRESENT LT_I_EURO (c) (=) : EQ_1_EURO 011 CP : COIN_PRESENT EQ_I_EURO GT_I_EURO

DROP CHANGER READY (d) (f) READY DROP 110 100 RETURN_10_CENT

DROP READY CHANGER_READY (e) (g) 111 101 DB = AB(EQ) + BC + BC(CP) + ABC CLR_ACC DEC_ACC

IE1204 Digital Design, Autumn2015 43 Decoder: Next state- DC

COIN_PRESENT (a) DC AB 000 00 01 11 10 COIN_PRESENT

COIN_PRESENT 0 CP - DR CR (b) C 001 1 1 0 0 1 COIN_PRESENT LT_I_EURO (c) CP : COIN_PRESENT 011 DR: DROP_READY GT_I_EURO EQ_I_EURO CR: CHANGER_READY DROP CHANGER READY (d) (f) READY DROP 110 100 RETURN_10_CENT

DROP READY CHANGER_READY D = AC(CP) + BC(DR) (e) (g) C 111 101 + AB(CR) + BC CLR_ACC DEC_ACC

IE1204 Digital Design, Autumn2015 44 Decoder: Output signals

COIN_PRESENT (a) • Output decoder is 000 COIN_PRESENT trivial, since its value

COIN_PRESENT is directly dependent (b) 001 on the current state COIN_PRESENT LT_I_EURO (c) 011 GT_I_EURO EQ_I_EURO DROP = ABC DROP CHANGER CLR_ACC =ABC READY (d) (f) READY DROP 110 100 RETURN_10_CENT RETURN_10_ CENT = ABC

DROP READY CHANGER_READY DEC_ACC = ABC (e) (g) 111 101 CLR_ACC DEC_ACC

IE1204 Digital Design, Autumn2015 45 Unused state?!

COIN_PRESENT (a) AB 000 (h) COIN_PRESENT 010 00 01 11 10

COIN_PRESENT (b) 0 a - d f 001 COIN_PRESENT C LT_I_EURO (c) 1 b c e g 011 EQ_I_EURO GT_I_EURO F = (010) DROP CHANGER ABC READY (d) (f) READY 100 DROP 110 RETURN_10_CENT

DROP READY CHANGER_READY (e) (g) 111 101

CLR_ACC DEC_ACC

+ + A = A× B× EQ + A× B×GT + A×C Þ A (010) ABC =1×1× EQ +1×1×GT + 0×1 = EQ + GT + + B = A× B× EQ + B ×C + B ×C ×CP + A× B ×C Þ B (010) ABC =1×1× EQ +1×1+... =1 C + = A×C ×CP + B ×C × DR + A× B×CR + B ×C + Þ C (010) ABC =1×1×CP +1×1× DR + 0×0×CR + 0×0 = CP + DR A+ B+C + = -1- = 010,110, 011,111® F, d, c, e

IE1204 Digital Design, Autumn2015 46 Vending Machine: Logic Design

COIN_PRESENT DA A D LT_I_EURO DROP EQ_I_EURO RETURN_I0_CENT GT_I_EURO DB B DROP_READY Next D Output CHANGER_READY State Decoder CLR_ACC Decoder A DEC_ACC DC C B D C Clk

Now you can design ”Next State Decoder” and ”Output Decoder” by knowing the logic function of Da, Db, Dc, and logic funtion of outputs ”Drop”, ”Return_10_Cent”, ”CLR_ACC”, and ”DEC_ACC”.

IE1204 Digital Design, Autumn2015 47 Vending Machine in VHDL: Entity • Entity describes the system ENTITY Vending_Machine IS as a 'black box ' PORT ( -- Inputs • Entity describes the interface coin_present : IN std_logic; to the outside world gt_1_euro : IN std_logic; • All inputs and outputs are eq_1_euro : IN std_logic; lt_1_euro : IN std_logic; described drop_ready : IN std_logic; • Apart from the input and changer_ready : IN std_logic; output signals, block diagram reset_n : IN std_logic; needs signals for clk : IN std_logic; -- Outputs – Clock dec_acc : OUT std_logic; – Reset (active low) clr_acc : OUT std_logic; drop : OUT std_logic; return_10_cent : OUT std_logic); END Vending_Machine;

IE1204 Digital Design, Autumn2015 48 Vending Machine in VHDL: Architecture • The architecture describes the function of the machine • We define – internal signals for the current and next states – three processes for next-state decoder, output decoder and state register

IE1204 Digital Design, Autumn2015 49 Vending Machine in VHDL: Internal Signals

• We need to create a type for internal signals • Since we describe the states, we use an enumerated type with the values a, b, c, d, e, f, g • We declare one variable for the current state (current_state) and one for the next state (next_state)

ARCHITECTURE Moore_FSM OF Vending_Machine IS TYPE state_type IS (a, b, c, d, e, f, g); SIGNAL current_state, next_state: state_type; BEGIN -- Moore_FSM …

IE1204 Digital Design, Autumn2015 50 Vending Machine in VHDL: Internal Signals

• If we do not specify a state assignment, synthesis tool will select it • We can force a certain encoding using attributes (NOTE: Attributes are dependent on synthesis tool and thus are not portable!)

ARCHITECTURE Moore_FSM OF Vending_Machine IS TYPE state_type IS (a, b, c, d, e, f, g); -- We can use state encoding according to BV 8.4.6 -- to enforce a particular encoding (for Quartus) ATTRIBUTE enum_encoding : string; ATTRIBUTE enum_encoding OF state_type : TYPE IS "000 001 011 110 111 100 101"; SIGNAL current_state, next_state : state_type; BEGIN -- Moore_FSM …

IE1204 Digital Design, Autumn2015 51 Vending Machine in VHDL: Process for Next-State Decoder

Next state Output Input-signals decoder Flip-flops decoder Output-signals (Combination (Combination al circuit) al circuit) Clk • Next-State-Decoder is described as a process • Sensitivity list contains all the inputs that 'activate' the process NEXTSTATE : PROCESS (current_state, coin_present, gt_1_euro, eq_1_euro, lt_1_euro, drop_ready, changer_ready) –- Sensitivity List BEGIN -- PROCESS NEXT_STATE …

IE1204 Digital Design, Autumn2015 52 Vending Machine in VHDL: Process for Next-State-Decoder

Next state Output Input-signals decoder Flip-flops decoder Output-signals (Combination (Combination al circuit) al circuit) Clk • We now use a CASE statement to describe the transitions to the next state from each state conditions

COIN_PRESENT CASE current_state IS (a) 000 WHEN a => IF coin_present = '1' THEN COIN_PRESENT

COIN_PRESENT next_state <= b; (b) 001 ELSE COIN_PRESENT LT_I_EURO (c) next_state <= a; 011 END IF; EQ_I_EURO GT_I_EURO DROP CHANGER WHEN b => IF coin_present = '0' THEN READY (d) (f) READY 110 100 next_state <= c; DROP RETURN_10_CENT ELSE DROP READY CHANGER_READY (e) (g) next_state <= b; 111 101 END IF; CLR_ACC DEC_ACC

IE1204 Digital Design, Autumn2015 53 Vending Machine in VHDL: Process for Next-State-Decoder

• We can simplify the description by specifying a default value for the next state … next_state <= current_state; CASE current_state IS WHEN a => IF coin_present = '1' THEN next_state <= b; END IF; WHEN b => IF coin_present = '0' THEN next_state <= c; END IF; … It is important to we specify all options for next_state signal. Otherwise we may implicitly set next_state <= next_state which generates a loop.

IE1204 Digital Design, Autumn2015 54 Vending Machine in VHDL: Process for Next-State-Decoder

• We terminate the CASE statement with a WHEN OTHERS statement. Here we specify that we should go to the state a if we end up in an unspecified state

… WHEN g => next_state <= c; WHEN OTHERS => next_state <= a; END CASE; END PROCESS NEXTSTATE;

IE1204 Digital Design, Autumn2015 55 Vending Machine in VHDL: Process for Output-Decoder

Next state Output Input-signals decoder Flip-flops decoder Output-signals (Combination (Combination al circuit) al circuit) Clk

• Output decoder is described as a separate process • Sensitivity list contains only the current state because the outputs are directly dependent on it

IE1204 Digital Design, Autumn2015 56 Vending Machine in VHDL: Process for Output-Decoder

OUTPUT : PROCESS (current_state) BEGIN -- PROCESS OUTPUT drop <= '0'; clr_acc <= '0'; dec_acc <= '0'; return_10_cent <= '0'; CASE current_state IS WHEN d => drop <= '1'; WHEN e => clr_acc <= '1'; WHEN f => return_10_cent <= '1'; WHEN g => dec_acc <= '1'; WHEN OTHERS => NULL; END CASE; END PROCESS OUTPUT;

IE1204 Digital Design, Autumn2015 57 Vending Machine in VHDL: Process for State register

Next state Output Input-signals decoder Flip-flops decoder Output-signals (Combination (Combination al circuit) al circuit) Clk

• State register is modeled as a synchronous process with asynchronous reset (active low) CLOCK : PROCESS (clk, reset_n) BEGIN -- PROCESS CLOCK IF reset_n = '0' THEN -- asynchronous reset (active low) current_state <= a; ELSIF clk‘EVENT AND clk = '1' THEN -- rising clock edge current_state <= next_state; END IF; END PROCESS CLOCK;

IE1204 Digital Design, Autumn2015 58 Quick question

• Which state machine is represented by this VHDL code?

IE1204 Digital Design, Autumn2015 59 Mealy machine

State

NEXT STATE STATE REGISTER OUTPUT DECODER DECODER Input Output signals signals

Clk

• In a Mealy machine, output signals depend on both the current state and inputs

IE1204 Digital Design, Autumn2015 60 Mealy machine in VHDL

• A Mealy machine can be modeled in the same way as the Moore machine • The difference is that output decoder is also dependent on the input signals • Process which models outputs needs to have input signals in the sensitivity list as well!

IE1204 Digital Design, Autumn2015 61 More on VHDL

• The sample code for bottle dispenser available on the course website • Look at the study of "VHDL synthesis" on the course website • Both Brown/Vranesic- and Hemert-book includes code samples

IE1204 Digital Design, Autumn2015 62 Summary

• PLD, PAL, CPLD • FPGA • ASIC – gate array and standard cell • Modeling sequential circuits with VHDL • Next lecture: BV pp. 584-640

IE1204 Digital Design, Autumn2015 63