IE1204 Digital Design F11: Programmable Logic, VHDL for Sequential Circuits Masoumeh (Azin) Ebrahimi ([email protected]) Elena Dubrova ([email protected]) KTH / ICT / ES This lecture • BV pp. 98-118, 418-426, 507-519 IE1204 Digital Design, Autumn2015 2 Programmable Logic Devices • Programmable logic devices (PLDs) were introduced in the 1970s • They are based on a structure with an AND-OR array that makes it easy to implement a sum-of-products expression IE1204 Digital Design, Autumn2015 3 Structure of a PLD x1 x2 xn Input buffers and inverters x1 x1 xn xn P1 AND plane OR plane Pk f1 fm IE1204 Digital Design, Autumn2015 4 Programmable Logic Array (PLA) x1 x2 x3 • Both AND and OR arrays are programmable OR P1 plane f1=x1x2+x1x3+x1x2x3 P2 f =x x +x x x +x x 2 1 2 1 2 3 1 3 P3 P4 AND plane f1 f2 IE1204 Digital Design, Autumn2015 5 Programmable Array Logic (PAL) x1 x2 x3 • Only the AND array is programmable P1 f =x x x +x x x 1 1 2 3 1 2 3 f1 P2 f2=x1x2+x1x2x3 P3 f2 P4 AND plane IE1204 Digital Design, Autumn2015 6 Combinatorial and register outputs • In earlier PLDs there were – combinatorial outputs – register outputs (outputs with a flip-flop) • For each circuit the number of combinational and register outputs was fixed • To increase flexibility, macrocells were introduced – one can choose if an output is combinatorial or has a flip-flop IE1204 Digital Design, Autumn2015 7 Macrocells in a PLD x1 x2 x3 Select P1 Enable f P2 1 P3 f2 f P4 1 Flip-flop D Q A programmable multiplexer can be Clock used to select the type of output To AND plane IE1204 Digital Design, Autumn2015 8 Programming of PLDs IE1204 Digital Design, Autumn2015 9 Complex PLD's (CPLD) • PLDs were quite small (PALCE 22V10 had 10 flip-flops) • To program larger functions, structures consisting of several PLD-like blocks were developed called Complex PLD (CPLD) IE1204 Digital Design, Autumn2015 10 IE1204 Autumn2015 Digital Design, I/O block I/O block CPLD Structure PAL-like PAL-like block block Interconnection wires PAL-like PAL-like block block k c o l b O / I k c o l b O / I 11 Programming of CPLDs via the JTAG interface • Modern CPLDs (and FPGAs) can be programmed by downloading circuit description (programming information) via a cable • Download usually uses a standard port called JTAG port (Joint Test Action Group) IE1204 Digital Design, Autumn2015 12 Programming via the JTAG port You can program the chips when they are soldered to the circuit board - using the (a) CPLD in a Quad Flat Pack (QFP) package programmer you can select which chip you To computer want to program through the JTAG port Printed circuit board (b) JTAG programming IE1204 Digital Design, Autumn2015 13 Field Programmable Gate Arrays • CPLDs are based on the AND-OR array • It is difficult to make really large functions using CPLDs • FPGAs use a different concept based on logic blocks IE1204 Digital Design, Autumn2015 14 Structure of an FPGA IE1204 Digital Design, Autumn2015 15 Look-up-tables (LUT) A LUT with n inputs can Programmable 0/1 realize all 1 cells combinational functions with up to n inputs. 0/1 0 The usual size of LUT 1 in an FPGA is n = 4 f 0/1 0 1 0/1 0 x2 x1 Two-input LUT IE1204 Digital Design, Autumn2015 16 Logic Block in a FPGA • A logic block in an FPGA often consists of a LUT, a flip-flop and a multiplexer to select register output Select Out Flip-flop In1 In2 LUT D Q In3 Clock IE1204 Digital Design, Autumn2015 17 Programming the LUT's and the connection matrix in an FPGA x f • Blue cross: switch 3 is programmed • Black cross: switch is not programmed x1 x1 0 x2 0 0 f 1 f 0 1 0 2 x x x f=f1+f2 2 2 1 3 0 f=x1x2+x2x3 f 1 0 1 f 1 f 2 1 IE1204 Digital Design, Autumn2015 18 DE2 University Board • DE2 Board – Cyclone II EP2C35 FPGA (Datorteknik- course) – 4 Mbytes of flash memory – 512 Kbytes of static RAM – 8 Mbytes of SDRAM – Several I/O-Devices – 50 MHz oscillator IE1204 Digital Design, Autumn2015 19 Cyclone II Logic Element IE1204 Digital Design, Autumn2015 20 Cyclone II Family (3) Total Number of 18x18 Multipliers DE2 IE1204 Digital Design, Autumn2015 21 Stratix III Family DE3 Board IE1204 Digital Design, Autumn2015 22 Multiple processors can be implemented on an FPGA • Nine II is a so-called 'soft- processor' (32-bit) that Nios II can be implemented on Altera’s FPGAs • Today's FPGAs are so large that multiple Nios II processors can fit on a single FPGA chip Very powerful multiprocessor systems can be created on an FPGA! IE1204 Digital Design, Autumn2015 23 ASICs • An ASIC (Application Specific Integrated Circuit) is a circuit which is manufactured at a semiconductor factory • In a full custom integrated circuit, the entire circuit is customized • In an ASIC, some design steps have already been made to reduce design time and cost • There are several types of ASICs: – Gate array ASICs – Standard cell ASIC IE1204 Digital Design, Autumn2015 24 ASICs: Gate Array • In a gate array ASIC, gates (or transistors) are already on silicon IE1204 Digital Design, Autumn2015 25 ASICs: Gate Array f • We only need 1 to create the x links between 1 the inputs and outputs of x2 gates x3 IE1204 Digital Design, Autumn2015 26 ASICs: Standard Cells • A standard cell can for example be AND, OR, Invert, XOR, XNOR, buffer, or a storage function as flipflop or latch. IE1204 Digital Design, Autumn2015 27 Comparison FPGA, Gate Array, Standard Cell Initial Cost Cost per part Performance Fabrication Time FPGA Low High Low Short Gate Array (ASIC) Standard Cell High Low High Long (ASIC) IE1204 Digital Design, Autumn2015 28 Design Trade-Offs Design Time Full Custom Standard Cell Gate Array Programmable Logic Microprocessor Performance IE1204 Digital Design, Autumn2015 29 VHDL: Sequential circuits IE1204 Digital Design, Autumn2015 30 Moore machine State NEXT STATE STATE REGISTER OUTPUT DECODER DECODER Input Output signals signals Clk • In a Moore-type machine output signals depend only on the current state IE1204 Digital Design, Autumn2015 31 How to model a state machine in VHDL? • In a Moore machine, we have three blocks – Next state decoder – Output decoder – State register • These blocks are executed in parallel IE1204 Digital Design, Autumn2015 32 Quick question • Which logic gate is represented by the following VHDL code? IE1204 Digital Design, Autumn2015 33 Quick question • Which logic gate is represented by the following VHDL code? IE1204 Digital Design, Autumn2015 34 Processes in VHDL • A architecture in VHDL can contain multiple processes • Processes are executed in parallel • A process is written as a sequential program IE1204 Digital Design, Autumn2015 35 Moore-machine processes • For a Moore machine, we create three processes – Next state decoder – Output decoder – State register IE1204 Digital Design, Autumn2015 36 Internal signals • Moore machine contains internal signals for – Current state – Next state • These signals are declared in the architecture description IE1204 Digital Design, Autumn2015 37 Bottle dispenser vending machine in VHDL • We use bottle dispenser vending machine as an example • We describe its system controller in VHDL COIN_PRESENT DROP GT_1_EURO DROP_READY DROP BOTTLE COIN EQ_1_EURO SYSTEM RECEIVER LT_1_EURO CONTROL DEC_ACC RETURN_10_CENT CLR_ACC CHANGER_READY COIN RETURN IE1204 Digital Design, Autumn2015 38 Vending Machine: Flow diagram Reset No Coin registered? Yes Total <1 € Total? Total = 1 € Total> € 1 Eject Return bottle 10 Cent Reset Decrease sum sum IE1204 Digital Design, Autumn2015 39 Vending Machine: State diagram COIN_PRESENT (a) 000 • The state diagram COIN_PRESENT contains all information COIN_PRESENT (b) required to generate an 001 implementation COIN_PRESENT LT_I_EURO (c) • Assumption: D flip-flops 011 GT_I_EURO are used as state EQ_I_EURO register DROP CHANGER READY (d) (f) READY • 7 states: 3 flip-flops are DROP 110 100 RETURN_10_CENT needed DROP READY CHANGER_READY The state variable order is (e) (g) ABC, i.e. state (c) is 111 101 A = 0, B = 1,C = 1 CLR_ACC DEC_ACC IE1204 Digital Design, Autumn2015 40 Vending Machine: Logic design Next state Output Input-signals decoder Flip-flops decoder Output-signals (Combination (Combination al circuit) al circuit) Clk ? ? COIN_PRESENT DA A D LT_I_EURO DROP EQ_I_EURO RETURN_I0_CENT GT_I_EURO DB B DROP_READY Next D Output CHANGER_READY State Decoder CLR_ACC Decoder A DEC_ACC DC C B D C Clk At next step, we develop the logic for the next state (DA, DB, DC) and outputs IE1204 Digital Design, Autumn2015 41 Decoder: Next state - DA COIN_PRESENT (a) DA AB 000 00 01 11 10 COIN_PRESENT COIN_PRESENT 0 0 - 1 1 (b) C 001 1 0 (=) + (>) 0 0 COIN_PRESENT LT_I_EURO (c) (=) : EQ_1_EURO 011 (>) : GT_1_EURO EQ_I_EURO GT_I_EURO DROP CHANGER READY (d) (f) READY DROP 110 100 RETURN_10_CENT DROP READY CHANGER_READY (e) (g) 111 101 DA = AB(EQ) + AB(GT) + AC CLR_ACC DEC_ACC IE1204 Digital Design, Autumn2015 42 Decoder: Next state - DB COIN_PRESENT (a) DB AB 000 00 01 11 10 COIN_PRESENT COIN_PRESENT 0 0 - 1 0 (b) C 001 1 CP (=) 0 1 COIN_PRESENT LT_I_EURO (c) (=) : EQ_1_EURO 011 CP : COIN_PRESENT EQ_I_EURO GT_I_EURO DROP CHANGER READY (d) (f) READY DROP 110 100 RETURN_10_CENT DROP READY CHANGER_READY (e) (g) 111 101 DB = AB(EQ) + BC + BC(CP) + ABC CLR_ACC DEC_ACC IE1204 Digital Design, Autumn2015 43 Decoder: Next state- DC COIN_PRESENT (a) DC AB 000 00 01 11 10 COIN_PRESENT COIN_PRESENT 0 CP - DR CR (b) C 001 1 1 0 0 1 COIN_PRESENT LT_I_EURO (c) CP : COIN_PRESENT 011 DR: DROP_READY GT_I_EURO EQ_I_EURO CR: CHANGER_READY DROP CHANGER READY (d) (f) READY DROP 110 100 RETURN_10_CENT DROP READY CHANGER_READY D = AC(CP) + BC(DR) (e) (g) C 111 101 + AB(CR)