Examples of FPLD Families: Actel ACT, Xilinx LCA, Altera MAX 5000 & 7000

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Actel ACT Family

¯ The Actel ACT family employs multiplexer-based logic cells.

¯ A row-based architecture is used in which the logic cells are arranged in rows with horizontal routing channels between adjacent rows of logic cells.

Interconnect

Logic cell

2 ACT 1 Logic Modules

¯ ACT 1 FPGAs use a single type of logic module. Logic Module Logic Module Logic Module

M1 A0 F A0 D Actel ACT 0 F1 A1 0 M3 F1 A1 1 '1' 1 SA F1 S F SA 0 F F2 C 0 M2 1 B0 1 B0 S D 0 B1 0 F2 B1 1 F2 '1' 1 SB (a) S SB S3 A S0 S3 S0 '0' S1 O1 S1 O1 B F=(A·B)+(B'·C)+D

(b) (c) (d)

(a) An Actel FPGA. (b) An ACT 1 logic module. (c) An implementation of an ACT 1 logic module using pass transistors. (d) An example of function implementation by an ACT 1 logic module.

3

ACT 2 and ACT 3 Logic Modules

¯ Both ACT 2 and ACT 3 FPGAs use two types of logic module.

C-Module S-Module (ACT 2) S-Module (ACT 3)

D00 D00 SED00 SE D01 D01 D01 D10 YOUTD10 YQD10 YQ D11 D11 D11 A1 A1 A1 B1 S1 B1 S1 B1 S1 A0 A0 A0 B0 S0 CLR S0 B0 S0 CLR CLK CLK (a) (b) (c)

SE (sequential element) SE

1 1 D D Q Q Z Z D 0 0 Q CLK C2 S S C1 master slave C2 latch latch CLR CLR C1

CLR combinational logic for clock flip-flop macro and clear D 1D Q CLK C1

(d) (e)

(a) The C-module used by both ACT 2 and ACT 3 FPGAs. (b) The ACT 2 S-module. (c) The ACT 3 S-module. (d) Equivalent circuit of the SE. (e) The sequential element configured as a positive-edge- triggered D flip-flops.

4 Routing Architecture of ACT Family

¯ A row-based architecture.

¯ Each horizontal channel consists of a number of routing tracks.

¯ Some routing tracks are segmented where adjacent segments can be connected through antifuses to form longer lines.

¯ There are also some vertical tracks running through the logic modules and horizon- tal channels.

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FILENAME.APP=6822FG13.PS

I/O module Antifuses Vertical segments

Segmented routing channels

Rows of logic modules

Routing architecture of an Actel ACT FPGA.

6 Xilinx LCA Family

¯ The Xilinx LCA family employs LUT-based logic cells.

¯ A symmetrical array architecture is used.

Interconnect

Logic cell

7

Configurable Logic Block of LCA Family

¯ We consider the XC4000 devices for an example.

¯ The XC4000 FPGAs use a single type of configurable logic block (CLB).

¯ Each CLB contains two 4-input LUTs that feed a 3-input LUT. This allows a CLB to implement any two logic functions with four or less variables, or some function with

five or more variables. ¢ ¯ A CLB can also be configured to be used as memory e.g. as two 16 1 memory SRAMs.

¯ The outputs of the function generators can be optionally stored in flip-flops inside a CLB.

8 6-37 Figure 6-32 Simplified Diagram of a Xilinx® Configurable Logic Block (Adapted with permission of Xilinx®, Inc.)

H1 DIN S/R EC G1 Look up Table G2 for G' G' G3 MUX G4 S/R 16 bits of SRAM ¥ DIN ¥ Control PRE F' D YQ ¥ G' ¥ H' S EC CLR MM Look up Table MUX for H' H' ¥ M ¥ 8 bits of SRAM MUX S 1 ¥ ¥ G' M ¥ H' Y S F1 Look up Table M F2 for F' F' ¥ F3 MUX F4 S/R 16 bits of SRAM DIN Control PRE ¥ F' D XQ G' ¥ H' S EC CLR MM MUX M K (CLOCK) ¥

MUX S 1 F' M H' X S

M - SRAM cell M 9

Routing Architecture of LCA Family

¯ A typical Xilinx LCA FPGA consists of a two-dimensional array of CLBs with hori- zontal routing channels between rows of blocks and vertical routing channels be- tween columns.

¯ Routing tracks are segmented which can be interconnected inside the switch ma- trices.

¯ Each interconnect point inside a switch matrix is formed by 6 pass transistors to allow connections between adjacent segments and/or between the vertical and horizontal lines that meet there.

10 T-153 Xilinx® XC4000™ FPGA Structure (Adapted with Permission of Xilinx, Inc.)

¥¥¥

Long lines Single length

¥¥¥ - Input/Output Block (IOB)

- Configurable logic block (CLB) - Switch matrix 11

M M M

M

M M acb

d e

(a) (b)

(a) A switch matrix. (b) Example of connections made through a switch matrix.

12 Altera MAX 5000 & 7000 Family

¯ The Altera MAX family employs PAL-based logic cells.

¯ The logic cells are called macrocells.

¯ A hierarchical PLD architecture is used where the macrocells are grouped into larger blocks called logic array blocks.

PLD block

Chipwide interconnect

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Logic Array Block of MAX Family

¯ Each logic array block (LAB) contains 16 macrocells.

¯ A simplified macrocell showing its basic PLD-like combinational logic structure:

. . .

¯ See Fig. 3.5 of text for the complete structure of a macrocell.

¯ In addition to the basic combinational logic structure shown above Ð each macrocell has a flip-flop Ð there are special connections that allow sharing of product terms between differ- ent macrocells in the same LAB.

14 Routing Architecture of MAX 5000 & 7000 Family

¯ The LABs are interconnected by a chipwide interconnect called programmable in- terconnect array (PIA).

¯ The PIA acts as a global bus and is built such that the connections between different pairs of LABs all have the same delay.

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T-150 Altera® MAX 7000™ Structure (Reprinted with Permission of Altera Corporation,© Altera Corp., 1991)

I/O control block

Logic Logic Logic Logic array array array array block block block block

Programmable interconnect array

Logic Logic Logic Logic array array array array block block block block I/O I/O control control block block Logic Logic Logic Logic array array array array block block block block

Logic Logic Logic Logic array array array array block block block block

I/O control block

16 Comparison of FPLD Families

Actel ACT 3 Xilinx XC4000 Altera MAX 7000 Programming antifuse SRAM EPROM technology Architecture row-based symmetrical array hierarchical-PLD Logic cell type multiplexer-based LUT-based PAL-based Interconnect segmented channels segmented channels with programmable interconnection switch matrices architecture Interconnect variable variable fixed delay Basic C-module and Configurable 16 macrocells logic cells S-module Logic Block (CLB) in a LAB Logic cell C-module: 4:1 MUX, 3 LUTs, Macrocell: contents 2-input OR, 2-input AND. 2 D flip-flops, 5 ANDs, 1 OR, 1 EXOR, S-module: 4:1 MUX, 2-input OR, 10 MUXes. 1 flip-flop, 3 MUXes. 2-input AND, latch/D flip-flop. Combinational One. Two or one. Multiple wide input functions Most 3-and 4-input Any two 4-input functions, functions per LAB

per logic cell functions. or one selected function of 9 inputs. Basic 104 S+96 C (A1415) 64 CLBs (XC4002XL) 32 macrocells (EPM7032) logic cells to to to per chip 697 S+680 C (A14100) 3136 CLBs (XC4085XL) 256 macrocells (EPM70256E)

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