MOS Microprocessor Data Manual 1983

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• iv-;:ovj MOS Microprocessor Data Manual 1983

Signetics Signetics reserves the right to make changes in the products contained in this book in order to improve design or performance and to supply the best possible products. Signetics also assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representations that the circuits are free from patent infringement. Applica- tions for any integrated circuits contained in this publication are for illustration purposes only and Signetics makes no representation or warranty that such applications will be suitable for the use specified without further testing or modification. Reproduction of any portion hereof without the prior written con- sent of Signetics is prohibited.

Signetics MICROPROCESSOR DIVISION JANUARY 1983 CONTENTS

Product Status Definitions iv

Section 1 — Data Communications SCN2651 Programmable Communications Interface (PCI) 1-1 SCN26521SCN68652 Multi-Protocol Communications Controller (MPCC) 1-15 SCN26531SCN68653 Polynomial Generator Checker (PGC) 1-33 SCN26611SCN68661 Enhanced Programmable Communications Interface (EPCI) 1-51 SCN2681 Series Dual Asynchronous Receiver/Transmitter (DUART) 1-68 Section 2 — Video Display CRT Chip Set Comparison Features 2-1 SCN2670 Display Character and Graphic Generator (DCGG) 2-3 SCN2671 Programmable Keyboard and Communications Controller (PKCC) 2-16 SCN2672 Programmable Video Timing Controller (PVTC) 2-37 SCB2673 Video Attributes Controller (VAC) 2-58 SCN2674 Advanced Video Display Controller (AVDC) 2-69 SCB2675 Color/Monochrome Attributes Controller (CMAC) 2-97 Section 3 — Single Chip Microcomputers SCN80 Series Single Chip 8-Bit Microcomputer 3-1 *SCC80 Series CMOS Single Chip 8-Bit Microcomputer 3-16 SCN8031/SCN8051 Single Chip 8-Bit Microcomputer 3-17 *SCC80C31/SCC80C51 CMOS Single Chip 8-Bit Microcomputer 3-24 Section 4 — SCN68000 16•Bit Family SCN68000 Series 16-Bit Microprocessor 4-1 *SCN68008 16-Bit Microprocessor with 8-Bit Bus 4-50 SCN68120/SCN68121 Intelligent Peripheral Controller 4-52 SCN68230 Parallel Interface/Timer 4-100 SCB68430 Direct Memory Access Interface (DMAI) 4-130 *SCN68451 Memory Management Unit 4-151 •SCN68454 Intelligent Multiple Disk Controller (IMDC) 4-152 •SCN68459 Disk Phase Locked Loop (DPLL) 4-153 *SCN68562 Dual Universal Serial Communications Controller 4-154 SCN68681 Dual Asynchronous Receiver/Transmitter (DUART) 4-156 Section 5 — Video Games *SCN2621/SCN2622 Universal Sync Generator (USG) 5-1 *SCN2636 Programmable Video Interface (PVI) 5-2 *SCN2637 Universal Video Interface (UVI) 5-3 *SCN2650A Microprocessor 5-5 Section 6 — Application Notes App Note M22 Interface Techniques for the 2651 PCI 6-1 App Note M24.A Using the 2651 PCI with BISYNC 6-7 App Note M26 Application Techniques for the 2651 PCI 6-9 App Note 400 Using the 2653 Polynomial Generator and Checker 6-11 App Note 401 Using the 2670/71/72173 CRT Terminal Chip Set 6-27 App Note 402 2661 Operating Mode Switching Procedures 6-43 App Note 403 2670/71/72/73 CRT Set Application Briefs 6-44

Section 7 — Microsystems SMDEV10000 S68000 User Work Station (UWS) 7-1 SMSFT1000 S68000 Cross Software Macro Assembler 7.4 SMSFT1600 S68000 Cross Software PASCAL Cross Compiler 7.6

Section 8 — Appendices General Information 8-1 Package Outlines 8-2 Sales Offices 8-7

*PRODUCT BRIEF, contact your Signetics sales offices for complete information. Signetics Iii

MICROPROCESSOR DIVISION JANUARY 1983

PRODUCT STATUS DEFINITIONS/PART NUMBERING SYSTEM

DEFINITION OF TERMS

Data Sheet Identification Product Status Definition

Preview Formative or This data sheet contains the design In Design specifications for product development. Specifications may change in any manner without notice.

Advance Information Sampling or This data sheet contains advance Pre-Production information and specifications are subject to change without notice. Preliminary First This data sheet contains preliminary Production data and supplementary data will be published at a later date. Signetics reserves the right to make changesat any time without notice in order to improve design and supply the best possible product.

No Full This data sheet contains final Identification Production specifications. Signetics reserves Noted the right to make changes at any time without notice in order to improve design and supply the best possible product.

PART NUMBERING SYSTEM

Example: SCN2661AC1 N28

S C N 2 6 1 A C 1 N_ T T T T 12 -8f

Microprocessor Division Pin Count Identifier — Always SC Basic Pa t Number 14, 16, 24, 28, 40, etc. 2621A 8031A 2622A 8035A Process/Power Variation 2636A 8039A Package N = N—Channel 2637A 8040A I= Ceramic C=C—MOS 2650A 8048A N = Plastic 13 = Bipolar 2651C 8049A 2652A 8050A Timing Variation 2653A 8051A See appropriate data sheet 2661A 80C35 26616 80C39 2661C 80C40 Temperature 2670A 80048 C =0°C to +70°C 26706 80C49 (Commercial) 2671A 80050 2672A 68000 A = — 40°C to +85°C 2673A 68120 (Automotive) 26736 68121 M = 55°C to + 125°C 26746 68230 (Military) 26756 68430 P= —20°C to +70°C 2675C 68681 (Philips) 2681A

iv Signetics Section 1 Data Communications

Signetics

MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI) SCN2651

DESCRIPTION OTHER FEATURES PIN CONFIGURATION The Signetics SCN2651 PCI is a universal • Internal or external baud rate clock synchronous/asynchronous data commu- • 16 internal rates-50 to 19,200 baud D2 nications controller chip designed for mi- • Double buttered transmitter and re- crocomputer systems. It interfaces direct- ceiver D3 D5 ly to the Signetics SCN2650 microproces- • Full or half duplex operation RxD VCC sor and may be used in a polled or inter- • Fully compatible with 2650 CPU GND RxC rupt driven system environment. The • TTL compatible inputs and outputs DTR SCN2651 accepts programmed instruc- • Single 5V power supply 04 tions from the microprocessor and sup- • No system clock required D5 RTS ports many serial data communication • 28-pin dual in-line package 06 DSR disciplines, synchronous and asyn- D7 RESET chronous, in the full or half-duplex mode. TxC BRCLK The PCI serializes parallel data characters APPLICATIONS Al TxD received from the microprocessor for • Intelligent terminals transmission. Simultaneously, it can • Network processors CE TxEMT/DSCHG receive serial data and convert it into • Front end processors Ao CTS parallel data characters for input to the • Remote data concentrators R/W DCD microcomputer. • Computer to computer links • Serial peripherals RxRDY TxRDY The SCN2651 contains a baud rate generator which can be programmed to either TOP VIEW accept an external clock or to generate internal transmit or receive clocks. Sixteen different baud rates can be selected under PIN DESIGNATION program control when operating in the in- PIN NO. ternal clock mode. SYMBOL NAME AND FUNCTION TYPE The PCI is constructed using Signetics 27,28,1,2, 5-8 Do-Di 8-bit data bus I/O n-channel silicon gate depletion load tech- 21 RESET Reset I nology and is packaged in a 28-pin DIP. 12,10 Ao-Al Internal register select lines I 13 R/W Read or write command I FEATURES 11 CE Chip enable input I • Synchronous operation 22 DSR Data set ready I 5 to 8-bit characters 24 DTR Data terminal ready 0 Single or double SYN operation 23 RTS Request to send 0 Internal character synchronization 17 CTS Clear to send I Transparent or non-transparent mode 16 DCD Data carrier detected I Automatic SYN or DLE-SYN insertion 18 TxEMT/DSCHG Transmitter empty or data set change 0 SYN or DLE stripping 9 TxC Transmitter clock I/O Odd, even, or no parity 25 RxC Receiver clock I/O Local or remote maintenance loop 19 TxD Transmitter data 0 RxD Receiver data I back mode 3 Baud rate: dc to 1M bps (1X clock) 15 TxRDY Transmitter ready 0 14 RxRDY Receiver ready 0 • Asynchronous operation 20 BRCLK Baud rate generator clock I 5 to 8-bit characters 26 Vcc +5V supply I 1, 1 1/2 or 2 stop bits 4 GND Ground I Odd, even, or no parity Parity, overrun and framing error detection Line break detection and generation ORDERING CODE False start bit detection Vcc = 5V :..: 5% Automatic serial echo mode PACKAGES COMMERCIAL AUTOMOTIVE MILITARY Local or remote maintenance loop back mode 0°C to +70°C —40°C to +85°C —55°C to +125°C Baud rate: dc to 1M bps (1X clock) Ceramic DIP SCN2651CC1128 SCN2651CA1128 SCN2651CM1128 de to 62.5K bps (16X clock) Contact Factory Not Available dc to 15.625K bps (64X clock) Plastic DIP SCN2651CC1N28

Signetics 1.1 MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI) SCN2651

Table 1 BAUD RATE GENERATOR CHARACTERISTICS CRYSTAL FREQUENCY = 5.0688MHz

THEORETICAL ACTUAL BAUD FREQUENCY FREQUENCY PERCENT RATE 16X CLOCK 16X CLOCK ERROR DIVISOR

50 0.8 KHz 0.8 KHz -- 6336 75 1.2 1.2 -- 4224 110 1.76 1.76 -- 2880 134.5 2.152 2.1523 0.016 2355 150 2.4 2.4 -- 2112 300 4.8 4.8 -- 1056 600 9.6 9.6 -- 528 1200 19.2 19.2 -- 264 1800 28.8 28.8 -- 176 2000 32.0 32.081 0.253 , 158 2400 38.4 38.4 -- 132 3600 57.6 57.6 -- 88 4800 76.8 76.8 -- 66 7200 115.2 115.2 -- 44 9600 153.6 153.6 -- 33 19200 " 307.2 316.8 3.125 16

NOTE "Error at 19200 can be reduced to zero by using crystal frequency 4.9152MHz 16X clock is used in asynchronous mode. In synchronous mode, clock multiplier is 1X.

Table 2 CPU-RELATED SIGNALS

PIN NAME PIN NO. INPUT/OUTPUT FUNCTION

Vcc 26 I +5V supply input GND 4 I Ground RESET 21 I A high on this input performs a master reset on the SCN2651. This signal asynchronously terminates any device activity and clears the Mode, Command and Status registers. The device assumes the idle state and remains there until initialized with the appropriate control words. Ai-A0 10,12 I Address lines used to select internal PCI registers. R/W 13 I Read command when low, write command when high. CE 11 I Chip enable command. When low, indicates that control and data lines to the PCI are valid and that the operation specified by the R/W, Al and Ao inputs should be performed. When high, places the Do-D7 lines in the tri-state condition. D7-Do 8,7,6,5, I/O 8-bit, three-state data bus used to transfer commands, data and status between PCI 2,1,28,27 and the CPU. Do is the least significant bit; D7 the most significant bit. TxRDY 15 0 This output is the complement of Status Register bit SRO. When low, it indicates that the Transmit Data Holding Register (THR) is ready to accept a data character from the CPU. It goes high when the data character is loaded. This output is valid only when the transmitter is enabled. It is an open drain output which can be used as an interrupt to the CPU. RxRDY 14 0 This output is the complement of Status Register bit SR1. When low, it indicates that the Receive Data Holding Register (RHR) has a character ready for input to the CPU. It goes high when the RHR is read by the CPU, and also when the receiver is disabled. It is an open drain output which can be used as an interrupt to the CPU. TxEMT/DSCHG 18 0 This output is the complement of Status Register bit SR2. When low, it indicates that the transmitter has completed serialization of the last character loaded by the CPU, or that a change of state of the DSR or DCD inputs has occurred. This output goes high when the Status Register is read by the CPU, if the TxEMT condition does not exist. Otherwise, the THR must be loaded by the CPU for this line to go high. It is an open drain output which can be used as an interrupt to the CPU.

1.2 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI) SCN2651

BLOCK DIAGRAM

SYN/DLE CONTROL DATA BUS DATA BUS D5-D7 BUFFER SYN 1 REGISTER (27, 28,1, 2, 5, 6, 7, 8) SYN 2 REGISTER

DLE REGISTER

OPERATION CONTROL (21) RESET (12) A0 MODE REGISTER 1 (10) Al MODE REGISTER 2 (15) TRANSMITTER TxRDY (13) 0 ► 61W (11) COMMAND REGISTER CE STATUS REGISTER TRANSMIT DATA HOLDING REGISTER (19) TRANSMIT TxD SHIFT REGISTER

(20) BRCLK BAUD RATE TxC (9) GENERATOR AND (14) CLOCK CONTROL RxRDY RxC (25) RECEIVER

RECEIVE SHIFT REGISTER (3) RECEIVE DATA RxD (22) HOLDING REGISTER DSR 0 (16) DCD 1 0 (17) CTS 0 MODEM (23) RTS CONTROL (26) DTR (24) VCC (18 (4) TxEMT/ GND DSCHG

BLOCK DIAGRAM Timing Modem Control The PCI consists of six major sections. The PCI contains a Baud Rate Generator The modem control section provides inter- These are the transmitter, receiver, timing, (BRG) which is programmable to accept ex- facing for three input signals and three out- operation control, modem control and ternal transmit or receive clocks or to divide put signals used for "handshaking" and sta- SYN/DLE control. These sections commu- an external clock to perform data communi- tus indication between the CPU and a nicate with each other via an internal data cations. The unit can generate 16 common- modem. bus and an internal control bus. The internal ly used baud rates, any one of which can be data bus interfaces to the microprocessor selected for full duplex operation. See Table SYN/DLE Control data bus via a data bus buffer. 1. This section contains control circuitry and Receiver three 8-bit registers storing the SYN1, SYN2, and DLE characters provided by the Operation Control The Receiver accepts serial data on the RxD CPU. These registers are used in the syn- This functional block stores configuration pin, converts this serial input to parallel for- chronous mode of operation to provide the and operation commands from the CPU and mat, checks for bits or characters that are characters required for synchronization, generates appropriate signals to various in- unique to the communication technique idle fill and data transparency. ternal sections to control the overall device and sends an "assembled" character to the operation. It contains read and write circuits CPU. to permit communications with the micro- INTERFACE SIGNALS processor via the data bus and contains Transmitter The PCI interface signals can be grouped Mode Registers 1 and 2, the Command Reg- The Transmitter accepts parallel data from into two types: the CPU-related signals ister, and the Status Register. Details of reg- the CPU, converts it to a serial bit stream, in- (shown in Table 2), which interface the 2651 ister addressing and protocol are presented serts the appropriate characters or bits to the microprocessor system, and the in the PCI Programming section of this data (based on the communication technique) device-related signals (shown in Table 3), sheet. and outputs a composite serial stream of which are used to interface to the communi- data on the TxD output pin. cations device or system.

Signetics 1.3 MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI) SCN2651

Table 3 DEVICE-RELATED SIGNALS

PIN NAME PIN NO. INPUT/OUTPUT FUNCTION BRCLK 20 I 5.0688MHz clock input to the internal baud rate generator. Not required if external receiver and transmitter clocks are used. RxC 25 I/O Receiver clock. If external receiver clock is programmed, this input controls the rate at which the character is to be received. Its frequency is 1X, 16X or 64X the baud rate, as programmed by Mode Register 1. Data is sampled on the rising edge of the clock. If internal receiver clock is programmed, this pin becomes an output at 1X the programmed baud rate. * TxC 9 I/O Transmitter clock. If external transmitter clock is programmed, this input controls the rate at which the character is transmitted. Its frequency is 1X, 16X or 64X the baud rate, as programmed by Mode Register 1. The transmitted data changes on the falling edge of the clock. If internal transmitter clock is programmed, this pin becomes an output at 1X the programmed baud rate. * RxD 3 I Serial data input to the receiver. "Mark" is high, "Space" is low. TxD 19 0 Serial data output from the transmitter. "Mark" is high, "Space" is low. Held in Mark condition when the transmitter is disabled. DSR 22 I General purpose input which can be used for Data Set Ready or Ring Indicator condition. Its complement appears as Status Register bit SR7. Causes a low output on TxEMT/DSCHG when its state changes. DCD 16 I Data Carrier Detect input. Must be low in order for the receiver to operate. Its complement appears as Status Register bit SR6. Causes a low output on TxEMT/DSCHG when its state changes. CTS 17 I Clear to Send input. Must be low in order for the transmitter to operate. If it goes high during transmission, the charaCter in the Transmit Shift Register will be transmitted before termination. DTR 24 0 General purpose output which is the complement of Command Register bit CR1. Normally used to indicate Data Terminal Ready. RTS 23 0 General purpose output which is the complement of Command Register bit CR5. Normally used to indicate Request to Send.

NOTE RxC and TxC outputs have short circuit protection max. CL 100pf

OPERATION assumed and the receiver continues to sam- the hunt mode is terminated and character The functional operation of the SCN2651 ple the input line at one bit time intervals assembly mode begins. If single SYN opera- is programmed by a set of control words until the proper number of data bits, the par- tion is programmed, the SYN DETECT sta- supplied by the CPU. These control words ity bit, and the stop bit(s) have been assem- tus bit is set. If double SYN operation is specify items such as synchronous or bled. The data is then transferred to the Re- programmed, the first character assembled asynchronous mode, baud rate, number of ceive Data Holding Register, the RxRDY bit after SYN1 must be SYN2 in order for the bits per character, etc. The programming in the status register is set, and the RxRDY SYN DETECT bit to be set. Otherwise, the procedure is described in the PCI Pro- output is asserted. If the character length is PCI returns to the hunt mode. (Note that the gramming section of this data sheet. less than 8 bits, the high order unused bits in sequence SYN1-SYN1-SYN2 will not the Holding Register are set to zero. The achieve synchronization). When synchroni- After programming, the PCI is ready to per- Parity Error, Framing Error, and Overrun zation has been achieved, the PCI continues form the desired communications func- Error status bits are strobed into the status to assemble characters and transfer them to tions. The receiver performs serial to paral- register on the positive going edge of RxC the Holding Register, setting the RxRDY lel conversion of data received from a corresponding to the received character status bit and asserting the RxRDY output modem or equivalent device. The transmit- boundary. If a break condition is detected each time a character is transferred. The PE ter converts parallel data received from the (RxD is low for the entire character as well as and OE status bits are set as appropriate. CPU to a serial bit stream. These actions are the stop bit I sl), only one character consist- Further receipt of the appropriate SYN se- accomplished within the framework specifi- ing of all zeros (with the FE status bit set) will quence sets the SYN DETECT status bit. If ed by the control words. be transferred to the Holding Register. The the SYN stripping mode is commanded, RxD input must return to a high condition SYN characters are not transferred to the Receiver before a search for the next start bit begins. Holding Register. Note that the SYN charac- The SCN2651 is conditioned to receive data ters used to establish initial synchronization when the DCD input is low and the RxEN bit When the PCI is initialized into the synchro- are not transferred to the Holding Register in the command register is true. In the nous mode, the receiver first enters the hunt in any case. asynchronous mode, the receiver looks for mode on a Oto 1 transition of RxEN (CR2). In a high to low transition of the start bit on the this mode, as data is shifted into the Receiv- Transmitter RxD input line. If a transition is detected, the er Shift Register a bit ata time, the contents The PCI is conditioned to transmit data state of the RxD line is sampled again after a of the register are compared to the contents when the CTS input is low and the TxEN delay of one-half of a bit time. If RxD is now of the SYN1 register. If the two are not equal, command register bit is set. The SCN2651 high, the search fora valid start bit is begun the next bit is shifted in and the comparison indicates to the CPU that it can accept a again. If RxD is still low, a valid start bit is is repeated. When the two registers match, character for transmission by setting the

1.4 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI) SCN2651

TxRDY status bit and asserting the TxRDY INITIAL RESET output. When the CPU writes a character into the Transmit Data Holding Register, rl these conditions are negated. Data is trans- LOAD ferred from the Holding Register to the MODE REGISTER 1 Transmit Shift Register when it is idle or

has completed transmission of the previ- LOAD NOTE ous character. The TxRDY conditions are MODE REGISTER 2 Mode Register 1 must be written then asserted again. Thus, one full charac- before 2 can be written. Mode Register 2 need not be programmed if external ter time of buffering is provided. clocks are used. In the asynchronous mode, the transmitter automatically sends a start bit followed by the programmed number of data bits, the least significant bit being sent first. It then appends an optional odd or even parity bit and the programmed number of stop bits. If, NOTE SYN1 Register must be written following transmission of the data bits, a before SYN2 can be written, and new character is not available in the Trans- SYN2 before DLE can be written. mit Holding Register, the TxD output remains in the marking (high) condition and the TxEMT/DSCHG output and its corresponding status bit are asserted. Trans- mission resumes when the CPU loads a new character into the Holding Register. The N transmitter can be forced to output a continuous low (BREAK) condition by setting the Send Break command bit high. In the synchronous mode, when the SCN2651 is initially conditioned to transmit, the TxD output remains high and the

TxRDY condition is asserted until the first 11. character to be transmitted (usually a SYN r character) is loaded by the CPU. Subse- LOAD quent to this, a continuous stream of char- COMMAND REGISTER acters is transmitted. No extra bits (other than parity, if commanded) are generated r— — — — — — by the PCI unless the CPU fails to send a OPERATE new character to the PCI by the time the transmitter has completed sending the previous character. Since synchronous communication does RECONFIGURE? not allow gaps between characters, the PCI asserts TxEMT and automatically "fills" the V gap by transmitting SYN1s, SYN1-SYN2 DISABLE doublets, or DLE-SYN1 doublets, depend- RCVR AND XMTR ing on the state of MR16 and MR17. Normal transmission of the message resumes when a new character is available in the Transmit Figure 1. 2651 Initialization Flow Chart Data Holding Register. If the SEND DLE bit in the command register is true, the DLE character is automatically transmitted prior Table 4 2651 REGISTER ADDRESSING to transmission of the message character in THR. CE Al Ao ii/W FUNCTION PCI PROGRAMMING Prior to initiating data communications, the 1 X X X Tri-state data bus SCN2651 operational mode must be pro- 0 0 0 0 Read receive holding register grammed by performing write operations to 0 0 0 1 Write transmit holding register the mode and command registers. In addi- 0 0 1 0 Read status register tion, if synchronous operation is pro- 0 0 1 1 Write SYN1/SYN2/DLE registers grammed, the appropriate SYN/DLE regis- 0 1 0 0 Read mode registers 1/2 1/2 ters must be loaded. The PCI can be 0 1 0 1 Write mode registers reconfigured at any time during program 0 1 1 0 Read command register execution. However, if the change has an 0 1 1 1 Write command register effect on the reception of a character the NOTE receiver should be disabled. Alternatively if See AC Characteristics section for timing requirements. Signetics 1.5 MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI) SCN2651

the change is made 11/2 RxC periods after 1 and 2 define the general operational In asychronous mode, MR17 and MR16 RxRDY goes active it will affect the next characteristics of the PCI, while the Com- select character framing of 1, 1.5, or 2 stop character assembly. A flowchart of the in- mand Register controls the operation with- bits. (If 1X baud rate is programmed, 1.5 stop itialization process appears in Figure 1. in this basic frame-work. The PCI indicates bits defaults to 1 stop bits on transmit). In synchronous mode, MR17 controls the The internal registers of the PCI are ac- its status in the Status Register. these number of SYN characters used to establish cessed by applying specific signals to the registers are cleared when a RESET input is synchronization and for character fill when CE, R/W, Al and Ao inputs. The conditions applied. the transmitter is idle. SYN1 alone is used if necessary to address each register are Mode Register 1 (MR1) MR17 = 1, and SYN1-SYN2 is used when shown in Table 4. Table 5 illustrates Mode Register 1. Bits MR17 = 0. If the transparent mode is speci- The SYN1, SYN2, and DLE registers are MR11 and MR10 select the communication fied by MR16, DLE-SYN1 is used for char- accessed by performing write operations format and baud rate multiplier. 00 specifies acter fill and SYN Detect, but the normal with the conditions Ai =0, Ao= 1 , and R/W= synchronous mode and 1X multiplier. 1X, synchronization sequence is used. Also 1. The first operation loads the SYN1 regis- 16X, and 64X multipliers are programmable DLE stripping and DLE Detect (with MR14 = ter. The next loads the SYN2 register, and for asynchronous format. However, the 0) are enabled. the third loads the DLE register. Reading or multiplier in asynchronous format applies loading the mode registers is done in a only if the external clock input option is Mode Register 2 (MR2) similar manner. The first write (or read) selected by MR24 or MR25. Table 6 illustrates Mode Register 2. MR23, operation addresses Mode Register 1, and a MR22, MR21, and MR20 control the fre- subsequent operation addresses Mode Reg- MR13 and MR12 select a character length of quency of the internal baud rate generator ister 2. If more than the required number of 5, 6, 7, or 8 bits. The character length does (BRG). Sixteen rates are selectable. When accesses are made, the internal sequencer not include the parity bit, if programmed, driven by a 5.0688 MHz input at the BRCLK recycles to point at the first register. The and does not include the start and stop bits input (pin 20), the BRG output has zero error pointers are reset to SYN1 Register and in asynchronous mode. except at 134.5, 2000, and 19,200 baud, Mode Register 1 by a RESET input or by MR14 controls parity generation. If enabled, which have errors of +0.016%, +0.235%, and performing a "Read Command Register" a parity bit is added to the transmitted +3.125% respectively. operation, but are unaffected by any other character and the receiver performs a parity MR25 and MR24 select either the BRG or the read or write operation. check on incoming data. MR15 selects odd external inputs TxC and RxC as the clock The SCN2651 register formats are summar- or even parity when parity is enabled by source for the transmitter and receiver, ized in Tables 5, 6, 7 and 8. Mode Registers MR14. respectively. If the BRG clock is selected,

Table 5 MODE REGISTER 1 (MR1)

MR17 MR16 MR15 MR14 MR13 MR12 MR11 MR10

Parity Type Parity Control Character Length Mode and Baud Rate Factor

ASYNCH: STOP BIT LENGTH 00 = INVALID 0 = ODD 0 = DISABLED 00 = 5 BITS 00 = SYNCHRONOUS 1X RATE 01 = 1 STOP BIT 1 = EVEN 1 = ENABLED 01 = 6 BITS 01 = ASYNCHRONOUS 1X RATE 10 = 11/2 STOP BITS 10 = 7 BITS 10 = ASYNCHRONOUS 16X RATE 11 = 2 STOP BITS 11 = 8 BITS 11 = ASYNCHRONOUS 64X RATE

SYNCH: NUMBER SYNCH: TRANS- OF SYN CHAR PARENCY CONTROL 0 = DOUBLE SYN 0 = NORMAL 1 = SINGLE SYN 1 = TRANSPARENT

NOTE Baud rate factor in asynchronous applies only if external clock is selected. Factor is 16X if internal clock is selected. Mode must be selected IMR11, MR101 in any case. Table 6 MODE REGISTER 2 (MR2)

MR27 MR26 MR25 MR24 MR23 MR22 MR21 MR20

Transmitter Receiver Baud Rate Selection Clock Clock 0 = EXTERNAL 0 = EXTERNAL 0000 = 50 BAUD 1000 = 1800 BAUD NOT USED 1 = INTERNAL 1 = INTERNAL 0001 = 75 1001 = 2000 0010 = 110 1010 = 2400 0011 = 134.5 1011 = 3600 0100 = 150 1100 = 4800 0101 = 300 1101 = 7200 0110 = 600 1110 = 9600 0111 = 1200 1111 = 19,200

1.6 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI) SCN2651

the baud rate factor in asynchronous mode sub-mode is determined by CR7 and CR6. SYN Detect status bits (SR3 and SR5). is 16X regardless of the factor selected by CR7-CR6 = 00 is the normal mode, with the Two diagnostic sub-modes can also be MR11 and MR10. In addition, the corre- transmitter and receiver operating inde- configured. In Local Loop Back mode sponding clock pin provides an output at lx pendently in accordance with the Mode and (CR7-CR6 = 10), the following loops are the baud rate. Status Register instructions. connected internally: In asynchronous mode, CR7-CR6 = 01 Command Register (CR) places the PCI in the Automatic Echo mode. 1. The transmitter output is connected to the Table 7 illustrates Command Register. Bits Clocked, regenerated received data is auto- receiver input. CR0 (TxEN) and CR2 (RxEN) enable or matically directed to the TxD line while 2. DTR is connected to DCD and RTS is connect- disable the transmitter and receiver respec- normal receiver operation continues. The ed to CTS. tively. A 0 to 1 transition of CR2 forces start receiver must be enabled (CR2 = 1), but the 3. The receiver is clocked by the transmit clock. 4. bit search (async mode) or hunt mode (sync transmitter need not be enabled. CPU to The DTR, RTS and TxD outputs are held high. mode) on the second RxC rising edge. Dis- 5. The CTS, DTD, DSR and RxD inputs are ig- receiver communications continues nor- nored. abling the receiver causes RxRDY to go mally, but the CPU to transmitter link is high (inactive). If the transmitter is disabled, disabled. Only the first character of a break Additional requirements to operate in the it will complete the transmission of the condition is echoed. The TxD output will go Local Loop Back mode are that CR0 (TxEN), character in the Transmit Shift Register (if high until the next valid start is detected. CR1 (DTR), and CR5 (RTS) must be set to 1. any) prior to terminating operation. The TxD The following conditions are true while in CR2 (RxEN) is ignored by the PCI. output will then remain in the marking state Automatic Echo mode: The second diagnostic mode is the Remote (high) while the TxRDY and TxEMT will go 1. Data assembled by the receiver is automatically Loop Back mode (CR7-CR6 = 11). In this high (inactive). If the receiver is disabled, it placed in the Transmit Holding Register and mode: will terminate operation immediately. Any retransmitted by the transmitter on the TxD character being assembled will be neglect- output. 1. Data assembled by the receiver is automatically The transmitter is clocked by the receive clock. ed. 2. placed in the Transmit Holding Register and 3. TxRDY output = 1. retransmitted by the transmitter on the TxD Bits CR1 (DTR) and CR5 (RTS) control the 4. The TxEMT/DSCHG pin will reflect only the output. DTR and RTS outputs. Data at the outputs is data set change condition. 2. The transmitter is clocked by the receive clock. the logical complement of the register data. 5. The TxEN command (CROI is ignored. 3. No data is sent to the local CPU, but the error In synchronous mode, CR7-CR6 = 01 status conditions (PE, OE, FE) are set. In asynchronous mode, setting CR3 will places the PCI in the Automatic SYN/DLE 4. The RxRDY, TxRDY, and TxEMT/DSCHG out- force and hold the TxD output low (spacing Stripping mode. The exact action taken puts are held high. condition) at the end of the current transmit- 5. CR1 (TxEN) is ignored. depends on the setting of bits MR17 and 6. All other signals operate normally. ted character. Normal operation resumes MR16: when CR3 is cleared. The TxD line will go Status Register high for a least one bit time before begin- 1. In the non-transparent, single SYN mode ning transmission of the next character in (MR17-MR16 = 10), characters in the data The data contained in the Status Register the Transmit Data Holding Register. In syn- stream matching SYN1 are not transferred to (as shown in Table 8) indicate receiver and the Receive Data Holding Register (RHR). chronous mode, setting CR3 causes the transmitter conditions and modem/data set 2. In the non-transparent, double SYN mode status. transmission of the DLE register contents (MR17-MR16 = 00), characters in the data prior to sending the character in the Trans- stream matching SYN1, or SYN2 if immediately SRO is the Transmitter Ready (TxRDY) sta- mit Data Holding Register. CR3 should be preceded by SYN1, are not transferred to the tus bit. It, and its corresponding output, are reset in response to the next TxRDY. RHR. However, only the f irst SYN1 of an SYN 1- valid only when the transmitter is enabled. If SYN1 pair is stripped. equal to 0, it indicates that the Transmit Setting CR4 causes the error flags in the 3. In transparent mode (MR16 =1), characters in Data Holding Register has been loaded by Status Register (SR3, SR4, and SR5) to be the data stream matching DLE, or SYN1 if the CPU and the data has not been trans- cleared. This is a one time command. There immediately preceded by DLE, are not transferred to the Transmit Shift Register. If set is no internal latch for this bit. ferred to the RHR. However, only the first DLE equal to 1, it indicates that the Holding of a OLE-DLE pair is stripped. The PCI can operate in one of four sub- Register is ready to accept data from the modes within each major mode (synchro- Note that Automatic Stripping mode does CPU. This bit is initially set when the Trans- nous or asynchronous). The operational not affect the setting of the DLE Detect and mitter is enabled by CRO, unless a character Table 7 COMMAND REG STER (CR)

CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 Request to Receive Data Terminal Transmit Operating Mode Reset Error Send Control (RxEN) Ready Control (TxEN) ASYNCH: 00 = NORMAL OPERATION 0 = NORMAL FORCE BREAK 01 = ASYNCH: AUTOMATIC 0 = FORCE RTS 1 = RESET 0 = NORMAL 0 = DISABLE 0 = FORCE DTR 0 = DISABLE ECHO MODE OUTPUT HIGH ERROR FLAG 1 = FORCE 1 = ENABLE OUTPUT HIGH 1 = ENABLE SYNCH: SYN AND/OR 1 = FORCE RTS IN STATUS REG BREAK 1 = FORCE DTR DLE STRIPPING MODE OUTPUT LOW (FE, OE, SYNCH: OUTPUT LOW 10 = LOCAL LOOP BACK PE/DLE DETECT) SEND DLE 11 = REMOTE LOOP BACK 0 = NORMAL 1 = SEND DLE Signelics 1.7 MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI) SCN2651

Table 8 STATUS REGISTER (SR) SR7 SR6 SR5 SR4 SR3 SR2 SR1 SRO Data Set Data Carrier FE/SYN Detect Overrrun PE/DLE Detect TxEMT/DSCHG RxRDY TxRDY Ready Detect 0 = DSR INPUT 0 = DCD INPUT ASYNCH: 0 = NORMAL 0 = NORMAL 0 = RECEIVE 0 = TRANSMIT IS HIGH IS HIGH 0 = NORMAL 1 = OVERRUN ASYNCH: 1 = CHANGE HOLDING REG HOLDING 1 = DSR INPUT 1 =DCD INPUT 1 = FRAMING ERROR 0 = NORMAL IN DSR OR EMPTY REG BUSY IS LOW IS LOW ERROR 1 = PARITY DCD, OR 1 = RECEIVE 1 = TRANSMIT ERROR TRANSMIT HOLDING REG HOLDING SYNCH: SHIFT REGIS- HAS DATA REG EMPTY 0 = NORMAL SYNCH: TER IS 1 = SYN CHAR 0 = NORMAL EMPTY DETECTED 1 = PARITY ERROR OR DLE CHAR RECEIVED has previously been loaded into the Holding ister. Note that in synchronous mode this bit when the receiver is disabled and by the Register. It is not set when the Automatic will be set even though the appropriate "fill" Reset Error command, CR4. Echo or Remote Loop Back modes are character is transmitted. TxEMT will not go In asynchronous mode, bit SR5 signifies programmed. When this bit is set, the active until at least one character has been that the received character was not framed TxRDY output pin is low. In the Automatic transmitted. It is cleared by loading the by the programmed number of stop bits. (If Echo and Remote Loop Back modes, the Transmit Data Holding Register. The 1.5 stop bits are programmed, only the first DSCHG condition is enabled when TxEN=1 output is held high. stop bit is checked.) If RHR =0 when SR5 =1 or RxEN=1. It is cleared when the Status a break condition is present. In synchro- SR1, the Receiver Ready (RxRDY) status bit, Register is read by the CPU. When SR2 is nous non-transparent mode (MR16 = 0), it indicates the condition of the Receive Data set, the TxEMT/DSCHG output is low. indicates receipt of the SYN1 character is Holding Register. If set, it indicates that a single SYN mode or the SYN1-SYN2 pair in character has been loaded into the Holding SR3, when set, indicates a received parity double SYN mode. In synchronous trans- Register from the Receive Shift Register and error when parity is enabled by MR14. In parent mode (MR16 = 1), this bit is set upon is ready to be read by the CPU. If equal to synchronous transparent mode (MR16 -= 1), detection of the initial synchronizing char- zero, there is no new character in the Hold- with parity disabled, it indicates that a characters (SYN1 or SYN1-SYN2) and, after ing Register. This bit is cleared when the acter matching the DLE Register has been synchronization has been achieved, when a CPU reads the Receive Data Holding Regis- received. However, only the first DLE of two DLE-SYN1 pair is received. The bit is reset ter or when the receiver is disabled by CR2. successive DLEs will set SR3. This bit is when the receiver is disabled, when the When set, the RxRDY output is low. cleared when the receiver is disabled and by Reset Error command is given in asynchro- the Reset Error command, CR4. nous mode, and when the Status Register is The TxEMT/DSCHG bit, SR2, when set, read by the CPU in the synchronous mode. indicates either a change of state of the DSR The Overrun Error status bit, SR4, indicates or DCD inputs or that the Transmit Shift that the previous character loaded into the SR6 and SR7 reflect the conditions of the Register has completed transmission of a Receive Holding Register was not read by DCD and DSR inputs respectively. A low character and no new character has been the CPU at the time a new received charac- input sets its corresponding status bit and a loaded into the Transmit Data Holding Reg- ter was transferred into it. This bit is cleared high input clears it.

DC ELECTRICAL CHARACTERISTICS4,5,6

LIMITS PARAMETER TEST CONDITIONS UNIT Min Typ Max Input voltage V VIL Low 0.8 VIH High 2.0 Output voltage V VOL Low IOL = 1.6mA 0.4 VOH High lou = -100µA 2.4 IL Input leakage current VIN = 0 to 5.25V -10 10 µA Tristate Output leakage current µA ILH Data bus high Vo = 4.0V -10 10 ILL Data bus low Vo = 0.45V -10 10 Icc Power supply current 150 mA

1.8 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI) SCN2651

ABSOLUTE MAXIMUM RATINGS'

PARAMETEF RATING UNIT

Operating ambient temperature2 Note 4 °C Storage temperature -65 to +150 °C All voltages with respect to ground3 -0.5 to +6.0 V

AC ELECTRICAL CHARACTERISTICS4,5,6 LIMITS PARAMETER TEST CONDITIONS UNIT Min Typ Max Pulse width ns tRES Reset 1000 tcE Chip enable 300 Setup and hold time ns tAS Address setup 20 tAH Address hold 20 tcs R/W control setup 20 tCH R/W control hold 20 tos Data setup for write 225 tDH Data hold for write 0 taxs Rx data setup 300 taxi-1 Rx data hold 350 too Data delay time for read CL = 100pF 250 ns tDF Data bus floating time for read CL = 100pF 150 ns tcED CE to CE delay 700 ns

Input clock frequency MHz fBRG Baud rate generator 1.0 5.0688 5.0738 frifr io TxC or RxC dc 1.0 Clock width ns tBRH 9 Baud rate high 70 tBRL9 Baud rate low 70 tR/TH TxC or RxC high 500 tR/TL10 TxC or RxC low 500 tTXD TxD delay from falling edge of TxC CL = 100pF 650 ns tTCS Skew between TxD changing and falling CL = 100pF 0 ns edge of TxC outputs

NOTES 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operation section of this specification is not implied. 2 For operating at elevated temperatures, the device must be derated based on +150'C maximum junction temperature. 3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. 4. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature range and operating supply range. 5. All voltage measurements are referenced to ground. All time measurements are at the 50% level for inputs (except tBRH and TBRL) and at 0.8V and 2.0V for outputs. Input levels for testing are 0.45V and 2.4V 6. Typical values are at + 25'C, typical supply voltages and typical processing parameters. 7. TxRDY, RxRDY and TxEMTIDSCHG outputs are open drain. 8. Parameter applies when internal transmitter clock is used. 9. Under test conditions of 5.0688MHz fBRG.IBRH and IBRL measured at VIH and VIL respectively. 10. 1R/T and tRITL shown for all modes except local loopback. For local loopback mode fRn- = 0.7MHz and tRiTL. 700ns min.

Signetics 1.9 MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI) SCN2651

CAPACITANCE TA = 25°C, Vcc = OV

LIMITS PARAMETER TEST CONDITIONS UNIT Min Typ Max

Capacitance pF CIN Input 20 fc = 1MHz COUT Output Unmeasured pins tied 20 to ground Clio Input/Output 20

TIMING DIAGRAMS

RESET CLOCK

tom.

RESET tRES BRCLK, TxC, RxC—i mean

TRANSMIT RECEIVE

1 BIT TIME (1, 16, OR 64 CLOCK PERIODS)--" TxC (INPUT) RxD

tRxS 41)01--4- TxD A_. F77C (IX) ITxD tTxD

tTCS TxC (OUTPUT) /

1-10 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI) SCN2651

TIMING DIAGRAMS (Cont'd)

TxRDY, TxEMT (Shown for 5-bit characters, no parity, 2 stop bits I in asynchronous mode I )

TxC (IX)

I1,213, 4 5 4 1 5 1 112 1 3,415 2 1 1, 24,5 1 1 2,3,4,5 1, 2,3 1 TxD DATA 1 DATA DATA 4 I DATA 3 ST"

TxEN . O x N TxRDY HRON 0

YNC TxEMT S

CE FOR WRITE OF THR DATA 1 DATA 2 DATA 3 DATA 4

1 2 D A 1 1 2 , 3 , 4, 5 B C A I I 2 1 3 1 4 1 5 B C A 1 , 2 1 3 1 4 1 5 B C D A TxD DATA 1 DATA 2 DATA 3 DATA 4

Ia TxEN M S OU TxRDY ON NCHR TxEMT ASY

CE FOR WRITE OF THR DATA 1 DATA 2 DATA 3 DATA 4 NOTES A = Start bit B = Stop bit 1 C = Stop bit 2 = TxD marking condition TxEMT goes low at the beginning of the last data bit, or, if parity is enabled, at the beginning of the parity bit.

READ AND WRITE

ICE tCED

Ao, Al

tAS tAH—." •)( RI W

tCH

Do-D7 (WRITE)

t DS r.---I"

Do-D7 V NOT BUS y DATA VALID X BUS FLOATING (READ) FLOATING A VALID s

Signetics

MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI) SCN2651

TIMING DIAGRAMS (Cont'd)

RxRDY (Shown for 5-bit characters, no parity, 2 stop bits in asynchronous mode I 71=Llillilf litThfilinThILFLIFLUMILUIFLUIL 1 1 2 1 3 i 4 5 2 1 31 4 1 5 1 2 3 4 5 1 2 3 4 5 1 1 2 3 1 4 1 5 1 1 2 1 3 1 4 5

RxD SYN 1 DATA 1 DATA 2 DATA 3 DATA 4 DATA 5

IGNORED RxEN DE

S MO SYNDET STATUS BIT NOU RO

CH RxRDY SYN

CE FOR READ READ READ READ READ READ READ STATUS STATUS RHR RHR RHR RHR (DATA 1) (DATA 2) (DATA 3) (DATA 3)

/ D 2 3 4 5 B 1 C 2 1 3 1 4 1 5 B I — I DI 1 2 3 4 5 BIC A 1 2 3 RxD DATA 1 DATA 2 DATA 3 DATA 4

MODE RxEN OUS

AxADY YNCHRON

S OVERRUN A STATUS BIT

CE FOR READ READ READ RHR RHR (DATA 1) (DATA 3)

NOTES A = Start bit = Stop bit 1 C = Stop bit 2 D = TxD marking condition

1.12 Signelics MICROPROCESSOR DIVISION JANUARY 1983

PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI) SCN2651

TYPICAL APPLICATIONS

ASYNCHRONOUS INTERFACE TO CRT TERMINAL

ADDRESS BUS

CONTROL BUS \--, 1

DATA BUS

/ \

vv r 1 RxD EIA TO TTL I CONVERT I TxD r (OPT) I SCN2651 L J

BRCLK 5.0688MHz CRT OSCILLATOR TERMINAL

ASYNCHRONOUS INTERFACE TO TELEPHONE LINES

ADDRESS BUS

L CONTROL BUS

C DATA BUS

'\7 vv RxD SCN2851 TO

DSR o- r PHONE LINE ASYNC INTERFACE DTR 0 r MODEM

CTS 0- i RTS 0 ► DCD 0-4

BRCLK -0 5.0688MHz OSCILLATOR TELEPHONE LINE

Signetics 1.13 MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI) SCN2651

TYPICAL APPLICATIONS (Cont'd)

SYNCHRONOUS INTERFACE TO TERMINAL OR PERIPHERAL DEVICE

ADDRESS BUS

L CONTROL BUS

DATA BUS

\ 7 \ 7 RxD

SCN2651 TxD SYNCHRONOUS RxC -4 TERMINAL OR PERIPHERAL TxC 4 DEVICE

SYNCHRONOUS INTERFACE TO TELEPHONE LINES

ADDRESS BUS

CONTROL BUS

DATA BUS

v \ 7 RxD SCN2651 TxD

RxC -4 PHONE LINE TxC t INTERFACE SYNC DCD 0 A MODEM

CTS 0.4 RTS 0

DSR Q

DTR 0

TELEPHONE LINE

Manufacturer reserves the right to make design and process changes and improvements.

1.14 Signetics MICROPROCESSOR DIVISION JANUARY 1983

MULTI-PROTOCOL COMMUNICATIONS CONTROLLER SCN26521SCN68652

DESCRIPTION comparison for BCP-BOP PIN CONFIGURATION The SCN2652/68652 Multi-Protocol Commu- Idle transmission of SYNC/FLAG or nications Controller (MPCC) is a monolithic MARK for BCP-BOP CE MM n-channel MOS LSI circuit that formats, • Automatic detection and generation of transmits and receives synchronous serial special BOP control sequences, i.e., RxC TxC data while supporting bit-oriented or byte FLAG, ABORT, GA RxSI TxSO • Zero insertion and deletion for BOP control protocols. The chip is TTL compat- SIF TxE ible, operates from a single +5V supply, • Short character detection for last BOP TxU and can interface to a processor with an 8 data character RxA or 16-bit bidirectional data bus. • SYNC generation, detection, and strip- RxDA TxBE ping for BCP FEATURES RxSA TxA • Maintenance Mode for self-testing • DC to 1Mbps or 2Mbps data rate RxE RESET • TTL compatible • Bit-oriented protocols (BOP): SDLC, • Single +5V supply GND VCC ADCCP, HDLC • Byte-control protocols (BCP): DDCMP, APPLICATIONS DB08 DB00 BISYNC (external CRC) • Intelligent terminals DB09 DB01 • Programmable operation • Line controllers 01310 DB02 8 or 16-bit tri-state data bus • Network processors DB11 DB03 Error control—CRC or VRC or none • Front end communications Character length-1 to 8 bits for BOP • Remote data concentrators DB12 DB04 or 5 to 8 bits for BCP • Communication test equipment DB13 DB05 SYNC or secondary station address • Computer to computer links DB14 DBO6

ORDERING CODE DB15 DB07

Vec . 5V -i- 5% 14/W DBEN

PACKAGES COMMERCIAL AUTOMOTIVE MILITARY A2 BYTE

0°C to +70°C —40°C to +85°C —55°C to +125°C Al AO 1MHz SCN2652AC1140 SCN2652AA1140 SCN2652AM1140 Ceramic DIP TOP VIEW 2MHz SCN2652AC2140 SCN2652AA2140 SCN2652AM2140 NOTE 1MHz SCN2652AC1N40 Contact Factory Not Available 00 is least significant bit. highest number (that is. Plastic DIP DB15, A2) is most significant bit. 2MHz SCN2652AC2N40 Contact Factory Not Available

NOTE: SCN68652 is identical to SCN2652. Order using part numbers shown above. BLOCK DIAGRAM

6 BITS *--8 BITS VCC PARAMETER CONTROL PARAMETER DATA SYNC/ADDRESS PCSAR CONTROL PCR GND Dggio< BUS REGISTER REGISTER BUFFER

RECEIVER TRANSMITTER DATA/STATUS RDSR DATA/STATUS TDSR REGISTER REGISTER

RESET

INTERNAL 6 BUS 6 A2-A0

BYTE READ/ RIW WRITE LOGIC CE AND RECE VER TRANSMITTER CONTROL LOGIC AND LOGIC AND DBEN CONTROL CONTROL

SIF RxE RxA RxDA RxC RxSI TxC TxSO RxSA

TxE TxA TxBE TxU Signetics 1.15 MICROPROCESSOR DIVISION JANUARY 1983 MULTI-PROTOCOL COMMUNICATIONS CONTROLLER SCN26521SCN68652

PIN DESIGNATION

MNEMONIC PIN NO. TYPE NAME AND FUNCTION

DB15-DBOO 17-10 I/O Data Bus: DB07-DBOO contain bidirectional data while DB15-DB08 contain control and status 24-31 information to or from the processor. Corresponding bits of the high and low order bytes can be WIRE OR'ed onto an 8-bit bus. The data bus is floating if either CE or DBEN are low. A2-A0 19-21 I Address Bus: A2-A0 select internal registers. The four 16-bit registers can be addressed on a word or byte basis. See Register Address section. BYTE 22 I Byte: Single byte (8 bit) data bus transfers are specified when this input is high. A low level specifies 16 bit data bus transfers. CE 1 I Chip Enable: A high input permits a data bus operation when DBEN is activated. R/W 18 I Read/Write: R/W controls the direction of data bus transfer. When high, the data is to be loaded into the addressed register. A low input causes the contents of the addressed register to be presented on the data bus. DBEN 23 I Data Bus Enable: After A2-A0, CE, BYTE and R/W are set up, DBEN may be strobed. During a read, the 3-state data bus (DB) is enabled with information for the processor. During a write, the stable data is loaded into the addressed register and TxBE will be reset if TDSR was addressed. RESET 33 I Reset: A high level initializes all internal registers (to zero) and timing. MM 40 I Maintenance Mode: MM internally gates TxSO back to RxSI and TxC to RxC for off line diagnostic purposes. The RxC and RxSI inputs are disabled and TxSO is high when MM is asserted. RxE 8 I Receiver Enable: A high level input permits the processing of RxSI data. A low level disables the receiver logic and initializes all receiver registers and timing. RxA 5 0 Receiver Active: RxA is asserted when the first data character of a message is ready for the processor. In the BOP mode this character is the address. The received address must match the secondary station address if the MPCC is a secondary station. In BCP mode, if strip-SYNC (PCSAR is) is set, the first non-SYNC character is the first data character; if strip-SYNC is zero, the character following the second SYNC is the first data character. In the BOP mode, the closing FLAG resets RxA. In the BCP mode, RxA is reset by a low level at RxE. RxDA* 6 0 Receiver Data Available: RxDA is asserted when an assembled character is in RDSRL and is ready to be presented to the processor. This output is reset when RDSRL is read. RxC 2 I Receiver Clock: RxC (1X) provides timing for the receiver logic. The positive going edge shifts serial data into the RxSR from RxSI. S/F 4 O SYNC/FLAG: S/F is asserted for one RxC clock time when a SYNC or FLAG ,character is detected. RxSA* 7 0 Receiver Status Available: RxSA is asserted when there is a zero to one transition of any bit in RDSRH except for RSOM. It is cleared when RDSRH is read. RxSI 3 I Receiver Serial Input: RxSI is the received serial data. Mark = '1', space = '0'. TxE 37 I Transmitter Enable: A high level input enables the transmitter data path between TDSRL and TxSO. At the end of a message, a low level input causes TxSO = 1 (mark) and TxA = 0 after the closing FLAG (BOP) or last character (BCP) is output on TxSO. TxA 34 0 Transmitter Active: TxA is asserted after TSOM (TDSIRs) is set and TxE is raised. This output will reset when TxE is low and the closing FLAG IBOPI or last character (BCP) has been output on TxSO. TxBE" 35 0 Transmitter Buffer Empty: TxBE is asserted when the TDSR is ready to be loaded with new control information or data. The processor should respond by loading the TDSR which resets TxBE. TxU* 36 0 Transmitter Underrun:TxU is asserted during a transmit sequence when the service of TxBE has been delayed for one character time. This indicates the processor is not keeping up with the transmitter. Line fill depends on PCSAR-m. TxU is reset by RESET or setting of TSOM (TDSR8), synchronized by the falling edge of TxC. TxC 39 I Transmitter Clock: TxC (1X) provides timing for the transmitter logic. The positive going edge shifts data out of the TxSR to TxSO. TxSO 38 0 Transmitter Serial Output. TxSO is the transmitted serial data. Mark = '1', space = '0'. Vcc 32 I +5V: Power supply. GND 9 I Ground: OV reference ground.

'Indicates possible interrupt signal. 1.16 Signetics MICROPROCESSOR DIVISION JANUARY 1983 MULTI-PROTOCOL COMMUNICATIONS CONTROLLER SCN26521SCN68652

Table 1 GLOSSARY

REGISTERS NO. OF BITS DESCRIPTION* Addressable PCSAR Parameter Control Sync/Address Register 16 PCSARH and PCR contain parameters common to PCR Parameter Control Register 8 the receiver and transmitter. PCSARL contains a programmable SYNC character (BOP) or secondary station address (BOP).

RDSR Receive Data/Status Register 16 RDSRH contains receiver status information. RDSRL = RxDB contains the received assembled character.

TDSR Transmit Data/Status Register 16 TDSRH contains transmitter command and status information. TDSRL = TxDB contains the character to be transmitted. Internal CCSR Control Character Shift Register 8 These registers are used for character assembly HSR Holding Shift Register 16 (CCSR, HSR, RxSR), disassembly (TxSR), and CRC RxSR Receiver Shift Register 8 accumulation/generation (RxCRC, TxCRC). TxSR Transmitter Shift Register 8 RxCRC Receiver CRC Accumulation Register 16 TxCRC Transmitter CRC Generation Register 16

NOTE 'H = High byte - bits 15-8 L = Low byte - bits 7-0 Table 2 ERROR CONTROL Table 3 SPECIAL CHARACTERS

CHARACTER DESCRIPTION OPERATION BIT PATTERN FUNCTION FCS Frame Check Sequence is BOP Frame message transmitted/received as 16 FLAG 01111110 Terminate communication bits following the last data ABORT 11111111 generation character of a BOP message. 01111111 detection The divisor is usually CRC- GA 01111111 Terminate loop mode repeater CCITT (X16 + X12 + X, + 1) with function dividend preset to l's but can Address (PCSARL)1 Secondary station address be otherwise determined by BCP ECM. The inverted remainder SYNC (PCSARL) or (TxDB)2 Character synchronization is transmitted as the FCS, generation

BCC Block Check Character is NOTES transmitted/received as two 1. 1if.iC 1 refers to contents of c.< 2. For IDLE = 0 or 1 respectively successive characters following the last data character 7 6 5 4 3 2 1 0 of a BCP message. The poly- 15 14 13 12 11 10 9 8 nomial is CRC-16 (Xls + xis ± PCSAR APA PROTO SS/GA SAM IDLE E C M S/AR X2 + 11 or CRC-CCITT with

dividend preset to O's (as 14 3 12 10 9 8 specified by ECM). The true Tx R .0 remainder is transmitted as PCR TxCL CLE L E Rx CL the BCC. 15 14 13 12 11 9 8

RAB/ RERR A B C ROR REOM RSOM RxDB FUNCTIONAL DESCRIPTION RDSR GA The MPCC can be functionally partitioned 15 14 13 12 11 10 into receiver logic, transmitter logic, registers that can be read or loaded by the pro- TDSR TERR NOT DEFINED TGA TABORT TEOM TSOM TxDB cessor, and data bus control circuitry. The register bit formats are shown in figure 1 NOTE while the receiver and transmitter data Refer to Register Formats for mneumonics and description. paths are depicted in figures 2 and 3. Figure 1. Short Form Register Bit Formats

Signetics 1.17

MICROPROCESSOR DIVISION JANUARY 1983 MULTI-PROTOCOL COMMUNICATIONS CONTROLLER SCN26521SCN68652

BCP • CRC TO RDSRL BOP • CRC .2\ BCP • CRC

a RxSI M SYNC CCSR (8) U RxSR (8) FF HSR (16) X SEL 1-BIT BOP • CRC DELAY DELETION) ZERO FROM SYNC/FLAG1 DELETION DELETION XMITTER COMPARATOR LOGIC CONTROL

MM PARITY (BCP) LOGIC BOP

S/F CRC-16 (BCP) OR CRC.18 = 0 RERR BCP RxCRC ACC CC RC-CCITT COMPARATOR (BOP) CRC-CCIT= FOBS

RESET RxE RECEIVER RxA CONTROL RxDA LOGIC NOTES RxSA 1. Detected in SYNC FF and 7 MS bits of CCSR. 2. In BOP mode, a minimum of two data characters RxC must be received to turn the receiver active. Figure 2. MPCC Receiver Data path

.IFZ:AL OR PCSARL (SYNC)

RESET SYNC TxE TxSO TRANS- TxSR (8) FF TxA MITTER CONTROL 1 BIT TxBE LOGIC DELAY TaU BOP M ZERO U INSERTION ZERO TxCRC ACC (16) LOGIC INSERTION CRC-16 OR CRC-CCITT CONTROL

BCP SEL1, 2 PARITY GENERATION

TCC

CONTROL CHARACTER GENERATOR f I NOTES FLAG ABORT GA 1. TxCRC selected if TEOM = 1 and the last data character has been shifted out of TxSR. 2. In BCP, parity selected will be generated after each character is shifted out of TxSR.

Figure 3. MPCC Transmitter Data Path

1.18 Signetics MICROPROCESSOR DIVISION JANUARY 1983 MULTI-PROTOCOL COMMUNICATIONS CONTROLLER SCN26521SCN68652

RECEIVER OPERATION General PROCESSOR After initializing the parameter control registers (PCSAR and PCR), the RxE input must be set high to enable the receiver data RxE -1 path. The serial data on the RxSI is synchronized and shifted into an 8-bit Control Character Shift Register (CCSR) on the rising edge of RxC. A comparison between CCSR contents and the FLAG (BOP) or SYNC (BCP) character is made until a match is found. At that time, the S/F output is = 1 asserted for one RxC time and the 16-bit FOR ONE RxC Holding Shift Register (HSR) is enabled. The BR TIME receiver then operates as described below. BOP Operation ASSEMBLE CHARACTER OVERRUN A flow chart of receiver operation in BOP IN RxSR, ZERO DELETION, S OSS OF ACCUMULATE CRC IF SUBSEQUENT mode appears in figure 4. Zero deletion SPECIFIED CHARACTERS (after five ones are received) is implemented on the received serial data so that a data character will not be interpreted as a FLAG, ABORT, or GA. Bits following the FLAG are SECONDARY shifted through the CCSR, HSR, and into YES STATION the Receiver Shift Register (RxSR). A char- ADDRESS acter will be assembled in the RxSR and transferred to the RDSRL for presentation to

the processor. At that time the RxDA output START OF will be asserted and the processor must take MESSAGE RxA- 1 the character no later than one RxC time RSOM =1 FOR ONE after the next character is assembled in the CHARACTER RxSR. If not, an overrun (RDSR1 = 1) will TIME occur and succeeding characters will be lost. FDDA -1 (PROCESSOR The first character following the FLAG is the SHOULD READ OB) secondary station address. If the MPCC is a secondary station (PCSAR12 = 1), the contents of RxSR are compared with the add- RXSA =1 ress stored in PCSARL. A match indicates (PROCESSOR SHOULD READ AND EXAMINE the forthcoming message is intended for the ROSRH — REOM, RAINGA, station; the RxA output is asserted, the ROVRN, ABC, RERR) character is loaded into RDSRL, RxDA is asserted and the Receive Start of Message S/F =1 FOR ONE RxC YES bit (RSOM) is set. No match indicates that BR TIME another station is being addressed and the AEON =1, Rx.A = 0 receiver searches for the next FLAG. Figure 4. BOP Receive If the MPCC is a primary station (PCSAR12 = 01, no secondary address check is made; RxA is asserted and RSOM is set once the first non-FLAG character has been loaded before, RxDA is asserted each time a char- length will be changed on the next receiver into RDSRL and RxDA has been asserted. acter has been transferred into RDSRL and character boundary. A received residual Extended address field can be supported by is cleared when RDSRL is read by the pro- (short) character will be transferred into software if PCSAR12 = 0. cessor. RDSRH should only be read when RxDB after the previous character in RxDB RxSA is asserted. This occurs on a zero to has been read, i.e. there will not be an over- When the 8 bits following the address char- one transition of any bit in RDSRH except run. In general the last two characters are acter have been loaded into RDSRL and for RSOM. RxSA and all bits in RDSRH protected from overrun. RxDA has been asserted, RSOM will be except RSOM are cleared when RDSRH is cleared. The processor should read this 8- read. The processor should check RDSR9_ The CRC-CCITT, if specified by PCSARs- bit character and interpret it as the Control seach time RxSA is asserted. If RDSR9 is 1 is, is accumulated in RxCRC on each char- field. set, then RDSR12-is should be examined. acter following the FLAG. When the closing Received serial data that follows is read and Receiver character length may be changed FLAG is detected in the CCSR, the received interpreted as the Information field by the dynamically in response to RxDA: read the CRC is in the 16-bit HSR. At that time, the processor. It will be assembled into charac- character in RxDB and write the new char- Receive End of Message bit (REOM) will be ter lengths as specified oy PCF18-10. As acter length into RxCL. The character set; RxSA and RxDA will be asserted. The Signetics 1.19 MICROPROCESSOR DIVISION JANUARY 1983 MULTI-PROTOCOL COMMUNICATIONS CONTROLLER SCN26521SCN68652

processor should read the last data character in RDSRL and the receiver status in PROCESSOR RDSR9-is. If RDSR is = 1, there has been a transmission error; the accumulated CRC- CCITT is incorrect. If RDSR12-14 0, the last data character is not of prescribed RxE —1 length. Neither the received CRC nor closing FLAG are presented to the processor. The processor may drop RxE or leave it active at the end of the received message.

BCP Operation

The operation of the receiver in BCP mode SW.1 FOR ONE is shown in figure 5. The receiver initially ReC BIT TIME searches for two successive SYNC characters, of length specified by PCR8_10, that match the contents of PCSARL. The next non-SYNC character or next SYNC character, if stripping is not specified (PCSARia

0), causes RxA to be asserted and enables RxA —1 the receiver data path. Once enabled, all (1) STNCe ARE ASSEMBLED characters are assembled in RxSR and ASSEMBLE CHARACTER (2) OVERRUN (ROVRN) CAUSES IN RxSR, STRIP VRC IF LOSS OF SUBSEQUENT loaded into RDSRL. RxDA is active when a SPECIFIED, ACCUMULATE CRC IF SPECIFIED CHARACTERS character is available in RDSRL. RxSA is active on a 0 to 1 transition of any bit in RDSRH. The signals are cleared when RxDA =1 (PROCESSOR SHOULD RDSRL or RDSRH are read respectively. READ RxDB) If CRC-16 error control is specified by PCSAR8-.10, the processor must determine the last character received prior to the CRC field. When that character is loaded into RDSRL and RxDA is asserted, the received RxSA .1 (PROCESSOR SHOULD CRC will be in CCSR and HSRL. To check READ AND EXAMINE for a transmission error, the processor must RDSRH — ROVRN, RERR (IF VRC SPECIFIED) read the receiver status (RDSRH) and examine RDSFIts. This bit will be set for one character time if an error free message has RxE-0 WHEN LAST been received. If RDSR15 = 0, the CRC-16 is CHARACTER HAS in error. The state of RDSR15 in BCP CRC BEEN SERVICED mode does not set RxSA. Note that this bit NOTES should be examined only at the end of a 1. Test made every RxC time. message. The accumulated CRC will in- 2. Test made on Rx character boundary. clude all characters starting with the first Figure 5. BCP Receive non-SYNC character if PCSAR13 = 1, or the character after the opening two SYNC's if PCSAR is = 0. This necessitates external CRC generation/checking when supporting TRANSMITTER OPERATION sage. TSOM should be cleared at the same IBM's BISYNC. This can be accomplished General time TDSRL is loaded (16-bit data bus) or immediately thereafter (8-bit data bus). using the Signetics 2653 Polynomial Gen- After the parameter control registers FLAGs are sent as long as TSOM = 1. For erator/Checker. See Typical Applications. (PCSAR and PCR) have been initialized, counting the number of FLAGs, the proces- TxSO is held at mark until TSOM (TDSR8) is If VRC had been selected for error control, sor should reassert TSOM in response to set and TxE is raised. Then, transmitter parity (odd or even) is regenerated on each the assertion of TxBE. operation depends on protocol mode. character and checked when the parity bit is received. A discrepancy causes RDSRis to All succeeding characters are loaded into be set and RxSA to be asserted. This must BOP Operation TDSRL by the processor when TxBE = 1. be sensed by the processor. The received Transmitter operation for BOP is shown in Each character is serialized in TxSR and parity bit is stripped before the character is figure 6. A FLAG is sent after the processor transmitted on TxSO. Internal zero insertion presented to the processor. sets the Transmit Start of Message bit logic stuffs a "0" into the serial bit stream (TSOM) and raises TxE. The FLAG is used to after five successive "1s" are sent. This When the processor has read the last char- synchronize the message that follows. TxA insures a data character will not match a acter of the message, it should drop RxE will also be asserted. When TxBE is asserted FLAG, ABORT, or GA reserved control which disables the receiver logic and initial- by the MPCC, the processor should load character. As each character is transmitted, izes all receiver registers and timing. TDSRL with the first character of the mes- the Frame Check Sequence (FCS) is gener-

1.20 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 MULTI-PROTOCOL COMMUNICATIONS CONTROLLER SCN26521SCN68652

ated as specified by Error Control Mode ROCESSOR MUST CLEAR (PCSAR8-10). The FCS should be the CRC- TABORTITGA IN RESPONSE TO TxBE =1) CCITT polynomial (Xle + X12+ X5+ 11 preset

PROCESSOR to 1s. If an underrun occurs (processor is not keeping up with the transmitter), TxU and TERR (TDSR15) will be asserted with ABORT or FLAG used as the TxSO line fill depending on the state of IDLE (PCSARii). ISOM =1 The processor must set TSOM to reset the TIE =1 NO underrun condition. To retransmit the mes- YES TIA 1 sage, the processor should proceed with the TaBE=1 normal start of message sequence. PROCESSOR SHOULD LOAD TxDB AND TSOM = 0) A residual character of 1 to 7 bits may be transmitted at the end of the Information field. In response to TxBE, write the residual (PROCESSOR MAY SET TABORT, ISA. character length into TxCL and load TxDB AS REQUIRED) with the residual character. Dynamic altera- TaSO=ABORT=11111111 IF IDLE= 0 FLAG= 01111110 IF IDLE=1 tion of character length should be done in exactly the same sequence. The character length will be changed on the next transmit character boundary.

After the last data character has been ON UNDERRUN: ES Tall =1, TERR =1 MO= ABORT IF IDLE=D loaded into TDSRL and sent to TxSR (TxBE (PROCESSOR SHOULD FLAG IF IDLE=1 SET TSOM) = 11, the processor should set TEOM (TDSR9). The MPCC will finish transmitting the last character followed by the FCS and SERIALIZE DATA CHARACTER IN TaDB, ZERO INSERTION, the closing FLAG. The processor should UBE =1 ACCUMULATE CRC IF (PROCESSOR SHOULD SPECIFIED BY ECM, ES clear TEOM and drop TxE when the next LOAD TIDE WITH TRANSMIT ON TWO NEXT DATA CHAR) TxBE is asserted. This corresponds to the start of closing FLAG transmission. When TxE has been dropped, TxA will be low 11/2 bit times after the last bit of the closing TEOM 1? FLAG has been transmitted. TxSO will be

YES marked after the closing FLAG has been transmitted. TRANSMIT ACCUMULATED FCS(IF SPECIFIED) AS INVERTED REMAINDER If TxE and TEOM are high, the transmitter continues to send FLAGs. The processor may initiate the next message by resetting TxBEtt 1 w— TRANSMIT FLAG ON TxSO TEOM and setting TSOM, or by loading TDSRL with a data character and then simply resetting TEOM (without setting TSOM). NO (PROCESSOR SHOULD RESET TEOM AND SET TSOM OR DROP TIE) BCP Operation YES Transmitter operation for BCP mode is shown in figure 7. TxA will be asserted after Es 0 TSOM = 1 and TxE is raised. At that time NO SYNC characters are sent from PCSARL or TDSRL (IDLE =0 or 1) as long as TSOM =1. TxBE is asserted at the start of transmission TaA — Es of the first SYNC character. For counting the number of SYNC's, the processor should reassert TSOM in response to the assertion

*GA will be transmitted it TGA is set together with TEOM of TxBE. When TSOM = 0 transmission is from TDSRL, which must be loaded with characters from the processor each time Figure 6. BOP Transmit TxBE is asserted. If this loading is delayed for more than one character time, an underrun results: TxU and TERR are asserted and the TxSO line fill depend on IDLE (PCSARii). The processor must set TSOM

Signetics 1.21

MICROPROCESSOR DIVISION JANUARY 1983 MULTI-PROTOCOL COMMUNICATIONS CONTROLLER SCN2652/SCN68652

The default value for all registers is zero. This corresponds to BOP, primary station PROCESSOR mode, 8-bit character length, FCS = CRC- CCITT preset to 1s.

For BOP mode the character length register TSOM =1 TxE=1 (PCR) may be set to the desired values

TxA -1 during system initialization. The address and control fields will automatically be 8- TRANSMIT SYNC ON TxSO bits. If a residual character is to be transmit- TxBE 1 SYNC FROM PCSARL - IDLE = 0 SYNC FROM TxDB IDLE=1 ted, TxCL should be changed to the residual character length prior to transmission of that character. AFTER SYNC(S), PROCESSOR 1-."- LOADS DATA CHARACTER IN TxDB AND ISOM =0 44>YES DATA BUS CONTROL The processor must set up the MPCC regis- SERIALIZE DATA CHARACTER TxBE -1 IN TxDB, GENERATE VIIIC ter address (A2-A0), chip enable ICE), byte (PROCESSOR SHOULD OR ACCUMULATE CRC AS LOAxDB)D T SPECIFIED, TRANSMIT ON TxSO select (BYTE), and read/write (R/W) inputs before each data bus transfer operation.

(PROCESSOR SHOULD GET During a read operation (R/W = 0), the TEOM AT END OF -J MESSAGE IF CRC leading edge of DBEN will initiate an MPCC SPECIFIED) read cycle. The addressed register will place its contents on the data bus. If BYTE= TUU = 1, TERR (PROCESSOR SHOULD TxSO = SYNC FROM PCSARL IF IDLE= 0 1, the 8-bit byte is placed on DB15-08 or SET TSOM =1) MARK IF IDLE=1 TRANSMIT ACCUMULATED UNTIL TSOM DB07-00 depending on the H/L status of the CRC SPEC FIED (IF NO CRC, TEOM SHOULD = 0) register addressed. Unused bits in RDSRL are zero. If BYTE = 0, all 16 bits (DB15-00) TAM =1 (PR CLESSOR SHOULD contain MPCC information. The trailing CLEAR TEOM AND DROP TxE) edge of DBEN will reset RxDA and/or RxSA TxSO = SYNC OR TxDB DEPENDING ON IDLE BIT if RDSRL or RDSRH is addressed respec- 0 tively. NO DBEN acts as the enable and strobe so that 4 the MPCC will not begin its internal read YES TxA -0 cycle until DBEN is asserted. 0 Figure 7. BCP Transmit During a write operation (g/W = 1), data must be stable on DBis-as and/or DB07-oo prior to the leading edge of DBEN. The and retransmit the message to recover. This LRC or CRC, TEOM should be set only if stable data is strobed into the addressed is not compatible with IBM's BISYNC, so SYNC's are required at the end of the register by DBEN. TxBE will be cleared if the that the user must not underrun when sup- message block. addressed register was TDSRH or TDSRL. porting that protocol. Special Case CRC-16, if specified by PCSAR8_io, is gen- The capability to transmit 16 spaces is pro- erated on each character transmitted from vided for line turnaround in half duplex TDSRL when TSOM = 0. The processor mode or for a control recovery situation. must set TEOM = 1 after the last data char- This is achieved by setting TSOM and acter has been sent to TxSR (TxBE =1). The TEOM, clearing TEOM when TxBE =1, and MPCC will finish transmitting the last data proceeding as required. character and the CRC-16 field before sending SYNC characters which are transmitted as long as TEOM = 1. If SYNCs are not PROGRAMMING desired after CRC-16 transmission, the pro- Prior to initiating data transmission or re- cessor should clear TEOM and lower TxE ception, PCSAR and PCR must be loaded when the TxBE corresponding to the start of with control information from the proces- CRC-16 transmission is asserted. When sor. The contents of these registers (see TEOM = 0, the line is marked and a new Register Format section) will configure the message may be iniated by setting TSOM MPCC for the user's specific data communi- and raising TxE. cation environment. These registers should be loaded during power-on initialization If VRC is specified, it is generated on each and after a reset operation. They can be data character and the data character changed at any time that the respective length must not exceed 7 bits. For software transmitter or receiver is disabled.

1.22 Signetics MICROPROCESSOR DIVISION JANUARY 1983 MULTI-PROTOCOL COMMUNICATIONS CONTROLLER SCN26521SCN68652

Table 4 MPCC REGISTER ADDRESSING A2 Al AO REGISTER

BYTE = 0 16-BIT DATA BUS = DB15 - DB00 0 0 X RDSR o i x TDSR 1 0 X PCSAR 1 1 X PCR*

BYTE = 1 8-BIT DATA BUS = DB 7.0 or DB15_8** 0 0 0 RDSRL 0 0 1 RDSRH 0 1 0 TDSRL 0 1 1 TDSRH 1 0 0 PCSARL 1 0 1 PCSARH 1 1 0 PCRL* 1 1 1 PCRH

NOTES PCR lower byte does not exist. It will be all "0"s when read. ** Corresponding high and low order pins must be tied together.

Table 5 PARAMETER CONTROL REGISTER (PCR)-(R/W) BIT NAME MODE FUNCTION 00-07 Not Defined 08-10 RxCL BOP/BCP Receiver Character Length is loaded by the processor when RxCLE = 0. The character length is valid after transmission of single byte address and control fields have been received. 10 9 8 Char. length (bits) 0 0 0 8 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 7 11 RxCLE BOP/BCP Receiver Character Length Enable should be zero when the processor loads RxCL. The remaining bits of PCR are not affected during loading. Always 0 when read. 12 TxCLE BOP/BCP Transmitter Character Length Enable should be zero when the processor loads TxCL. The remaining bits of PCR are not affected during loading. Always 0 when read. 13-15 TxCL BOP/BCP Transmitter Character Length is loaded by the processor when TxCLE = 0. Character bit length specification format is identical to RxCL. It is valid after transmission of single byte address and control fields.

Signetics 1.23 MICROPROCESSOR DIVISION JANUARY 1983 MULTI-PROTOCOL COMMUNICATIONS CONTROLLER SCN2652/SCN68652

Table 6 PARAMETER CONTROL SYNC/ADDRESS REGISTER (PCSAR)-(RIW) BIT NAME MODE FUNCTION

00-07 S/AR BOP SYNC/ADDRESS Register. Contains the secondary station address if the MPCC is a secondary station. The contents of this register is compared with the first received non- FLAG character to determine if the message is meant for this station. BCP SYNC character is loaded into this register by the processor. It is used for receive and transmit bit synchronization with bit length specified by RxCL and TxCL. 08-10 ECM BOP/BCP Error Control Mode 10 9 8 Suggested Mode Char. length CRC-CCITT preset to 1's 0 0 0 BOP 1-8 CRC-CCITT preset to 0's 0 0 1 BCP 8 Not used 0 1 0 --- CRC-16 preset to 0's 0 1 1 BCP 8 VRC odd 1 0 0 BCP 5-7 VRC even 1 0 1 BCP 5-7 Not used 1 1 0 --- No error control 1 1 1 BCP/BOP 5-8 ECM should be loaded by the processor during initialization or when both data paths are idle. 11 IDLE Determines line fill character to be used if transmitter underrun occurs (TxU asserted and TERR set) and transmission of special characters for BOP/BCP. BOP IDLE = 0, transmit ABORT characters during underrun and when TABORT = 1. IDLE = 1, transmit FLAG characters during underrun and when TABORT = 1. BCP IDLE = 0 transmit initial SYNC characters and underrun line fill characters from the S/AR. IDLE = 1 transmit initial SYNC characters from TxDB and marks TxSO during underrun. 12 SAM BOP Secondary Address Mode = 1 if the MPCC is a secondary station. This facilitates automatic recognition of the received secondary station address. When transmitting, the processor must load the secondary address into TxDB. SAM = 0 inhibits the received secondary address comparison which serves to activate the receiver after the first non-FLAG character has been received. 13 SS/GA Strip SYNC/Go Ahead. Operation depends on mode. BOP SS/GA = 1 is used for loop mode only and enables GA detection. When a GA is detected as a closing character, REOM and RAB/GA will be set and the processor should terminate the repeater function. SS/GA = 0 is the normal mode which enables ABORT detection. It causes the receiver to terminate the frame upon detection of an ABORT or FLAG. BCP SS/GA = 1, causes the receiver to strip SYNC's immediately following the first two SYNC's detected. SYNC's in the middle of a message will not be stripped. SS/GA = 0, presents any SYNC's after the initial two SYNC's to the processor. 14 PROTO Determines MPCC Protocol mode BOP PROTO = 0 BCP PROTO = 1 15 APA BOP All Parties Address. If this bit is set, the receiver data path is enabled by an address field of '11111111' as well as the normal secondary station address.

Table 7 TRANSMIT DATA/STATUS REGISTER (TDSR) (R/W except TDSR 15) BIT NAME MODE FUNCTION 00-07 TxDB BOP/BCP Transmit Data Buffer. Contains processor loaded characters to be serialized in TxSR and transmitted on TxSO. 08 TSOM Transmitter Start of Message. Set by the processor to initiate message transmission provided TxE = 1. BOP TSOM = 1 generates FLAGs. When TSOM = 0 transmission is from TxDB and FCS generation (if specified) begins. FCS, as specified by PCSAR8_,0, should be CRC- CCITT preset to 1's. BCP TSOM = 1 generates SYNCS from PCSARL or transmits from TxDB for IDLE = 0 or 1 respectively. When TSOM = 0 transmission is from TxDB and CRC generation (if specified) begins.

1.24 Signetics MICROPROCESSOR DIVISION JANUARY 1983

MULTI-PROTOCOL COMMUNICATIONS CONTROLLER SCN26521SCN68652

Table 7 TRANSMIT DATA/STATUS REGISTER (TDSR) (RIW except TDSR 15) (Continued) BIT NAME MODE FUNCTION 09 TEOM Transmit End of Message. Used to terminate a transmitted message.

BOP TEOM = 1 causes the FCS and the closing FLAG to be transmitted following the transmission of the data character in TxSR. FLAGs are transmitted until TEOM = 0. ABORT or GA are transmitted if TABORT or TGA are set when TEOM = 1. BCP TEOM = 1 causes CRC-16 to be transmitted (if selected) followed by SYNCs from PCSARL or TxDB (IDLE = 0 or 1). Clearing TEOM prior to the end of CRC-16 transmission (when TxBE = 1) causes TxSO to be marked following the CRC-16. TxE must be dropped before a new message can be initiated. If CRC is not selected, TEOM should not be set. 10 TABORT BOP Transmitter Abort = 1 will cause ABORT or FLAG to be sent (IDLE = 0 or 1) after the current character is transmitted. (ABORT = 11111111) 11 TGA BOP Transmit Go Ahead (GA) instead of FLAG when TEOM = 1. This facilitates repeater termination in loop mode. (GA = 01111111)

12-14 Not Defined Transmitter Error = 1 indicates the TxDB has not been loaded in time (one character 15 TERR Read time -1/2 TxC period after TxBE is asserted) to maintain continuous transm ission. TxU only will be asserted to inform the processor of this condition. TERR is cleared by setting TSOM. See timing diagram. BOP ABORT's or FLAG's are sent as fill characters (IDLE = 0 or 11 BCP SYNC's or MARK's are sent as fill characters (IDLE = 0 or 1). For IDLE = 1 the last character before underrun is not valid. Table 8 RECEIVER DATA/STATUS REGISTER (RDSR)-(Read Only) BIT NAME MODE FUNCTION 00-07 RxDB BOP/BCP Receiver Data Buffer. Contains assembled characters from the RxSR. If VRC is specified, the parity bit is stripped. 08 RSOM BOP Receiver Start of Message = 1 when a FLAG followed by a non-FLAG has been received and the latter character matches the secondary station address if SAM = 1. RxA will be asserted when RSOM =1. RSOM resets itself after one character time and has no effect on RxSA. 09 REOM BOP Receiver End of Message = 1 when the closing FLAG is detected and the last data character is loaded into RxDB or when an ABORT/GA character is received. REOM is cleared on reading RDSRH, reset operation, or dropping of RxE. 10 RAB/GA BOP Received ABORT or GA character =1 when the receiver senses an ABORT character if SS/GA = 0 or a GA character if SS/GA =1. RAB/GA is cleared on reading RDSRH, reset operation, or dropping of RxE. A received ABORT does not set RxDA. 11 ROR BOP/BCP Receiver Overrun = 1 indicates the processor has not read last character in the RxDB within one character time +1/2 RxC period after RxDA is asserted.Subsequent characters will be lost.ROR is clearedon readingRDSRH,reset operation,or dropping of RxE. 12-14 ABC BOP Assembled Bit Count. Specifies the number of bits in the last received data character of a message and should be examined by the processor when REOM =1 (RxDA and RxSA asserted). ABC = 0 indicates the message was terminated (by a FLAG or GA) on a character boundary as specified by PCR8_10. Otherwise, ABC = number of bits in the last data character. ABC is cleared when RDSRH is read, reset operation, or dropping RxE. The residual character is right justified in RDSRL. 15 RERR BOP/BCP Receiver Error indicator should be examined by the processor when REOM =1 in BOP, or when the processor determines the last data character of the message in BCP with CRC or when RxSA is set in BCP with VRC. CRC-CCITT preset to 1's/0's as specified by PCSAR8-10: RERR = 1 indicates FCS error ICRC # FOBS/ # 0) RERR = 0 indicates FCS received correctly (CRC = FOB /=0) CRC-16 preset to O's on 8-bit data characters specified by PSCAR8-10: RERR = 1 indicates CRC-16 received correctly (CRC = 0). RERR = 0 indicates CRC-16 error (CRC # 0) VRC specified by PCSARs- to: RERR = 1 indicates VRC error RERR = 0 indicates VRC is correct Signetics 1-25 MICROPROCESSOR DIVISION JANUARY 1983

MULTI-PROTOCOL COMMUNICATIONS CONTROLLER SCN26521SCN68652

ABSOLUTE MAXIMUM RATINGsi

PARAMETER RATING UNIT

TA Operating ambient temperature2 Note 4 °C TSTO Storage temperature -65 to +150 °C Input or output voltages with respect to GND3 -0.3 to +15 V Vcc With respect to GND -0.3 to+7 V

DC ELECTRICAL CHARACTERISTICS4,5 LIMITS PARAMETER TEST CONDITIONS UNIT Min Typ Max Input voltage V VIL Low 0.8 VIH High 2.0 Output voltage V VOL Low IOL = 1.6mA 0.4 VOH High 10H = -100µA 2.4 Icc Power supply current Vcc = 5.25V, TA = 0°C 150 mA Leakage current µA IL Input VIN = 0 to 5.25V 10 IOL Output VOUT = 0 to 5.25V 10 Capacitance pF CIN Input VIN = OV, f = 1MHz 20 COUT Output VOuT = OV, f = 1MHz 20

AC ELECTRICAL CHARACTERISTICS4,5,6 1MHz Clock Version 2MHz Clock Version PARAMETER UNIT Min Typ Max Min Typ Max

Setup and hold time ns tAcs Address/control setup 50 50 tACH Address/control hold 0 0 tos Data bus setup (write) 50 50 toi-i Data bus hold (write) 0 0 tRXS Receiver serial data setup 150 150 1AxH Receive serial data hold 150 150 Pulse width ns NES RESET 250 250 tDBEN DBEN 250 m7 200 m7 Delay time ns top Data bus (read) 200 170 tlX Transmit serial data 325 250 tDBEND DBEN to DBEN delay 200 200 toF Data bus float time (read) 150 150 ns

f Clock (RxC, TxC) frequency 1.0 2.0 MHz tCLK1 Clock high (MM = 0) 340 165 ns tCLK1 Clock high (MM = 1) 490 240 tcLko Clock low 490 240

1.26 Signetics MICROPROCESSOR DIVISION JANUARY 1983 MULTI-PROTOCOL COMMUNICATIONS CONTROLLER SCN26521SCN68652

NOTES 1. Stresses above those listed under "Absolute Maximum Ratings" may cause 4. Parameters are valid over operating temperature range unless otherwise specified. permanent damage to the device. This is a stress rating only and functional operation See ordering code table for applicable temperature range and operating supply of the device at these or at any other condition above those indicated in the operation range. sections of this specification is not implied, 5. All voltage measurements are referenced to ground. All time measurements are at 2. For operating at elevated temperatures the device must be derated based on +150°C 0.8V or 2.0V. Input voltage levels for testing are 0.4V and 2.4V. maximum junction temperature. 6. Output load CL,- 100pF. 3 This product includes circuitry specifically designed for the protection of its internal 7. m= TxC low and applies to writing to TDSRH only. devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.

TIMING DIAGRAMS RESET READ AND WRITE DATA BUS

OBEN DBEN

AO-A27cs=_.,4 #—

RESET CE, tRES BYTE --,... tACS —'^ '6— NOT tACH LOATING VALID VALID X FLOATING DREAD) -.— tDD —I" -4— tDF DO D15 (WRITE) •••

Signetics 1.27 MICROPROCESSOR DIVISION JANUARY 1983 MULTI-PROTOCOL COMMUNICATIONS CONTROLLER SCN2652/SCN68652

TIMING DIAGRAMS (Cont'd)

TRANSMIT—START OF MESSAGE

TxC

8 TxC1

IAVs0 MARK SYNC/FLAG1 1ST CHAR

TxBE

SET TSOM LOAD 1st CHAR RESET TSOM LOAD 2nd CHAR

DBEN

TxE

TxA NOTES 1st CHAR 1. SYNC may be 5 to 8 bits and will contain parity bit as specified. 2. TxA goes high relative to TxC rising edge after TSOM has been set and TxE has been raised. 3. TxBE goes low relative to DBEN falling edge on the first write transfer into TDSR. It is reasserted 1 TxC time before the first bit of the transmitted SYNC/FLAG. TxBE then goes low relative to DBEN falling edge when writing into TDSRH and/or TDSRL. It is reasserted on the rising edge of the TxC that corresponds to the transmission of the last bit of each character, except in BOP mode when the CRC is to be sent as the next character (see Transmit Timing—End of Message).

TRANSMIT—END OF BOP MESSAGE

TxC ,11_1111.„1-111

TxSO NEXT TO LAST CHAR I LAST CHAR I CRC I FLAG MARK

Ta BE4

LOAD LAST CHAR SET TEOM RESET TEOM

DBEN

TxE5

TxA6

NOTES 4. TxBE goes low relative to the falling edge of DBEN corresponding to loading TDSRH,_. It goes high one TxC before character transmission begins and also when TxA has been dropped. 5. TxE can be dropped before resetting TEOM if TxBE (corresponding to the closing FLAG) is high. Alternatively TxE can remain high and a new message initiated. 6. TxA goes low after TxE has been dropped and 1 1/2 TxC's after the last bit of the closing FLAG has been transmitted.

1.28 Signetics MICROPROCESSOR DIVISION JANUARY 1983 MULTI-PROTOCOL COMMUNICATIONS CONTROLLER SCN26521SCN68652

TIMING DIAGRAMS (Cont'd)

TRANSMIT TIMING—END OF BCP MESSAGE TxC ,111111,

TxSO NEXT TO LAST CHAR I LAST CHAR cqc7 MARK

TxBE

LOAD LAST CHAR SET TEOM RESET TEOM

DBEN

TxE

TxA NOTES

7. When 2652 generated CRC is not required, TEOM should only be set if SYNCS are to follow the message block. In that case, TxE should be dropped in response to TxBE (which corresponds to the start of transmission of the last character). When CRC is required, TxE must be dropped before CRC transmission is complete. Otherwise, the contents of TxDB will be shifted out on TxSO. This facilitates transmission of contiguous messages.

TRANSMIT UNDERRUN

TxC

SET TSOM OBEN

NOTES 6. TxU goes active relative to TxC falling edge if TxBE has not been serviced after n-1/2 TxC times (where n = transmit character length). TxU is reset on the TxC falling edge following assertion of the TSOM command. 9. An underrun will occur at the next character boundary if TEOM is reset and the transmitter remains enabled, unless the TSOM command is asserted ora character is loaded into the TxDB.

Signetics 1.29 MICROPROCESSOR DIVISION JANUARY 1983 MULTI-PROTOCOL COMMUNICATIONS CONTROLLER SCN26521SCN68652

TIMING DIAGRAMS (Cont'd)

RECEIVE—START OF MESSAGE

RxA

1st CHAR READY 2nd CHAR READY TO BE READ ---.- TO BE READ RxDA"

1st CHAR READ 2nd CHAR READ

DBEN

SIF11

RxE J NOTES 9. RxA goes high relative to falling edge of RxC when RxE is high and: a. A data character following two SYNC's is in RxDB (BCP mode) b. Character following FLAG is in RxDB IBOP primary station mode/ c. Character following FLAG is in RxDB and character matches the secondary station addressor All Parties Address (BOP secondary station model. 10 RxDA goes high on RxC falling edge when a character in RxDB is ready to be read. It comes up before RxSA and goes low on'the falling edge of DBEN when RxDB is read. 11. S/F goes high relative to rising edge of RxC anytime a SYNC (BCP) or FLAG (BON is detected.

RECEIVE END OF MESSAGE

RxC

RxDA

RxSA12

READ rk READ DATA FLIT STATUS DBEN (8.BIT)

S/F

RxE13

Rxt.,14

NOTES 12. At the end of a BOP message, RxSA goes high when FLAG detection IS/F =11 forces REOM to be set. Processor should read the last data character IRDSRLI and status (RDSRH) which resets RxDA and RxSA respectively. For BCP end of message, RxSA may not be set and S/F = 0. The processor should read the last data character and status. 13.Rep must be dropped for BCP with non-contiguous messages. It may be left on at the end of a BOP message Isee BOP Receive Operation). 14. RxA is reset relative to the falling edge of RxC after the closing FLAG of a BOP message (REOM = 1 and RxSA active;) or when RxE is dropped.

"I.30 Signetics MICROPROCESSOR DIVISION JANUARY 1983 MULTI-PROTOCOL COMMUNICATIONS CONTROLLER SCN26521SCN68652

TYPICAL APPLICATIONS

2652 MPCC MICROPROCESSOR INTERFACE

RESET

,--I TS BUFFER TxC STATUS RESET im POR DATA BUS RxC DBO- DB7 im B.BIT SYNCHRO MPCC NOUS SCN2652 MODEM ADDRESS CONTROL 52-A0, RIW DBEN CE CLOCK T SO

Po SI C) BYTE

RxE I TxE RTS, CTS, DTR, DSR, DCD

MODEM DCD CTS CONTROL 1 LOGIC

NOTES 1. Possible µP interrupt requests are: RxDA, RxSA, TxBE, TxU. 2. Other 2652 status signals and possible uses are: S/F line: idle indicator, frame delimiter. RxA handshake on RxE, line turn around control TxA handshake on TxE, line turn around control. 3. Line Drivers/Receivers ILD/LIRI convert EIA to TTL voltages and vice-versa 4. RTS should be dropped after the CRC (BCP) or FLAG (BOP) has been transmitted. This forces CTS low and TxE low. 5. Corresponding high and low order bits of DB must be OR tied.

DMA/PROCESSOR INTERFACE

DATA BUS B OR 16 BITS

RDREQ RxDA DB15-DBOO DATA BUS DATA BUS WORD COUNT RxA ADDRESS PTR TO PROCESSOR RxE R/W CONTROL RxSA WRREQ t TxBE TxA PROCESSOR (P) TxE AND RxDA R/W SCN2652 Txu SUPPORT LOGIC: DMA MEMORY 1 INITIALIZES TxBE CONTROLLER SIF SCN2652 A2-AO 2. SETS/RESETS TSOM, TEOM SCN2652 BYTE RESET 3. RESPONDS ADDRESS AND R/W TO RxSA CONTROL CE MM DBEN

ADDRESS, 171/W, _ ADDRESS, ADDRESS, R/W CONTROLS R C TxC RxSI TxSO CONTROL CE, RIW

MODEM OR DCE

SYSTEM ADDRESS AND CONTROL BUS

For non-DMA operation, TxBE and RxDA are sent to the processor which then loads or reads data characters as required. Signetics 1.31

MICROPROCESSOR DIVISION JANUARY 1983 MULTI-PROTOCOL COMMUNICATIONS CONTROLLER SCN26521SCN68652

TYPICAL APPLICATIONS (Cont'd)

CHANNEL INTERFACE

BAUD BAUD RATE RATE GENERATOR GENERATOR

LD iiim

$ $ TxC RxC TxC RxC LD

COMPUTER COMPUTER OR MPCC MPCC OR TERMINAL SCN2652 SCN2652 TERMINAL

TxSO LD RxSI

RxSI LD TxSO

No Modem—DC Baseband Transmission

2652/2653 INTERFACE TYPICAL PROTOCOLS: BISYNC, DDCMP, SDLC, HDLC

INTERRUPTS TxBE, TxU, RxDA, RxSA

MPCC TxD SCN2652

A2 RxD Al AO TxC RIW RxC DBEN CE DB7-DBO CPU

CEO PGC SCN2653 Al

AO CE1

INT (OPEN DRAIN) 5V

1.32 Signetics MICROPROCESSOR DIVISION JANUARY 1983 POLYNOMIAL GENERATOR CHECKER (PGC) SCN26531SCN68653

DESCRIPTION SCN2661 Enhanced Programmable Commu- PIN CONFIGURATION The Signetics SCN2653/68653 Polynomial nications Interface (EPCI). When used in Generator Checker (PGC) is a polynomial BISYNC modes with the SCN2661, software requirements are minimized by the SCN2653- generator checker/character comparator SCN2661 control character comparisons, circuit that complements a receiver/trans- character sequence comparisons, and auto- mitter (R/T or USART/USRT/UART) in the matic DLE insertion/detection. support of character oriented data link controls. Table 1 defines many of the more Other bus oriented R /Ts can be interfaced commonly used PGC terms and abbrevi- to the PGC with a minimum of external cir- ations. cuitry. See figure 1 for a typical system con- Parallel data characters transferred be- figuration. tween the CPU and R /T are monitored by This NMOS LSI circuit is TTL compatible, the PGC which performs block check char- operates from a single + 5V supply and is acter (BCC) and parity (VRC) genera- contained in a 16 pin dual in line package. tion/checking, single character detection, and two character sequence detection. FEATURES Since the PGC operates on parallel charac- • Parallel Block Check Character APPLICATIONS ters, the data transmission format may be accumulation/checking: CRC-16, • Character oriented data link control: serial (synchronous or asynchronous) or CRC-12, LRC-8 —dedicated to one USART/USRT parallel. • BISYNC normal and transparent modes —multiplexed among several There are four modes of BCC accumulation • Automatic or single character accumu- USART/USRTs and each mode can select one of three poly- lation modes • Automated BISYNC with 2661 (minimal nomials to compute the BCC. In the BISYNC • Character detection - up to 128 charac- software intervention) normal and transparent modes, the PGC de- ters • BCC and VRC generation/detection on termines which characters are to be accu- • Two character sequence detection; ex- a block of memory or peripheral data mulated and which characters are to be examples: DLE-STX, ACK 0, ACK 1, • Programmable character array compa- cluded from the accumulation. The block WACK, RVI, DISC, WBT rator terminating characters and the initiation and • 6, 7, or 8-bit characters termination of BISYNC transparent text can • VRC generation/checking on data bus be detected and an interrupt generated. The • Four maskable interrupt conditions BLOCK DIAGRAM single interrupt output represents the inclu- • Four classes of characters The PGC consists of six major sections. sive OR of four maskable status conditions. • Internal power-on reset These are the operation control, character • Maximum character accumulation rate class array, DLE ROM, character register, In the automatic accumulation mode, all of 500 kHz (4 Mbps) BCC and parity generators, and BCC regis- characters are accumulated while the single • Directly compatible with Signetics ters. These sections communicate with accumulate mode requires a specific accu- SCN2651, SCN2652 and SCN2661 each other via an internal data bus and an mulation command for each character to be • No system clock required internal control bus. The internal data bus accumulated. • TTL compatible inputs and outputs interfaces to the CPU data bus via a data Character accumulation control and charac- • Single 5V supply bus buffer. ter comparisons are facilitated by a charac- • 16-pin dual in line package ter class array which places each of 128 characters into one of four character ORDERING CODE classes. The four classes are normal, COMMERCIAL RANGES SYN/BISYNC not included, block terminat- PACKAGES ing character (BTC)/search character (GC) Vcc = 5V ± 5%, TA = 0°C to + 70°C and secondary search character (SSC). Ceramic DIP SCN2653AC4116 Additional PGC applications include off-line Plastic DIP SCN2653AC4N16 R /T operation where the BCC is generated NOTE on data not sent to the R /T, BCC multiplex- SCN58653 is identical to SCN2653. Order using part numbers shown above. ing by sharing the PGC among several R /Ts and reading /writing the partial BCC accumulation on a character by character basis, VRC generation/checking on characters appearing on a bidirectional data bus, and programmable character comparisons or searches. PGC operation is half duplex (either receive or transmit, one way or two way alternate). Full duplex (two way simultaneous) is achieved by using two PGCs. The device is directly compatible with the Signetics SCN2651 Program- mable Communications Interface (PCI) and Signetics 1.33

MICROPROCESSOR DIVISION JANUARY 1983 POLYNOMIAL GENERATOR CHECKER (PGC) SCN2653/SCN68653

BLOCK DIAGRAM

DATA BUS DO-D7 CHARACTER REGISTER BUFFER DATA BUS

DLE DLE DETECT INTR OPERATION CONTROL BCC AND VRC GENERATION UNIT AO MODE REGISTER a Al rn 16 COMMAND REGISTER a CEI STATUS REGISTER RIW

CEO O BCC UPPER BCC LOWER re.

CHARACTER CLASS ARRAY

PIN DESIGNATION

MNEMONIC PIN NO. TYPE NAME AND FUNCTION

VCC 16 I +5V: Power supply GND 8 I Ground

Al-AO 11,12 I Address Lines: Used to select internal PGC registers or character class array 13/W 13 I Read/Write: Read command when low, write command when high

CEO 15 l Chip Enable: Connected to chip enable input of a receiver/transmitter (R /T) circuit. It is used to strobe data being transferred between the CPU and the 14/T into the PGC character register. CET 14 I Chip Enable: Used in conjunction with the R /W signal to enable the transfer of data between the PGC and the CPU or DMA controller and to initialize the PGC registers.

D7-DO 9,7-1 I /0 Data Bus: 8-bit three-state bidirectional bus used to transfer data to or from the PGC via CEO or CEI. All data, mode words, command words, and status information are transferred on this bus. DO is the least significant bit; 07 is the most significant bit.

INT 10 0 Interrupt: Open drain active low interrupt output that signals the CPU that one or more maskable conditions are true: BCC error, VRC error, BTC/SC detect, SSC detect. The true conditions can be determined by reading the status register which in turn deactivates INT. A power on, clear BCC, or master reset command causes INT to be inactive (high).

1.34 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 POLYNOMIAL GENERATOR CHECKER (PGC) SCN26531SCN68653

Table 1 GLOSSARY Operation Control Unit This functional block stores configuration TERM/ABBREVIATION DEFINITION and operation instructions from the CPU and BCC Block check character generates appropriate signals to control the device operation. It also contains read and BTC Block terminating character write circuits to permit communications be- SC Search character tween the CPU and the PGC registers via SSC Second search character (preceded by DLE) the data bus. The mode, command, and sta- CRC-16 X16 + X15 + X2 + 1 divisor, dividend pre-cleared tus registers are in this logic block. CRC-12 X12 + X11 + X3 + X2 + X + 1 divisor, dividend Character Register pre-cleared Characters to be considered for BCC gen- LRC-8 Horizontal parity on least significant 7 bits; vertical eration, parity generation and checking, or parity on most significant bit character comparisons are loaded into this register by either CEO or CEI. This register VRC Vertical redundancy check (character parity) serves as an input to the BCC and VRC gen- R/T Receiver/transmitter circuit. Also known as erator, where the accumulation and parity USART/USRT/UART/PCl/MPCC generation takes place. The character reg- BISYNC IBM binary synchronous communications (BSC), ister also serves as the input for character ANSI X3.28, ISO 1745 class array and DLE comparisons. MSB Most significant bit Character Class Array LSB Least significant bit This 128 x 2 array holds the character class Rx Receive associated with each of 128 possible 7-bit characters. The array is zero after a master Tx Transmit reset. When the character class array is loaded (see PGC Addressing), the character on the data bus is placed in the class specified by the contents of command regis- TxC Rir ter bits CR2 and CR3. The PGC uses these two command bits to represent four different character classes. These are:

TxD 1. Normal class (included in the accumula- USART tion) OR USRT 2. SYN character/ BISYNC not included DO-D7 RxD class a 3. Block terminating character /search class

CEO 4. Second search character class (preced- RIw ed by OLE) CPU AO Al These encoded character classes are used by the PGC: SCN2553 PGC CE1 1. To control the BCC accumulation of associated characters in BISYNC modes only. BCC accumulation in automatic or INT single accumulation modes is carried out independent of the character classes. NOTES 1. Open drain INT may be OR tied with SCN2651 PCI, SCN2661 EPCI, or other open drain 2. To detect characters and two character interrupt outputs. sequences in all modes of accumulation 2. No external circuitry necessary if SCN2651 or SCN2661 is the USART. and to set the control character detect Figure 1. Typical System Configuration bits in the status register. It should be noted that any number of characters (up to 128 for CRC-16 or LRC-8; up to 64 for CRC-12) can be put into any one class. If VRC is specified along with CRC-16 then the least significant 7 bits of the character are used for character array comparison. If VRC is not enabled, but CRC-16 is, the MSB of the character then determines whether a

Sig' et 1-35

MICROPROCESSOR DIVISION JANUARY 1983 POLYNOMIAL GENERATOR CHECKER (PGC) SCN26531SCN68653

character comparison is to take place. If the MSB is 0, the comparison takes place; if the MSB is 1, the comparison does not take place and the character is processed as though it were in the normal class. This en- a) CRC.16 ables the PGC to detect all communication control characters and DLE-SSC sequences.

Only the first 64 locations of the array are NO YES DISABLE accessed if CRC-12 is selected. The user CHARACTER should right justify each six bit character COMPARISON (DO-D5) to be written into the character YES NO class array. Bit 6 must be zero. If VRC is enabled, the generated parity becomes the most significant bit of the charac- ENABLE COMPARISON ter to be compared. VRC is not allowed in ON LOWER 7 BITS (D6-DO) BISYNC transparent mode. MSB IS IGNORED The method in which the character register contents is compared against the character class array depends on the BCC polynomial chosen. Figure 2 illustrates the comparison b) CRC.12 process. DLE Read Only Memory The DLE characters are stored internally and are selected by the error polynomial as ENABLE COMPARISON follows: ON LOWER 6 BITS (D5-DO) CRC-12: 01 1111 MSB IS IGNORED LCR-8 or CRC-16: BIT 6 MUST BE ZERO No VRC or odd VRC: 0001 0000 Even VRC: 1001 0000 BCC and Parity Generator This functional block performs all the neces- c) LRC•8 sary computation to generate and update the BCC accumulation on a character by character basis. It contains the three generator polynomials (CRC-16, CRC-12, and LRC-8) that can be selected to compute the ENABLE COMPARISON BCC. This block also checks and generates ON LOWER 7 BITS (D6-DO) odd or even parity for 7-bit (ASCII) charac- MSB IS IGNORED ters. NOTE Transparent mode always disables the SSC comparison. BCC Registers This block consists of two 8-bit registers (BCC upper and BCC lower) which contain Figure 2. Character Class Array Comparison Operation the high and low order bytes of the BCC accumulation. The result of the accumulation from the BCC and parity generator is The length of the block check character de- The BCC register(s) are read by the CPU stored in these registers. A recirculating pends on the error checking polynomial that after the last data character is transmitted. register address pointer is initialized by a is selected. If LRC-8 is chosen, the BCC They can then be sent to the R /T to com- power on, master reset, or clear BCC com- result is stored entirely in BCC upper. The plete a transmitted block of data. These reg- mand. The pointer alternately selects BCC BCC lower remains unchanged from pre- isters are read and loaded when one PGC is upper and lower on successive BCC register vious setting. Both BCC registers are used time-shared by several R /Ts. Refer to Appli- accesses for CRC-16 or CRC-12. For LRC- when CRC-16 is specified. When CRC-12 is cations Information - Multiplexed PGC. 8, BCC upper is always selected. selected, the block check character is 12 BCC upper and lower are cleared by a clear bits long. The six least significant bits of the PGC Addressing BCC or master reset command. The highest BCC are stored in the least significant bits All internal registers and the character class array are selected by the unique address term of the BCC polynomial is always repre- of the BCC lower. The remaining upper six codes shown in table 2. sented by bit 0 of BCC upper; the lowest bits of the BCC are stored in least signifi- term is always represented by bit 7 of BCC cant bits of BCC upper. The two most signifi- lower (see figure 3, Orientation of BCC Poly- cant bits in each BCC register are filled with nomials.) zero.

1.36

MICROPROCESSOR DIVISION JANUARY 1983 POLYNOMIAL GENERATOR CHECKER (PGC) SCN26531SCN68653

M (X) =. (X)+ R (X) , WHERE R (X1= AnXn+ An_iXn-1 . . . + A5X5 G (X) G (X) M ((): BINARY POLYNOMIAL (DATA STREAM) G (X) : FIXED DIVISOR TO GENERATE BCC 0(X) : QUOTIENT AFTER BCC GENERATION R(X) : REMAINDER AFTER BCC GENERATION

BCC LOWER BCC UPPER (8 BITS) (8 BITS)

07 DO 07 DO

A5X5 A7X7 A5X5

CRC — 16 = X16 + X15 + X7 +1

D7 D6 D5 DO D7 06 D5 DO 10 1 0 111 I t I (1 1 ° Iti jil

A0 X0 A5X5 A6)(6 Aii X71

CRC — 12 =X12 +X11

+X3 + X2 + X + 1

07 DO D7 D6 DO X X P —1+4LRCS (DON'T CARE) PARITY + (7-BIT LRC)

LRC — 8= HORIZONTAL PARITY ON 7 LSB VERTICAL PARITY ON MSB

RECEIVED, OR TRANSMITTED CHARACTER BITS RECEIVE, OR TRANSMITTED CHARACTER BITS (TO BE INCLUDED IN BCC ACCUMULATION ) (TO BE INCLUDED IN BCC ACCUMULATION)

3 14 5 1 6 1 7 1 8 1 9 110111112113114115 1311 C3 5 1.10,11,12,13 1 1 1 ,14,1M61f 1 FEEDBACK DATA FEEDBACK DATA

OPERATION OF BCC REGISTER FOR CRC-18 BCC OPERATION OF BCC REGISTER FOR LRC BCC ACCUMULATION (SIMPLIFIED) ACCUMULATION (SIMPLIFIED)

Figure 3. Orientation of BCC Polynomials

Signetics 1.37 MICROPROCESSOR DIVISION JANUARY 1983 POLYNOMIAL GENERATOR CHECKER (PGC) SCN2653/SCN68653

Table 2 ADDRESS CODES into the character register when in receive mode (MR2 = 0 and R/W = 0) while CEO CE1 Al AO R/W FUNCTION CPU/DMA characters are loaded into the 0 0 X X X Operation not guaranteed character register when in transmit mode (MR2 = 1 and Ft /W = 1). The time between 0 1 0 0 0 If MR2 = 0 load data bus into character register consecutive chip enables is given by tCEC If MR2 = 1 PGC not selected, or tCED• 0 1 0 0 1 If MR2 = 1 load data bus into character register If MR2 = 0 PGC not selected, The open drain active low interrupt signal (INT) goes active whenever one or more of 0 1 0 1 X PGC not selected, four maskable status conditions (SRO-SR3) 0 1 1 0 X PGC not selected, are true (= 1). A status read deactivates 0 1 1 1 X PGC not selected, INT. 1 0 0 0 0 Read character register The same techniques used In interfacing the 1 0 0 0 1 Load data bus into character register if MR1,0 SCN2651 PCI to 8-bit microprocessors can be * 002; write character class array using CR3, used to interface the SCN2653 PGC (consult CR2 class code if MR1,0 = 003,4 Application Note M22). Note that when ad- 1 0 0 1 0 Read Status register dressing the R/T's holding registers, the PGC 1 0 0 1 1 Write command register pins must have Al, A0=00 and that the address and R/W signals must be stable (set up) 1 0 1 0 0 Read mode register prior to the active low chip enable. When 1 0 1 0 1 Write mode register using the SCN2651 or SCN2661 as the R/T, 1 0 1 1 0 Read BCC upper/lower, the PGC's Al, A0, P-1-/W, and CEO are directly 1 0 1 1 1 Write BCC upper/lower, connected to comparable SCN2651 or SCN2661 signals. Schematics of an SCN2653 1 1 X X X PGC not selected, monitoring data transfers to/from the NOTES Signetics SCN2651/2661 and SCN2652 are 1. Data bus is 3-state shown in figures 4 and 5. 2. Character will not be accumulated unless MR3 = 1. 3. Character will not be accumulated even if MR3 = 1. An alternate interfacing technique is to treat 4. The mode bits MR1 and MRO are cleared to 00 by power-on-reset, master reset, or by the PGC as an independent peripheral de- loading the mode register bits MR1 and MRO. vice. This necessitates a write character 5. Recirculating internal pointer selects BCC Upper on first access, BCC lower on next register instruction after the CPU reads or access for all BCCs except for LRC-8; in case of LRC-8, the pointer only selects BCC upper. writes a character to or from the R /T.

INTERFACE SIGNALS AND TIMING PGC data transfers are controlled by Al, AO, and R/W which must be stable prior to the active low going chip enable pulse. CEO is used for PGC monitoring of data transfers between a CPU/DMA controller and a R /T; CE1 is used for direct CPU-to-PGC transfers. MR3 must be set prior to loading the character register in order to accumulate or compare characters via CE1. The active low (leading) edge of chip enable initiates a PGC read/write cycle; the rising (trailing) edge ends the cycle and also serves as a write strobe.

When loading the character, mode, or command register, the data bus is strobed into the selected register on the trailing (rising) edge of the appropriate CE. When writing into the character class array, the data on the bus (the special character) is placed in the class specified by command register bits CR3 and CR2.

Characters are transferred into the character register when CEO is active (low) depending on the state of MR2 and the R/W Figure 4. SCN2651 or SCN2661 /2653 Interface input. Characters from the R/T are loaded

1.38 Signetics MICROPROCESSOR DIVISION JANUARY 1983 POLYNOMIAL GENERATOR CHECKER (PGC) SCN26531SCN68653

register for BCC accumulation, VRC INTERRUPTS TxBE, TxU, RxDA, RxSA generation/ checking, BTC/ SC and DLE- SSC comparisons. See table 3 for a summary of BCC accumulation modes. DB7-DBO SCN2652 TxD BCC accumulation depends on the mode se- MPCC lected. A2 RXD Al BISYNC Normal AO TxC In BISYNC normal mode, all characters load- 14/W RxC ed into the character register are accumu- OBEN lated except those in the SYN/BISYNC not CE DB7-DBO CPU included class. During receive (MR2 = 0), a BTC/SC match will cause the BCC accumu- CEO lation to stop after the next one (LRC-8) or SC N2653 two (CRC-12 or CRC-18) characters have PGC Al been accumulated. At that time, if the BCC accumulation does not equal zero, the BCC 171/W error bit (SRO) will be set and INT will go AO active if the corresponding mask bit (CR4) is CE1 enabled (= 1). In transmit (MR2 = 1), the BCC accumulation is automatically stopped INT once the BTC / SC character has been accu- (OPEN DRAIN) mulated. The CPU must read the BCC upper and BCC lower (CRC-12 or CRC-16) regis- O + 5V ter(s) and transmit them to the R /T. Figure 5. SCN2652/2653 Interface — Typical Protocols: BISYNC, DDCMP, Note that the received BCCs are not subject SDLC, HDLC to VRC if CRC-18 is selected. If LRC-8 is selected, the received BCC is subject to VRC. An incorrect result will set the VRC PGC PROGRAMMING places all characters in the normal class error bit (SRI). After its accumulation, the least significant 7 bits of BCC upper are The PGC operational mode must be initially (included in the BCC accumulation). checked and a non-zero result will set the programmed by the CPU (see figure 6). The BCC error bit (SRO). BCCs are not checked mode register, command register and char- OPERATION against the character class array nor are acter class array should be written into, The PGC should be initially configured by they compared to the DLE ROM. after a power-on-reset or a master reset the CPU (via CE1) prior to systems oper- command. The character class array should ation. This is done by loading the mode reg- Second search character (SSC) detection be programmed only for the classes perti- ister, command register and character class is enabled so that a DLE-STX or two charac- nent to the application. After a master reset, array (see PGC PROGRAMMING). Charac- ter communication control sequence can be the character class array is zero which ters may then be loaded into the character detected.

Table 3 SUMMARY OF BCC ACCUMULATION MODES ACCUMULATION START STOP CHARACTERS EXCLUDED MODES ACCUMULATION ACCUMULATION FROM ACCUMULATION BISYNC normal and Clear BCC registers command After BTC has been detected SYN/BISYNC not included BISYNC transparent and received BCC is class in normal mode Mode register is loaded with accumulated BISYNC or automatic mode DLE-SYN/not included class After transmitted BTC has been and first DLE of a DLE non SYN Start accumulation command accumulated pair in transparent mode. These characters are not ex- Load BCC registers Single mode is selected eluded if preceded by an odd number of DLEs

Automatic Same as above Single mode selected None Single Start accumulation command After each character has been Up to user who must generate accumulated start accumulation command for each character to be included

1.39 MICROPROCESSOR DIVISION JANUARY 1983 POLYNOMIAL GENERATOR CHECKER (PGC) SCN26531SCN68653

are accumulated (depending on LRC-8 or CRC-12/ 16, respectively) and the PGC will (POWER ON) automatically stop further accumulation. However, the PGC can continue the accumulation if a start accumulate command is issued or either BISYNC mode is MASTER RESET COMMAND loaded into the mode register. The start ac- CR1, CRO=11 cumulate command should be given to the PGC before loading the character that follows the detected BTC /SC. This procedure LOAD COMMAND REGISTER WITH CR3, CR2= 01 enables a special search character to be (SYN/NI CLASS) detected (the BTC/SC detect bit (SR2) will be set and an interrupt generated if CR6 = 1) with the BCC accumulation continuing WRITE SYN/BISYNC NOT INCLUDED CHARACTERS INTO (see figures 7 and 8). CHARACTER CLASS ARRAY Automatic Accumulate All characters loaded into the character LOAD COMMAND REGISTER WITH CR3, CR2 =10 register are accumulated, BTC/ SC and SSC (BTC/SC CLASS) detection is enabled. The BCC accumulation is not automatically terminated. (The CPU must use single accumulate mode to stop WRITE BTC/SC CHARACTERS INTO CHARACTER CLASS the accumulation). When in receive mode, ARRAY the BCC error bit (SRO) is set /reset after accumulating each character so that the CPU must examine this bit after the last LOAD COMMAND REGISTER WITH CR3, CR2=11 character is accumulated. SRO = 0 if the (SSC CLASS) accumulated remainder in the BCC register(s) is zero; otherwise SRO = 1. Examples of use of automatic accumulate mode usage WRITE SCC CHARACTERS include an R/T (SCN2651/SCN2661) in trans- INTO CHARACTER CLASS ARRAY parent DLE/SYN strip mode and asynchronous/synchronous/parallel DDCMP.

LOAD MODE REGISTER Single Accumulate WITH MRI, MRO = 01, 10, OR 11 All characters for which a start accumulate (FOR SELECTED BCC POLYNOMIAL) command (CR), CRO = 01) is given are accumulated and compared against the character class array. If not given, the BCC ac- ( OPERATE ) cumulation is not updated and BTC/SC and SSC detection is disabled. Operation in this mode is otherwise identical to automatic ac- Figure 6. PGC Programming cumulate. Single accumulate mode can be used to se- BISYNC Transparent In receive and transmit modes, the termina- lectively accumulate characters under CPU BISYNC transparent mode should be used tion of BCC accumulation works exactly as control or to accumulate characters that were unintentionally excluded in one of the for data blocks beginning with DLE-STX if in BISYNC normal, except that the BTC/ SC other modes. the DLEs are transferred between CPU and must be immediately preceded by an odd R /T (CEO) or CPU and PGC (CE1), i.e., DLEs number of DLEs to be identified as a Polynomial Selection and DLE are not stripped. VRC should be disabled in BTC SC. this mode. Characters excluded from the Comparison Second search character detection is not BCC accumulation are the first DLE of a The BCC polynomial may be CRC-16, CRC- enabled in BISYNC transparent. DLE-non SYN sequence pair and the DLE- 12 or LRC-8. The cyclic redundancy check SYN sequence if not preceded by an odd After a BTC/ SC class character is detected (CRC) is generated by dividing the binary number of DLEs. For example, consider the by the PGC when receiving in either BISYNC value of a character in the character regis- following transparent mode character string: mode, the following one or two characters ter by the selected polynomial. The quotient is discarded and the remainder is used as the BCC (two 6-bit characters for CRC-12, two 8-bit characters for CRC-16). CRC-16 DLE DLE SYN DLE DLE DLE SYN DLE ETX ••••••••••••••••, uses all 8 bits of each BCC register. CRC-12 uses the least significant 6 bits of the BCC exclude include exclude include exclude exclude include registers. The two most significant bits of both both the BCC registers are cleared to zero whenever CRC-12 is selected (see figure 3).

1.40 Signetics MICROPROCESSOR DIVISION JANUARY 1983 POLYNOMIAL GENERATOR CHECKER (PGC) SCN26531SCN68653

SHADED AREAS ACCUMULATED CHARACTER CLASS ARRAY: Rx = RECEIVE MODE SYN/BISYNC NOT INCLUDED: SYN, SOH NO DLE/SYN STRIPPING BTCISC: ETX, ETB, ITB, ENO SSC: STX CRC-16 OR CRC.12

SYN SYN SOH STX C BCC. PAD

SET BISYNC ETC BCC ERROR (Rx) IF ACCUMULATION z0. NORMAL MODE DETECT ACCUMULATION STOPPED AFTER 2nd (ALL EXAMPLES) BCC. NO PARITY CHECK ON BCCs

LRC.8

SYN SYN SYN SYN PAD 2.

CPU RESETS BCC REGISTERS BTC BCC ERROR (11x) IF 7 LS BITS OF BCC° # 0. AFTER SOFTWARE DETECT DETECT VRC ERROR IF MS BIT IS INCORRECT OF STX. THIS EFFECTIVELY PARITY. ACCUMULATION STOPPED EXCLUDES STX. AFTER 1 BCC.

BLOCK 1 BLOCK 2

SYN SYN SOH T 17E1 BCC BCC . SYN SYN 'DLE ST' 4 BTC OPTIONAL SSC DETECT BTC POSSIBLE DETECT SET BISYNC DETECT BCC ERROR TRANSPARENT

POSSIBLE BCC ERROR. (IF SO RESET BCC REGISTERS). RESET BCC REGISTERS OR SET BISYNC NORMAL

4. SYN SYN SOH D LE STX ETB ITB ETX DLE DLE SYNIDLE SYNI DLEFTX IBCGIBCCIPAD

SSC DETECT BTC POSSIBLE SET BISYNC DETECT BCC ERROR TRANSPARENT MODE

BLOCK 1 BLOCK 2

SYN SYN DLE-ST• T IN SYN DLE SYN IDLEF4M DLEIITBI4C+TX1 TXIECAECCl PAD 4 SSC ETC POSSIBLE BTC DETECT DETECT BCC ERROR DETECT

SET BISYNC POSSIBLE TRANSPARENT AND RESET BCC BCC ERROR RESET BCC REGISTERS REGISTERS (IF BCC ERROR) NOTES AND SET BISYNC 1. BCC error only for receive mode. In transmit mode, CPU must respond to BTC detect by NORMAL reading the BCC register(s) and sending them to the R /T. The accumulation is stopped after the BTC is accumulated. 2. ENO (DLE-ENO) in a text message should be treated as an abort. 3. Opening SYNs may be stripped by the R /T. 4. The single accumulate mode and command can be used to accumulate a character that inadvertently was excluded. (For example, the DLE of a DLE-STX if the PGC was in transparent mode and there was not a line turnaround prior to the DLE). The single accumulation should be done using CE1 after the BCC(s) have been accumulated.

Figure 7. Examples — Bisync Text Message BCC Accumulation Signetics 1.41 MICROPROCESSOR DIVISION JANUARY 1983 POLYNOMIAL GENERATOR CHECKER (PGC) SCN26531SCN68653

is selected as the BCC polynomial. MR4 = 1

BTC/SC: EOT, NAK enables VRC generation and detection for SCC: ACKO, ACK1, WACK, RVI both receive and transmit operations. Char- SINGLE ACCUMULATION MODE acters loaded into the character register will STOPS BCC ACCUMULATION have VRC generated on the least significant CONTROL STATION POLL OR 1. SYN SYN IEOTI PAD I SYN SYN I a- - I ENO SELECTION OF A TRIBUTARY 7 bits with the generated parity bit written STATION into the character register MSB. If the generated parity does not match the MSB of the BTC/SC BTC/SC loaded character, the VRC error bit (SRI) is DETECT DETECT set and INT asserted if the corresponding a REPRESENTS A UNIQUE POLLING OR SELECTION ADDRESS mask bit was enabled (CR5 = 1). Thus, if 7- TRIBUTARY STATION PREPARED bit characters are to be transmitted with 2. SYN SYN I ACK 0 TO RECEIVE OR POSITIVE ACKNOWLEDGEMENT OF EVEN VRC, CR5 should be zero and SR 1 ignored. NUMBERED TEXT BLOCK 8-bit characters with a VRC bit in the MSB SCC position are parity checked by the PGC in DETECT both transmit (to R /T) and receive (from

TRIBUTARY STATION NOT READY R/T) modes, i.e., the PGC operates as a 3. SYN SYN I NAK 'PAD] TO RECEIVE OR NEGATIVE data bus parity checker. ACKNOWLEDGEMENT OF TEXT BLOCK CHARACTER CLASSES BTCISC DETECT Normal (Included in the TRIBUTARY STATION TEMPORARILY 4. SYN SYN I WACK NOT READY TO RECEIVE Accumulation) Any character that belongs to this class is normal data, i.e., the character is not a com- SCC munication control or other special charac- DETECT ter. Characters in this class are always ac- REVERSE INTERRUPT FROM s. SM SYN I RVI RECEIVING STATION TO REQUEST cumulated in BISYNC, automatic and single TERMINATION OF THE CURRENT accumulation modes. TRANSMISSION BECAUSE THE RECEIVER WANTS TO TRANSMIT SYN Character/BISYNC Not SSC DETECT Included NOTES SYN characters are never accumulated in 1. BCC accumulation should be ignored for control messages. This can be effected by BISYNC normal accumulation mode. In single accumulate mode without single accumulate commands. BISYNC transparent accumulation mode, 2. Characters programmed as SSCs should be the binary equivalent of the second character of the DLE-SSC sequence. the DLE-SYN character pair is not accumulated, but a SYN not preceded by a DLE is Figure 8. Examples — Bisync Control Messages accumulated. (OLE is implied as an odd number of DLEs). Block Terminating Character When the PGC is in receive mode (MR2 = the character is compared against the char- (BTC)/Search Character (SC) 0), the received BCC will be accumulated. acter class array, the MSB is not used. This BTC /SC characters have two functions in The result will be zero for an error free mes- may result in a false BTC or SSC detection if the PGC: termination of BCC accumulation sage. there is a VRC error. However, the VRC er- and character detection. In BISYNC trans- ror bit (SR1) will be set under that condition. parent mode, a BTC /SC must be preceded CRC-12 is used with 6-bit codes. The inter- by an odd number of DLEs to be recognized. nal 6-bit transcode DLE character hex 1F is The LRC-8 is generated by the exclusive OR selected by CRC-12. VRC should be dis- of the 7 least significant bits of the charac- • Termination of BCC abled (MR4 = 0) for CRC-12 operation. The ter register and the BCC upper. The most Accumulation two most significant bits of the character significant bit of the LRC-8 check character In BISYNC normal and transparent accu- register are ignored when compared to the is a vertical odd/even parity bit (MR5 = mulation modes, the PGC will stop the ac- internal 6-bit DLE. When the character is 0/ 1), which is generated on the least signifi- cumulation upon the detection of the checked against the character class array, cant bits of that character. The selection of BTC /SC character. Examples of BTCs the MSB is ignored and the next MSB (bit 6) LRC-8 implies VRC is enabled and that only are ETX, ETB, ITB, ENQ. is assumed to be zero. If CRC-12 is speci- the BCC upper is used for the BCC accumu- In receive mode, the accumulation is fied, the user must write to the character lation. The BCC lower remains unchanged stopped after the following one (LRC-8) class array with bit 6 cleared. from previous setting. or two (CRC-12, CRC-16) character(s) CRC-16 or LRC-8 implies the use of ASCII or have been accumulated. In transmit EBCDIC although any 7-bit plus parity or 8- VRC Generation and Detection mode, the accumulation is stopped after bit no parity code may be used (with DLE = Parity (VRC) is enabled by MR4 and speci- the BTC /SC character has been accumu- hex 10 or hex 90). The DLE character com- fied as odd or even by MR5. VRC should be lated. The BTC /SC character is always pare is on an 8-bit basis with the generated disabled when in BISYNC transparent mode accumulated in all of the accumulation parity (if VRC is enabled) as the MSB. When and whenever CRC-12 or CRC-16 (EBCDIC) modes.

1.42 Signetics MICROPROCESSOR DIVISION JANUARY 1983 POLYNOMIAL GENERATOR CHECKER (PGC) SCN2653/SCN68653

• Character Detection Second Search Character number of DLE5. Under those conditions, the BTC /SC characters will be detected in Class (SSC) SSC status bit (SR3) will be set. any of the four accumulation modes when Control functions in character oriented data The SSC character is always accumulated that character is being accumulated. The link control procedures can be represented in all of the accumulation modes. BTC /SC status bit (SR2) is set on detec- by a sequence of two characters, the first tion. Since detection also stops BISYNC character being a DLE. Examples include REGISTER BIT DESCRIPTION BCC accumulation, the BISYNC accumu- ACKO, ACK1, WACK, RVI, DISC, WBT and The operation of the PGC is determined by lation must be restarted if the character is the initiation of transparent text (DLE-STX). programming the mode register and the not a BTC. This can be effected by load- The PGC will detect such sequences, ex- command register. The status register pro- ing BISYNC mode into the mode register cept in BISYNC transparent mode, when an vides feedback on potential interrupt condi- or generating a start accumulation com- SSC class character is being accumulated tions. Formats of these registers are shown mand. after being immediately preceded by an odd in table 4.

Table 4. PGC REGISTER BIT FORMATS

MR7 MRS MR5 MR4 MR3 MR2 MR1 MRO

ACCUMULATION MODET I--- BCC POLYNOMIAL 00 SINGLE 00 START UP MODE 01 AUTOMATIC 01 CRC•18 10 BISYNC NORMAL 10 CRC.12 11 BISYNC TRANSPARENT 11 LRC.8

ODD/EVEN PARITY RECEIVE/TRANSMIT 0 ODD 0 RECEIVE 1 EVEN 1 TRANSMIT

VRC ENABLE ENABLE ACCUMULATION 1= 11 WITH CEI (=1) MODE REGISTER

CR7 CR6 CR5 CR4 CR3 CR2 CR1 CRO

SECOND SEARCH CHARACTER ONE•TIME COMMANDS DETECT INTERRUPT 00 NOP ENABLE = 1 01 START ACCUMULATION 10 CLEAR BCC REGISTER 11 MASTER RESET

BTC/SC DETECT INTERRUPT ENABLE = 1 CHARACTER CLASS 00 NORMAL CLASS 01 SYN/NI CLASS 10 BTC/SC CLASS VRC ERROR INTERRUPT 11 SSC CLASS ENABLE = 1

BCC ERROR INTERRUPT ENABLE= 1

COMMAND REGISTER

SR7 SR6 SR5 SR4 SR3 SR2 SR1 SRO

CR7 BCC ERROR (= 1) CR8 VRC ERROR (= 1) CR5 BTC/SC DETECT 1= 1) CR4 SSC DETECT I=1) STATUS REGISTER Signelics 1.43 MICROPROCESSOR DIVISION JANUARY 1983 POLYNOMIAL GENERATOR CHECKER (PGC) SCN26531SCN68653

Table 5 BCC ACCUMULATION BY CHARACTER CLASS BISYNC BISYNC AUTOMATIC SINGLE CR3 CR2 CLASS NORMAL TRANSPARENT ACCUM ACCUM 0 0 Normal Yes Yes Yes Yes 0 1 SYN /BISYNC No Yes, unless preceded by Yes Yes not included an odd number of DLEs 1 0 BTC /SC Yes Yes Yes Yes 1 1 SSC" Yes Yes Yes Yes

NOTE 'Preceded by DLE

Mode Register acter class array and DLE ROM. This bit character accumulated is the character that The mode register defines general PGC op- setting should be used when the CPU /DMA is in the character register at the time the eration characteristics. MR1 and MRO = 00 controller sends data characters to be ac- command is given. The accumulation stops permit the character class array to be pro- cumulated or compared to the PGC and the immediately after the character has been grammed. These bits will be zero after a R/T is inactive (off line). If the R/T were accumulated. If the command is given in ei- power on or master reset command. After active, then a DLE or BTC loaded into the ther of the BISYNC or automatic accumula- the character class array is programmed, character register via CEO would cause in- tion modes, it enables the PGC to accumu- these bits should be set to 01, 10, or 11 to correct accumulation and character com- late the BCC starting with the next character select the CRC-16, CRC-12 or LRC-8 poly- parisons if the next character was loaded loaded into the character register. This is a nomials. via CE1. means of restarting a BISYNC normal accumulation after detection of a BTC /SC that is MR2 (Tx/Fix) determines whether or not the MR4 is a VRC enable bit. If MR4 = 1, VRC is not a valid BTC (example; CR, LF, TAB). In PGC is to generate (Tx) or generate and enabled as odd /even by MR5. VRC is gen- all accumulation modes, a previously de- check (Rx) the BCC. It is used with 711/W to erated on the 7 LS bits of the character and tected DLE will not be cancelled by this determine if the data bus is to be loaded into the MS bit is checked against the generated command. the character register when CEO, CE1, Al, parity. If not equal, SR1 is set. If MR4 = 0, AO = 0100. VRC is not enabled. MR4 = 0 is used for CR1, CR0 = 10 is a clear BCC registers BISYNC transparent mode with ASCII code, command. Both BCC registers are cleared If MR2 = 1: 1) the PGC will generate the and for both BISYNC modes for EBCDIC and along with the associated internal pointer BCC, but will never set the BCC error bit SBT. and SRO-SR3. The pointer points to BCC up- (SRO). 2) If the R/W pin is high when CEO, per. INT is forced high. This command per- CE1, Al, AO = 0100, then the data bus will MR5 is an odd/even VRC bit. If MR5= 1, the mits BCC accumulation, starting with the be loaded into the character register. If W total number of 1 bits in the character in- next character loaded into the character is low under these conditions, the PGC is not cluding the parity bit is even. If MR5= 0, the register in BISYNC or auto modes. Single selected. total number of bits is odd. This bit is accumulate mode requires a start BCC ac- ignored if MR4 = O. If MR2 = 0: 1) the PGC will accumulate the cumulation command. BCC and set the BCC error bit (SRO) when MR7, MR6 select the BCC accumulation CR1, CRO = 11 is a master reset command. appropriate. 2) If the R/W pin is low when mode. These modes have been previously All internal registers (except the character CEO, CE1, Al, AO = 0100, then the data bus discussed in the operation section. register), the internal pointer, and the entire will be loaded into the character register. If character class array are cleared. INT is R/W is high under these conditions, the Command Register forced high. PGC is not selected. The command register contains four inter- CR3 and CR2 are used for programming the rupt enables, a 2-bit character class code MR3 is a CE1 accumulate/compare enable character class array. During a write char- used when programming the character class bit. If MR3 = 0, characters loaded into the acter class array instruction, the character array, and 2 bits that specify three one time character register by CE1 are not accumu- corresponding to the 7 LS bits of the data commands and a NOP. lated, checked against the character class bus is placed in the class contained in CR3 array, or compared to the DLE ROM. Parity CR1, CR0 = 00 is a NOP. This bit setting is and CR2. The encoded character classes will be generated and checked if VRC is en- used when changing CR7-CR2 without af- control the accumulation of the associated abled (MR4 = 1). The primary use of MR3 = fecting any of the 3 one time commands. character as shown in table 5. 0 is to generate parity on a 7-bit character Detection operates under the conditions which is to be transmitted to an HIT. The CR1, CR0 = 01 is a start BCC accumulation CPU loads the character register with the 7- command. In single accumulation mode, the shown in table 6. bit character and reads the 8-bit VRC gener- Table 6 BTC/SC AND SSC DETECTION CONDITIONS ated character via CE1. This 8-bit character is then transferred to the R/T via CEO. An- BISYNC BISYNC AUTO SINGLE other application of MR3 = 0 is for a CPU to CLASS NORMAL TRANSPAR- ACCUM ACCUM interleave parity checking on memory data ENT (CE1) with on line R/T data transfers (CEO). BTC /SC Yes Yes • Yes Yes t If MR3 = 1, characters loaded into the char- SSC Yes* No Yes' Yes • t acter register by CE1 will be accumulated NOTES (according to the BCC accumulation mode • Only if immediately preceded by an odd number of DLEs. selected) and compared against the char- Start accumulate command necessary for detection.

1.44 Signetics MICROPROCESSOR DIVISION JANUARY 1983 POLYNOMIAL GENERATOR CHECKER (PGC) SCN26531SCN68653

CR7, CR6, CR5, CR4 are interrupt enables only be set when in BISYNC normal, auto, or BCC registers. These registers are that individually enable/disable INT when single accumulate modes. When set, it indi- accessed via CE1. There must be a sepa- the corresponding status register condition cates that the character being accumulated rate save area for each R/T (serial channel) is true (set). Each bit is set in order to en- is of the SSC class when that character was and a channel pointer indicating the last R/T able INT upon the condition. Each bit is reset immediately preceded by an odd number of that transferred or received a data charac- to disable INT upon the condition. The state DLEs. ter (see figure 10). of these bits may be read via the status SR7, SR6, SR5, SR4 are interrupt enables. The loading of the BCC registers will clear register (SR7, SR6, SR5, SR4). These 4 bits reflect the state of the inter- SRO-SR3 and all previously detected spe- The corresponding status bits (SR3, SR2, rupt enable command bits CR7, CR6, CR5, cial characters, i.e., DLE, BTC/ SC, BCC SRI, SRO) are set independent of the inter- and CR4, as follows: (BISYNC modes). The BCC accumulation rupt enables. The bit assignments are: SR4 - BCC error will start again when the next character is loaded into the character register in all ac- CR4 - BCC error interrupt enable SR5 - VRC error cumulation modes except single. That mode CR5 - VRC error interrupt enable SR6 - BTC/ SC detect requires a start accumulation command. Figures 11 and 12 represent software flow CR6 - BTC/SC detect interrupt enable SR7 - SSC detect diagrams for transmit and receive service CR7 - DLE-SSC detect interrupt enable APPLICATIONS INFORMATION requests. Note that interrupts from all other Status Register Dedicated PGC R /Ts must be masked during a read or write to the BCC registers so as not to affect the This register reflects the status of the 4 con- The most efficient use of the 2653 is to dedi- internal BCC address pointer. It is recom- ditions that are potential interrupt (INT) cate one to each R/T for two way alternate mended that all R/T interrupts be masked sources and the 4 interrupt enables in the (half duplex) operation or two to each R/T while servicing an interrupt that accesses command register. A status register read for two way simultaneous (full duplex) oper- any PGC register. clears SRO, SRI, SR2, SR3 and deactivates ation (see figure 9). The CPU configures INT. These bits are also cleared by a master each PGC (using CE1) by initializing the reset or clear BCC command. mode register, command register, and char- BISYNC Operation Table 7 is a concise listing of 2651/2661 SRO is a BCC error bit. This bit can only be acter class array. Data transfers to or from operating modes with recommended corre- set in receive mode (MR2 = 0). In BISYNC the R/T can then be on a DMA basis with sponding 2653 BCC accumulation modes. normal and BISYNC transparent modes, SRO each receiver holding register ready signal will be set/reset once the accumulation has used as a read request (RREQ) and each Character Comparator transmit holding register available signal been stopped by the detection of the The PGC can be used as a programmable used as a write request (WREQ) to the DMA BTC/SC character and accumulation of the data bus character comparator which moni- controller. The CPU needs only to respond BCC(s). tors data bus transfers (CPUiperipheral, to enabled interrupts from each of the PGCs. In automatic and single accumulate modes, CPUCPU, CPU,—imemory, memorp—peri- The individual INT outputs can be wire-OR'd SRO is set /reset after each character in the pheral (via DMA)). The user selectively into a single CPU interrupt (INTRPT) with one character register has been accumulated. loads the character class array with pull up resistor. Each PGC in this system has BTC/SC and SSC characters to be com- a unique address that is decoded into the The rules for the detection of a BCC error pared. Status bits will be set and an interrupt respective chip enables. are: can be generated upon SC and DLE - SSC SRO = 1 LRC-8: 7 least significant bits The CPU or DMA controller could send a detection. A match on one to 128 different of BCC upper # 0 block of memory data to the PGC to be error characters or DLE - SSC sequences can be CRC-12, CRC-16: BCC upper checked without sending that data to the programmed. or BCC lower # 0 R /T. In that case, CE1 is used. Figure 13 depicts an arrangement where the SRO = 0 LRC-8: 7 least significant bits Multiplexed PGC DMA controller or slave CPU handles data of BCC upper = 0 One PGC may be time-shared among a few bus transfers, the PGC interrogates the data CRC-12, CRC-16: BCC upper R /Ts if the CPU saves and restores the bus, and the host CPU responds to PGC and BCC lower = 0 mode register and partial BCC result in the interrupts.

SR1 is a VRC error bit. When set, this bit Table 7 BISYNC (ANSI 3.28, ISO 1745) MODES FOR 2651/2661 reports a character parity error (on receive AND 2653 or transmit) when parity is enabled (MR4 = 1). Parity is odd/even as specified by MR5. 2651/2661 2653 The parity bit will be regenerated in the OPERATING MODES BCC ACCUMULATION MODE character register. Sync normal non-strip BISYNC normal SR2 is a BTC/SC detect bit. When set, this Sync transparent non-strip BISYNC transparent bit indicates the character being accumulat- Normal SYN/DLE strip, BISYNC normal ed is of the BTC/SC class for BISYNC normal, automatic and single accumulate Transparent SYN/DLE strip, Automatic accumulate2 modes. In BISYNC transparent mode, the Async (with SYN /DLE BISYNC normal BTC /SC character being accumulated must characters) be immediately preceded by an odd number of DLEs for this bit to be set. NOTES 1. CPU should switch to non-strip mode after BTC detect. Otherwise a received BCC could be inadvertently stripped. SR3 is a DLE SSC detect bit. This bit can 2. SSC detect should be ignored. Signetics 1.45 MICROPROCESSOR DIVISION JANUARY 1983 POLYNOMIAL GENERATOR CHECKER (PGC) SCN26531SCN68653

WREOABC RRE.ABc ADDR F CE TxD N/W DIRECT RECIXMT RxD READ/WRITE MEMORY MEMORY ACCESS WREOA \ POC RREOA

CE1 CEO

TxD REXIXMT

CPU RxD DATA CONTROL ADDRESS WRECIB PGC RREOB INT CEO CE1

TxD ADVANTAGES: RECIXMT • HIGHER THROUGHPUT WITH DMA RxD • NO SOFTWARE OVERHEAD FOR MULTIPLEXING 17 WRE0c PGC 1 RRECIc R/Ts USE DEDICATED PGCs TO GENERATE AND DETECT BOTH VRC, LRC, CRC AND SPECIAL CHARACTERS ._ CE1 CEO

FROM CPU

Figure 9. One PGC Per Receiver/Transmitter

ADDRESS DATA R/W TxD RECIXMT RxD CEO READ/WRITE MEMORY TxD RECIXMT RxD CEO

TxD RECIXMT RxD ADDRESS, DATA, giw, CEO ADDR CPU DATA RIW CE1 CEO PGC INT

ONE PGC IS TIME-SHARED BY THREE R/Ts. THE CPU READS AND RESTORES THE PARTIAL BCC REMAINDER FOR EACH SERIAL CHANNEL. Figure 10. PGC Services Multiple Receivers/Transmitters

1.46 Signetics MICROPROCESSOR DIVISION JANUARY 1983 POLYNOMIAL GENERATOR CHECKER (PGC) SCN26531SCN68653

Tx HOLDING REGISTER AVAILABLE CHANNEL 1

IS CHANNEL NO READ BCC AND STORE IN BCC CHANNEL I POINTER = I SAVE AREA SPECIFIED BY BCC AND CHANNEL POINTER. MODE DATA READ MODE REGISTER AND BCCA AND STORE IN SAVE AREA. MODE e R

YES

I.CHANNEL POINTER

LOAD CHARACTER INTO RIT AND PGC VIA ZO

READ PGC ISTATUS REGISTER

CHECK STATUS BITS AND PROCEED AS REQUIRED

Figure 11. Multiplexed PGC — Transmit to R/T

Rx HOLDING REGISTER READY

READ BCCA 1 AND STORE IN BCC SAVE AREA SPECIFIED BY CHANNEL POINTER. READ MODE REGISTER AND STORE IN SAVE AREA.

CHANNEL j BCC AND MODE DATA BCCuo AND MODE REGISTER

• CHANNEL POINTER

READ CHARACTER FROM R/T AND LOAD INTO PGC VIA CEO

I READ PGC STATUS REGISTER

CHECK STATUS BITS AND PROCEED AS REQUIRED

Figure 12. Multiplexed PGC — Receiver from R/T

Signetics 1.47

MICROPROCESSOR DIVISION JANUARY 1983 POLYNOMIAL GENERATOR CHECKER (PGC) SCN26531SCN68653

INT AS, Al, A/W

CE1 PGC

PERIPHERAL DEVICE

CPU DATA BUS 8/

SLAVE CPU CEO

ITI/ W MEMORY

APPLICATIONS INCLUDE CHARACTER ARRAY MA, MC COMPARISIONS, VRC AND/OR BCC CHECKS ON THE DATA BUS.

DMA' NOTE CONTROLLER * CPU initializes DMA controller for each block transfer of data.

Figure 13. PGC Data Bus Monitoring with DMA Transfers

ABSOLUTE MAXIMUM RATINGS1

PARAMETER RATING UNIT Operating ambient temperature2 0 to +70 °C Storage temperature -65 to +150 °C All voltages with respect to ground3 -0.5 to +6.0 V

NOTES 1. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operation sections of this specification is not implied.

2. For operating at elevated temperatures the device must be derated based on +150°C maximum junction temperature.

3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. However, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.

1.48 Signetics MICROPROCESSOR DIVISION JANUARY 1983 POLYNOMIAL GENERATOR CHECKER (PGC) SCN26531SCN68653

DC ELECTRICAL CHARACTERISTICS TA = 0°C to 70°C, Vcc = 5.0V ± 5%

LIMITS PARAMETER TEST CONDITIONS UNIT Min Typ Max Input voltage V VIL Low 0.8 VIH High 2.0 Output voltage V VOL Low IOL = 2.2mA 0.25 0.45 VOH High 10H = —400AA 2.4 2.8 !IL Input load current VIN = 0 to 5.5V 10 AA Output leakage current µA ILD Data bus VOUT = 4.0V 10 ILO Open drain VOUT = 4.0V 10 ICC Power supply current 45 75 mA

AC CHARACTERISTICS TA = 0° to +70°C, VCC = 5v ± 5%1 2 3

LIMITS PARAMETER UNIT Min Max ICE Chip enable pulse width 250 ns tCED Chip enable period D 1750 ns ICEC4 Chip enable period C 1750 ns tAS Address setup 10 ns tAH Address hold 10 ns tCS Control setup 10 ns tCH Control hold 10 ns tDS5 Data setup 150 ns tDH Data hold 10 ns t0D6 Data delay time for read 200 ns tDF6 Data bus floating time for read 100 ns tINTL7 Interrupt low delay 1600 ns tINTH7 Interrupt high delay 600 ns

NOTES 1. Parameters are valid over operating temperature range unless otherwise specified. 2. All voltage measurements are referenced to ground. All time measurements are at 50% level for inputs and at the 0.8V or 2.0V level for outputs. Input levels for testing are 0.45V and 2.4V. 3. Typical values are at +25°C, typical supply voltages and typical processing parameters. 4. tCEC = 600ns during PGC initialization when no BCC accumulation is in progress. 5. tps = 50ns whenever CEO is used. 6. Test conditions: CL = 150 pF. 7. INT is an open drain output.

Signetics 1.49 MICROPROCESSOR DIVISION JANUARY 1983 POLYNOMIAL GENERATOR CHECKER (PGC) SCN2653ISCN68653

CEO, CEI

tCED

CE1 (WRITE TO MODE OR COMMAND REG READ BCC REGSITERS, STATUS REG ) 10EC

al (WRITE TO CHARACTER REGISTER tCED WRITE CHARACTER CLASS ARRAY) 4 p AO, Al

1AS AH tAS.- tAH

RIW S tCS tCH 'Cs BCH

DO-D7 (WRITE)

IDS tDH H

DO-D7 (READ)

tDF tDF INT

tINTL

1INTH

Figure 14. PGC Timing

1.50 Signetics

MICROPROCESSOR DIVISION JANUARY 1983

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE SCN2661/68661

DESCRIPTION Transparent or non-transparent mode PIN CONFIGURATIONS The Signetics SCN2661 EPCI is a universal Transparent mode DLE stuffing (Tx) synchronous/asynchronous data commu- and detection (Rx) nications controller chip that is an Automatic SYN or DLE-SYN insertion D2 enhanced version of the SCN2651. It inter- SYN, DLE and DLE-SYN stripping 03 Do faces easily to all 8-bit and 16-bit micro- Odd, even, or no parity RxD Vcc processors and may be used in a polled or Local or remote maintenance loop back interrupt driven system environment. The mode GND RxC/BKDET SCN2661 accepts programmed instruc- Baud rate: dc to 1M bps (1X clock) D4 DTR Asynchronous operation tions from the microprocessor while sup- • 05 RTS porting many serial data communications 5 to 8-bit characters plus parity 06 DSR disciplines—synchronous and asynchro- 1, 134 or 2 stop bits transmitted nous—in the full or half-duplex mode. Odd, even, or no parity D7 RESET Special support for BISYNC is provided. Parity, overrun and framing error TxC/XSYNC BRCLK detection The EPCI serializes parallel data charac- Al Tx0 Line break detection and generation ters received from the microprocessor for False start bit detection CE Tx ENIT/DSCHG transmission. Simultaneously, it can Automatic serial echo mode (echoplex) CTS receive serial data and convert it into Ao Local or remote maintenance loop back parallel data characters for input to the RIW DCD mode microcomputer. Baud rate: dc to 1M bps (1X clock) RxRDY TxRDV The SCN2661 contains a baud rate genera- dc to 62.5K bps (16X clock) tor which can be programmed to either TOP VIEW dc to 15.625K bps (64X clock) 28-PIN accept an external clock or to generate internal transmit or receive clocks. Sixteen OTHER FEATURES different baud rates can be selected under • Internal or external baud rate clock program control when operating in the in- • 3 baud rate sets ternal clock mode. Each version of the • 16 internal rates for each set D3 D2 EPCI (A, B, C) has a different set of baud • Double buffered transmitter and RxD D1 rates. receiver The EPCI is available in two packages: a • Dynamic character length switching GND DO 28-pin (0.6" wide) DIP and a 24-pin (0.4" • Full or half duplex operation D4 Vcc wide) DIP. The following are the differ- • TTL compatible inputs and outputs 05 RxC/BKDET ences between the 24-pin and the 28-pin • RxC and TxC pins are short circuit pro- 06 RTS versions: tected 1. The 24-pin version provides a single in- • Single 5V power supply D7 RESET terrupt output (INTR) instead of the • No system clock required TxCIXSYNC BRCLK three interrupt outputs (RxRDY, TxRDY, Al TxD TxEMT/DSCHG) supplied on the 28-pin APPLICATIONS version. INTR will be asserted (low) • Intelligent terminals CE CTS • Network processors when one or more of the status bits AO DCD • Front end processors SRO, SR1 or SR2 is a logic one. Niw INTR • Remote data concentrators 2. Two modem interface pins, the DTR • Computer to computer links output and the DSR input, are elimi- TOP VIEW • Serial peripherals 24-PIN nated in the 24-pin version. Because of • BISYNC adaptors this, status bit SR7 should be ignored and the setting of status bit SR2 due to ORDERING CODE a data set change (DSCHG) can be caused only by a change of the DCD in- Vcc = 5V ± 5% put. Since the DTR output is elimi- COMMERCIAL AUTOMOTIVE MILITARY nated, command register bit CR1 does PACKAGES 0°C to +70°C —40°C to +85°C —55°C to +125°C not perform any function, although it remains writable and readable. Ceramic DIP SCN2661AC1I28 SCN2661AA1I28 SCN2661AM1128 28-Pin SCN2661BC1128 SCN2661BA1128 SCN2661BM1128 Other than the above, the functional oper- 0.6" Wide SCN2661CC1128 SCN2661CA1128 SCN2661CM1128 ation, DC electrical characteristics, and AC electrical characteristics of the 24-pin Plastic DIP SCN2661AC1N28 version are identical to the 28-pin version. 28-Pin SCN2661BC1N28 Contact Factory Not Available 0.6" Wide SCN2661CC1N28 FEATURES Plastic DIP SCN2661AC1N24 • Synchronous operation 24-Pin SCN2661BC1N24 Contact Factory Not Available 5 to 8-bit characters plus parity 0.4" Wide SCN2661CC1N24 Single or double SYN operation NOTES Internal or external character 1. See table 1 for baud rates. Specify SCN2661A, B, or C depending on baud rate selected. synchronization 2. The SCN68661 is identical to the SCN2661. Order using part numbers above. Signetics 1.51 MICROPROCESSOR DIVISION JANUARY 1983

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE SCN2661/68661

BLOCK DIAGRAM

DATA BUS < SNE/DLE CONTROL Do-D7 DATA BUS BUFFER SYN 1 REGISTER SYN 2 REGISTER DLE REGISTER OPERATION CONTROL RESET

Ao MODE REGISTER 1 Al MODE REGISTER 2 TRANSMITTER TxRDY* RIW COMMAND REGISTER CE STATUS REGISTER TRANSMIT DATA HOLDING REGISTER TRANSMIT TxD SHIFT REGISTER BRCLK BAUD RATE TxC/SYNC, GENERATOR AND CLOCK CONTROL RECEIVER RxRDY* RxCIBKDET RECEIVE DATA HOLDING REGISTER DSR t r 0 RECEIVE RxD SHIFT REGISTER DCD w 0 CTS w 0 MODEM CONTROL RTS 0 DTR t TxRDY 0 RxRDY INTR. ++ TxEMTI* TxEMT DSCHG DSCHG NOTE *Open drain output pin. + 28-pin only ++ 24-pin only

BLOCK DIAGRAM Table 1 BAUD RATE GENERATOR CHARACTERISTICS The EPCI consists of six major sections. SCN2661A (BRCLK = 4.9152MHz) These are the transmitter, receiver, timing, operation control, modem control and ACTUAL SYN/DLE control. These sections communi- BAUD FREQUENCY PERCENT cate with each other via an internal data bus MR23-20 RATE 16X CLOCK ERROR DIVISOR and an internal control bus. The internal data 0000 50 0.8kHz 6144 bus interfaces to the microprocessor data 0001 75 1,2 - 4096 bus via a data bus buffer. 0010 110 1.7598 -0.01 2793 0011 134.5 2.152 - 2284 Operation Control 0100 150 2.4 2048 This functional block stores configuration 0101 200 3.2 1536 and operation commands from the CPU and 0110 300 4.8 1024 generates appropriate signals to various in- 0111 600 9.6 - 512 ternal sections to control the overall device 1000 1050 16.8329 0.196 292 operation. It contains read and write circuits 1001 1200 19.2 - 256 to permit communications with the 1010 1800 28.7438 -0.19 171 microprocessor via the data bus and con- 1011 2000 31.9168 -0.26 154 tains mode registers 1 and 2, the command 1100 2400 38.4 128 register, and the status register. Details of 1101 4800 76.8 64 register addressing and protocol are pre- 1110 9600 153.6 32 sented in the EPCI programming section of 1111 19200 307.2 16 this data sheet.

1.52 Signetics MICROPROCESSOR DIVISION JANUARY 1983

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE SCN2661/68661

Timing Table 1 BAUD RATE GENERATOR CHARACTERISTICS (Cont'd) The EPCI contains a baud rate generator SCN2661B (BRCLK = 4.9152MHz) (BRG) which is programmable to accept ex ternal transmit or receive clocks or to divide ACTUAL an external clock to perform data communi- BAUD FREQUENCY PERCENT cations. The unit can generate 16 commonly MR23-20 RATE 16X CLOCK ERROR DIVISOR used baud rates, any one of which can be 0000 45.5 0.7279kHz 0.005 6752 selected for full duplex operation. See 0001 50 0.8 6144 table 1. 0010 75 1.2 - 4096 0011 110 1.7598 -0.01 2793 Receiver 0100 134.5 2.152 2284 The receiver accepts serial data on the RxD 0101 150 2.4 2048 pin, converts this serial input to parallel for- 0110 300 4.8 1024 mat, checks for bits or characters that are 0111 600 9.6 512 unique to the communication technique and 1000 1200 19.2 256 sends an "assembled" character to the 1001 1800 28.7438 -0.19 171 CPU. 1010 2000 31.9168 -0.26 154 1011 2400 38.4 128 Transmitter 1100 4800 76.8 64 The transmitter accepts parallel data from 1101 9600 153.6 32 the CPU, converts it to a serial bit stream, 1110 19200 307.2 16 inserts the appropriate characters or bits 1111 38400 614.4 8 (based on the communication technique) and outputs a composite serial stream of data on the TxD output pin. SCN2661C (BRCLK = 5.0688MHz) Modem Control ACTUAL BAUD FREQUENCY PERCENT The modem control section provides inter- MR23-20 RATE ERROR DIVISOR facing for three input signals and three out- 16X CLOCK put signals used for "handshaking" and sta- 0000 50 0.8kHz 6336 tus indication between the CPU and a 0001 75 1.2 4224 modem. 0010 110 1.76 2880 0011 134.5 2.1523 0.016 2355 SYN/DLE Control 0100 150 2.4 2112 This section contains control circuitry and 0101 300 4.8 1056 three 8-bit registers storing the SYN1, 0110 600 9.6 528 SYN2, and DLE characters provided by the 0111 1200 19.2 264 CPU. These registers are used in the syn- 1000 1800 28.8 176 chronous mode of operation to provide the 1001 2000 32.081 0.253 158 characters required for synchronization, idle 1010 2400 38.4 132 fill and data transparency. 1011 3600 57.6 88 1100 4800 76.8 66 1101 7200 115.2 44 1110 9600 153.6 33 1111 19200 316.8 3.125 16

NOTE I6X clock is used in asynchronous mode. In synchronous mode, clock multiplier is I X and ERG can be used only for TxC.

Signetics 1.53 MICROPROCESSOR DIVISION JANUARY 1983

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE SCN2661168661

Table 2 CPU-RELATED SIGNALS OPERATION The functional operation of the 2661 is pro- 24- 28- INPUT/ grammed by a set of control words supplied PIN NAME PIN PIN OUTPUT FUNCTION by the CPU. These control words specify RESET X X I A high on this input performs a master items such as synchronous or asynchronous mode, baud rate, number of bits per charac- reset on the 2661. This signal asynchro- ter, etc. The programming procedure is de- nously terminates any device activity and scribed in the EPCI programming section of clears the mode, command and status reg- the data sheet. isters. The device assumes the idle state and remains there until initialized with the After programming, the EPCI is ready to per- appropriate control words. form the desired communications functions. Al-AO X X I Address lines used to select internal EPCI The receiver performs serial to parallel con- registers. version of data received from a modem or fi/W X X I Read command when low, write command equivalent device. The transmitter converts when high. parallel data received from the CPU to a serial bit stream. These actions are accom- CE X X I Chip enable command. When low, indi- plished within the framework specified by cates that control and data lines to the the control words. EPCI are valid and that the operation specified by the R /W, Al and AO inputs Receiver should be performed. When high, places The 2661 is conditioned to receive data the Do-D7 lines in the three-state condi- when the DCD input is low and the RxEN bit tion. in the command register is true. In the asyn- X D7-Do X I/O 8-bit, three-state data bus used to transfer chronous mode, the receiver looks for a high commands, data and status between EPCI to low (mark to space) transition of the start and the CPU. Do is the least significant bit; bit on the RxD input line. If a transition is D7 the most significant bit. detected, the state of the RxD line is sam- TxRDY X 0 This output is the complement of status pled again after a delay of one-half of a bit register bit SRO. When low, it indicates time. If RxD is now high, the search for a that the transmit data holding register valid start bit is begun again. If RxD is still (THR) is ready to accept a data character low, a valid start bit is assumed and the from the CPU. It goes high when the data receiver continues to sample the input line character is loaded. This output is valid at one bit time intervals until the proper num- only when the transmitter is enabled. It is ber of data bits, the parity bit, and one stop an open drain output which can be used as bit have been assembled. The data are then an interrupt to the CPU. transferred to the receive data holding register, the RxRDY bit in the status register is RxRDY X 0 This output is the complement of status set, and the RxRDY output is asserted. If the register bit SR 1. When low, it indicates character length is less than 8 bits, the high that the receive data holding register order unused bits in the holding register are (RHR) has a character ready for input to set to zero. The parity error, framing error, the CPU. It goes high when the RHR is read and overrun error status bits are strobed by the CPU, and also when the receiver is into the status register on the positive going disabled. It is an open drain output which edge of RxC corresponding to the received can be used as an interrupt to the CPU. character boundary. If the stop bit is TxEMT / present, the receiver will immediately begin DSCHG X 0 This output is the complement of status its search for the next start bit. If the stop bit register bit SR2. When low, it indicates is. absent (framing error), the receiver will that the transmitter has completed serial- interpret a space as a start bit if it persists ization of the last character loaded by the into the next bit time interval. If a break con- CPU, or that a change of state of the DSR dition is detected (RxD is low for the entire or DCD inputs has occurred. This output character as well as the stop bit), only one goes high when the status register is read character consisting of all zeros (with the by the CPU, if the TxEMT condition does FE status bit SR5 set) will be transferred to not exist. Otherwise, the THR must be the holding register. The RxD input must reloaded by the CPU for this line to go high. It turn to a high condition before a search for is an open drain output which can be used the next start bit begins. as an interrupt to the CPU. Pin 25 can be programmed to be a break INTR X 0 This is an active low output which is the detect output by appropriate setting of wire-OR of the TxRDY, RxRDY, and TxEMT/ MR27-MR24. If so, a detected break will DSCHG outputs on the 28-pin version. See cause that pin to go high. When RxD returns above. to mark for one RxC time, pin 25 will go low. Refer to the break detection timing diagram. 1.54 Signetics MICROPROCESSOR DIVISION JANUARY 1983

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE SCN2661/68661

Table 3 DEVICE-RELATED SIGNALS When the EPCI is initialized into the synchro nous mode, the receiver first enters the hunt 24• 28• INPUT/ mode on a 0 to 1 transition of RxEN(CR2). In PIN NAME PIN PIN OUTPUT FUNCTION this mode, as data are shifted into the re ceiver shift register a bit at a time, the con- BRCLK X X I Clock input to the internal baud rate gener- tents of the register are compared to the ator (see table 1). Not required if external contents of the SYN 1 register. If the two are receiver and transmitter clocks are used. not equal, the next bit is shifted in and the RxC /BKDET X X I/O Receiver clock. If external receiver clock comparison is repeated. When the two regis programmed, this input controls the rate isters match, the hunt mode is terminated at which the character is to be received. and character assembly mode begins. If sin- Its frequency is lx, 16X or 64X the baud gle SYN operation is programmed, the SYN rate, as programmed by mode register 1. DETECT status bit is set. If double SYN op- Data are sampled on the rising edge of the eration is programmed, the first character clock. If internal receiver clock is pro- assembled after SYN 1 must be SYN2 in or- grammed, this pin can be a 1X/ 16X clock der for the SYN DETECT bit to be set. Other- or a break detect output pin. wise, the EPCI returns to the hunt mode. TxC/XSYNC X X I/O Transmitter clock. If external transmitter (Note that the sequence SYN1-SYN1-SYN2 clock is programmed, this input controls will not achieve synchronization.) When syn- the rate at which the character is transmit- chronization has been achieved, the EPCI ted. Its frequency is 1X, 16X or 64X the continues to assemble characters and baud rate, as programmed by mode regis- transfer them to the holding register, setting ter 1. The transmitted data changes on the the RxRDY status bit and asserting the falling edge of the clock. If internal trans- RxRDY output each time a character is mitter clock is programmed, this pin can transferred. The PE and OE status bits are be a 1X/ 16X clock output or an external set as appropriate. Further receipt of the jam synchronization input. appropriate SYN sequence sets the SYN RxD X X I Serial data input to the receiver. "Mark" is DETECT status bit. If the SYN stripping high, "space" is low. mode is commanded, SYN characters are TxD X X 0 Serial data output from the transmitter. not transferred to the holding register. Note "Mark" is high, "space" is low. Held in that the SYN characters used to establish mark condition when the transmitter is dis- initial synchronization are not transferred to abled. the holding register in any case. DSR X I General purpose input which can be used External jam synchronization can be for data set ready or ring indicator condi- achieved via pin 9 by appropriate setting of tion. Its complement appears as status MR27-MR24. When pin 9 is an XSYNC input, register bit SR7. Causes a low output on the internal SYN1, SYN1-SYN2, and DLE- TxEMT/DSCHG when its state changes if SYN1 detection is disabled. Each positive CR2 or CRO = 1. going signal on XSYNC will cause the re- DCD X X I Data carrier detect input. Must be low in ceiver to establish synchronization on the order for the receiver to operate. Its com- rising edge of the next RxC pulse. Character plement appears as status register bit assembly will start with the RxD input at this SR6. Causes a low output on edge. XSYNC may be lowered on the next TxEMT/DSCHG when its state changes if rising edge of RxC. This external synchroni- CR2 or CRO = 1. If DCD goes high while zation will cause the SYN DETECT status bit receiving, the RxC is internally inhibited. to be set until the status register is read. Refer to XSYNC timing diagram. CTS X X I Clear to send input. Must be low in order for the transmitter to operate. If it goes Transmitter high during transmission, the character in The EPCI is conditioned to transmit data the transmit shift register will be transmit- when the CTS input is low and the TxEN ted before termination. command register bit is set. The 2661 indi- DTR X 0 General purpose output which is the com- cates to the CPU that it can accept a char- plement of command register bit CR I. Nor- acter for transmission by setting the TxRDY mally used to indicate data terminal ready. status bit and asserting the TxRDY output. RTS X X 0 General purpose output which is the com- When the CPU writes a character into the plement of command register bit CR5. Nor- transmit data holding register, these condi- mally used to indicate request to send. If tions are negated. Data are transferred from the transmit shift register is not empty the holding register to the transmit shift reg- when CR5 is reset (1 to 0), then RTS will ister when it is idle or has completed trans- go high one TxC time after the last serial mission of the previous character. The bit is transmitted. TxRDY conditions are then asserted again. Thus, one full character_ time of buffering is provided.

Signetics 1.55 MICROPROCESSOR DIVISION JANUARY 1983

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE SCN2661168661

In the asynchronous mode, the transmitter Table 4 2661 REGISTER ADDRESSING automatically sends a start bit followed by the programmed number of data bits, the CE Al AO 711/W FUNCTION X X . least significant bit being sent first. It then .- 0- 0 - 0 0 X Three•state data bus appends an optional odd or even parity bit

0 0 Read receive holding register and the programmed number of stop bits. If, 0 0 Write transmit holding register following transmission of the data bits, a

0 1 Read status register new character is not available in the trans- ,- 0- 0 ,- 0 . 1 Write SYN1/SYN2/DLE registers mit holding register, the TxD output remains .-

,- 0 Read mode registers % in the marking (high) condition and the

. 0 Write mode registers 1/2

TxEMT/DSCHG output and its correspond- ,--

,- 1 Read command register ing status bit are asserted. Transmission 1 Write command register resumes when the CPU loads a new charac- NOTE ter into the holding register. The transmitter See AC characteristics section for timing requirements. can be forced to output a continuous low (BREAK) condition by setting the send break command bit (CR3) high. INITIAL RESET In the synchronous mode, when the 2661 is initially conditioned to transmit, the TxD out- LOAD put remains high and the TxRDY condition is MODE REGISTER 1 asserted until the first character to be trans-

mitted (usually a SYN character) is loaded LOAD NOTE by the CPU. Subsequent to this, a continu- MODE REGISTER 2 Mode register 1 must be written before ous stream of characters is transmitted. No 2 can be written. Mode register 2 need not be programmed if external clocks extra bits (other than parity, if commanded) are used. are generated by the EPCI unless the CPU SYNCHRONOUS tails to send a new character to the EPCI by the time the transmitter has completed Y sending the previous character. Since syn- LOAD chronous communication does not allow SYNC REGISTER NOTE gaps between characters, the EPCI asserts SYN1 register must be written TxEMT and automatically "fills" the gap by before SYN2 can be written, and SYN2 before DLE can be written. transmitting SYN1s, SYN1-SYN2 doublets, or DLE-SYN1 doublets, depending on the state of MR16 and MR17. Normal transmission of the message resumes when a new TRANSPARENT character is available in the transmit data LOAD MODE? SYN2 REGISTER holding register. If the SEND DLE bit in the N command register is true, the DLE character is automatically transmitted prior to trans- TRANSPARENT mission of the message character in the MODE? THR.

LOAD EPCI PROGRAMMING OLE REGISTER Prior to initiating data communications, the 2661 operational mode must be pro- r grammed by performing write operations to LOAD the mode and command registers. In addi- COMMAND REGISTER tion, if synchronous operation is pro- -1 grammed, the appropriate SYN/DLE regis- r — --- , ters must be loaded. The EPCI can be I OPERATE reconfigured at any time during program execution. A flowchart of the intialization process appears in figure 1. RECONFIGURE The internal registers of the EPCI are accessed by applying specific signals to the CE, 14/W, Al and AO inputs. The conditions DISABLE necessary to address each register are RCVR AND XMTR shown in table 4. The SYN1, SYN2, and DLE registers are accessed by performing write operations Figure 1. 2661 Initialization Flow Chart with the conditions Al = 0, AO = 1, and

1.56 Signetics MICROPROCESSOR DIVISION JANUARY 1983 ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE SCN2661/68661

R/W = 1. The first operation loads the acter and the receiver performs a parity To effect assembly /disassembly of the next SYN1 register. The next loads the SYN2 check on incoming data. MR15 selects odd received/transmitted character, MR12.15 register, and the third loads the DLE regis- or even parity when parity is enabled by must be changed within n bit times of the ter. Reading or loading the mode registers is MR14. active going state of RxRDY /TxRDY. Trans- done in a similar manner. The first write (or parent and non-transparent mode changes read) operation addresses mode register 1, In asynchronous mode, MR17 and MR16 se- (MR 16) must occur within n-1 bit times of the and a subsequent operation addresses lect character framing of 1, 1.5, or 2 stop character to be affected when the receiver mode register 2. If more than the required bits. (If 1X baud rate is programmed, 1.5 or transmitter is active. (n = smaller of the number of accesses are made, the internal stop bits defaults to 1 stop bits on transmit.) new and old character lengths.) sequencer recycles to point at the first reg- In synchronous mode, MR17 controls the ister. The pointers are reset to SYN1 regis- number of SYN characters used to establish Mode Register 2 (MR2) ter and mode register 1 by a RESET input or synchronization and for character fill when Table 6 illustrates mode register 2. MR23, by performing a read command register op- the transmitter is idle. SYN1 alone is used if MR22, MR21 and MR20 control the frequen- eration, but are unaffected by any other read MR17 = 1, and SYN1-SYN2 is used when cy of the internal baud rate generator (BRG). or write operation. MR 17 = 0. If the transparent mode is speci- Sixteen rates are selectable for each EPCI The 2661 register formats are summarized fied by MR16, DLE-SYN1 is used for charac- version (-1, —2, —3). Version 1 and 2 speci- in tables 5, 6, 7 and 8. Mode registers 1 and ter fill and SYN detect, but the normal syn- fy a 4.9152 MHz TTL input at BRCLK (pin 2 define the general operational character- chronization sequence is used to establish 20); version 3 specifies a 5.0688 MHz input istics of the EPCI, while the command regis- character sync. When transmitting, a DLE which is identical to the Signetics 2651. ter controls the operation within this basic character in the transmit holding register will MR23-20 are don't cares if external clocks framework. The EPCI indicates its status in cause a second DLE character to be trans- are selected (MR25-MR24 = 0). The individ- the status register. These registers are mitted. This DLE stuffing eliminates the soft- ual rates are given in table 1. cleared when a RESET input is applied. ware DLE compare and stuff on each transparent mode data character. If the send DLE MR24-MR27 select the receive and transmit Mode Register 1 (MR1) command (CR3) is active when a DLE is clock source (either the BRG or an external input) and the function at pins 9 and 25. Re- Table 5 illustrates Mode Register 1. Bits loaded into THR, only one additional DLE will fer to table 6. MR11 and MR10 select the communication be transmitted. Also, DLE stripping and DLE format and baud rate multiplier. 00 specifies detect (with MR14 = 0) are enabled. synchronous mode and 1X multiplier. 1X, 16X, and 64X multipliers are programmable The bits in the mode register affecting char- Command Register (CR) for asynchronous format. However, the mul- acter assembly and disassembly (MR 12- Table 7 illustrates the command register. tiplier in asynchronous format applies only if MR 16) can be changed dynamically (during Bits CRO (TxEN) and CR2 (RxEN) enable or the external clock input option is selected active receive/transmit operation). The disable the transmitter and receiver respec- by MR24 or MR25. character mode register affects both the tively. A 0 to 1 transition of CR2 forces start transmitter and receiver; therefore in syn- bit search (async mode) or hunt mode (sync MR13 and MR12 select a character length of chronous mode, changes should be made mode) on the second RxC rising edge. Dis- 5, 6, 7 or 8 bits. The character length does not only in half duplex mode (RxEN = 1 or abling the receiver causes RxRDY to go include the parity bit, if programmed, and TxEN = 1, but not both simultaneously = 1). high (inactive). If the transmitter is disabled, does not include the start and stop bits in it will complete the transmission of the char- asynchronous mode. In asynchronous mode, character changes should be made when RxEN and TxEN=0 or acter in the transmit shift register (if any) MR14 controls parity generation. If enabled, when TxEN = 1 and the transmitter is mark- prior to terminating operation. The TxD out- a parity bit is added to the transmitted char- ing in half duplex mode (RxEN = 0). put will then remain in the marking state

Table 5 MODE REGISTER 1 (MR 1)

MR17 MR16 MR15 MR14 MR13 MR12 MR11 MR10

Character Mode and Baud Sync/Async Parity Type Parity Control Length Rate Factor

Async: Stop Bit Length 00 = Invalid 0 = Odd 0 = Disabled 00 = 5 bits 00 = Synchronous 1X rate 01 = 1 stop bit 1 = Even 1 = Enabled 01 = 6 bits 01 = Asynchronous 1X rate 10 = 1% stop bits 10 = 7 bits 10 = Asynchronous 16X rate 11 = 2 stop bits 11 = 8 bits 11 = Asynchronous 64X rate

Sync: Sync: Number of Transparency SYN char Control 0 = Double 0 = Normal SYN 1 = Transparent 1 = Single SYN

NOTE Baud rate factor in asynchronous applies only if external clock is selected. Facto is 16X it internal clock is selected. Mode must be selected (MR11, MR10) in any case. Signetics 1.57 MICROPROCESSOR DIVISION JANUARY 1983 ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE SCN2661/68661

Table 6 MODE REGISTER 2 (MR2) MR27—MR24 MR23—MR20 TxC RxC Pin 9 PIn 25 TxC RxC Pin 9 Pin 25 Mode Baud Rate Selection 0000 E E TxC RxC 1000 E E XSYNC' RxC /TxC sync 0001 E I TxC 1X 1001 E I TxC BKDET async 0010 I E lx RxC 1010 I E XSYNC' RxC sync 0011 I I lx 1X 1011 I I 1X BKDET async See baud rates in table 1 0100 E E TxC RxC 1100 E E XSYNCI RxC /TxC sync 0101 E I TxC 16X 1101 E I TxC BKDET async 0110 I E 16X RxC 1110 I E XSYNC' RxC sync 0111 I I 16X 16X 1111 I I 16X BKDET async NOTES 1. When pin 9 is programmed as XSYNC input, SYN1, SYN I -SYN2, and DLE-SYN I deter tion is disabled. E = External clock I = Internal clock (BRG) 1X and 165 are clock outputs Table 7 COMMAND REGISTER (CR)

CR7 CR6 CR5 CR4 CR3 CR2 CR1 CRO

Receive Transmit Request Control Data Terminal Control Operating Mode To Send Reset Error Sync/Async (RxEN) Reedy (TxEN)

00 = Normal operation 0 = Force RTS 0 = Normal Async: 01 = Async: output high 1 = Reset Force break Automatic one clock time error flags 0 = Normal 0 = Disable 0 = Force DTR 0 = Disable echo mode after TxSR in status register 1 = Force break 1 = Enable output high 1 = Enable Sync: SYN and /or serialization (FE, OE, PE/DLE 1 = Force DTR detect.) DLE stripping mode 1 = Force RTS output low 10 = Local loop back output low (Not applicable In 11 = Remote loop back 24-pin version.)

Sync: Send DLE 0 = Normal 1 = Send DLE Table 8 STATUS REG STER (SR) SR7 SR6 SR5 SR4 SR3 SR2 SR1 SRO

Data Set Data Carrier Ready Detect FE/SYN Detect Overrun PE/DLE Detect TxEMT/DSCHG RxRDY TxRDY

0 = DSR input 0 = DCD input Async: 0 = Normal Async: is high is high 0 = Normal 1 = Overrun 0 = Normal 0 = Normal 0 = Receive 0 = Transmit 1 = DSR input 1 = DCD input 1 = Framing Error 1 = Parity error 1= Change In DSR holding holding is low is low Error (28-pin version only), register empty register busy or DCD, or transmit 1 = Receive 1 = Transmit shift register is empty holding register holding register has data empty

Sync: Sync: (Should be ignored in 0 = Normal 0 = Normal 24-pin version.) 1 = SYN - 1 = Parity error or detected DLE received

(high) while 1 ,16. sT, and TWO will go high In asynchronous mode, setting CR3 will data holding register. Since this is a one (inactive). If the receiver is disabled, it will force and hold the TxD output low (spacing time command, CR3 does not have to be terminate operation immediately. Any char- condition) at the end of the current transmit- reset by software. CR3 should be set when acter being assembled will be neglected. A ted character. Normal operation resumes entering and exiting transparent mode and 0 to 1 transition of CR2 will initiate start bit when CR3 is cleared. The TxD line will go for all DLE—non-DLE character sequences. search (async) or hunt mode (sync). high for at least one bit time before beginning transmission of the next character in Bits CR1 (28-pin only) (DTR) and CR5 (RTS) the transmit data holding register. In syn- Setting CR4 causes the error flags in the control the DTR and RTS outputs. Data at the chronous mode, setting CR3 causes the status register (SR3, SR4, and SR5) to be outputs are the logical complement of the transmission of the DLE register contents cleared. This is a one time command. There is register data. prior to sending the character in the transmit no internal latch for this bit. 1.58 Signetics MICROPROCESSOR DIVISION JANUARY 1983

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE SCN2661168661

Table 9 SCN2661 EPCI vs SCN2651 PCI are not transferred to the RHR. However, only the first DLE of a DLE-DLE pair is FEATURE EPCI PCI stripped.

1. MR2 Bit 6, 7 Control pin 9, 25 Not used Note that automatic stripping mode does not 2. DLE detect-SR3 SR3 = 0 for DLE-DLE, SR3 = 1 for DLE-DLE, affect the setting of the DLE detect and SYN DLE-SYNC1 DLE-SYNC1 detect status bits (SR3 and SR5). 3. Reset of SR3, OLE Second character after Receiver disable, or CR4 = 1 Two diagnostic sub-modes can also be detect DLE, or receiver disable, configured. In local loop back mode (CR7- or CR4 = 1 CR6 = 10), the following loops are connect- 4. Send DLE-CR3 One time command Reset via CR3 on next TxRDY ed internally: 5. DLE stuffing in Automatic DLE stuffing when None 1. The transmitter output is connected to transparent mode OLE is loaded except if the receiver input. CR3 = 1 2. DTR is connected to DCD and RTS is con- 6. SYNC1 stripping All SYNC1 First SYNC1 of pair nected to CTS. in double sync 3. The receiver is clocked by the transmit non-transparent clock. mode 4. The DTR, RTS and TxD outputs are held 7. Baud rate Three One high. versions 5. The CTS, DCD, DSR and RxD inputs are ignored. 8. Terminate ASYNC Reset CR5 in response to Reset CR0 when TxEMT transmission TxRDY changing from 1 to 0 goes from 1 to 0. Then reset Additional requirements to operate in the lo- (drop RTS) CR5 when TxEMT goes from cal loop back mode are that CR0 (TxEN), 0 to 1 CR1 (DTR), and CR5 (RTS) must be set to 1. 9. Break detect Pin 25' FE and null character CR2 (RxEN) is ignored by the EPCI. 10. Stop bit searched One Two The second diagnostic mode is the remote 11. External jam sync Pin 92 No loop back mode (CR7-CR6 = 11). In this 12. Data bus timing Improved over 2651 - mode: 13. Data bus drivers Sink 2.2mA Sink 1.6mA 1. Data assembled by the receiver are Source 400µA Source 100p.A automatically placed in the transmit holding register and retransmitted by the NOTES 1. Internal BRG used for RxC. transmitter on the TxD output. 2. Internal BRG used for TxC. 2. The transmitter is clocked by the receive clock. When CR5 (RTS) is set, the RTS pin is forced 1. Data assembled by the receiver are 3. No data are sent to the local CPU, but the low. A 1 to 0 transition of CR5 will cause RTS automatically placed in the transmit hold- error status conditions (PE, FE) are set. to go high (inactive) one TxC time after the ing register and retransmitted by the 4. The RxRDY, TxRDY, and TxEMT/DSCHG last serial bit has been transmitted (if the transmitter on the TxD output. outputs are held high. transmit shift register was not empty). 2. The transmitter is clocked by the receive 5. CR1 (TxEN) is ignored. clock. The EPCI can operate in one of four sub- 6. All other signals operate normally. 3. TxRDY output = 1. modes within each major mode (synchro- 4. The TxEMT /DSCHG pin will reflect only nous or asynchronous). The operational Status Register the data set change condition. sub-mode is determined by CR7 and CR6. The data contained in the status register (as 5. The TxEN command (CR0) is ignored. CR7-CR6 = 00 is the normal mode, with the shown in table 8) indicate receiver and transmitter and receiver operating indepen- In synchronous mode, CR7-CR6 = 01 places transmitter conditions and modem/data set dently in accordance with the mode and sta- the EPCI in the automatic SYN /DLE strip- status. tus register instructions. ping mode. The exact action taken depends SRO is the transmitter ready (TxRDY) status on the setting of bits MR17 and MR16: In asynchronous mode, CR7-CR6 = 01 bit. It, and its corresponding output, are valid places the EPCI in the automatic echo 1. In the non-transparent, single SYN mode only when the transmitter is enabled. If equal mode. Clocked, regenerated received data (MR17-MR16 = 10), characters in the to 0, it indicates that the transmit data hold- are automatically directed to the TxD line data stream matching SYN1 are not ing register has been loaded by the CPU and while normal receiver operation continues. transferred to the receive data holding the data has not been transferred to the The receiver must be enabled (CR2 = 1), but register (RHR). transmit shift register. If set equal to 1, it the transmitter need not be enabled. CPU to 2. In the non-transparent, double SYN mode indicates that the holding register is ready receiver communications continues normal- (MR17-MR16 = 00), characters in the to accept data from the CPU. This bit is ly, but the CPU to transmitter link is dis- data stream matching SYN1, or SYN2 if initially set when the transmitter is enabled abled. Only the first character of a break immediately preceded by SYN1, are not by CRO, unless a character has previously condition is echoed. The TxD output will go transferred to the RHR. been loaded into the holding register. It is high until the next valid start is detected. 3. In transparent mode (MR 16 = 1), charac- not set when the automatic echo or remote The following conditions are true while in ters in the data stream matching DLE, or loopback modes are programmed. When automatic echo mode: SYN1 if immediately preceded by DLE, this bit is set, the TxRDY output pin is low. In Signetics 1.59 MICROPROCESSOR DIVISION JANUARY 1983 ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE SCN2661 /68661

the automatic echo and remote loop back cleared by loading the transmit data holding when the receiver is disabled or by the reset modes, the output is held high. register. The DSCHG condition is enabled error command, CR4. when TxEN = 1 or RxEN = 1. It is cleared SRI, the receiver ready (RxRDY) status bit, In asynchronous mode, bit SR5 signifies that when the status register is read by the indicates the condition of the receive data the received character was not framed by a CPU. If the status register is read twice and holding register. If set, it indicates that a stop bit, i.e., only the first stop bit is SR2 = 1 while SR6 and SR7 remain un- character has been loaded into the holding checked. If RHR = 0 when SR5 = 1, a break changed, then a TxEMT condition exists. register from the receive shift register and is condition is present. In synchronous non- When SR2 is set, the TxEMT/DSCHG output ready to be read by the CPU. If equal to transparent mode (MR16 = 0), it indicates is low. zero, there is no new character in the hold- receipt of the SYN1 character in single SYN ing register. This bit is cleared when the SR3, when set, indicates a received parity mode or the SYN1-SYN2 pair in double SYN CPU reads the receive data holding register error when parity is enabled by MR14. In mode. In synchronous transparent mode or when the receiver is disabled by CR2. synchronous transparent mode (MR16 = 1), (MR16 = 1), this bit is set upon detection of When set, the RxRDY output is low. with parity disabled, it indicates that a char- the initial synchronizing characters (SYN1 acter matching DLE register was received or SYN1-SYN2) and, after synchronization The TxEMT/DSCHG bit, SR2, when set, indi- and the present character is neither SYN1 has been achieved, when a DLE-SYN1 pair cates either a change of state of the DSR nor DLE. This bit is cleared when the next is received. The bit is reset when the receiv- (28-pin only) or DCD inputs (when CR2 or character following the above sequence is er is disabled, when the reset error com- CRO= 1) or that the transmit shift register has loaded into RHR, when the receiver is dis- mand is given in asynchronous mode, or completed transmission of a character and abled, or by a reset error command, CR4. when the status register is read by the CPU no new character has been loaded into the in the synchronous mode. transmit data holding register. Note that in The overrun error status bit, SR4, indicates synchronous mode this bit will be set even that the previous character loaded into the SR6 and SR7 (28-pin only) reflect the condi- though the appropriate "fill" character is receive holding register was not read by the tions of the DCD and DSR inputs respective- transmitted. TxEMT will not go active until at CPU at the time a new received character ly. A low input sets its corresponding status least one character has been transmitted. It is was transferred into it. This bit is cleared bit, and a high input clears it.

ABSOLUTE MAXIMUM RATINGS1

PARAMETER RATING UNIT

Operating ambient temperature2 Note 4 °C Storage temperature —65 to +150 °C All voltages with respect to ground' —0.5 to +6.0 V

DC ELECTRICAL CHARACTERISTICS4,5,6

LIMITS PARAMETER TEST CONDITIONS UNIT Min Typ Max

Input voltage V VIL Low 0.8 VIH High 2.0 Output voltage V VOL Low IOL = 2.2mA 0.4 V01-17 High IOH = —400µA 2.4 IIL Input leakage current VIN = 0 to 5.5 V 10 µA

3-state output leakage current µA ILH Data bus high VO = 4.0V 10 ILL Data bus low Vo = 0.45V 10

ICC Power supply current 150 mA

CAPACITANCE TA = 25°C, VCC = OV LIMITS PARAMETER TEST CONDITIONS UNIT Min Typ Max

Capacitance pF CIN Input 20 COOT Output fc = 1MHz 20 C110 Input /Output Unmeasured pins tied to ground 20

Notes on following page 1.60 Signetics MICROPROCESSOR DIVISION JANUARY 1983

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE SCN2661/68661

AC ELECTRICAL CHARACTERISTICS4,5,6

PARAMETER TEST CONDITIONS Min Typ Max ' UNIT

Pulse width ns tRES Reset 1000 tCE Chip enable 250 Setup and hold time ns tAS Address setup 10 tAH Address hold 10 tCS R/W control setup 10 tCH R/W control hold 10 tDS Data setup for write 150 tDH Data hold for write 0 tRXS Rx data setup 300 tRXH Rx data hold 350 100 Data delay time for read CL = 150pF 200 ns IDF Data bus floating time for read CL = 150pF 100 tCED CE to CE delay 600 Input clock frequency MHz fBRG Baud rate generator (2661A,8) 1.0 4.9152 4.9202 fBRG Baud rate generator (2661C) 1.0 5.0688 5.0738 f Rale TxC or RxC dc 1.0

Clock width ns tBRH9 Baud rate high (2661A,B) 75 tBRH9 Baud rate high (2661C) 70 tBRL9 Baud rate low (2661A,B) 75 tBRL9 Baud rate low (2661C) 70 tR/TH TxC or RxC high 480 tR/TL1° TxC or RxC low 480 tTXD TxD delay from falling edge of TxC CL = 150pF 650 ns tTCS Skew between TxD changing and falling edge of TxC output s CL = 150pF 0

NOTES 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operation section of this specification is not implied. 2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature. 3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. 4. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature range and operating supply range. 5. All voltage measurements are referenced to ground. All time measurements are at the 50% level for inputs (except tBRH and tBAL) and at 0.8V and 2.0V for outputs. Input levels swing between 0.4V and 2.4V, with a transition time of 2Ons maximum. 6. Typical values are at +20°C, typical supply voltages and typical processing parameters. 7. INTR, TxRDY, RxRDY and TxEMT/DSCHG outputs are open drain. 8. Parameter applies when internal transmitter clock is used. 9. Under test conditions of 5.0688MHz f BRG (2661C) and 4.9152MHz fBRG (2661A,B), tBRH and tBRL measured at VIM and VIL respectively. 10. In asynchronous local loopback mode, using lx clock, the following parameters apply: fRj-j-= 0.83M Hz MU. tRim= 700ns min.

Signetics 1.61 MICROPROCESSOR DIVISION JANUARY 1983

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE SCN2661/68661

TIMING DIAGRAMS

RESET CLOCK

tBRL 1R/TL RESET -,711 BRCLK, tRES TxC, RxC 1/16RG lif R/T

TRANSMIT RECEIVE

1 BIT TIME (1, 16, OR 64 CLOCK PERIODS) (IN X;

- RxD

TxD X_ 1RXS 1F(XH TxD 1TxD RxC (IX)

tTCS TxC (OUTPUT)

1.62 Signetics MICROPROCESSOR DIVISION JANUARY 1983

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE SCN2661/68661

TIMING DIAGRAMS (Cont'd)

TxRDY, TxEMT (Shown for 5-bit characters, no parity, 2 stop bits [in asynchronous mode) )

TxC (1X)

I 1 2 , 3 , 4 , 5 1 , 2 , 3 4 , 5 1 2 , 3 , 4 , 5 1 , 2 , 3 4 5 1 1 2 I 3 1 4 5 Tx D DATA 1 DATA 2 DATA 3 SYN 1 DATA 4

TxEN MODE

NOUS TxRDY • • RHO

YNC TxEMT S

CE FOR WRITE • OF THR DATA 1 DATA 2 DATA 3 DATA 4

D A 1 , 2 , 3 , 4 , 5 B C A 1 2 , 3 , 4 , 5 B C A 1 , 2 , 3 4 , 5 B C D A 1 2

TxD DATA 1 DATA 2 DATA 3 DATA 4 I I TxEN ODE US M

NO TxR DY RO CH TxEMT ASYN

CE FOR WRITE 114 OF THR DATA 1 DATA 2 DATA 3 DATA 4

NOTES A Start bit B = Stop bit 1 C = Stop bit 2 = TxD marking condition TxEMT goes low at the beginning of the last data bit, or, if parity is enabled, at the beginning of the parity bit.

Signetics 1.63 MICROPROCESSOR DIVISION JANUARY 1983

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE SCN2661/68661

TIMING DIAGRAMS (Cont'd)

EXTERNAL SYNCHRONIZATION WITH XSYNC

1X ReC gm* ss tes tes = XSYNC SETUP TIME = 300ns tH = XSYNC HOLD TIME = ONE RxC

XSYNC ti,

RxD 1111 0 111.11111.1111111111

V CHARACTER ASSEMBLY

BREAK DETECTION TIMING

Rx CHARACTER= 5 BITS, NO PARITY

RxC 16 OR 64

I I LOOK FOR START BIT = LOW OF RxD IS HIGH, LOOK FOR HIGH TO LOW TRANSITION) RxD FALSE START BIT CHECK MADE (RxD LOW)

MISSING STOP BIT DETECTED SET FE BIT• 1st DATA BIT MISSING STOP BIT DETECTED, SET FE BIT. SAMPLED 0—. RHR, ACTIVATE RxRDY. SET BKDET PIN RxD INPUT --...11xSR UNTIL A MARK TO SPACE TRANSITION OCCURS.

NOTE * II the stop bit is present. the start bit search will commence immediately .

1.64 Signetics MICROPROCESSOR DIVISION JANUARY 1983

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE SCN2661/68661

TIMING DIAGRAMS (Cont'd)

RxRDY (Shown for 5-bit characters, no parity, 2 stops bits [in asynchronous mode] )

RxCH-- 1 1121314151112131415 112/ 3 1 4 1 5 ( 2 1 3 1 4 1 5 1 / 2 1 31415 11 2131415

RxD SYN 1 DATA 1 DATA 2 DATA 3 DATA 4 DATA 5

IGNORED RxEN

SYNDET STATUS BIT

SYNCHRONOUS MODE RxRDY • •

CE FOR READ J READ READ READ RHR READ RHR READ RHR READ RHR STATUS STATUS (DATA 1) (DATA 2) (DATA 3) (DATA 3)

A 1 2 1 3 4 5 BIC A 1 1 21314(5 B 1C1-101-- A 1i 2(31415 B[C A 112(31

RxD DATA 1 DATA 2 DATA 3 DATA 4

RxEN S MODE

RxRDY L

OVERRUN STATUS BIT

ASYNCHRONOU CE FOR READ READ RHR READ RHR (DATA 1) (DATA 3)

NOTES A = Start bit B = Stop bit 1 C = Stop bit 2 D = TxD marking condition Only one stop bit is detected.

Signetics 1.65 MICROPROCESSOR DIVISION JANUARY 1983

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE SCN2661168661

TYPICAL APPLICATIONS

ASYNCHRONOUS INTERFACE TO CRT TERMINAL

ADDRESS BUS

CONTROL BUS __.

DATA BUS

\7 \7 \7 r 1

RxD 1 -I EIA TO TTL I CONVERT I (OPT) TxD I ► SCN2661 I. J

BAUD RATE CLOCK BRCLK CRT OSCILLATOR TERMINAL

ASYNCHRONOUS INTERFACE TO TELEPHONE LINES

ADDRESS BUS

CONTROL BUS

DATA BUS

\Z \ RxD

TxD

DSR 0-. PHONE ASYNC LINE DTR 0 MODEM INTERFACE

SCN2661 CTS 0 RTS 0 DC D 0.*

BRCLK BAUD RATE CLOCK OSCILLATOR TELEPHONE LINE

1-66 Signetics MICROPROCESSOR DIVISION JANUARY 1983

ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE SCN2661/68661

TYPICAL APPLICATIONS (Cont' d)

SYNCHRONOUS INTERFACE TO TERMINAL OR PERIPHERAL DEVICE

ADDRESS BUS

CONTROL BUS

DATA BUS

\Z RxD TO SYNCHRONOUS RxC -a TERMINAL OR SCN2661 PERIPHERAL T C DEVICE

SYNCHRONOUS INTERFACE TO TELEPHONE LINES

ADDRESS BUS

CONTROL BUS

C DATA BUS

vv / RxD

TxD

RxC PHONE LINE TxC INTERFACE SYNC O"' MODEM SCN2661 MD CTS 0.1 RTS 0

DSR O-

DTRO

TELEPHONE LINE

Signetics 1.67

MICROPROCESSOR DIVISION JANUARY 1983 DUAL ASYNCHRONOUS RECEIVERITRANSMITTER (DUART) SCN2681 SERIES

Preliminary

DESCRIPTION FEATURES PIN CONFIGURATION The Signetics SCN2681 Dual Universal • Dual full-duplex asynchronous receiver/ Asynchronous Receiver/Transmitter transmiter (DUART) is a single chip MOS-LSI com- • Quadruple buffered receiver data regis- AO VCC munications device that provides two in- ters IP3 IP4 dependent full-duplex asynchronous • Programmable data format Al IP5 receiver/transmitter channels in a single —5 to 8 data bits plus parity 11,1 IP6 package. It interfaces directly with micro- —Odd, even, no parity or force parity processors and may be used in a polled or A2 IP2 —1, 1.5 or 2 stop bits programmable in interrupt driven system. A3 CEN 1/16 bit increments IPO RESET The operating mode and data format of • Programmable baud rate for each re- WRN X2 each channel can be programmed inde- ceiver and transmiter selectable from: pendently. Additionally, each receiver and —18 fixed rates: 50 to 38.4K baud RDN Xl/CLK transmitter can select its operating speed —One user defined rate derived from RXDB RXDA as one of eighteen fixed baud rates, a 16x programmable timer/counter TXDB TXDA clock derived from a programmable —External lx or 16x clock OP1 OPO counter/timer, or an external lx or 16x • Parity, framing, and overrun error detec- clock. The baud rate generator and OP3 OP2 tion counter/timer can operate directly from a OP5 OP4 crystal or from external clock inputs. The • False start bit detection OP7 OP6 ability to independently program the • Line break detection and generation Dl DO operating speed of the receiver and trans- • Programmable channel mode D3 D2 mitter make the DUART particularly attrac- —Normal (full duplex) Ds D4 tive for dual-speed channel applications —Automatic echo D7 D6 such as clustered terminal systems. —Local loopback GND INTRN Each receiver is quadruply buffered to —Remote loopback minimize the potential of receiver overrun • Multi-function programmable 16-bit or to reduce interrupt overhead in inter- counter/timer rupt driven systems. In addition, a flow • Multi-function 7-bit input port AO VCC control capability is provided to disable a —Can serve as clock or control inputs Al IP2 remote DUART transmitter when the buf- —Change of state detection on four A2 CEN fer of the receiving device is full. inputs A3 RESET Also provided on the SCN2681 are a multi- • Multi-function 8-bit output port WRN X2 —Individual bit set/reset capability purpose 7-bit input port and a multipur- RDN Xl/CLK pose 8-bit output port. These can be used —Outputs can be programmed to be RXDB RXDA as general purpose I/O ports or can be status/interrupt signals TXDB TXDA assigned specific functions (such as clock • Versatile interrupt system inputs or status/interrupt outputs) under —Single interrupt output with eight OP1 OPO program control. maskable interrupting conditions D1 DO The SCN2681 is available in three package —Output port can be configured to pro- D3 D2 versions to satisfy various system require- vide a total of up to six separate wire• 05 04 ments: 40-pin and 28-pin, both 0.6" wide OR'able interrupt outputs D7 D6 DIPs, and a compact 24-pin, 0.4" wide, • Maximum data transfer: 1X — 1MB/sec, GND INTRN DIP. 16X — 125KB/sec • Automatic wake-up mode for multidrop applications A, AO • Start-end break interruptIstatus A2 VCC • Detects break which originates in the A3 CEN middle of a character WRN RESET • On-chip crystal oscillator RDN X1ICLK • TTL compatible RXDB RXDA • Single + 5V power supply TXDB TXDA ORDERING CODE D1 DO Vcc = 5V -!..- 5%, TA = 0°C to 70°C D3 D2 PACKAGES 24 Pint 28 Pin2 40 Pin2 D5 D4 D7 D6 Ceramic DIP Not available SCN2681AC1I28 SCN2681AC1140 Plastic DIP SCN2681AC1N24 SCN2681AC1N28 SCN2681AC1N40 GND INTRN

1400 mil wide DIP TOP VIEWS 2600 mil wide DIP

1.68 Signetics MICROPROCESSOR DIVISION JANUARY 1983

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN2681 SERIES

Preliminary

BLOCK DIAGRAM

DO-D7 BUS BUFFER CHANNEL A

TRANSMIT HOLDING REG ox. TxDA TRANSMIT SHIFT REGISTER

OPERATION RDN CONTROL RECEIVE WRN HOLDING REG ADDRESS (3) CEN DECODE RxDA RECEIVE AO A3 SHIFT REG R/W CONTROL RESET MRA1,2

CRA SRA

INTERRUPT CONTROL • — TxDB INTRN CHANNEL B IMR (AS ABOVE) RxDB ISR

co INPUT PORT 3

CHANGED STATE DATA 1 7 TIMING DETECTORS (4) IPO IP6 NAL BAUD RATE GENERATOR IPCR 2 ACR

CLOCK SELECTORS OUTPUT PORT

COUNTER/ FUNCTION TIMER SELECT LOGIC N ► OPO-OP7 X1 /CLK XTAL OSC OPCR X2 OPR

CSRA

CSRB Vcc

ACR GND CTUR

CTLR

Signetics 1.69 MICROPROCESSOR DIVISION JANUARY 1983

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN2681 SERIES

Preliminary PIN DESIGNATION

APPLICABLE MNEMONIC TYPE NAME AND FUNCTION 40 28 24 DO-D7 X X X I/O Data Bus: Bidirectional 3-state data bus used to transfer commands, data and status between the DUART and the CPU. DO is the least significant bit. CEN X X X I Chip Enable: Active low input signal. When low, data transfers between the CPU and the DUART are enabled on DO-D7 as controlled by the WRN, RDN and AO-A3 inputs. When high, places the DO-D7 lines in the 3-state condition. WRN X X X I Write Strobe: When low and CEN is also low, the contents of the data bus is loaded into the addressed register. The transfer occurs on the rising edge of the signal. RDN X X X I Read Strobe: When low and CEN is also low, causes the contents of the addressed register to be presented on the data bus. The read cycle begins on the falling edge of RDN. AO-A3 X X X I Address Inputs: Select the DUART internal registers and ports for read/write operations. RESET X X X I Reset: A high level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OPO-OP7 in the high state, stops the counter/timer, and puts channels A and B in the inactive state, with the TxDA and TxDB outputs in the mark (high) state. INTRN X X X 0 Interrupt Request: Active low, open drain, output which signals the CPU that one or more of the eight maskable interrupting conditions are true. X1/CLK X X X I Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. When a crystal is used, a capacitor must be connected from this pin to ground (see figure 5). X2 X X 0 Crystal 2: Connection for other side of the crystal. Should be connected to ground if a crystal is not used. When a crystal is used, a capacitor must be connected from this pin to ground (see figure 5). RxDA X X X I Channel A Receiver Serial Data Input: The least significant bit is received first. 'Mark' is high, 'space' is low. RxDB X X X I Channel B Receiver Serial Data Input: The least significant bit is received first. 'Mark' is high, 'space' is low. TxDA X X X 0 Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the 'mark' condition when the transmitter is disabled, idle, or when operating in local loopback mode. 'Mark' is high, 'space' is low. TxDB X X X 0 Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the 'mark' condition when the transmitter is disabled, idle, or when operating in local loopback mode. 'Mark' is high, 'space' is low. OPO X X 0 Output 0: General purpose output, or channel A request to send (RTSAN, active low). Can be deactivated on receive or transmit. OP1 X X 0 Output 1: General purpose output, or channel B request to send (RTSBN, active low). Can be deactivated on receive or transmit. OP2 X 0 Output 2: General purpose output, or channel A transmitter lx or 16X clock output, or channel A receiver 1X clock output. OP3 X 0 Output 3: General purpose output, or open drain, active low counter/timer output, or channel B transmitter 1X clock output, or channel B receiver 1X clock output. OP4 X 0 Output 4: General purpose output, or channel A open drain, active low, RxRDYA/FFULLA output. OP5 X 0 Output 5: General purpose output, or channel B open drain, active low, RxRDYB/FFULLB output. OP6 X 0 Output 6: General purpose output, or channel A open drain, active low, TxRDYA output. OP7 X 0 Output 7: General purpose output, or channel B open drain, active low, TxRDYB output. IPO X I Input 0: General purpose input, or channel A clear to send active low input (CTSAN). IP1 X I Input 1: General purpose input, or channel B clear to send active low input (CTSBN). IP2 X X I Input 2: General purpose input, or counter/timer external clock input. IP3 X I Input 3: General purpose input, or channel A transmitter external clock input (TxCA). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. 1-70 Signetics MICROPROCESSOR DIVISION JANUARY 1983

DUAL ASYNCHRONOUS RECEIVERITRANSMITTER (DUART) SCN2681 SERIES

Preliminary PIN DESIGNATION (Continued) APPLICABLE MNEMONIC TYPE NAME AND FUNCTION 40 28 24 IP4 X I Input 4: General purpose input, or channel A receiver external clock input (RxCA). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. IP5 X I Input 5: General purpose input, or channel B transmitter external clock input (TxCB). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. IP6 X I Input 6: General purpose input or channel B receiver external clock input (RxCB). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. Vcc X X X I Power Supply: + 5V supply input GND X X X I Ground

BLOCK DIAGRAM Timing Circuits Communications Channels The 2681 DUART consists of the following The timing block consists of a crystal A and B eight major sections: data bus buffer, oscillator, a baud rate generator, a pro- Each communications channel of the 2681 operation control, interrupt control, tim- grammable 16-bit counter/timer, and four comprises a full duplex asynchronous re- ing, communications channels A and B, in- clock selectors. The crystal oscillator ceiver/transmitter (UART). The operating put port and output port. Refer to the operates directly from a 3.6864MHz crys- frequency for each receiver and transmit- block diagram. tal connected across the X1/CLK and X2 ter can be selected independently from inputs. If an external clock of the appropri- the baud rate generator, the counter timer, Data Bus Buffer ate frequency is available, it may be con- or from an external input. nected to X1/CLK. The clock serves as the The data bus buffer provides the interface The transmitter accepts parallel data from between the external and internal data basic timing reference for the baud rate generator (BRG), the counter/timer, and the CPU, converts it to a serial bit stream, busses. It is controlled by the operation other internal circuits. A clock signal inserts the appropriate start, stop, and op- control block to allow read and write within the limits specified in the specifica- tional parity bits and outputs a composite operations to take place between the con- tions section of this data sheet must serial stream of data on the TxD output trolling CPU and the DUART. always be supplied to the DUART. pin. The receiver accepts serial data on the RxD pin, converts this serial input to Operation Control The baud rate generator operates from the parallel format, checks for start bit, stop The operation control logic receives oscillator or external clock input and is bit, parity bit (if any), or break condition operation commands from the CPU and capable of generating 18 commonly used and sends an assembled character to the generates appropriate signals to internal data communications baud rates ranging CPU. sections to control device operation. It from 50 to 38.4K baud. The clock outputs contains address decoding and read and from the BRG are at 16X the actual baud Input Port write circuits to permit communications rate. The counter/timer can be used as a The inputs to this unlatched 7-bit port can with the microprocessor via the data bus timer to produce a 16X clock for any other be read by the CPU by performing a read buffer. baud rate by counting down the crystal clock or an external clock. The four clock operation at address D16. A high input re- Interrupt Control selectors allow the independent selection, sults in a logic 1 while a low input results for each receiver and transmitter, of any of in a logic 0. D7 will always be read as a A single active low interrupt output these baud rates or an external timing sig- logic 1. The pins of this port can also serve (INTRN) is provided which is activated nal. as auxiliary inputs to certain portions of upon the occurence of any of eight inter- the DUART logic. nal events. Associated with the interrupt The counter/timer (CIT) can be program- system are the interrupt mask register med to use one of several timing sources Four change-of-state detectors are pro- (IMR) and the interrupt status register as its input. The output of the CIT is avail- vided which are associated with inputs (ISR). The IMR may be programmed to able to the clock selectors and can also be I P3, I P2, IPI, and IPO. A high-to-low or low- select only certain conditions to cause programmed to be output at OP3. In the to-high transition of these inputs lasting INTRN to be asserted. The ISR can be read counter mode, the contents of the CIT can longer than 25-50gs will set the corre- by the CPU to determine all currently ac- be read by the CPU and it can be stopped and started under program control. In the sponding bit in the input port will change tive interrupting conditions. timer mode, the C/T acts as a program- register. The bits are cleared when the Outputs OP3-0P7 can be programmed to mable divider. register is read by the CPU. Any change of provide discrete interrupt outputs for the state can also be programmed to generate transmitters, receivers, and counter/timer. an interrupt to the CPU.

Signetics 1.71 MICROPROCESSOR DIVISION JANUARY 1983

DUAL ASYNCHRONOUS RECEIVERITRANSMITTER (DUART) SCN2681 SERIES

Preliminary

Output Port low condition by issuing a send break strobed into the SR at the received charac- command. ter boundary, before the RxRDY status bit The 8-bit multi-purpose output port can be is set. If a break condition is detected used as a general purpose output port, in The transmitter can be reset through a (RxD is low for the entire character in- which case the outputs are the comple- software command. If it is reset, operation cluding the stop bit), a character con- ments of the output port register (OPR). ceases immediately and the transmitter sisting of all zeros will be loaded into the OPR[n]= 1 results in OP[n]= low and vice- must be enabled through the command RHR and the received break bit in the SR versa. Bits of the OPR can be individually register before resuming operation. If CTS is set to 1. The RxD input must return to a set and reset. A bit is set by performing a operation is enabled, the CTSN input must high condition for at least one-half bit time write operation at address E16 with the ac- be low in order for the character to be before a search for the next start bit companying data specifying the bits to be transmitted. if it goes high in the middle of begins. set (1 = set, 0= no change). Likewise, a bit a transmission, the character in the shift is reset by a write at address F16 with the register is transmitted and TxDA then re- The RHR consists of a first-in-first-out accompanying data specifying the bits to mains in the marking state until CTSN (FIFO) stack with a capacity of three char- be reset (1 = reset, 0= no change). goes low. The transmitter can also control acters. Data is loaded from the receive the deactivation of the RTSN output. If shift register into the topmost empty posi- Outputs can be also individually assigned programmed, the RTSN output will be re- tion of the FIFO. The RxRDY bit in the specific functions by appropriate pro- set one bit time after the character in the status register is set whenever one or gramming of the channel A mode registers transmit shift register and transmit hold- more characters are available to be read, (MR1A, MR2A), the channel B mode regis- ing register (if any) are completely trans- and a FFULL status bit is set if all three ters (MR1B, MR2B), and the output port mitted, if the transmitter has been dis- stack positions are filled with data. Either configuration register (OPCR). abled. of these bits can be selected to cause an interrupt. A read of the RHR outputs the data at the top of the FIFO. After the read OPERATION Receiver cycle, the data FIFO and its associated The 2681 is conditioned to receive data status bits (see below) are 'popped' thus Transmitter when enabled through the command reg- emptying a FIFO position for new data. ister. The receiver looks for a high to low The 2681 is conditioned to transmit data In addition to the data word, three status (mark to space) transition of the start bit when the transmitter is enabled through bits (parity error, framing error, and reon the RxD input pin. If a transition is de- the command register. The 2681 indicates ceived break) are also appended to each tected, the state of the RxD pin is sampled to the CPU that it is ready to accept a data character in the FIFO (overrun is not). each 16X clock for 7-1/2 clocks (16X clock character by setting the TxRDY bit in the Status can be provided in two ways, as mode) or at the next rising edge of the bit status register. This condition can be pro- programmed by the error mode control bit time clock (1X clock mode). If RxD is grammed to generate an interrupt request in the mode register. In the 'character' sampled high, the start bit is invalid and at OP6 or OP7 and INTRN. When a charac- mode, status is provided on a character- the search for a valid start bit begins ter is loaded into the transmit holding reg- by-character basis: the status applies only again. If RxD is still low, a valid start bit is ister (THR), the above conditions are to the character at the top of the FIFO. In assumed and the receiver continues to negated. Data is transferred from the hold- the 'block' mode, the status provided in sample the input at one bit time intervals ing register to the transmit shift register the SR for these three bits is the logical at the theoretical center of the bit, until when it is idle or has completed transmis- OR of the status for all characters coming the proper number of data bits and the sion of the previous character. The TxRDY to the top of the FIFO since the last 'reset parity bit (if any) have been assembled, conditions are then asserted again which error' command was issued. In either and one stop bit has been detected. The means one full character time of buffering mode reading the SR does not affect the least sigificant bit is received first. The is provided. Characters cannot be loaded FIFO. The FIFO is 'popped' only when the data is then transferred to the receive into the THR while the transmitter is dis- RHR is read. Therefore the status register holding register (RHR) and the RxRDY bit should be read prior to reading the FIFO. abled. in the SR is set to a 1. This condition can If the FIFO is full when a new character is The transmitter converts the parallel data be programmed to generate an interrupt at received, that character is held in the re- from the CPU to a serial bit stream on the OP4 or OP5 and INTRN. If the character ceive shift register until a FIFO position is TxD output pin. It automatically sends a length is less than eight bits, the most available. If an additional character is restart bit followed by the programmed significant unused bits in the RHR are set ceived while this state exits, the contents number of data bits, an optional parity bit, to zero. of the FIFO are not affected: the character and the programmed number of stop bits. After the stop bit is detected, the receiver previously in the shift register is lost and The least significant bit is sent first. Fol- will immediately look for the next start bit. the overrun error status bit (SR[4]) will be lowing the transmission of the stop bits, if However, if a non-zero character was reset upon receipt of the start bit of the new a new character is not available in the ceived without a stop bit (framing error) (overruning) character. THR, the TxD output remains high and the and RxD remains low for one half of the bit TxEMT bit in the status register (SR) will The receiver can control the deactivation period after the stop bit was sampled, be set to 1. Transmission resumes and the of RTS. If programmed to operate in this then the receiver operates as if a new start TxEMT bit is cleared when the CPU loads a mode, the RTSN output will be negated new character into the THR. If the trans- bit transition had been detected at that when a valid start bit was received and the point (one-half bit time after the stop bit mitter is disabled, it continues operating FIFO is full. When a FIFO position be- was sampled). until the character currently being trans- comes available, the RTSN output will be mitted is completely sent out. The trans- The parity error, framing error, overrun er- re-asserted automatically. This feature mitter can be forced to send a continuous ror and received break state (if any) are can be used to prevent an overrun, in the

1.72 Signetics MICROPROCESSOR DIVISION JANUARY 1983

DUAL ASYNCHRONOUS RECEIVERITRANSMITTER (DUART) SCN2681 SERIES

Preliminary receiver, by connecting the RTSN output ate normally whether or not the receiver is MR1A — Channel A Mode to the CTSN input of the transmitting enabled. Register 1 device. MR1A is accessed when the channel A MR If the receiver is disabled, the FIFO char- PROGRAMMING pointer points to MR1. The pointer is set acters can be read. However, no additional to MR1 by RESET or by a 'set pointer' com- characters can be received until the re- The operation of the DUART is program- mand applied via CRA. After reading or ceiver is enabled again. If the receiver is med by writing control words into the ap- writing MR1A, the pointer will point to reset, the FIFO and all of the receiver propriate registers. Operational feedback MR2A. status, and the corresponding output is provided via status registers which can ports and interrupt are reset. No addi- be read by the CPU. The addressing of the MR1A[7] — Channel A Receiver Request- tional characters can be received until the registers is described in table 1. to-Send Control — This bit controls the receiver is enabled again. The contents of certain control registers deactivation of the RTSAN output (OPO) by Multidrop Mode are initialized to zero on RESET. Care the receiver. This output is normally asserted by setting OPR[0] and negated by The DUART is equipped with a wake up should be exercised if the contents of a register are changed during operation, resetting OPR[0]. MR1A[7] = 1 causes mode used for multidrop applications. RTSAN to be negated upon receipt of a This mode is selected by programming since certain changes may cause operational problems. For example, changing valid start bit if the channel A FIFO is full. bits MR1A[4:3] or MR1B[4:3] to '11' for the number of bits per character while the However, OPR[0] is not reset and RTSAN channels A and B respectively. In this transmitter is active may cause the trans- will be asserted again when an empty mode of operation, a 'master' station FIFO position is available. This feature transmits an address character followed mission of an incorrect character. In general, the contents of the MR, the CSR, and can be used for flow control to prevent by data characters for the addressed the OPCR should only be changed while overrun in the receiver by using the 'slave' station. The slave stations, with the receiver(s) and transmitter(s) are not RTSAN output signal to control the CTSN receivers that are normally disabled, ex- enabled, and certain changes to the ACR input of the transmitting device. amine the received data stream and 'wake- should only be made while the C/T is up' the CPU (by setting RxRDY) only upon stopped. MR1A(61 — Channel A Receiver Interrupt receipt of an address character. The CPU Select — This bit selects either the chan- compares the received address to its sta- Mode registers 1 and 2 of each channel are nel A receiver ready status (RXRDY) or the tion address and enables the receiver if it accessed via independent auxiliary point- channel A FIFO full status (FFULL) to be wishes to receive the subsequent data ers. The pointer is set to MR1x by RESET used for CPU interrupts. It also causes the characters. Upon receipt of another ad- or by issuing a 'reset pointer' command selected bit to be output on OP4 if it is dress character, the CPU may disable the via the corresponding command register. programmed as an interrupt output via the receiver to initiate the process again. Any read or write of the mode register OPCR. A transmitted character consists of a start while the pointer is at MR1x switches the bit, the programmed number of data bits, pointer to MR2x. The pointer then remains MR1A[5] — Channel A Error Mode Select an address/data (A/D) bit, and the pro- at MR2x, so that subsequent accesses are — This bit selects the operating mode of grammed number of stop bits. The polarity always to MR2x unless the pointer is reset the three FIFOed status bits (FE, PE, re- of the transmitted A/D bit is selected by to MR1x as described above. ceived break) for channel A. In the 'charac- the CPU by programming bit MR1A[2]/ Mode, command, clock select, and status ter' mode, status is provided on a charac- MR1 B[2]. MR1A[2]/MR1 B[2] = 0 transmits a registers are duplicated for each channel ter-by-character basis: the status applies zero in the A/D bit position, which iden- to provide total independent operation only to the character at the top of the tifies the corresponding data bits as data, and control. Refer to table 2 for register bit FIFO. In the 'block' mode, the status pro- while MR1A[2]/MR1B[2]= 1 transmits a descriptions. vided in the SR for these bits is the ac- one in the A/D bit position, which identifies the corresponding data bits as an ad- Table 1 2681 REGISTER ADDRESSING dress. The CPU should program the mode A3 A2 Al AO READ (RDN =0) WRITE (WRN =0) register prior to loading the corresponding 1 data bits into the THR. 0 0 0 Mode Register A (M R1A, MR2A) Mode Register A (MR1A, MR2A)

00 0 0 1 Status Register A (SRA) Clock Select Reg. A (CSRA) In this mode, the receiver continuously 0 1 0 *Reserved* Command Register A (CRA) looks at the received data stream, whether 0 1 1 RX Holding Register A (RHRA) TX Holding Register A (THRA) it is enabled or disabled. If disabled, it 1 0 0 Input Port Change Reg. (IPCR) Aux. Control Register (ACR) sets the RxRDY status bit and loads the 1 0 1 Interrupt Status Reg. (ISR) Interrupt Mask Reg. (I M R) character into the RHR FIFO if the re- 1 1 0 Counter/Timer Upper (CTU) CIT Upper Register (CTUR) ceived A/D bit is a one (address tag), but

000000 1 1 1 Counter/Timer Lower (CTL) CIT Lower Register (CTLR) discards the received character if the 0 0 0 Mode Register B (MR1B, MR2B) Mode Register B (MR1B, MR2B) received A/D bit is a zero (data tag). If 0 0 1 Status Register B (SRB) Clock Select Reg. B (CSRB) enabled, all received characters are trans- 0 1 0 *Reserved* Command Register B (CRB) ferred to the CPU via the RHR. In either 0 1 1 RX Holding Register B (RHRB) TX Holding Register B (THRB) case, the data bits are loaded into the data 1 0 0 *Reserved* 'Reserved* FIFO while the A/D bit is loaded into the 1 0 1 Input Port Output Port Conf. Reg. (OPCR) status FIFO position normally used for Start Counter Command Set Output Port Bits Command parity error (SRA[5] or SRB[5]). Framing 1 1 0

Reset Output Port Bits Command error, overrun error, and break detect oper- 1 1 1 Stop Counter Command Signetics 1.73 MICROPROCESSOR DIVISION JANUARY 1983

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN2681 SERIES

Preliminary Table 2 REGISTER BIT FORMATS BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO RX RTS RX INT ERROR PARITY PARITY MODE BITS PER CHAR, CONTROL SELECT MODE TYPE

MR1A 0= no 0= RXRDY 0= char 00= with parity 0= even 00=5 MRI B 1= yes 1= FFULL 1= block 01= force parity 1= odd 01= 6 10= no parity 10= 7 11 = multi-drop mode 11 = 8

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO Tx RTS CTS CHANNEL MODE STOP BIT LENGTH° CONTROL ENABLE Tx

MR2A 00= Normal 0= no 0= no 0=0.563 4=0.813 8=1.563 C=1.813 MR2B 01= Auto echo 1 = yes 1= yes 1 = 0.625 5=0.875 9=1.625 D= 1.875 10= Local loop 2=0.688 6=0.938 A=1.688 E=1.938 11= Remote loop 3=0.750 7=1.000 B= 1.750 F=2.000 *Add 0.5 to values shown for 0-7 if channel is programmed for 5 bitslchar. BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO RECEIVER CLOCK SELECT TRANSMITTER CLOCK SELECT CSRA CSRB See text See text

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO MISCELLANEOUS COMMANDS DISABLE Tx ENABLE Tx DISABLE Rx ENABLE Rx CRA not used— CRB must be 0 See text 0= no 0= no 0= no 0= no 1= yes 1= yes 1= yes 1= yes

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO RECEIVED FRAMING PARITY OVERRUN TxEMT TxRDY FFULL RxRDY BREAK ERROR ERROR ERROR SRA 0= no 0= no 0= no 0= no 0= no 0=no 0= no 0= no SRB 1= yes 1= yes 1= yes 1= yes 1= yes 1= yes 1= yes 1= yes

'These status bits are appended to the corresponding data character in the receive FIFO. A read of the status register provides these bits (7:5) from the top of the FIFO ogether with bits 4:0. These bits are clea ed by a 'reset error status' command. In character mode they are discarded when the corresponding data character is read from the FIFO. BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO OP7 OP6 OP5 OP4 OP3 OP2 0= OPR[7] 0= OPR[6] 0= OPR[5] 0= OPR[4] 00= °PR[3] 00= OPR[2] OPCR 1= TxRDYB 1= TxRDYA 1= RxRDY/ 1= RxRDY/ 01 = CIT OUTPUT 01 = TxCA (16X) FFULLB FFULLA 10= TxCB (1X) 10= TxCA (1X) 11 = RxCB (1X) 11 = RxCA (1X)

BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO BRG SET COUNTER/TIMER DELTA DELTA DELTA DELTA SELECT MODE AND SOURCE IP3 INT IP2 INT IP1 INT IPO INT ACR 0= sett See table 4 0= off 0= off 0= off 0= off 1= set2 1= on 1= on 1= on 1= on

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO DELTA DELTA DELTA DELTA IP3 IP2 IP1 IPO IPCR IP3 IP2 IPI IPO 0= no 0= no 0= no 0= no 0= low 0= low 0= low 0= low 1= yes 1= yes 1= yes 1= yes 1= high 1= high 1= high 1= high

1.74 Signetics MICROPROCESSOR DIVISION JANUARY 1983

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN2681 SERIES

Preliminary

Table 2 REGISTER BIT FORMATS (Continued) BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO INPUT DELTA RxRDYI COUNTER DELTA RxRDYI PORT TxRDYB TxRDYA BREAK B FFULLB READY BREAK A FFULLA ISR CHANGE 0= no 0= no 0= no 0= no 0 = no 0 = no 0 = no 0= no 1= yes 1= yes 1= yes 1= yes 1= yes 1= yes 1.= yes 1= yes

BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO IN. PORT DELTA RxRDYI COUNTER DELTA RxRDYI TxRDYB TxRDYA CHANGE BREAK B FFULLB READY BREAK A FFULLA INT INT IMR INT INT INT INT INT INT 0= off 0= off 0= off 0= off 0= off 0= off 0= off 0 = off 1= on 1= on 1= on 1= on 1= on 1= on 1= on 1= on

BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO C/T[15] C/T[14] CIT[13] CfT[12] CIT[11] CIT[10] C/T[9] CIT[8] CTUR

BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO CIT[7] CIT[6] C/T[5] C/T[4] CIT[3] CIT[2] C/T[1] CIT[0] CTLR

cumulation (logical OR) of the status for MR2A — Channel A Mode 6. Character framing is checked, but the all characters coming to the top of the Register 2 stop bits are retransmitted as received. FIFO since the last 'reset error' command 7. A received break is echoed as received MR2A is accessed when the channel A MR for channel A was issued. until the next valid start bit is detected. pointer points to MR2, which occurs after any access to MR1A. Accesses to MR2A 8. CPU to receiver communication contin- MR1A[4:3] — Channel A Parity Mode do not change the pointer. ues normally, but the CPU to transmit- Select — If 'with parity' or 'force parity' is ter link is disabled. selected, a parity bit is added to the trans- MR2A[7:6] — Channel A Mode Select — Two diagnostic modes can also be config- mitted character and the receiver per- ured. MR2A[7:6]= 10 selects local loop- forms a parity check on incoming data. Each channel of the DUART can operate in back mode. In this mode: MR1A[4:3]= 11 selects channel A to oper- one of four modes. MR2A[7:6]= 00 is the ate in the special multidrop mode de- normal mode, with the transmitter and re- 1. The transmitter output is internally scribed in the Operation section. ceiver operating independently. MR2A[7:6] connected to the receiver input. = 01 places the channel in the automatic 2. The transmit clock is used for the re- echo mode, which automatically retrans- ceiver. MR1A[2] — Channel A Parity Type Select mits the received data. The following con- 3. The TxDA output is held high. — This bit selects the parity type (odd or ditions are true while in automatic echo even) if the 'with parity' mode is program. mode: 4. The RxDA input is ignored. med by MR1A[4:3], and the polarity of the 5. The transmitter must be enabled, but 1. Received data is reclocked and retrans- forced parity bit if the 'force parity' mode the receiver need not be enabled. mitted on the TxDA output. is programmed. It has no effect if the `no 6. CPU to transmitter and receiver com- 2. The receive clock is used for the trans- parity' mode is programmed. In the special munications continue normally. multidrop mode it selects the polarity of mitter. the A/D bit. 3. The receiver must be enabled, but the The second diagnostic mode is the remote transmitter need not be enabled. loopback mode, selected by MR2A[7:6]= 11. In this mode: MR1A[1:01 — Channel A Bits per Character 4. The channel A TxRDY and TxEMT Select — This field selects the number of status bits are inactive. 1. Received data is relocked and retrans- data bits per character to be transmitted 5. The received parity is checked, but is mitted on the TxDA output. and received. The character length does not regenerated for transmission, i.e., 2. The receive clock is used for the trans- not include the start, parity, and stop bits. transmitted parity bit is as received. mitter.

Signetics 1.75 MICROPROCESSOR DIVISION JANUARY 1983

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN2681 SERIES

Preliminary

3. Received data is not sent to the local (IPO) each time it is ready to send a charac- Baud Rate CPU, and the error status conditions ter. If IPO is asserted (low), the character is CLOCK = 3.6864MHz are inactive. transmitted. If it is negated (high), the CSRA[7:4] ACR[7]= 0 ACR[7] = 1 4. The received parity is not checked and TxDA output remains in the marking state 0 0 0 0 50 75 is not regenerated for transmission, and the transmission is delayed until 0 0 0 110 110 i.e., transmitted parity bit is as re- CTSAN goes low. Changes in CTSAN 0 0 0 134.5 134.5 ceived. while a character is being transmitted do not affect the transmission of that charac- 0 0 200 150 5. The receiver must be enabled. ter. 0 0 0 300 300 6. Character framing is not checked, and 0 0 600 600 the stop bits are retransmitted as re- MR2A[3:0] — Channel A Stop Bit Length 0 0 1,200 1,200 ceived. Select — This field programs the length of 0 1,050 2,000 2,400 7. A received break is echoed as received the stop bit appended to the transmitted 0 0 0 2,400 until the next valid start bit is detected. character. Stop bit lengths of 9/16 to 1 and 0 0 4,800 4,800 1-9/16 to 2 bits, in increments of 1/16 bit, 0 0 7,200 1,800 9,600 The user must exercise care when switch- can be programmed for character lengths 0 9,600 19.2K ing into and out of the various modes. The of 6, 7, and 8 bits. For a character length of 0 0 38.4K 0 Timer Timer selected mode will be activated immedi- 5 bits, 1-1/16 to 2 stop bits can be pro- IP4-16X IP4-16X ately upon mode selection, even if this oc- grammed in increments of 1/16 bit. The re- 0 IP4-1X curs in the middle of a received or trans- ceiver only checks for a 'mark' condition IP4-1X mitted character. Likewise, if a mode is de- at the center of the first stop bit position The receiver clock is always a 16X clock selected, the device will switch out of the (one bit time after the last data bit, or after except for CSRA[7:4] = 1111. mode immediately. An exception to this is the parity bit if parity is enabled) in all switching out of autoecho or remote loop- cases. CSRA[3:0] — Channel A Transmitter Clock back modes: if the de-selection occurs If an external 1X clock is used for the Select — This field selects the baud rate just after the receiver has sampled the transmitter, MR2A[3]= 0 selects one stop clock for the channel A transmitter. The stop bit (indicated in autoecho by asser- bit and MR2A[3]= 1 selects two stop bits field definition is as per CSRA[7:4] except tion of RxRDY), and the transmitter is to be transmitted. as follows: enabled, the transmitter will remain in Baud Rate autoecho mode until the entire stop bit MR1B — Channel B Mode CSRA[3:0] ACR[7] = 0 ACR[7]= 1 has been retransmitted. Register 1 1 1 1 0 IP3-16X IP3-16X IP3-1X MR2A[5] — Channel A Transmitter Re- MR1B is accessed when the channel B MR 1 1 1 1 IP3-1X pointer points to MR1. The pointer is set guest-to-Send Control — This bit controls The transmitter clock is always a 16X to MR1 by RESET or by a 'set pointer' com- the deactivation of the RTSAN output clock except for CSRA[3:0]= 1111. (OPO) by the transmitter. This output is mand applied via CRB. After reading or normally asserted by setting OPR[0] and writing MR1B, the pointer will point to CSRB — Channel B Clock Select negated by resetting OPR[0]. MR2A[5]= 1 MR2B. Register causes OPR[0] to be reset automatically The bit definitions for this register are CSR13[7:4] — Channel B Receiver Clock one bit time after the characters in the identical to the bit definitions for MR1A, Select — This field selects the baud rate channel A transmit shift register and in except that all control actions apply to the clock for the channel B receiver. The field the THR, if any, are completely transmit- channel B receiver and transmitter and the definition is as per CSRA[7:4] except as ted, including the programmed number of corresponding inputs and outputs. stop bits, if the transmitter is not enabled. follows: This feature can be used to automatically MR2B — Channel B Mode Baud Rate terminate the transmission of a message Register 2 CSRB[7:4] ACR[7] = 0 ACR[7] =1 as follows: MR2B is accessed when the channel B MR 1 1 1 0 IP6-16X IP6-16X 1. Program auto-reset mode: MR2A[5]= 1. pointer points to MR2, which occurs after 1 1 1 1 IP6-1X IP6-1X 2. Enable transmitter. any access to MR1B. Accesses to MR2B The receiver clock is always a 16X clock 3. Assert RTSAN: OPR[0]= 1. do not change the pointer. except for CSRB[7:4]= 1111. 4. Send message. The bit definitions for this register are CSRB[3:0] — Channel B Transmitter Clock 5. Disable transmitter after the last char- identical to the bit definitions for MR2A, Select — This field selects the baud rate acter is loaded into the channel A THR. except that all control actions apply to the clock for the channel B transmitter. The channel B receiver and transmitter and the 6. The last character will be transmitted field definition is as per CSRA[7:4] except corresponding inputs and outputs. and OPR[0] will be reset one bit time as follows: after the last stop bit, causing RTSAN Baud Rate to be negated. CSRA — Channel A Clock Select Register CSRI3[3:0] ACR[7]= 0 ACR[7]= 1 1 1 1 0 IP5-16X IP5-16X MR2A[4] — Channel A Clear-to-Send Con. CSRA[7:4] — Channel A Receiver Clock 1 1 1 1 IP5-1X IP5-1X trol — If this bit is 0, CTSAN has no effect Select — This field selects the baud rate on the transmitter. If this bit is a 1, the clock for the channel A receiver as fol- The transmitter clock is always a 16X transmitter checks the state of CTSAN lows: clock except for CSRB[3:0]= 1111.

1.76 Signetics MICROPROCESSOR DIVISION JANUARY 1983

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN2681 SERIES

Preliminary CRA — Channel A Command times. TXDA will remain high for When this bit is set, the channel A 'change Register one bit time before the next in break' bit in the ISR (ISR[2]) is set. ISR[2] character, if any, is transmitted. is also set when the end of the break con- CRA is a register used to supply com- dition, as defined above, is detected. mands to channel A. Multiple commands CRA(3) — Disable Channel A Transmitter The break detect circuitry can detect can be specified in a single write to CRA — This command terminates transmitter breaks that originate in the middle of a as long as the commands are non-conflict- operation and resets the TxRDY and received character. However, if a break ing, e.g., the 'enable transmitter' and TxEMT status bits. However, if a character begins in the middle of a character, it must 'reset transmitter' commands cannot be is being transmitted or if a character is in persist until at least the end of the next specified in a single command word. the THR when the transmitter is disabled, character time in order for it to be de- the transmission of the character(s) is CRA[6:4] — Channel A Miscellaneous tected. completed before assuming the inactive Commands — The encoded value of this state. field may be used to specify a single com- SRA[6] — Channel A Framing Error —This mand as follows: bit, when set, indicates that a stop bit was CRA[2] — Enable Channel A Transmitter not detected when the corresponding data CRA[6:4] COMMAND — Enables operation of the channel A character in the FIFO was received. The transmitter. The TxRDY status bit will be stop bit check is made in the middle of the 0 0 0 No command. asserted. first stop bit position. 0 0 1 Reset MR pointer. Causes the channel A MR pointer to point to CRAM — Disable Channel A Receiver — SRAM — Channel A Parity Error — This MR1. This command terminates operation of bit is set when the 'with parity' or 'force 0 1 0 Reset receiver. Resets the chan- the receiver immediately — a character parity' mode is programmed and the corre- nel A receiver as if a hardware being received will be lost. The command sponding character in the FIFO was re- reset had been applied. The re- has no effect on the receiver status bits or ceived with incorrect parity. ceiver is disabled and the FIFO any other control registers. If the special In the special multidrop mode the parity is flushed. multidrop mode is programmed, the re- error bit stores the received A/D bit. 0 1 1 Reset transmitter. Resets the ceiver operates even if it is disabled. See channel A transmitter as if a Operation section. SRAM — Channel A Overrun Error — This hardware reset had been ap- bit, when set, indicates that one or more plied. CRAM — Enable Channel A Receiver — characters in the received data stream Enables operation of the channel A re- 1 0 0 Reset error status. Clears the have been lost. It is set upon receipt of a ceiver. If not in the special wakeup mode, channel A Received Break, Par- new character when the FIFO is full and a this also forces the receiver into the ity Error, Framing Error, and character is already in the receive shift search for start-bit state. Overrun Error bits in the status register waiting for an empty FIFO posi- register (SRA[7:4]). Used in char- tion. When this occurs, the character in acter mode to clear OE status CRB — Channel B Command the receive shift register (and its break (although RB, PE, and FE bits Register detect, parity error and framing error status, if any) is lost. will also be cleared) and in block CRB is a register used to supply com- mode to clear all error status mands to channel B. Multiple commands This bit is cleared by a 'reset error status' after a block of data has been can be specified in a single write to CRB command. received. as long as the commands are non-conflict- 1 0 1 Reset channel A break change ing, e.g., the 'enable transmitter' and SRA[3] — Channel A Transmitter Empty interrupt. Causes the channel A 'reset transmitter' commands cannot be (TxEMTA) — This bit will be set when the break detect change bit in the in- specified in a single command word. channel A transmitter underruns, i.e., both terrupt status register (ISR[2]) to the transmit holding register (THR) and The bit definitions for this register are be cleared to zero. the transmit shift register are empty. It is identical to the bit definitions for CRA, ex- set after transmission of the last stop bit 1 1 0 Start break. Forces the TXDA cept that all control actions apply to the of a character if no character is in the THR output low (spacing). If the channel B receiver and transmitter and the awaiting transmission. It is reset when the transmitter is empty the start of corresponding inputs and outputs. THR is loaded by the CPU or when the the break condition will be de- transmitter is disabled. layed up to two bit times. If the SRA — Channel A Status transmitter is active the break SRA[2] — Channel A Transmitter Ready begins when-transmission of the Register (TxRDYA) — This bit, when set, indicates character is completed. If a char- SRA[7] — Channel A Received Break — that the THR is empty and ready to be acter is in the THR, the start of This bit indicates that an all zero character loaded with a character. This bit is cleared the break will be delayed until of the programmed length has been re- when the THR is loaded by the CPU and is that character, or any others ceived without a stop bit. Only a single set when the character is transferred to loaded subsequently are trans- FIFO position is occupied when a break is the transmit shift register. TxRDY is reset mitted. The transmitter must be received: further entries to the FIFO are in- when the transmitter is disabled and is set enabled for this command to be hibited until the RxDA line returns to the when the transmitter is first enabled, viz., accepted. marking state for at least one-half a bit characters loaded into the THR while the 1 1 1 Stop Break. The TXDA line will time (two successive edges of the internal transmitter is disabled will not be trans- go high (marking) within two bit or external lx clock). mitted.

Signetics 1.77 MICROPROCESSOR DIVISION JANUARY 1983

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN2681 SERIES

Preliminary

SRAM — Channel A FIFO Full (FFULLA) OPCR[4] — OP4 Output Select — This bit OPCR[1:0] — OP2 Output Select — This — This bit is set when a character is trans- programs the OP4 output to provide one of field programs the OP2 output to provide ferred from the receive shift register to the the following: one of the following: receive FIFO and the transfer causes the — The complement of OPR[4] — The complement of OPR[2] FIFO to become full, i.e., all three FIFO — The channel A receiver interrupt out- positions are occupied. It is reset when — The 16X clock for the channel A trans- put, which is the complement of [SR[1]. the CPU reads the RHR. If a character is mitter. This is the clock selected by When in this mode OP4 acts as an open waiting in the receive shift register be- CSRA[3:0], and will be a 1X clock if collector output. Note that this output cause the FIFO is full, FFULL will not be CSRA[3:0]= 1111. is not masked by the contents of the reset when the CPU reads the RHR. — The 1X clock for the channel A trans- IMR. mitter, which is the clock that shifts the SRAM — Channel A Receiver Ready OPCR[3:2] — OP3 Output Select — This transmitted data. If data is not being (RxRDY.A) — This bit indicates that a char- field programs the OP3 output to provide transmitted, a free running 1X clock is acter has been received and is waiting in one of the following: output. the FIFO to be read by the CPU. It is set — The complement of OPR[3] — The 1X clock for the channel A receiver, when the character is transferred from the which is the clock that samples the — The counter/timer output, in which receive shift register to the FIFO and reset received data. If data is not being re- case OP3 acts as an open collector out- when the CPU reads the RHR, if after this ceived, a free running 1X clock is out- read there are no more characters still in put. In the timer mode, this output is a put. the FIFO. square wave at the programmed frequency. In the counter mode, the out- SRB — Channel B Status Register put remains high until terminal count is ACR — Auxiliary Control Register reached, at which time it goes low. The The bit definitions for this register are output returns to the high state when identical to the bit definitions for SRA, ex- ACR[7] — Baud Rate Generator Set Select the counter is stopped by a stop cept that all status applies to the channel — This bit selects one of two sets of baud counter command. Note that this out- B receiver and transmitter and the corre- rates to be generated by the BRG: put is not masked by the contents of sponding inputs and outputs. the IMR. Set 1: 50, 110, 134.5, 200, 300, 600, 1.05K, 1.2K, 2.4K, 4.8K, 7.2K, 9.6K, and — The 1X clock for the channel B trans- OPCR — Output Port Configur• 38.4K baud. ation Register mitter, which is the clock that shifts the transmitted data. If data is not being Set 2: 75, 110, 134.5, 150, 300, 600, 1.2K, OPCR[7] — OP7 Output Selact — This bit transmitted, a free running 1X clock is 1.8K, 2.0K, 2.4K, 4.8K, 9.6K, and programs the OP7 output to provide one of output. 19.2K baud. the following: — The 1X clock for the channel B receiver, The selected set of rates is available for — The complement of OPR[7] which is the clock that samples the use by the channel A and B receivers and — The channel B transmitter interrupt received data. If data is not being re- transmitters as described in CSRA and output, which is the complement of ceived, a free running 1X clock is out- CSRB. Baud rate generator characteristics TxRDYB. When in this mode OP7 acts put. are given in table 3. as an open collector output. Note that this output is not masked by the contents of the IMR. Table 3 BAUD RATE GENERATOR CHARACTERISTICS CRYSTAL OR CLOCK = 3.6864M Hz OPCR[6] — OP6 Output Select — This bit programs the OP6 output to provide one of NOMINAL RATE (BAUD) ACTUAL 16X CLOCK (KHz) ERROR (PERCENT) the followng: 50 0.8 0 — The complement of OPR[6] 75 1.2 0 110 1.759 -0.069 — The channel A transmitter interrupt 134.5 2.153 0.059 output, which is the complement of 150 2.4 0 TxRDYA. When in this mode OP6 acts 200 3.2 0 as an open collector output. Note that 300 4.8 0 this output is not masked by the con- 600 9.6 0 tents of the IMR. 1050 16.756 -0.260 OPCR[6] — OP5 Output Select — This bit 1200 19.2 0 programs the OP5 output to provide one of 1800 28.8 0 the following: 2000 32.056 0.175 2400 38.4 0 — The complement of OPR[5] 4800 76.8 0 — The channel B receiver interrupt out- 7200 115.2 0 put, which is the complement of ISR[5]. 9600 153.6 0 When in this mode OP5 acts as an open 19.2K 307.2 0 collector output. Note that this output 38.4K 614.4 0

is not masked by the contents of the NOTE IMR. Duty cycle of 16X clock is 50% ± 1%.

1.78 Signetics MICROPROCESSOR DIVISION JANUARY 1983

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN2681 SERIES

Preliminary ACR[6:4]—Counter/Timer Mode and Clock Table 4 ACR [6:4] FIELD DEFINITION Source Select — This field selects the operating mode of the counter/timer and ACR[6:4] MODE CLOCK SOURCE its clock source as shown in table 4. 0 0 0 Counter External (IP2) 0 0 1 Counter TXCA — 1X clock of channel A transmitter ACR[3:0] — IP3, IP2, IP1, IPO Change of State Interrupt Enable — This field selects 0 1 0 Counter TXCB — 1X clock of channel B transmitter which bits of the Input Port Change regis- 0 1 1 Counter Crystal or external clock (X1/CLK) divided by 16 ter (IPCR) cause the input change bit in 1 0 0 Timer External (IP2) the interrupt status register (ISR[7]) to be 1 0 1 Timer External (IP2) divided by 16 set. If a bit is in the 'on' state, the setting 1 1 0 Timer Crystal or external clock (X1/CLK) of the corresponding bit in the IPCR will also result in the setting of ISR[7], which 1 1 1 Timer Crystal or external clock (X1/CLK) divided by 16 results in the generation of an interrupt output if IMR[7]= 1. If a bit is in the 'off' state, the setting of that bit in the IPCR has no effect on ISR[7]. ISMS] — Channel B Change in Break — ISR[2] — Channel A Change in Break — This bit, when set, indicates that the chan- This bit, when set, indicates that the chan- IPCR — Input Port Change nel B receiver has detected the beginning nel A receiver has detected the beginning Register or the end of a received break. It is reset or the end of a received break. It is reset when the CPU issues a channel B 'reset when the CPU issues a channel A 'reset IPCR[7:4] — IP3, IP2, IP1, IPO Change of break change interrupt' command. break change interrupt' command. State — These bits are set when a change of state, as defined in the Input Port sec- ISR[5] — Channel B Receiver Ready or !SR[1] — Channel A Receiver Ready or tion of this data sheet, occurs at the re- FIFO Full — The function of this bit is pro- spective input pins. They are cleared when FIFO Full — The function of this bit is programmed by MR1A[6]. If programmed as the IPCR is read by the CPU. A read of the grammed by MR1B[6]. If programmed as receiver ready, it indicates that a character the input change receiver ready, it indicates that a character IPCR also clears ISR[7], has been received in channel A and is bit in the interrupt status register. has been received in channel B and is waiting in the FIFO to be read by the CPU. waiting in the FIFO to be read by the CPU. The setting of these bits can be program- It is set when the character is transferred It is set when the character is transferred med to generate an interrupt to the CPU. from the receive shift register to the FIFO from the receive shift register to the FIFO and reset when the CPU reads the RHR. If and reset when the CPU reads the RHR. If IPCR[3:0] — 1P3, IP2, IP1, IPO Current State after this read there are more characters after this read there are more characters — These bits provide the current state of still in the FIFO the bit will be set again still in the FIFO the bit will be set again the respective inputs. The information is after the FIFO is 'popped'. If programmed after the FIFO is 'popped'. If programmed unlatched and reflects the state of the in- as FIFO full, it is set when a character is as FIFO full, it is set when a character is put pins at the time the IPCR is read. transferred from the receive holding regis- transferred from the receive holding register to the receive FIFO and the transfer ter to the receive FIFO and the transfer ISR — Interrupt Status Register causes the channel B FIFO to become full, causes the channel A FIFO to become full, i.e., all three FIFO positions are occupied. This register provides the status of all i.e., all three FIFO positions are occupied. It is reset when the CPU reads the RHR. If potential interrupt sources. The contents It is reset when the CPU reads the RHR. If a character is waiting in the receive shift of this register are masked by the interrupt a character is waiting in the receive shift register because the FIFO is full, the bit mask register (IMR). If a bit in the ISR is a register because the FIFO is full, the bit will be set again when the waiting charac- '1' and the corresponding bit in the IMR is will be set again when the waiting character is loaded into the FIFO. also a '1', the INTRN output will be as- ter is loaded into the FIFO. serted. If the corresponding bit in the IMR ISR[0] — Channel A Transmitter Ready — is a zero, the state of the bit in the ISR has — ISR[4] — Channel B Transmitter Ready This bit is a duplicate of TxRDYA (SRA[2]). no effect on the INTRN output. Note that This bit is a duplicate of TxRDYB (SRB[2]). the IMR does not mask the reading of the ISR — the true status will be provided regardless of the contents of the IMR. The ISR[3] — Counter Ready — In the counter IMR — Interrupt Mask Register mode, this bit is set when the counter contents of this register are initialized to The programming of this register selects reaches terminal count and is reset when 0016 when the DUART is reset. which bits in the ISR cause an interrupt the counter is stopped by a stop counter output. If a bit in the ISR is a '1' and the command. ISR[7] — Input Port Change Status — This corresponding bit in the IMR is also a '1', bit is a '1' when a change of state has In the timer mode, this bit is set once each the INTRN output will be asserted. If the occurred at the IPO, IP1, IP2, or IP3 inputs cycle of the generated square wave (every corresponding bit in the IMR is a zero, the and that event has been selected to cause other time that the counter/timer reaches state of the bit in the ISR has no effect on an interrupt by the programming of zero count). The bit is reset by a stop the INTRN output. Note that the IMR does ACR[3:0]. The bit is cleared when the CPU counter command. The command, how- not mask the programmable interrupt out- reads the IPCR. ever, does not stop the counter/timer. puts OP3-0P7 or the reading of the ISR.

Signetics 1.79 MICROPROCESSOR DIVISION JANUARY 1983

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN2681 SERIES

Preliminary CTUR and CTLR — Counter/Timer current timing cycle and to begin a new and ISR[3] is cleared when the counter is Registers cycle using the values in CTUR and CTLR. stopped by a stop counter command. The The counter ready status bit (ISR[3]) is set CPU may change the values of CTUR and The CTUR and CTLR hold the eight MSBs once each cycle of the square wave. The CTLR at any time, but the new count be- and eight LSBs respectively of the value to bit is reset by a stop counter command comes effective only on the next start be used by the counter/timer in either the (read with A3-A0= 1111). The command, counter command. If new values have not counter or timer modes of operation. The however, does not stop the CIT. The gen- been loaded, the previous count values minimum value which may be loaded into erated square wave is output on OP3 if it is are preserved and used for the next count the CTUR/CTLR registers is 000216. Note programmed to be the C/T output. cycle. that these registers are write-only and can- In the counter mode, the current value of not be read by the CPU. In the counter mode, the CIT counts down the number of pulses loaded into CTUR the upper and lower 8 bits of the counter In the timer (programmable divider) mode, and CTLR by the CPU. Counting begins (CTU, CTL) may be read by the CPU. It is the C/T generates a square wave with a upon receipt of a start counter command. recommended that the counter be stop- period of twice the value (in clock periods) Upon reaching terminal count (000016), the ped when reading to prevent potential pro- of the CTUR and CTLR. If the value in counter ready interrupt bit (ISR[3]) is set. blems which may occur if a carry from the CTUR or CTLR is changed, the current The counter continues counting past the lower 8-bits to the upper 8-bits occurs bet- half-period will not be affected, but subse- terminal count until stopped by the CPU. If ween the times that both halves of the quent half periods will be. In this mode the OP3 is programmed to be the output of the counter are read. However, note that a C/T runs continuously. Receipt of a start C/T, the output remains high until terminal subsequent start counter command will counter command (read with A3-A0 = count is reached, at which time it goes cause the counter to begin a new count 1110) causes the counter to terminate the low. The output returns to the high state cycle using the values in CTUR and CTLR.

ABSOLUTE MAXIMUM RATINGS' PARAMETER RATING UNIT Operating ambient temperature2 0 to + 70 °C Storage temperature - 65 to + 150 °C All voltages with respect to ground3 - 0.5 to + 6.0 V NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operation section of this specification is not implied. 2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature 3. This product includes circuitry specifically designed for the protection of its internal devices from damaging et- feels of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.

DC ELECTRICAL CHARACTERISTICS TA = 0°C tO + 70°C, Vcc = 5.0V +504,5,6 LIMITS PARAMETER TEST CONDITIONS UNIT Min Typ Max

VIL Input low voltage 0.8 V VIH Input high voltage (except X1/CLK) 2.0 V VIH Input high voltage (X1/CLK) 4.0 V VOL Output low voltage 10,_= 2.4mA 0.4 V VOH Output high voltage (except o.c. outputs) IGH = - 400AA 2.4 V I IL Input leakage current VIN= 0 to Vcc - 10 10 µA ILL Data bus 3-state leakage current VG = 0 to Vcc - 10 10 µA loc Open collector output leakage current VG = 0 to Vcc - 10 10 AA Icc Power supply current 150 mA NOTES: 4. Parameters are valid over specified temperature range. 5. All voltage measurements are referenced to ground (GND). For testing, all input signals swing between 0.4V and 2.4V with a transition time of 2Ons maximum. All time measurements are referenced at input voltages of 0.8V and 2.0V and output voltages of 0.8V and 2.0V as appropriate. 6. Typical values are at +25°C, typical supply voltages, and typical processing parameters.

1.80 Signetics MICROPROCESSOR DIVISION JANUARY 1983

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN2681 SERIES

Preliminary

AC ELECTRICAL CHARACTERISTICS TA = 0°C to + 70°C, Vcc = 5.0V ± 5%4,5,8,7 TENTATIVE LIMITS PARAMETER UNIT Min Typ Max Reset Timing (figure 1) tRES RESET pulse width 1.0 As Bus Timing (figure 2)8 tAS A0-A3 setup time to RDN, WRN low 10 ns tAH A0-A3 hold time from RDN, WRN high 0 ns tcs CEN setup time to RDN, WRN low 0 ns tcH CEN hold time from RDN, WRN high 0 ns tRw WRN, RDN pulse width 225 ns tDD Data valid after RDN low 175 ns t DF Data bus floating after RDN high 100 ns tDS Data setup time before WRN high 100 ns tDH Data hold time after WRN high 20 ns t !gm High time between READs and/or WRITEs9,1° 200 ns Port Timing (figure 3)8 tps Port input setup time before RDN low 0 ns tpH Port input hold time after RDN high 0 ns tpD Port output valid after WRN high 400 ns Interrupt Timing (figure 4) tIR INTRN (or OP3-0P7 when used as interrupts) high from: Read RHR (RXRDY/FFULL interrupt) 300 ns Write THR (TXRDY interrupt) 300 ns Reset command (delta break interrupt) 300 ns Stop C/T command (counter interrupt) 300 ns Read IPCR (input port change interrupt) 300 ns Write IMR (clear of interrupt mask bit) 300 ns Clock Timing (figure 5) tCLK X1/CLK high or low time 100 ns f CLK X1/CLK frequency 2.0 3.6864 4.0 MHz t CTC CTCLK (IP2) high or low time 100 ns f crc CTCLK (IP2) frequency 0 4.0 MHz tRx RxC high or low time 220 ns fax RxC frequency (16X) 0 2.0 MHz (1X) 0 1.0 MHz tTX TxC high or low time 220 ns f TX TxC frequency (16X) 0 2.0 MHz (1X) 0 1.0 MHz Transmitter Timing (figure 6) tTXD TxD output delay from TxC low 350 ns tTCS TxC output skew from TxD output data 0 150 ns Receiver Timing (figure 7) t605 RxD data setup time to RXC high 240 ns tRXH RxD data hold time from RXC high 200 ns NOTES: 4. Parameters are valid over specified temperature range. 5. All voltage measurements are referenced to ground (GND). For testing, all input signals swing between 0.4V and 2.4V with a transition time of 20ns maximum. All time measurements are referenced at input voltages of 0.8V and 2.0V and output voltages of 0.80 and 2.0V as appropriate. 6. Typical values are at + 25°C, typical supply voltages, and typical processing parameters. 7. Test condition for outputs: CL= 150pF, except interrupt outputs. Test condition for interrupt outputs: CL = 50pF, RL =2.7K ohm to Vcc. 8. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the 'strobing' input. In this case, all timing specifications apply referenced to the falling and rising edges of CEN. 9. If CEN is used as the 'strobing' input, this parameter defines the minimum high time between one CEN and the next. 10 Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.

Signetics 1.81 MICROPROCESSOR DIVISION JANUARY 1983

DUAL ASYNCHRONOUS RECEIVERITRANSMITTER (DUART) SCN2681 SERIES

Preliminary

RESET

tRES

Figure 1. Reset Timing

A0-A3

CEN

RDN

DO-D7 (READ)

WRN

DO-D7 (WRITE)

Figure 2. Bus Timing

1.82 Signetics MICROPROCESSOR DIVISION JANUARY 1983

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN2681 SERIES

Preliminary

RDN

IPS -a- IPH

IP0.1P6

WRN

f IPOs

OP0.0P7 OLD DATA NEW DATA

Figure 3. Port Timing

RDN OR WRN

tl R

INTRN OR OP3.0P7

Figure 4. Interrupt Timing

+ 5V Cl: 10-15pF +(STRAY < 5pF) C2: 0-5pF + (STRAY < 5pF) CLOCK TO OTHER 74LSO4 CHIPS

X1ICLK CTCLK RxC TxC Cl

3.6864MHz Figure 5. Clock Timing CRYSTAL SERIES RESISTANCE SHOULD BE LESS THAN 180 OHMS. Signetics 1.83 MICROPROCESSOR DIVISION JANUARY 1983

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN2681 SERIES

Preliminary

1 BIT TIME (1 OR 16 CLOCKS)

TxC (INPUT)

H--ITXD TxD EMI

)TCS

TxC IIX OUTPUT)

Figure 6. Transmit

RxC (IX INPUT)

RxD

Figure 7. Receive

TxD

TRANSMITTER ENABLED

TxRDY (SR2)

WRN

D3 START D4 STOP 05 WILL BREAK BREAK NOT BE TRANSMITTED GTSN' IIPOI

RTSN2 (OPO)

NOTES 1. TIMING SHOWN FOR MR2(4)=1. 2. TIM NG SHOWN FOR MR2(5)=1.

Figure 8. Transmitter Timing

1.84 Signetics MICROPROCESSOR DIVISION JANUARY 1983

DUAL ASYNCHRONOUS RECEIVERITRANSMITTER (DUART) SCN2681 SERIES

Preliminary

RxD

RECEIVER _I ENABLED

RxRDY (SRO)

FFUL (SRI)

RxRDY/ FFULL (0P5)2

RDN STATUS DATA D5 WILL \ STATUS DATA STATUS DATA STATUS DATA D1 BE LOST D2 C7-1)3 D4 OVERRUN VALET BY COMMAND (SR4)

RTS1 (OPO) OPR(0)= 1 NOTES 1. TIMING SHOWN FOR MR1(7)=1. 2. SHOWN FOR OPCR(4) = 1 AND MR(6)= O. Figure 9. Receiver Timing

MASTER STATION BIT 9 BIT9 BIT 9 TxD ADD#11 1 DO 10 1 ADD#211

TRANSMITTER I ENABLED

TxRDY ISR2)

WRN

MR1(4 - 3)=11 ADD#1 MR1(2). 0 DO MR1(2)=1 ADD#2 MR1(2)= 1

PERIPHERAL STATION BIT 9 BIT 9 BIT 9 BIT 9 BIT 9

RxD 10 IADD 2i 1 0 45-

RECEIVER ENABLED

RxRDY (SRO)

RDN/WRN

MR1(4 - 3)=11 ADD#I STATUS DATA STATUS DATA DO ADD#2 Figure 10. Wake Up Mode

Signetics 1.85

Section 2 Video Display

Signetics

MICROPROCESSOR DIVISION JANUARY 1983

CRT CHIP SET COMPARISON FEATURES

FEATURES 2672 2674 System Configurations Row buffer mode • • Transparent mode • • Shared mode • • Independent mode • • Clock interleaving mode • • Screen format 1 to 256 characters per row • • 1 to 16 lines per row • • 1 to 128 rows per screen • • Vertical synchronization Programmable front porch • • Programmable sync width • Programmable back porch • • Horizontal synchronization Programmable front porch • • Programmable sync width • • Programmable back porch • • Interlace capability Non-interlace • • Interlace • • Composite sync RS170 compatible • • Cursor Readable • • Writable • • Incrementable • • Programmable size and blink • • 16K addressing limit • • 4MHz maximum character clock rate • • Smooth scrolling Bidirectional • • Automatic • Programmable scroll region • Split screen Screen start register 1 • • Screen start register 2 • Multiple splits • • Automatic split • Light pen register • AC line lock (external sync) • Bit mapped graphics hardware support • Double height rows Tops • Bottoms • Both • • Double width rows control output • Dynamic RAM refresh • •

Signetics 2.1 MICROPROCESSOR DIVISION JANUARY 1983

CRT CHIP SET COMPARISON FEATURES

FEATURES 2673 2675 Attributes Reverse video • • Blank • Blink • • Highlight • Light pen strike-thru • Underline • • Two general purpose • Eight foreground colors • Eight background colors • Monochrome gray levels 3 4 Dot width control Double width • Field oriented • Character oriented • • Background intensity Programmable • • Composite blank • • Automatic • 25MHz video dot rate (See note 1) • • Programmable dot stretching • Compatible with 2672, 2674 and 2670 • • Programmable character clock 6 to 12 dots See note 2

NOTES: 1. For faster dot rates, consult factory. 2. Two versions of dots per character: SCB2675B possible dots are 7, 8, 9, 10. SCB2675C possible dots are 6, 8, 9, 10.

2.2 Signetics MICROPROCESSOR DIVISION JANUARY 1983 DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG) SCN2670

DESCRIPTION FEATURES PIN CONFIGURATION The Signetics Display Character and • 128 10X9 matrix characters Graphics Generator (DCGG) is a mask- • 256 graphic characters programmable 11,648-bit line select char- • Optional thin graphics for forms acter generator. It contains 128 10X9 char- • Character and line address latches acters placed in a 10X16 matrix, and has • Internal descend logic the capability of shifting certain characters, • 200nsec and 300nsec character select such as j, y, g, p and q, that normally extend access time versions below the baseline. Character shifting, pre- • Control character output inhibit logic • Static operation—no clocks required viously requiring additional external circuit- • Single 5V power supply ry, is now accomplished internally by the • TTL compatible inputs and outputs DCGG; effectively, the 9 active lines are lowered within the matrix to compensate for the character's position.

Seven bits of an 8-bit address code are used to select 1 of the 128 available characters. The eighth bit functions as a chip enable signal. Each character is defined by a pattern of logic Is and Os stored in a 10X9 matrix. When a specific 4-bit binary line address code is applied, a word of 10 parallel bits appears at the output. The lines can be sequentially selected, providing a 9-word sequence of 10 parallel bits per word for each character selected by the address in- ORDERING CODE puts. As the line address inputs are sequen- Vcc = 5V -± 5%, TA = 0°C to 70°C tially addressed, the device will automati- PACKAGES cally place the 10X9 character in 1 of 2 pre- tcA = 200ns tcA = 300ns programmed positions on the 16-line matrix Ceramic DIP SCN2670*C2128 SCN2670•C3128 with the positions defined by the 4-line ad- Plastic DIP SCN2670*C2N28 SCN2670•C3N28 dress inputs. One or more of the 10 parallel outputs can be used as control signals to NOTE Substitute letter corresponding to standard font for' in part number for standard parts. See back of data sheet. Con- selectively enable functions such as half- tact sales office for custom ROM patterns. dot shift, color selection, etc. The 2670 DCGG includes latches to store BLOCK DIAGRAM the character address and line address data. A control input to inhibit character SCD data output for certain groups of characters VCC is also provided. The 2670 also includes a GM GND graphics capability, wherein the 8-bit character code is translated directly into 256 CAO-CA7 possible user programmable graphic patterns. Thus, the DCGG can generate data for CSTROBE CHARACTER LATCH OUTPUT 384 distinct patterns, of which 128 are de- INHIBIT fined by the mask programmable ROM. See CONTROL figure 1 for a typical applications display.

GRAPHICS ADDRESS DECODER. LOGIC LAO- LA3

LINE READ ONLY SELECT MEMORY MULTI- OUTPUT (128 DO-D9 x 91) PLEXERS DRIVERS

LINE ADDRESS LINE LAO-LA3 TRANSLATION ROM LATCH (32 x 101

LSTROBE

Signetics 2-3 MICROPROCESSOR DIVISION JANUARY 1983 DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG) SCN2670

PIN DESIGNATION

MNEMONIC PIN NO. TYPE NAME AND FUNCTION

CAO-CA7 3-6, 8-11 I Character Address: Eight bit code specifies the character or graphic pattern for which matrix data is to be supplied. In character mode (GM=O), CAO thru CA6 select one of the 128 ROM- defined characters and CA7 is a chip enable. The outputs are active when CA7=1 and are tri- stated when CA7=0. In graphics mode (GM= 1), the outputs are active and CAO thru CA7 select one of 256 possible graphic patterns to be output. CSTROBE 7 I Character Strobe: Used to store the character address (CAO thru CA7) and graphics mode (GM) inputs into the character latch. Data is latched on the negative going edge of CSTROBE. GM 12 I Graphics Mode: GM=O (low) selects character mode; GM= 1 (high) selects graphics mode. LAO-LA3 1, 25-27 I Line Address: In character mode, selects one of the 16 lines of matrix data for the selected character to appear at the 10 outputs. LAO is the LSB and LA3 is the MSB. The input codes which cause each of the nine lines of character data to be output are specified as part of the programming data for both non-shifted and shifted fonts. Cycling through the nine specified counts at the LAO thru LA3 inputs cause successive lines of data to be output on DO thru D9. The 7 non-specified codes for both non-shifted and shifted characters cause blanks (logic zeros) to be output. In graphics mode, the line address gates the latched graphics data directly to the outputs. LSTROBE 2 I Line Strobe: Used to store the line address data (LAO thru LA3) in the line address latch. Data is latched on the negative going edge of LSTROBE. SCD 13 I Selected Character Disable: In character mode, a high level at this input causes all outputs (regardless of line address) to be blanks (zeros) for characters for which CA6 and CA5 are both 0. A low level input selects normal operation. Inoperative in the graphics mode. D9-DO 15-24 0 Data Outputs: Provide the data for the specified character and line. VCC 28 I +5V power supply. GND 14 I Ground.

Figure 1. Typical Application

2.4 Signetics MICROPROCESSOR DIVISION JANUARY 1983 DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG) SCN2670

FUNCTIONAL DESCRIPTION of the 128 character fonts stored in the ROM graphics symbols and an example where The DCGG consists of nine major sections. section of the DCGG. (CA7 thru CAO) = H'65'. The outputs from the graphics logic go to the line select Line and character codes are strobed into Read Only Memory the line and character latches. The charac- multiplexers. The multiplexers route the The 11,648-bit ROM stores the fonts for the ter latch outputs are presented to the three graphic symbol data to the outputs when 128 matrix-defined characters. The data for sources of data; the ROM through an ad- GM = 1. each character consists of 91 bits. Ninety dress decoder, the graphics logic, and the bits represent the 10X9 matrix and one bit output inhibit control. The output inhibit con- Thin Graphics Option specifies whether the character data is out- trol (together with the SCD input) sup- As a customer specified option, 16 of the put at the normal (unshifted) lines or at the presses the ROM data for selected charac- possible graphic codes (I-1'80' to H'8F') may descended (shifted) lines. The 90 data bit ter codes. The outputs from the line latch be used to generate the special graphic outputs are supplied to the line select drive the line address translation ROM characters illustrated in figure 3. For each of multiplexers. The descend control bit is an which maps the character ROM data onto 9 these characters, the vertical component input to the line address translation ROM. of 16 line positions. Finally, the line select appears on the D4 output. The horizontal multiplexers route the ROM or graphics data Graphics Logic component occurs on LH which is specified to the output drivers on DO through D9. When the GM input is zero (low), the DCGG by the customer. The vertical components operates in the character mode. When it is specified by CAO and CA2 are output for line Character Latch one (high), it operates in the graphics mode. addresses zero thru LH and LH thru fifteen, respectively. The character latch is a 9-bit edge triggered In graphics mode, output data is generated latch used to store the character address by the graphics logic instead of the ROM. Line Select Multiplexers (CAO thru CA7) and graphics mode (GM) The graphics logic maps the latched char- The ten line select multiplexers select ROM inputs. The data is stored on the falling edge acter address (CAO thru CA7) to the outputs data as specified by the line address trans- of CSTROBE. Seven latched addresses (DO thru D9) as a function of line address lation ROM when GM=O, or graphics data (CAO thru CA6) are inputs to the ROM char- (LAO thru LA3). For any particular line ad- when GM= 1. The inputs to each multiplexer acter address decoder. In character mode dress value, two of the CA bits are output: are the nine line outputs from the ROM, an (GM=0), CA7 operates as a chip enable. CAO, CA2, CA4 or CA6 is output on DO thru output from the graphics logic and a logic The output drivers are enabled when CA7=1 D4 and CA1, CA3, CA5 or CA7 is output on zero (ground). and are tri-stated when CA7=0. In graphics D5 thru D9. The outputs are paired: When mode (GM= 1), the output drivers are always CAO is output on DO thru D4, CA1 is output Output Drivers on D5 thru D9 and likewise for CA2-CA3, enabled and the CAO thru CA7 outputs of the Ten output drivers with 3-state capability CA4-CA5 and CA6-CA7. latch are used to generate graphic symbols. serve as buffers between the line select A ROM within the graphics logic allows the multiplexers and external logic. The 3-state Character Address Decoder specific line numbers for which each pair of control input to these drivers is supplied This circuit decodes the 7-bit character ad- bits is output to be specified by the custom- from the CA7 latch when GM=O. When dress from the character latch to select one er. Figure 2 illustrates the general format for GM= 1, the outputs are always active.

LINE ADDRESS LINE LF = 0 — 0 -

— CAO CA1 GROUP 1 1 — 1 2 — 3 —

CA2 CA3 GROUP 2 4 — 5 — 5 — 6 —

CA4 CA5 GROUP 3 7 — 8 — 9 —

10 — CA6 CA7 GROUP 4 10 —

Li. — 1 11 —

EIE212A8'86- 26' GROUP LINE ADDRESSES ARE SPECIFIED BY THE CUSTOMER EXAMPLE: CA7-CAO= H'65' GROUP 1 SPECIFIED FOR LINES 0, 1, 2 GROUP 2 SPECIFIED FOR LINES 3, 4, 5 GROUP 3 SPECIFIED FOR LINES 6, 7, 8 GROUP 4 SPECIFIED FOR LINES 9, 10, 11 SPACE SPECIFIED FOR LINES 12, 13, 14, 15

Figure 2. Graphics Symbols — General Format

Signetics 2.5 MICROPROCESSOR DIVISION JANUARY 1983 DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG) SCN2670

Output Inhibit Control The output inhibit control logic operates only GENERAL FORMAT if GM=0. It causes the output of the line 10 x 16 CHARACTER BLOCK select multiplexers to be logic zero if the LO SCD input is high and CA6 and CA5 of the latched character address are 00. If the SCD input is low, normal operation occurs. (This feature is useful in ASCII coded applications to selectively disable character generation for non-displayable characters such as line feed, carriage return, etc.) CAO Line Address Latch The line address latch is a 4-bit latch used CA1 to store the line address (LAO-LA3). The data is stored on the negative edge of the CA2 LSTROBE input. LH CA3 Line Address Translation ROM This 32X10 ROM translates the 5-bit code CA4 0 consisting of the 4 outputs from the line address latch and the descend control bit from CA5 0 the ROM into a 1-of-10 code for the line select multiplexers. Programming informa- CA6 0 tion provided by the customer specifies the address which selects each line of ROM CA7 1 data for both shifted and non-shifted characters. Thus, there are nine line addresses which select ROM data for unshifted characters and nine addresses for shifted characters. These combinations are usually specified by the customer in either ascending or descending order. For the remaining 14 codes (7 each for unshifted and shifted 115 characters), the translation ROM forces zeros at the outputs of the line select DO D4 D9 multiplexers. THIN GRAPHIC FONTS FOR This circuitry only operates if GM=0. When CA7 - CAO = HEX 80-HEX OF GM= 1, the line select multiplexers are forced to select the outputs from the graphics logic.

Figure 4 shows an example of data outputs 80 81 82 83 where the customer has specified line 14 as the first line for unshifted characters, line 11 as the first line for shifted characters and line address combinations in descending order. H 84 85 86 87 CUSTOM PATTERN PROGRAMMING INSTRUCTIONS A computer-aided technique utilizing punched computer cards is employed to specify a custom version of the 2670. This technique requires that the customer supply 88 89 8A 8B Signetics with a deck of standard 80-column computer cards describing the data to be stored in the ROM array, the programmable ni line address translation ROM, thin graphics option, and the graphics line font translation

ROM. BC 8D BE OF Figure 3. Special Graphic Characters

2.6 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG) SCN2670

LINE

15 •••••••••• :"*PAPP"••• 40+0+0+0+0+0+0 +++++++++••• 14 0+0+0 0+0#0+0+0+0 6+ +6+6+6+6+6+ 13 0+0+0+0+ • .0000 0++0+0++0++0++0++0+0+0 +.+4 o++d h+ •• 12 k+ +diid+ + + + mF+. '+ +w 11 eai tr+i rd; • • •• +++++++++ 10 k di TMS+ SI 6+ +6+6+6+6+6+++6 9 "+. + + + 6+ 0+6+6+6+64•k6+6 8 +6+22+w POW 6+ +6+6+6+6+6+6+6+6 7 + .1w 2+ 6 • • 000 0 6+ +6+6+6+6+6+6+6+6 ++ +++++++ 6+6+6+6+6+6+6+6+6+6 5 6+ +6+6+6+6+6+6+6+6 0+0+0+0+0+0+0+0+0+0 4 • 00090000 o+ weei ow. 0+0+0+0+0+0+0+040+0 3 • +0+0+0+0+0+0+0+0+• 2 • •4 0+0+0+0+0+0+0+.404. 1 ••••••••••+•••••+•+••••teeei•tove.++ •••••••••• 0

CUSTOMER SPECIFIED

Figure 4. Customer Specified Example

On receipt of a card deck, Signetics will CUSTOMER ID CARD #2 CUSTOMER ID CARD #5 THRU N translate the card deck to a truth table using the Signetics Computer Aided Design (CAD) COLUMN DATA COLUMN DATA facility. The truth table and font diagrams 1 C 1 C will then be sent to the customer for final 2 blank 2 blank approval. On receipt of final approval, 3-70 Customer contact 3-70 Any information desired Signetics will produce masks and proceed person name/ 71-80 blank with manufacturing. phone number Programming information can also be input 71-80 blank on TTY 7-level tape as card images. Each card image must be terminated with a carriage return-line feed. An EOT character must signify the end of the data set. CUSTOMER ID CARD #3 Customer identification cards are always COLUMN DATA labeled with a C in column 1. For customer identification, four cards are required. Any 1 C number of additional customer identification 2 blank cards are permitted. The following data 3-70 Customer address should be included: 71-80 blank

CUSTOMER ID CARD #1

COLUMN DATA CUSTOMER ID CARD #4 1 C DATA 2 blank COLUMN 3-9 2670/CP 1 C 10-14 blank 2 blank 15-70 Company name/ 3-70 Customer city, state, company part number zip code 71-80 blank 71-80 blank

Signetics 2.7 MICROPROCESSOR DIVISION JANUARY 1983 DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG) SCN2670

The following masking information cards must be included:

Mask Information Card #1: MASK INFORMATION CARD #2: Shift and Nonshift Character Translation Data Graphics Translation Data COLUMN DATA COLUMN DATA 1-9 NONSHIFT= 1-14 THIN GRAPHICS= 10 Line address in hex which outputs the first font 15-17 YES or NOW, where 0 = blank. Specifies wheth- word for nonshifted ROM fonts er graphics address hex 80 thru hex 8F will 11 select the special thin graphics font. 12 Line address in hex which outputs the second 18-19 blank font word for nonshifted ROM fonts 20-23 HOR= 13 24 The line address in hex for the horizontal seg- 14 third ments of line graphics fonts. Leave blank if col- 15 umns 15 thru 17 are NO 16 fourth 25-29 blank 17 30-45 Graphics group number 1 or 2 or 3 or 4 or blank. 18 fifth Columns 30 thru 45 correspond to line address 19 hex 0 thru hex F respectively. The group num- 20 sixth ber specified in each column will cause the 21 , graphics data generated by that group to be 22 seventh output at the corresponding line address. A 23 blank specifies no data for that address. 24 eighth 46-80 blank 25 ninth 26 MASK INFORMATION CARD #3 THRU #130: 27-29 blank 30-35 SHIFT= ROM Font Data 36 Line address in hex which outputs the first font COLUMN DATA word for shifted ROM fonts 1-2 Character address in hex (CA6 thru CAO)* 37 , 3 blank 38 second 4 S for shifted; N for nonshifted. 39 5 blank 40 third 6-8 Data for first ROM font word in hex (D9 thru DO). 41 9 blank 42 fourth 10-12 second 43 13 blank 44 fifth 14-16 third 45 17 blank 46 sixth 18-20 fourth 47 21 blank 48 seventh 22-24 fifth 49 25 blank 50 eighth 26-28 sixth 51 29 blank 52 ninth 30-32 seventh 53-59 blank 33 blank 601 0 or 1 34-36 eighth 61-64 blank 37 blank 652 0 or 1 38-40 ninth 66-80 blank 41-80 blank NOTES 1. Column 60 specifies the font truth table horizontal for- NOTE •A separate card is required for each character address mat. 0 specifies left to right printing of DO thru D9. 1 specifies D9 thru DO. hex 00 thru hex 7F. 2. Column 65 specifies the font truth table vertical printout format. 0 specifies top to bottom printing of line address hex 0 thru F. 1 specifies hex F thru 0.

2.8 Signetics MICROPROCESSOR DIVISION JANUARY 1983 DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG) SCN2670

Printouts SAMPLE CARD DECK INPUT Signetics will translate the card deck to the following printouts to be submitted to the SIGNETICS C 2670/CP1000PA 2670 TEST RUN 04/16/79 customer for approval: THIN GRAPHICS.TES 808.7 1111222233334444 NONSHIFT.1.2v3,4.5.6.7v8,9 S611E7=3.4.5.6,7,8,9,8.0 • A repeat of all customer information. 00 N 022 026 028 n32 OAA 088 088 088 070 40 N 078 084 082 nCA 088 072 002 084 078 • A separate font drawing for each of the 01 N ODC 002 00C n10 08E 088 OF8 088 08B 41 N 010 028 044 n82 082 OFE 082 082 082 128 ROM characters and 256 graphics 02 N 010 002 000 n10 08E 050 020 050 088 42 N 03E 044 084 n44 03C 044 084 044 03E fonts. The font drawings are positioned on 03 N OlE 002 ODE 002 09E 050 020 050 OBB 43 N 078 084 002 602 002 002 002 084 078 a 10 X 16 matrix as specified by the cus- 04 N DIE 002 00E 002 OlE 028 020 020 020 44 N 03E 044 084 684 084 084 084 044 03E tomers translation data. 05 N OlE 002 00E 002 06E 090 090 000 0E0 45 N GEE 002 002 002 03E 002 002 002 OFE 06 N 000 012 OlE n12 092 050 030 050 090 46 N OFE 002 002 002 03E 002 002 002 002 07 N GOE 012 00E n12 ODE 010 010 010 0E0 47 N 078 084 002 002 002 0E2 082 004 088 08 N ODE 012 00E 012 OEE 010 060 080 070 48 N 082 082 082 n82 OFE 082 082 082 082 09 N 012 012 OlE n12 012 028 022 02C 020 49 N 070 010 010 n10 010 010 510 010 07C OA N 002 002 002 nIE 0E0 010 070 010 010 4A N 0E0 040 040 n40 040 040 042 042 03C 08 N 022 022 022 n14 00B OF8 020 020 020 48 N 082 092 022 n12 00A 016 322 042 082 OC N 01E 002 00E 602 0F2 010 070 010 010 40 N 002 002 002 002 002 002 002 002 070 OD N 01C 002 002 602 07C 090 G70 050 090 4D N 082 006 OAA n92 092 082 092 082 082 OE N 010 002 00C n10 06E 090 090 090 060 4E N 082 082 086 088 092 002 002 082 082 OF N 010 002 00C n10 OEE 040 040 040 0E0 4F N 038 044 082 n82 082 082 042 044 038 10 N 00E 012 012 012 00E 010 010 010 0E0 50 N 07E 082 082 n82 07E 002 002 002 002 11 N 00E 012 012 n12 04E 060 040 040 0E0 51 N 038 044 082 n82 082 092 002 044 0E9 12 N DOE 012 012 012 06E 090 040 020 0E0 52 N 07E 082 082 782 07E 012 022 042 062 13 N 000 012 012 012 06E 080 060 080 070 53 N 078 084 002 nO4 038 040 360 042 030 14 N DOE 012 012 n12 04E 060 050 0Fe 040 54 N OFE 010 010 n10 010 010 010 CIO 010 15 N 012 016 018 n12 092 050 030 050 090 55 N 082 082 082 n82 082 082 092 044 039 16 N 01C 002 00C 010 080 050 020 020 020 56 N 082 082 082 n44 044 028 028 013 010 17 N ODE 002 00E 002 07E 090 070 090 070 57 N 082 082 082 n82 082 092 092 OAA 044 18 N 010 002 002 302 OIC 090 070 000 0.0 58 N 082 082 044 n28 010 028 044 082 082 19 N 010 002 000 302 OIE 088 008 086 088 59 N 082 082 044 026 010 010 010 010 010 18 N OOC 002 DOC n10 07E 090 070 090 070 5A N OFE 080 040 020 010 008 004 002 OFE 10 N OIE 002 00E 002 01E 0E0 010 010 0E0 5B N 070 004 004 004 004 004 004 004 07C IC N OlE 002 00E 002 0E2 010 060 080 070 50 N 000 002 004 nOB 010 020 040 080 000 ID N 010 002 01A n12 OEC 010 060 080 070 50 N 070 040 040 n40 040 040 040 040 07C IE N DOE 012 00E n0A OF2 010 060 080 070 5E N 010 038 054 010 010 010 010 010 010 IF N 012 012 012 012 OEC 010 060 080 070 5F N 000 000 008 004 OFE 004 008 000 000 20 N 000 000 000 n00 000 000 000 000 000 60 N 018 018 010 020 000 000 000 000 000 21 N 010 010 010 n10 010 000 000 010 010 61 N 000 000 000 n30 040 07C 042 042 060 22 N 028 028 028 n28 000 000 000 000 000 62 N 002 002 002 n3A 046 042 042 046 03A 23 N 028 028 OFE n28 028 028 OFT 028 028 63 N 000 000 000 030 C42 002 002 042 03C 24 N 028 OFC 028 628 07C 088 008 07E 028 64 N 040 040 040 n5C 062 042 042 062 05C 25 N 004 088 044 n20 010 008 044 082 040 65 N 000 000 000 030 042 07E 002 002 03C 26 N 00C 012 012 nOC OOC 012 082 042 OBC 66 N 030 048 008 008 03E 008 008 008 008 27 N 018 018 008 004 000 000 000 000 000 67 s 000 05C 062 042 062 05C 040 042 03C 28 N 020 010 008 nO8 008 008 000 010 020 68 N 002 002 002 n3A 046 042 042 042 042 29 N 008 010 020 n20 020 020 020 010 008 69 N 000 010 000 018 010 010 010 010 038 28 N 000 010 054 n38 OFE 038 054 010 000 60 S 000 060 040 n40 040 040 040 044 038 20 N 000 010 010 n10 OFE 010 010 010 000 68 N 002 002 002 n22 012 00A 016 022 042 2C S 000 000 000 000 000 018 018 008 004 6C N 018 010 010 010 010 010 010 010 038 20 N 000 000 000 000 OFE 000 000 000 000 60 N 000 000 000 068 096 092 092 092 092 2E N 000 000 000 600 000 000 000 018 018 6E N 000 000 000 03A 046 042 042 042 042

2F N 000 080 040 n20 010 008 004 002 000 6F N 000 000 000 03C 042 042 042 042 030 30 N 038 044 002 682 092 08A 086 044 038 70 S 000 030 046 042 046 030 002 002 002

31 N 010 018 014 n10 010 010 010 010 07C 71 S 000 050 062 042 062 050 040 040 040 32 N 070 082 080 040 038 004 002 002 OFE 72 N 000 000 000 n3A 046 002 002 002 002 33 N 070 082 080 n80 070 080 080 082 07C 73 N 000 000 000 n3C 042 00C 030 042 030 34 N 040 060 050 048 044 OFE 040 040 040 74 N 000 008 008 n10 008 008 008 048 030 35 N OFE 002 002 602 07E 080 080 082 07C 75 N ODO 000 000 042 042 042 042 062 050 36 N 078 084 002 802 07A 086 092 082 070 76 N 000 000 000 844 044 044 044 028 010 37 N OFE 080 080 n40 020 010 008 004 002 77 N 000 000 000 082 082 092 092 092 06C 38 N 070 082 082 044 038 044 082 082 07C 78 N 000 000 000 042 024 018 018 024 042 39 N 07C 082 082 002 OBC 080 080 042 03C 79 S 000 042 042 n42 062 05C 040 042 03C 38 N 000 000 000 018 018 000 000 018 01B 78 N 000 000 000 07E 020 010 008 004 07E 3B S 000 018 018 000 000 018 018 008 004 7B N 030 008 008 608 004 008 008 008 030 3C N 020 010 008 004 002 004 008 010 020 7C N 010 010 010 000 000 000 010 010 010 3D N 000 000 000 nFE 000 000 OFE 000 000 70 N 018 020 020 n20 040 020 020 020 018 3E N 008 010 020 n40 080 040 020 010 008 7E N 000 000 000 nOC 092 060 000 000 000 3F N 07C 082 082 n80 060 010 010 000 010 7F N 088 054 GAA 054 OAA 054 OAA 054 OAA

Signetics 2.9 MICROPROCESSOR DIVISION JANUARY 1983 DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG) SCN2670

ABSOLUTE MAXIMUM RATINGS1 PARAMETER RATING UNIT Supply voltage 6.0 V Operating ambient temperature2 0 to +70 ,ic Storage temperature —65 to +150 °C All voltages with respect to ground3 —0.3 to +6.0 V

DC ELECTRICAL CHARACTERISTICS TA = 0°C to 70°C, VCC = 5.0V ± 5% t,2,3

LIMITS PARAMETER TEST CONDITIONS UNIT Min Typ Max VIL Input low voltage 0 0.8 V

VIM Input high voltage 2.0 VCC V VOL Output low voltage 10 = 1.6mA 0 0.4 V VON Output high voltage 10 = —100AA 2.4 VCC V III, Input leakage current VIN = 0 to 4.25V 10 µA

SOL Output leakage current Vo = 0.4 to 4V ± 10 µA

ICC Supply current VCC = 5.25V 35 80 mA CIN Input capacitance All other pins grounded 10 pF Cow. Output capacitance 15 pF

AC CHARACTERISTICS TA = 0°C to + 70°C, Vcc= 5V -± 5%12'3'4 LIMITS PARAMETER 300ns 200ns Min Max Min Max Unit tws Strobe pulse width 100 100 ns

t LAS Line address setup 50 50 ns

t LAH Line address hold 25 25 ns

tCAS Character address setup 25 15 ns tcAH Character address hold 25 15 ns

tcA Character select access 300 200 ns

t LA Line select access 500 350 ns

tSEL Chip select delay 250 150 ns

'DES Chip deselect delay 200 125 ns tsc Special character blank/unblank time 300 200 ns NOTES 1. Parameters are valid over operating temperature range unless otherwise specif led. 2. All voltage measurements are referenced to ground. All time measurements are at the 0.8V or 2.0V level for inputs and outputs. Input levels are OV and 2.4V. 3. Typical values are at + 25°C, typical supply voltages and typical processing parameters. 4. Test conditions: CL= 100pF and 1 TTL load.

2.10 Signetics MICROPROCESSOR DIVISION JANUARY 1983

DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG) SCN2670

TIMING DIAGRAMS

1ws

LSTROBE

tLAS 1LAH

LAO-LA3

ILA

DO-D9

SCDI

CA5, CAS

DO-D9

-osc

NOTE 1. WHEN GM =1, SCD INPUT IS INACTIVE

CSTROBE

CCAS 1CAH

CAO-CA7, GM

ICA

130-09

CSTROBE

CA71

tSEL "tn- tDES

OUTPUTS TRI.STATE DO D9 OUTPUTS ACTIVE

NOTE 1. CA7 OPERATES AS OUTPUT ENABLE ONLY IN CHARACTER MODE (GM =0)

Signetics 2.11

MICROPROCESSOR DIVISION JANUARY 1983 DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG) SCN2670

.... 8 Si 0 1"2.l,,.i „ ;!! „ s!'.s killiiii :_;!2E22S°: !01S0 :;:i Fj! go:" lc' 0000

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2.12 Signetics MICROPROCESSOR DIVISION JANUARY 1983 DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG) SCN2670 1

- ' ,,,T :44,43"', EgOliNNEEERIN r i

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Signetics 2.13 MICROPROCESSOR DIVISION JANUARY 1983 DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG) SCN2670 1

?Rini PROMPRIAliiiiiiii NMNILO :I .H.7. So 3E!lig" 311111 ..2111111ii, ill" 031112 iiiiiiiiii 8 :111111!,:!Iliiiiiiii!!2!!!"11111111111111119112"911111111111111 00000 000 $ • .. L. 'olimmo6,8 .... „ . .... , II .....iiim g 111111EME ...... !Emil miiiiiiim paiiimia,E i 7 0, MEPUE1177:7411171E I1117•"1 iir7iiiiiiii 11117771111111171111111 :!INIFIRCHIP!!!! 0. iii NE1211111 PORE" 'D. niiiiiii B i82 i" ::,, "Milirintlignil ligliWNE :11"7T9oiiii;„:fliii 670 V:9; ; : MEN111111111 MEEIRIS !0_. IMRE" i

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5 G Ci' 1 § 1 ....; 8 2.14 Signetics MICROPROCESSOR DIVISION JANUARY 1983

DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG) SCN2670

Iiiiiiiii111711111111"711111111711111111111P,',E""11111117111,00,,,,

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CII* 2

Signetics 2.15 MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC) SCN2671

DESCRIPTION FEATURES PIN CONFIGURATION The Signetics 2671 Programmable Key- • Keyboard interface board and Communications Controller Contact or capacitive keyboard (PKCC) is an MOS LSI device which pro- Up to 128 keys on an 8 X 16 matrix vides a versatile keyboard encoder and an Encoded or unencoded operation HYS VCC independent full duplex asynchronous com- Four code levels per key KDRES RxD munications controller. It is intended for use Latched key option—separate KCLK TXD in microprocessor based systems and pro- depress and release codes vides an eight bit data bus interface. Programmable scan rate and debounce KC3 XTAL 2/BRCLK time KC2 XTAL 1 The keyboard encoder handles the scan- Programmable rollover modes ning, debounce, and encoding of a keyboard KCI RxC Programmable auto-repeat for matrix with a maximum of 128 keys. It pro- KCO TxC selected keys vides four levels of key encoding corre- Tone output—two frequencies KR2 A2 sponding to the separate SHIFT and CON- • Asynchronous communication Al TROL input combinations. Four keyboard KR1 interface rollover modes can be programmed includ- KRO AO Internal baud rate generator-16 rates ing provisions for up to 16 latched keys. Full duplex operation REPEAT CE Control outputs are provided for interfacing Detection of start and end of break SHIFT RD with contact or capacitive keyboards. An Programmable break generation eight bit keyboard status register provides CONTROL WR Programmable character parameters status information to the CPU. TONE INTA Auto-echo and maintenance loopback The receiver section of the communications modes KRET D7 controller accepts serial data from the RxD • Polled or Interrupt operation DO 06 Interrupt priority controller and vector pin and converts it to parallel data charac- • DI D5 ters. Simultaneously, the transmitter section generator accepts parallel data from the data bus and • Operates directly from crystal or D2 D4 outputs serialized data onto the TxD pin. Re- external clocks D3 INTR ceived data is checked for parity and fram- • TTL compatible vss XINTR ing errors, and break conditions are flagged. • Single +5 volt power supply Character lengths can be programmed as 5, • 40 pin dual in-line package TOP VIEW 6, 7, or 8 bits not including parity, start or stop bits. An internal baud rate generator APPLICATIONS (BRG) with 16 divider ratios can be used to • CRT terminals Operation Control derive the receive and/or transmit clocks. • Hard copy terminals This functional block stores configuration The BRG can accept an external clock or • Word processing systems and operation commands from the CPU and operate directly from a crystal. An eight bit • Data entry terminals generates appropriate signals to various in- communications status register provides • Small business computers ternal sections to control the overall device status information to the CPU. FUNCTIONAL DESCRIPTION operation. It contains read and write circuits to permit communications with the The PKCC has an interrupt mask register to The PKCC consists of six major sections microprocessor via the data bus and con- selectively enable certain keyboard and (see block diagram). These are the trans- tains mode registers KMR and CMR, the communications status bits to generate in- mitter, receiver, timing, operation control, command decoder, and status registers terrupts. Priority encoded interrupt keyboard encoder, and a priority encoded KSR and CSR. Details of operating modes vectoring is available. Upon receipt of an interrupt control unit. These sections com- and status information are presented in the interrupt acknowledge, an interrupt vector municate with each other via an internal Operation section of this data sheet. The will be output on DO-D7 reflecting the source data bus and an internal control bus. The register addressing is specified in table 1. of the interrupt. The interrupt source can internal data bus interfaces to the also be read from an interrupt status regis- microprocessor data bus via a bidirectional ter. data bus buffer. Timing The PKCC contains a baud rate generator (BRG) which is programmable to accept external transmit or receive clocks or to divide an external clock to perform data communications. The unit can generate 16 baud rates, any of which can be selected for full duplex operation. The external clock to the baud rate generator can be applied directly ORDERING CODE to the XTAL2 input (see figure 21) or can be generated internally by connecting a crystal COMMERCIAL RANGES across the XTAL1, XTAL2 input pins. The PACKAGES VCC= 5V ±5%, TA= 0°C to 70°C clock input is also utilized by the keyboard Ceramic DIP SCN2671AC1140 encoder section. Thus, a clock must be provided even if external transmitter and re- Plastic DIP SCN2671AC1N40 ceiver clocks are used.

2.16 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC) SCN2671

PIN DESIGNATION MNEMONIC PIN NO. TYPE NAME AND FUNCTION DO-D7 18-19, I/O Data Bus: 8-bit three-state bidirectional data bus. All data, command and status transfers are 23-26 made using this bus. DO is the least significant bit; D7 is the most significant bit.

AO-A2 31-33 I Address Lines: Used to select internal PKCC registers or commands.

RD 29 I Read Strobe: When low, gates the selected PKCC register onto the data bus if CE is also low.

WR 28 I Write Strobe: When low, gates the contents of the data bus into the selected PKCC register if CE is also low. CE 30 I Chip Enable: When high, places the DO-D7 output drivers in a three-state condition. If a is low, data transfers are enabled in conjuction with the RD and WR inputs.

INTR 22 0 Interrupt Request: Several conditions may be programmed to request an interrupt to the CPU. It is an active low open-drain output. This pin will be inactive after power on reset or a master reset command.

INTA 27 I Interrupt Acknowledge: Used to indicate that an interrupt request has been accepted by the CPU. When INTA goes low, the PKCC outputs an 8-bit address vector on DO-D7 corresponding to the highest priority interrupt currently active.

XINTR 21 I External interrupt: An active low external interrupt input to the PKCC interrupt priority resolver.

TxC 34 I/O Transmitter Clock: The function of this pin depends on bit 7 of the baud rate control register (BRR7). If external transmitter clock is selected (BRR7 = 0), it is an input for the transmitter clock. If internal transmitter clock is selected (BRR7 = 1), this pin is an output which is a multiple of the actual baud rate (1X, 16X) as selected by BRR5. The data is transmitted on the falling edge of TxC. It is an input after power on and after master reset or communications reset commands.

RxC 35 I/O Receiver Clock: The function of this pin depends on BRR6. If external receiver clock is selected (BRR6 = 0), it is an input for the receiver clock. If internal receiver clock is selected (BRR6 = 1), this pin is an output which is a multiple of the actual baud rate (1X, 16X) as selected by BRR4. The received data is sampled on the rising edge of RxC. It is an input after power on and after master reset or communications reset commands.

TxD 38 0 Transmitter Data: This output is the transmitted serial data; the least significant bit is transmitted first. This pin is high after power on reset or a reset command that affects the transmitter.

RxD 39 I Receiver Data: This input is the serial data input to the receiver. The least significant bit is received first.

XTAL 1 36,37 I Connections for Crystal: Provides an on-chip clock generator for the internal baud rate XTAL2/BRCLK generator and the keyboard interface logic. If an external clock is provided, use XTAL2 as the clock input. See figures 20 and 21.

All timing parameters such as keyboard scan time, tone frequency, and baud rate assume a clock input at the specified BRG input frequency. If this frequency is different, the timing parameters will vary proportionately.

KRO-KR2 10-8 0 Keyboard Row Scan: Decoded externally; selects one of eight rows.

KCO-KC3 7-4 0 Keyboard Column Scan: Decoded externally; selects one of 16 columns.

KRET 15 I Key Return: An active high level indicates that the key being scanned is closed.

SHIFT 12 I SHIFT Key: Active low input from the SHIFT key. The combination of SHIFT and CONTROL inputs select one of four possible codes from the internal key encoding ROM.

CONTROL 13 I CONTROL Key: Active low input from the CONTROL key. The combination of SHIFT and CONTROL inputs select one of four possible codes from the internal key encoding ROM.

Signetics 2.17 MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC) SCN2671

PIN DESIGNATION (Cont.)

REPEAT 11 I REPEAT Key: Active low input from the REPEAT key. Causes the key depression currently active to be repeated at a rate of approximately 15 times per second.

KCLK 3 0 Keyboard Clock: High frequency (approximately 400 kHz) output used to scan capacitive keyboards.

KDRES 2 0 Key Detect Reset: Resets the analog detector before scanning a key. Used for capacitive keyboards.

HYS 1 0 Hysteresis Output: Sent to the analog detector for capacitive keyboard applications. A low indicates the key currently being scanned has been recognized on previous scan cycles.

TONE 14 0 Square Wave Output: Used for tone generation.

VCC 40 I +5V power supply.

VSS 20 I Ground.

Receiver scanning signals for a matrix keyboard. Key OPERATION The receiver accepts serial data on the RxD depressions are detected on the KRET in- Keyboard Encoder pin, converts this serial input to parallel for- put. The debounced and verified key codes The keyboard is continuously scanned by mat, checks for break conditions, framing (or matrix addresses) are loaded into the KCO-KC3 and KRO-KR2 which are decoded and parity errors, and loads an "assembled" key holding register for access by the CPU. externally to handle 128 possible keys (see character in the receive holding register for Figures 1 and 2 illustrate the PKCC interface figures 1 and 2). KCO-KC3 select one of 16 access by the CPU. to contact and capacitive keyboards, re- columns and KRO-KR2 multiplex the eight spectively. row return lines into the KRET pin. Transmitter Interrupt Control Debouncing is accomplished by remember- The transmitter accepts parallel data loading a 1 state at the KRET pin when a key is The interrupt controller unit contains a soft- ed by the CPU into the transmit holding reg- being addressed and verifying it one scan ware programmable interrupt mask register ister and converts it to a serial bit stream later. Once the key is verified, a key code is which selectively enables status conditions framed by the start bit, calculated parity bit loaded into the keyboard data register from the keyboard encoder and communica- (if specified), and atop bit(s). The compos- (KDR). If the keyboard holding register tion controller to generate interrupts. The ite serial stream of data is transmitted on (KHR) is empty, the contents of the KDR will interrupts are priority encoded and individ- the TxD output pin. be transferred to the KHR immediately; if the ually generate an eight bit vector which is KHR is full (i.e., the CPU has not read the Keyboard Encoder output on the data bus in response to a CPU previous key code), the transfer will be held The keyboard encoder provides encoded interrupt acknowledge on the INTA input pin. off until the KHR is read. The data transfer to the KHR causes keyboard data ready (KRDY) to be set in the keyboard status register. Table 1 2671 REGISTER ADDRESSING For capacitive keyboards, the high frequency output KCLK can be used to gate the Uff A2 Al AO RD /WR FUNCTION column scan to the keyboard (see figure 2). The key detector reset (KDRES) output 1 X X XX Three-state data bus resets the analog detector prior to scanning 0 0 0 0 WR Reset command (see table 6) each key location. The output from the ana- 0 0 0 0 14-15 Read interrupt status register (ISR) log multiplexer is sensed and then latched in 0 0 0 1 AT), WR Read/write communications mode register the analog detector. The HYS output con- (CMR) trols the sense level. A 0 will lower the 0 0 1 0 WR Write transmit holding register (TxHR) sense level causing hysteresis, and a 1 will 0 0 1 0 RD Read receiver holding register (RxHR) raise the sense level with no hysteresis. 0 0 1 1 WR Write baud rate mode register (BRR) 0 0 1 1 RD Read communications status register (CSR) The REPEAT input enables the keyboard 0 1 0 0 RD,WR Read/write interrupt mask register (IMR) logic to recognize any key repeatedly, 15 0 1 0 1 RD, WR Read/ write keyboard mode register (KMR) times per second. Additionally, certain keys 0 1 1 0 RD Read keyboard holding register (KHR) can be programmed to repeat automatically 0 1 1 1 N5 Read keyboard status register (KSR) if depressed for more than one-half second. 0 1 1 1 WR Miscellaneous commands (see description) A square wave is output on the TONE pin NOTE when the CPU issues a ring tone command X .. don't care to the PKCC.

2.18 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC) SCN2671

BLOCK DIAGRAM

DATA REPEAT DBO-DB7 BUS BUFFER KEYBOARD ENCODER KCLK

MODE & TIMING KDRES CONTROL HYS OPERATION CONTROL RD CMR WR KMR KCO-KC3 CE KEYBOARD CSR SCANNER & KRET KSR ENCODER/ DECODER AO-A2 COMMAND DECODER KRO-KR2

SHIFT 4 x 128 x8 READ-ONLY MEMORY CONTROL XINTR INTERUPT CONTROL & ... VECTOR GENERATOR INTA

INTR KEYBOARD IMR DATA REGISTER

KEY HOLDING VCC REGISTER GND

TONE TONE GENERATOR TIMING

BAUD RATE GENERATOR TxC xx

RxC -• BAUD RATE CONTROL TRANSMITTER REGISTER

TRANSMIT HOLDING REGISTER

TRANSMIT - TxD SHIFT REGISTER

XTAL1/BRCLK

XTAL2 RECEIVER

INTERRUPTS RECEIVE HOLDING REGISTER TIMING RECEIVE CONTROLS SHIFT REGISTER Rx0

Signetics 2.19 MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC) SCN2671

the code in the KDR is transferred to the KHR and the KRDY status bit is set (KSRO). KRET N-Key Rollover With Latched Keys: This mode is the same as regular N-key KR2-KRO DIGITAL MULTIPLEXER rollover, except that the keys which are 8 ROWS assigned to row 0 of the keyboard matrix PKCC (KR2-KRO = 000) produce a code both when depressed and when released. The codes are independent of the states of the inputs at SHIFT and CONTROL. If one 1 OF 16 16 KC3-KCO DECODE COLUMNS or more of the latched keys are depressed when the keyboard is enabled (after a keyboard reset), the corre- CONTACT sponding codes will be sent out as the KEYBOARD keys are scanned and debounced. Note MATRIX that simultaneous latched keys will not set KERR (KSR1) and that latched keys will not be auto-repeat and will not be Figure 1. Contact Keyboard Interface affected by the REPEAT input. Two-Key Rollover: The first key code is loaded into the KDR immediately and the second code is loaded only after the first key is released. Simultaneous keys will ANALOG set KERR (KSR1). If three or more keys DETECTOR remain closed at any given time, the KRET KERR bit will also be set. All keys must HYS then be released before the next KRET

KDRES will be processed. Two-Key Inhibit: All keys must be re- KR2-KRO ANALOG MULTIPLEXER leased between keystrokes; otherwise, KERR (KSR1) will be set.

PKCC 8 ROWS Bit KMR4 specifies the key encoding mode. Each key is assigned four 8-bit codes, corresponding to the states of the SHIFT and CONTROL inputs. If the encoded mode is KCLK programmed, the row/column address of 1 OF 16 the detected key is used to load one of the DECODE 16 COLUMNS KC3-KCO four key codes into the KDR. See table 2 for key code assignments. If the non-encoded mode is programmed, the row /column ad- CAPACITIVE KEYBOARD dress is loaded directly into the KDR with MATRIX the following format:

Figure 2. Capacitive Keyboard Interface KDR 7 6 5 4 3 2 0

Keyboard Mode Register Bits KMR6-KMR5 select the rollover modes Operating modes are selected by program- for keyboard processing: KR2, KR 1, KRO ming the keyboard mode register (KMR), N-key Rollover: In this mode, the code KC3, KC2, KC1 , KCO whose format is illustrated in figure 3. corresponding to each key depression is loaded into the KDR as soon as that key "0" for momentary keys Bit KMR7 is used for testing the device. For is debounced, independent of the re- "1" for latched keys release normal operation, this bit should always be lease of other keys. Two or more clo- "0" for latched keys depress written to a 0. sures occurring within one scan cycle are considered to be simultaneous, which will set keyboard error in the keyboard status register (KSR1). As soon as the keyboard holding register is empty,

2.20 Signetics MICROPROCESSOR DIVISION

PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC) SCN2671

Table 2 STANDARD KEY CODES (HEX)

ROW (KR2-KRO) COLUMN (KC3-KCO) 0 1 2 3 4 5 6 7 El) CO 1B ESC 09 HT 1F US 1A SUB 30 0 2B + 0 FO DO 1B ESC 09 HT 1F US lA SUB 30 0 3B EO CO 1B ESC 09 • HT iF US 5A Z 30 0 2B + FO DO 1B ESC 09 • HT 1F US 7A z 30 0 36 ;

E1 C1 21 I II DC1 SiSOH01 18 CAN 3D = 2A • 1 F1 D1 31 1 11 DC1 01 SOH 18 CAN 2D — 3A : E1 C1 21 I 51 0 41 A 58 X 30 • = 2A • F1 DI 31 1 71 q 61 a 78 x 2D • — 3A :

E2 C2 22 ETB 13 DC3 03 ETX 1E RS 1F US 2 F2 D2 32 2 17 ETB 13 DC3 03 ETX 1E RS 1F US E2 C2 22 v 57 W 53 S 43 C 7E ts. 7F • DEL F2 D2 32 2 77 w 73 s 63 c 5E $ 5F • — E3 C3 23 # 05 ENO 04 EOT 16 SYN 1C FS 1B ESC 3 F3 D3 33 3 05 ENO 04 EOT 16 SYN 1C FS 1B ESC E3 C3 23 # 45 E 44 D 56 V 7C : 7B [ F3 03 33 3 65 e 64 d 76 v 5C \ 5B [

E4 C4 24 $ 12 DC2 06 ACK 02 STX 08 BS 1D GS 4 F4 D4 34 4 12 DC2 06 ACK 02 SIX 08 BS 1D GS E4 C4 24 $ 52 R 46 F 42 B 08 • BS 7D } F4 D4 34 4 72 r 66 f 62 b 08 • BS 5D I

E5 C5 25 0/0 14 DC4 07 BEL OE SO 10 DLE 08 BS 5 F5 05 35 5 14 DC4 07 BEL OE SO 10 OLE 08 BS E5 CS 25 % 54 T 47 G 4E N 50 P 08 BS F5 D5 35 5 74 t 67 g 6E n 70 p 08 • BS

E6 C6 26 & 19 EM 08 BS OD CR 00 NUL 09 HT 6 F6 D6 36 6 19 EM 08 BS OD CR 00 NUL 09 HT E6 C6 26 & 59 V 48 H 4D M 60 ' 09 • HT F6 D6 36 6 79 y 68 h 6D m 40 @ 09 • HT

E7 C7 27 ' 15 NAK OA LF 3C < 7F DEL 20 SP 7 F7 D7 37 7 15 NAK OA LF 2C , 7F DEL 20 SP E7 C7 27 ' 55 U 4A J 3C < 7F DEL 20 • SP F7 D7 37 7 75 u 6A j 2C , 7F DEL 20 • SP E8 C8 28 ( 09 HT OB VT 3E > OA LF 013 VT 8 F8 D8 38 8 09 HT OB VT 2E . OA LF 06 VT E8 C8 28 ( 49 I 48 K 3E > OA LF OB • VT F8 D8 38 8 69 i 6B k 2E OA LF OB • VT

E9 C9 29 ) OF SI OC FF 3F ? OD CR OA LF 9 F9 D9 39 9 OF SI OC FF 2F / OD CR OA LF E9 C9 29 ) 4F 0 4C L 3F ? OD CR OA • LF F9 D9 39 9 6F o 6C I 2F / OD CR OA • LF EA CA 37 7 34 4 31 30 0 AO A6 A FA DA 37 7 34 4 31 1 30 0 BO f36 EA CA 37 7 34 4 31 30 0 AO A6 FA DA 37 7 34 4 31 1 30 0 BO f36 EB CB 38 8 35 5 32 2 2E . Al A7 B FB DB 38 8 35 5 32 2 2E . B1 B7 EB CB 38 8 35 5 32 2 2E . Al A7 FB DB 38 8 35 5 32 2 2E . B1 B7 EC CC 39 9 36 6 33 3 BF A2 A8 C FC DC 39 9 36 6 33 3 AF B2 88 EC CC 39 9 36 6 33 3 9F A2 A8 FC DC 39 9 36 6 33 3 8F B2 B8 ED CD 90 93 82 95 A3 A9 D FD DD 90 93 82 95 83 B9 ED CD 90 93 82 • 95 A3 • A9 • FD DD 90 93 82 • 95 B3 • B9 • EE CE 91 80 84 81 A4 AA E FE DE 91 80 84 B4 BA EE CE 91 80 • 84 81 • A4 • AA • FE DE 91 80 • 84 81 • B4 • BA • EF CF 92 94 83 96 A5 AB F FF DF 92 94 83 96 B5 BB EF CF 92 94 83 • 96 A5 • AB • FF DF 92 94 83 • 96 B5 • BB "

CONTROL XX YYY SHIFT (Pin 12 = 0) (Pin 13 = 0) XX YYY XX • YYY Latched key code for release This row contains the latched XX • YYY Latched key code for depress keys when that mode is selected (KMR6, KMR5 = 00).

Key codes in hex ASCII equivalent (if any) Indicates Auto-Repeat keys Signetics 2.21 MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC) SCN2671

KMR 7 6 5 4 3 2 0

Test mode Tone select 1 = Enable 0 = 1kHz 0 = Disable 1 = 2kHz

Rollover modes Key 00 = N-key with MATRIX SCAN SIZE latched keys KMR2 KMR1 TIME 01 = N-Key 0 0 128 toms 10 = Two key 0 128 2.5ms 11 = Two key 0 80 6.4ms inhibit 80 1.6ms

0 = Encoded Auto repeat keyboard 0 = Disable 1 = Non encoded 1 = Enable keyboard

Figure 3. Keyboard Mode Register Format

Bit KMR3 enables the auto-repeat mode. In sample. The status bits are the comple- interrupt and is cleared by the reset com- this mode, if a key that is programmed for ments of the input levels. mand with D2 = 1. auto-repeat is depressed for longer than KSR5 reflects the state of the internal shift Keyboard error (KSR1) is set when the oper- one-half second, the key code will be load- lock flag which is controlled by the ator depresses more keys than are allowed ed into the KDR approximately 15 times per set/reset shift lock commands. in the selected rollover mode, or when keys second until that key is released. Only the are depressed simultaneously (within one non-control key codes will auto-repeat, i.e. KSR3 indicates that the keyboard controller scan cycle). This bit can be specified (by CONTROL = 1. Table 2 specifies the auto- is enabled. It is controlled by the set/clear IMR3) to generate an interrupt and is repeat keys. keyboard enable command. cleared by the reset command with D1 = 1. Keyboard overrun (KSR2) is set when both KMR2 and KMR1 select the key matrix size Keyboard data ready (KSRO) is set when the KHR and KDR are full and a third key is and debounce time (scan rate). The key- the key code or address is transferred from validated. The original content of the KHR is board row outputs (KR2, KR1, KRO) always the KDR to the KHR. This bit can be speci- preserved and the content of the KDR is scan from 0 to 7. The column outputs (KC3, fied (by IMR2) to generate an interrupt. It is overwritten with the new key code. This bit KC2, KC1, KCO) scan from 0 to 15 fora 128 cleared when the CPU reads the KHR. key matrix and from 0 to 9 for an 80 key can be specified (by IMR1) to generate an matrix.

KMRO selects between a 1kHz and 2kHz frequency to be output on the TONE pin in re- 7 5 4 3 0 sponse to a ring tone command. KSR

Keyboard Status Register CONTROL L KRDY The keyboard status register (KSR) provides operational feedback to the CPU. Its format is illustrated in figure 4. SHIFT KERR

KSR7, 6 and 4 reflect the state of the inputs SHIFT LOCK KOVR at the corresponding pins. CONTROL and SHIFT are latched at the time the key is Keyboard Enabled accepted. As the verified codes are loaded REPEAT into the KDR, the corresponding states of CONTROL and SHIFT are loaded into the Figure 4. Keyboard Status Register Format KSR. REPEAT is updated on every matrix

2.22 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC) SCN2671

Communications Controller sent first. Following the transmission of the affect assembly of a received character, the The communications controller section of stop bits, if a new character is not available CMR must be updated within n —1 bit times the PKCC comprises a full duplex asynchro- in the transmit holding register (TxHR), the of the receipt of that character's start bit. To nous receiver/transmitter (UART) with a TxD output remains high and the TxEMT bit affect a transmitted character, the CMR baud rate generator. Registers associated in the CSR will be set to 1. Transmission must be updated within n —1 bit times of with these elements are the communica- resumes and the TxEMT bit is cleared when transmitting that character's start bit. (n tions mode register (CMR), the baud rate the CPU loads a new character into the the smaller of the new and old character control register (BRR), and the communica- TxHR. The transmitter can be forced to send lengths). a continous low condition by a transmit tions status register (CSR). The UART can operate in one of four modes, break command. as illustrated in figure 6. The operating Receiver If the transmitter is disabled, it continues modes are selected by bits CMR7 and The receiver accepts serial data on the RxD operating until the character currently being CMR6, which should only be changed when pin, converts the serial input to parallel for- transmitted is completely sent out. both the transmitter and receiver are dis- mat, checks for start bit, stop bit, parity bit abled. CMR7-CMR6 = 00 is the normal (if any), or break condition, and presents the Communication Mode Register mode, with the transmitter and receiver op- assembled character to the CPU. The re- Figure 5 illustrates the bit format of the erating independently. CMR7-CMR6 = 01 ceiver looks for a high to low (mark to CMR, which controls the operational mode places the UART in the automatic echo space) transition of the start bit on the RxD of the communications controller and the mode, which automatically retransmits the input pin. If a transition is detected, the state character parameters. received data. The following conditions are true while in automatic echo mode: of the RxD pin is sampled again after a delay Bits CMR1-CMR0 select a character length 1. Data assembled by the receiver is auto- of one half of the bit time. If RxD is then high, of 5, 6, 7, or 8 bits. The character length matically placed in the transmit holding the start bit is invalid and the search for a does not include the parity, start, or stop register and retransmitted on the TxD valid start bit begins again. If RxD is still low, bits. a valid start bit is assumed and the receiver output. continues to sample the input at one bit time CMR2 selects the transmitted character 2. The receive clock is used for the trans- intervals at the theoretical center of the bit, framing as one or two stop bits. The receiver mitter. until the proper number of data bits and the always checks for one stop bit. 3. The receiver must be enabled, but the transmitter need not be enabled. parity bit (if any) have been assembled, and The parity format is selected by bits CMR4 4. Status bit TxRDY is not set. TxEMT oper- one stop bit has been detected. The least and CMR3. If parity or force parity is select- ates normally. significant bit is received first. The data is ed, a parity bit is added to the transmitted 5. The received parity is checked, but is not then transferred to the receive holding reg- character and the receiver performs a parity regenerated for transmission, i.e., trans- ister (RxHR) and the RxRDY bit in the CSR is check on incoming data. CMR5 selects odd mitted parity bit is as received. set to a 1. If the character length is less than or even parity and determines the polarity of 6. Only the first character of a break condi- eight bits, the most significant unused bits in the parity bit in the force parity mode. the RxHR are set to zero. tion is echoed; the TxD output will go high The bits in the mode register affecting char- until the next received character is as- After the stop bit is detected, the receiver acter assembly and disassembly (CMR5- sembled. will immediately look for the next start bit. CMRO) can be changed dynamically and af- 7. CPU to receiver communication contin- However, if a non-zero character was re- fect the characters currently being assem- ues normally, but the CPU to transmitter ceived without a stop bit (i.e. framing error) bled in RxSR and transmitted by TxSR. To link is disabled. and RxD remains low for one half of the bit period after the stop bit was sampled, then the space is interpreted as a start bit.

The parity error, framing error and overrun 7 6 5 4 3 2 1 0 error (if any) are strobed into the CSR at the CMR received character boundary. If a break condition is detected (RxD is low for the entire character including the stop bit) only one Operating mode I—Character length character consisting of all zeros will be 00 = Normal 00 = 8 transferred to the RxHR and the received 01 = Auto echo 01 = 5 break bit in the CSR is set to 1 (RxRDY is not 10 = Local loopback 10 = 6 set when a break is received ). The RxD 11 = Remote loopback 11 = 7 input must return to a high condition for one bit time before a search for the next start bit Parity 0 — Two stop bits begins. 0 = Odd /force 0 1 = One stop bit 1 = Even/force 1 Parity mode Transmitter 00 = With parity The transmitter accepts parallel data from 01 = Force parity the CPU and converts it to a serial bit stream 10 = No parity on the TxD output pin. It automatically sends 11 = Not allowed a start bit followed by the data bits, an optional parity bit, and the programmed num- Figure 5. Communications Mode Register Format ber of stop bits. The least significant bit is Signetics 2.23

MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC) SCN2671

Two diagnostic modes can also be configured. In local loopback mode (CMR7- CMR6 = 10): 1. The transmitter output is internally connected to the receiver input. 2. The transmit clock is used for the receiv-

TRANSMITTER er. MICRO. 3. The TxD output is held high. EXTERNAL COMPUTER 4. The RxD input is ignored. DEVICE SYSTEM 5. The transmitter must be enabled, but the RECEIVER receiver need not be enabled. 6. CPU to transmitter and receiver communications continue normally. (a) The second diagnostic mode is the remote loopback mode (CMR7-CMR6 = 11). In this mode: 1. Data assembled by the receiver is auto- TRANSMITTER matically placed in the transmit holding

MICRO. EXTERNAL register and retransmitted on the TxD COMPUTER DEVICE SYSTEM output. 2. The receive clock is used for the trans- RECEIVER mitter. 3. No data is sent to the local CPU, but the error status conditions (parity and fram- (b) ing) are set if required. 4. The received parity is checked, but is not regenerated for transmission, i.e., transmitted parity bit is as received. 5. The receiver must be enabled, but the TRANSMITTER transmitter need not be enabled. MICRO. EXTERNAL COMPUTER DEVICE SYSTEM Baud Rate Control Register RECEIVER The baud rate control register (BRR) controls the frequency generated by the baud rate generator (BRG) and the clock source (c) used by the receiver and transmitter. Its format is illustrated in figure 7.

BRR3-BRRO select one of sixteen frequencies to be generated by the BRG. See table TRANSMITTER 3.

MICRO• EXTERNAL COMPUTER BRR7 and BRR6 select the source of the DEVICE SYSTEM transmit and receive clocks. If external RECEIVER clocks are chosen, (BRR7 = 0 or BRR6 = 0), then the clock rate factor is determined by BRR5 and BRR4. The external clock in- (d) pugs) should be the desired baud rate multiplied by the clock rate factor.

(a) Normal operating mode. If internal clock(s) are specified, (BRR7 = 1 (b) Automatic echo mode. or BRR6 = 1), the clock is supplied by the (c) Local loopback mode. internal baud rate generator at the selected (d) Remote loopback mode. baud rate. The clock rate factor for internally generated clocks is always 16. Pins 35 and 34 become outputs for transmit or receive clocks, respectively. See table 4 for Figure 6. Operating Modes of the 2671 UART the description and selection of these outputs.

2.24 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC) SCN2671

BRR 7 5 4 3 2 1 0

Tx Clock source —1 Baud rate select—See table 3 0 = External 1 = Internal (BRG) Rx Clock source Clock rate factor for external 0 = External clocks 1 = Internal (BRG) 00 = 16X 01 = 32X 10 = 64X 11 = 1X For internal clocks these bits specify the output frequency on pin 34 and pin 35. See table 4.

Figure 7. Baud Rate Control Register Format

Table 3 BAUD RATE GENERATOR CHARACTERISTICS (BRCLK= 4.9152MHz) ACTUAL BAUD FREQUENCY PERCENT BRR3-0 RATE 16X CLOCK ERROR DIVISOR 0000 50 0.8 kHz — 6144 0001 110 1.7598 —0.01 2793 0010 134.5 2.152 — 2284 0011 150 2.4 — 2048 0100 200 3.2 — 1536 0101 300 4.8 — 1024 0110 600 9.6 — 512 0111 1050 16.8329 +0.20 292 1000 1200 19.2 — 256 1001 1800 28.7438 —0.20 171 1010 2000 31.9168 —0.26 154 1011 2400 38.4 — 128 1100 4800 76.8 — 64 1101 9600 153.6 — 32 1110 19200 307.2 — 16 1111 38400 614.4 — 8

Signetics 2.25

MICROPROCESSOR DIVISION JANUARY 1983

PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC) SCN2671

Table 4 BAUD RATE CONTROL REGISTER CLOCK SOURCE PIN FUNCTIONS BRR7- PIN PIN BRR3-BRRO BRR4 TxC RxC 34 35 BAUD RATE SELECTION 00' ' E E TxC RxC The baud rates are 01" E I TxC 1X listed in table 3. 10' • I E 16X RxC 1100 I I 1X 1X 1101 I I 1X 16X 1110 I I 16X 1X 1111 I I 16X 16X

NOTES 1. • • = Clock rate factor for external clocks: 00 = 16X 01 = 32X 10 = 64X 11 = 1X 2. E = External clock. 3. I = Internal clock (BRG). 4. 1X and 16X are clock outputs at 1 or 18 times the actual baud rate. For receive, the 1X output is the actual data sample clock. 5. BRR7-BRR6 = 01 or 10 not permitted in automatic echo or remote loopback modes unless BRR5-BRR4 = 00.

Communications Status Register when RxD returns to a high state for at least tus register (ISR) which can be enabled to one bit time. generate an active low interrupt request on Figure 8 illustrates the bit format of the com- the INTR output. The eight interrupt condi- Receiver overrun (CSR5) indicates that the munications status register (CSR), which tions in the ISR are individually enabled by previous character in the RxHR has not been provides UART status to the CPU. writing a 1 into the corresponding bit of the read by the CPU and that a new character interrupt mask register (IMR). Receiver ready (CSRO) indicates that a re- has been loaded into the RxHR. This bit is ceived character is assembled and trans- cleared by a reset command with D3 = 1. Each of the interrupt conditions is assigned ferred to the RxHR and is ready to be read a priority and a vector. When an enabled ISR Framing error (CSR6) indicates that the by the CPU. This bit can be specified (by bit is set, the 2671 asserts the INTR output. stop bit has not been detected. The stop bit IMRO) to generate an interrupt and is reset If the CPU activates the INTA input, the 2671 check is made in the middle of the first stop by reading the RxHR. responds by placing the corresponding 8-bit bit position. This bit is cleared by a reset vector on the data bus (D7-D0). If multiple Transmitter ready (CSR1) indicates that the command with D3 = 1. TxHR is empty and ready to be loaded with a interrupts are pending, the vector corre- character. This bit will be cleared when the Parity error (CSR7) indicates that a charac- sponds to the condition with the highest pri- TxHR is loaded and has not yet transferred ter was received with incorrect parity when ority. The interrupt will persist until all pend- the character to the transmit shift register 'with parity' or 'force parity' is enabled. This ing interrupt conditions are cleared. bit is cleared by a reset command with D3 = (TxSR). TxRDY is reset when the transmitter The ISR can also be polled by reading at 1. is disabled. It will be set when the transmit- address A2-A0 = 000. All pending interrupt ter is enabled, provided that no data was Interrupt Controller conditions which are enabled by the IMR will loaded into the TxHR during the time the The 2671 contains a maskable interrupt sta- be read independent of priority. transmitter was disabled. This bit can be specified (by IMR7) to generate an interrupt. Transmitter empty (CSR2) indicates that the transmitter has underrun, i.e., both the TxHR and TxSR are empty. This bit can only be set CSR 7 5 4 3 0 after transmission of at least one character, and is cleared when the TxHR is loaded by the CPU. TxEMT is reset when the transmit- Parity error L RxRDY ter is disabled. This bit can be specified (by IMR6) to generate an interrupt. Framing error TxRDY CSR3 will be set when the PKCC receives a command to transmit a break. This bit will be Overrun error TxEMT cleared after the break is completed. Received break (CSR4) indicates that an all Received break Transmit break zero character of the programmed length has been received without a stop bit. Breaks originating in the middle of a received char- Figure 8. Communications Status Register Format acter can be detected. This bit is cleared

2.26 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC) SCN2671

The bit assignments of the ISR and IMR and A reset command with D7-DO = 111XXXX1 the break which can be extended indefinite- corresponding vectors and priorities are is a master reset for the 2671. This com- ly (by 200ms or one character time incre- listed in table 5. mand must be given following a power on ments) by reasserting the command in re- condition to release the internal power on sponse to TxRDY. Note that these COMMANDS reset latch which deactivates the 2671 on commands reset TxRDY. When a transmit In addition to the control exercised by pro- power up. break command is asserted, CSR3 will be gramming of the PKCC control registers, set. This bit will be cleared after the break is several functions can be performed by ex- completed. ecuting command operations. There are two Miscellaneous Commands classes of commands which are initiated by The miscellaneous command format is illus- The ring tone commands cause the tone writing to the 2871 at address A2-A0 = 000 trated in figure 10. generator to output a square wave on the (reset command) and address A2-A0 = 111 TONE output . The tone durations are speci- (miscellaneous commands). Individual com- The transmit break commands force a break fied by the commands: mands are specified by the bit pattern on the (steady low output) on the TxD pin immedi- data bus (D7-D0). ately or after the character in the TxSR (if Ring tone short = 25ms any) is transmitted. A timed break lasts for Ring tone long = 100ms Reset Commands approximately 200ms, and a character The reset command bit format is illustrated break lasts for one character time including The tone frequency is either 1kHz or 2kHz, in figure 9 and the detail command descrip- parity and stop bit time. In either case, as specified by KMRO. tions are given in table 6. TxRDY (CSR1) will be set at the beginning of

TABLE 5 INTERRUPT MASK REGISTER (IMR) AND INTERRUPT STATUS REGISTER (ISR) BIT IN INTERRUPT VECTOR ON D7-DO IMR/ISR CONDITION PRIORITY BINARY I HEX CONDITION RESET BY: IMRO/ISRO RxRDY 1 11001111 CF Read RxHR IMR1/ISR1 KOVR 2 11010111 D7 Reset CMD (D2 = 1) IMR2/ISR2 KRDY 3 11011111 DF Read KHR IMR3 / ISR3 KERR 4 11100111 E7 Reset CMD (D1 = 1) IMR4/ISR4 XINT1 5 11101111 EF External IMR5/ISR5 ABREAK2 6 11110111 F7 Reset CMD (D4 = 1) IMR6 / ISR6 TxEMT 7 11000111 C7 Load TxHR IMR7 / ISR7 TxRDY 8 11000111 C7 Load TxHR

NOTES: 1. XINT is an Input from an external interrupt source, active low (pin 21). 2. ABREAK refers to the change of a received break condition.

7 6 5 4 3 2 0

00X No effect Keyboard reset 010 Set RxE 011 Reset RxE KERR reset 100 Set TxE 101 Reset TxE 110 Set TxE and RxE KOVR reset 111 Communications reset

Break detect change reset Communications error reset

Figure 9. Reset Command Format

Signetics 2.27 MICROPROCESSOR DIVISION JANUARY 1983

PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC) SCN2671

Table 6 RESET COMMAND DESCRIPTION COMMAND RESETS COMMENTS Keyboard reset KMR7-KMRO The keyboard controller is reset, ignoring the input at KSR5, KSR3-KSRO KRET. IMR3-IMR1 KERR reset KSR 1 Keyboard error status bit reset. KOVR reset KSR2 Keyboard overrun status bit reset. Communications error reset CSR7-CSR5 Resets the receiver overrun, parity, and framing error status bits. Break detect change reset ISR5 Resets the break detect change bit in the interrupt status register. Set RxE See note. Enables receiver operation. Reset RxE CSR7-CSR4, CSRO Disables the receiver. See note. Set TxE See note. Enables transmitter operation. Reset TxE CSR3-CSR 1 Disables the transmitter. Sets the TxD output to a 1 after See note. transmitting the character in TxSR. Communications reset CMR, CSR, BRR, Resets the communication controller. The RxD input is TxE, RxE, IMR7-IMR5, IMRO ignored and the TxD output is set to a 1. Master reset CMR, CSR, BRR, Resets the keyboard and communication controllers. In- TxE, RxE, KMR, puts at KRET and RxD are ignored and the TxD output is KSR5, KSR3-KSRO, set to a 1. IMR7-IMRO. Releases the internally latched power on reset. NOTE Command does not affect the CMR or the BRR.

The set/clear shift lock commands control command, and the current state of the key- • Key codes the state of the internal shift lock flip flop. board (key depressions and latched key • Auto-repeat keys When shift lock is set, the keyboard control- states) is preserved internally. When the • Scan times, tone frequency, and tone ler encodes all key depressions as if the keyboard is subsequently enabled, key duration SHIFT input was asserted. The state of the processing resumes, old and new keys are • Baud rates shift lock flip flop is reflected in KSR5. debounced, and latched keys are encoded if • Interrupt vectors there has been a change in their state. The set keyboard enable command enables Consult your local Signetics representative the keyboard controller and sets KSR3 in MASK PROGRAMMABLE OPTIONS for costs, minimum quantities, and data sub- the keyboard status register. The clear key- Characteristics of certain portions of the mission requirements for customized ver- board enable command resets KSR3 and PKCC are internally programmed by means sions of the PKCC. disables key processing at the KRET input. of a read only memory. The items which can The keyboard controller is not reset by this be programmed are:

7 6 5 4 3 0

Clear keyboard enable L Transmit character break

Set keyboard enable Transmit timed break

Clear shift lock Ring tone short

Set shift lock Ring tone long

Figure 10. Miscellaneous Commands Format

2.28 Signetics MICROPROCESSOR DIVISION JANUARY 1983

PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC) SCN2671

ABSOLUTE MAXIMUM RATINGS1

PARAMETER RATING UNIT

Operating ambient temperature2 0 to +70 °C Storage temperature —65 to +150 °C All voltages with respect to ground3 —0.5 to +6.0 V

DC ELECTRICAL CHARACTERISTICS TA= 0 °C to + 70°C, Vcc= 5V -± 5% 4'56 LIMITS PARAMETER TEST CONDITIONS Unit Min Typ Max VIL Input low voltage 0.8 V VIH Input high voltage XTAL1, XTAL2 4.0 V All other inputs 2.0 V VOL Output low voltage IOL = 1.6mA 0.4 V VOH Output high voltage (except INTR) IOH= — 100µA 2.4 V IR_ Input leakage current VIN = 0 to Voo XTAL2/BRCLK — 100 µA All other inputs — 10 10 µA ILL Data bus 3-state leakage current Vo= 0 to Vcc — 10 10 µA ICC Power supply current 150 mA

AC ELECTRICAL CHARACTERISTICS TA = 0 ° to + 70°C, Vcc = 5V th- 5% 456

LIMITS PARAMETER TEST CONDITIONS UNIT Min Typ Max Read timing? tAS Address setup to RD 50 ns tCS CE setup to RD 50 ns tpw RD pulse width 250 nu tAH Address hold from RD 20 ns tCH CE hold from RD 0 nu tDD Data delay for read CL = 150pF 200 ns tDF Data bus floating time for read CL = 150pF 10 100 ns tAD Access delay from any read to next read or write 250 ns Write timing8 tAS Address setup to WR 50 ns ICS CE setup to WR 50 ns tpw WR pulse width 250 ns tAH Address hold from WR 20 ns ICH CE hold from WR 0 ns IDS Data setup 100 ns IDH Data hold 10 ns IAD Access delay from any write to next read or write 250 ns IAD Access delay from reset command to next read or write 1.0 As

NOTES 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent 4 Parameters are valid over operating temperature range unless otherwise specified. damage to the device. This is stress rating only and functional operation of the device 5 All voltage measurements are referenced to ground (VSs). All input signals swing at these or al any other condition above those indicated in the operation section of this between 0.4V and 2.4V with a transition time of 20ns maximum and time measurements specification is not implied. are referenced at input voltages of 0.8V, 2.0V and at output voltages of 0.8V, 2.0V as 2. For operating et elevated temperatures, the device must be derated based on +150°C appropriate, unless otherwise specified. maximum junction temperature. 6. Typical values are at +25°C, typical supply voltages and typical processing param- 3. This product includes circuitry specifically designed for the protection of its internal eters. devices from damaging effects of excessive static charge. Nonetheless, it is suggest- 7 See figure 11. ed that conventional precautions be taken to avoid applying any voltages larger than 8 See figure 12. the rated maxima.

Signetics 2.29 MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC) SCN2671

AC ELECTRICAL CHARACTERISTICS (Cont.) LIMITS PARAMETER TEST CONDITIONS UNIT Min Typ Max

Interrupt acknowledge timing9 tpWl INTA pulse width 300 ns tDDI Data delay time for interrupt vector CL = 150pF 250 ns tDFI Data bus floating time after INTA CL = 150pF 10 100 ns Vol INTA to INTA access delay 300 ns INTR reset timing10 tRi INTR delay from: Read RxHR (RxRDY) 400 ns Read KHR (KRDY) 400 ns Reset commands (KOVR,KERR,BREAK) 450 ns Load TxHR (TxEMT,TxRDY) 400 ns Mask bit reset 300 ns Keyboard timing11 fKCLK KCLK frequency 409 kHz tKBD KRi, KCi to KRET sample delay: FAST SCAN 12.0 /is SLOW SCAN 55.0 Ats tpos Scan time per matrix position: FAST SCAN 20 As SLOW SCAN 80 As tKRD KDRES delay from KCLK CL = 150pF 400 ns tKRH KDRES hold from KCLK CL = 150pF 400 ns tHYSD HYS delay from KCLK CL = 150pF 600 ns tRCD KIRI, KCl delay from KCLK CL = 150pF 400 ns UART timing12 tRXS RxD setup time 200 ns tRxH RxD hold time 200 ns tTxD TxD delay from falling edge of TxC CL = 150pF 300 ns tTCS Skew between TxD transition and falling edge of TxC output CL = 150pF 0 ns tBRH XTAL1 clock high13 70 ns tBRL XTAL1 clock low13 70 ns fBRG BRG input frequency 1.0 4.9152 5.075 MHz fR/T TxC or RxC input frequency Clock rate factor = 16X, 32X, 64X 1.3 MHz fR/T TxC or RxC input frequency Clock rate factor = 1X 1.0 MHz tR /TH TxC or RxC clock high 350 ns tR/TL TxC or RxC clock low 350 ns

NOTES 9. See figure 13. 10. See figure 14. 11. See figure 15 and 18. 12. See figure 17, 18, and 19. 13. See figures 20 and 21 for XTAL1, XTAL2 connections for driving XTAL2 with an external clock. Input levels for XTAL1 and XTAL2 are VIL < 0.8V, V1H > 4.0V, and 1BRL and tBRH are measured at these levels.

2.30 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC) SCN2671

CE VIL

tCS A2-00 IAS tAH - PW RD Jr IAD IDD --000 tDF D7 DO VAL D >

Figure 11. Read Timing

VIH CE VIL I •—.• ICS tCH A2-00

IAS •AH tPW WR IAD IDH IDS

D7-DO VAL D

Figure 12. Write Timing

INTA VIH tpwi tADI VIL tool -011. tpF1 D7-DO (INTR VECTOR) VALID >

Figure 13. Interrupt Acknowledge Timing

Signetics 2.31 MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE KEYBOARD & COMM CONTROLLER (PKCC) SC2671

X1H I474

IR'

INTR

Figure 14. Interrupt Reset Timing

'FOS

KCLK 400KHz 1/)KCLK

tKRD tKRH

KDRES tHYSD HVS - X tRC D K RO-KR2 KC0-KC3

tKI3D KRET, SHIFT CONTROL & REPEAT SAMPLE TIME

NOTE SCAN TIMING SHOWN IS FOR FAST SCAN (KMR1 = 1). FOR SLOW SCAN (KMR1 = 0)ALL SIGNALS EXCEPT KCLK RUN ATX THE SHOWN RATES.

Figure 15. Keyboard Scan Timing

2.32 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC) SCN2671

1 SCAN CYCLE 22 KC3 22 22 I 22 i 22

KEY 1 KEY 1 KEY2 KEY 1 KEY2 KEY 1

KRET

HYS 2 2 2 2 1.1 N-KEY ROLLOVER MODES ONLY

KRDY (KSRO) 1 'kJ,. 2 KEY ROLLOVER tKR = P..° 2 KEY INHIBIT

CE RESET KERR READ KHR 2 KEY INHIBIT MODE ONLY

KERR

(K:42R

Figure 16. Keyboard Timing

Clock

1BRH ▪ tBRL 1RITH • 1R/TL

XTAL1, TxC, RxC 211-VIL 11 BRG litR/T

Transmit

1 BIT TIME (1, 16, OR 64 CLOCK PERIODS) TxC (INPUT)

TxD

tTxD 1TxD

1TCS TxC (OUTPUT) /

Receive

RxD

tRXS tRXH

RxC (IX) itviLVIH

Figure 17.

Signetics 2.33

MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC) SCN2671

TxC B C A B C B C TxD DATA 1 DATA 2 DATA 3

TxEN

CE FOR WRITE OF THR

TxRDY (CSR1)

Tx EMT (CSR2)

B C A B C A B C D TxD BREAK 1 BREAK 2 DATA 3

TxEN CE FOR BREAK COMMAND I I

Tx RDY 11110 (CSR1) I

TRANSIT BREAK CSR3

TxEMT (CSR2)

WRITE OF THR IF NO WRITE OF THR

A = START BIT B =1st STOP BIT C =2nd STOP BIT D = MARK

Figure 18. Transmitter Timing (5-Bit Characters, no Parity, 2 Stop Bits)

2.34 Signetics MICROPROCESSOR DIVISION JANUARY 1983

PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC) SCN2671

RxC

B C A B C A B C B C A RxD

RxEN CE FOR READ OF RHR

RxRDV I (CSRO)

ROV RUN (CSR5)

A B C A B A

RxD DATA 1 DATA 2 DATA 3

RxEN

FRAMING ERROR (CSR6)

RECEIVED BREAK (CSR4) CE FOR RESET COMMAND WITH D4=1

ISR5 (BREAK DETECT CHANGE) A =START BIT B= 1ST STOP BIT C= 2ND STOP BIT

Figure 19. Receiver Timing (5•Bit Characters, no Parity, 2 Stop Bits)

2671

XTALI

4.9152MHz

XTAL2

Figure 20. Crystal Connections BRG Clock Figure 21. Connection for External BRG Clock Source

Signetics 2.35 MICROPROCESSOR DIVISION PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC) SCN2671

Table 7 REGISTER FORMAT SUMMARY I 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 Test mode Rollover modes Keyboard Auto repeat Tone select Key 1 = Enable 00 = N-key with latched 0 = Encoded 0 = Disable Matrix Scan 0 = 1kHz keys KMR2 KMR1 Size Time KMR 0 = Disable 01 = N-key 1 = Non en- 1 = Enable 0 0 128 10ms 1 = 2kHz 10 = Two keys coded 0 1 128 2.5ms 11 = Two key inhibit 1 0 80 6.4ms 1 1 80 1.6ms

KSR CONTROL SHIFT SHIFT LOCK REPEAT Keyboard KOVR KERR KRDY Enabled

Operating Mode Parity Parity Mode Stop Bits Character Length 00 = Normal 0 = Odd/ 00 = With parity 0 = Two 00 = 8 01 = Auto echo force 0 01 = Force parity 01 = 5 CMR 10 = Local loopback 10 = No parity 1 = One 10 = 6 11 = Remote loopback 1 = Even/ 11 = Not allowed 11 = 7 force 1

Tx Clock Rx Clock Clock rate factor source source for external clocks Baud rate select (BRR3 • BRRO in hex) 0 = External 0 = External 00 = 16X 0 = 50 4 = 200 8 = 1200 C = 4800 01 = 32X 1 = 110 5 = 300 9 = 1800 D = 9600 1 = Internal 1 = Internal 10 = 64X 2 = 134.5 6 = 600 A = 2000 E = 19200 (BRG) (BRG) 11 = lx 3 = 150 7 = 1050 B = 2400 F = 38400 BRR For internal clocks these bits specify the output fre- (BRCLK = 4.9152MHz) quency on pins 34 and 35 (table 4).

CSR Parity error Framing error Overrun error Received Transmit TxEMT TxRDY RxRDY break break

IMR/ISR TxRDY TxEMT BREAK XINT KERR KRDY KOVR RxRDY CHANGE

00X = No effect 101 = Reset TxE Break detect Communica- KOVR reset KERR reset Keyboard Reset 010 = Set RxE 110 = Set TxE and change reset tions error reset Command 011 = Reset RxE RxE reset Format 100 = Set TxE 111 = Communica- tions reset

Miscellaneous Clear Set Clear Set Ring Ring Transmit Transmit Commands keyboard keyboard shift shift tone tone timed character Format enable enable lock lock long short break break

2.36 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC) SCN2672

DESCRIPTION FEATURES PIN CONFIGURATION The Signetics SCN2672 Programmable 4MHz and 2.7MHz character Video Timing Controller (PVTC) is a pro- rateversions grammable device designed for use in • Up to 256 characters per row CRT terminals and display systems that • 1 to 16 raster lines per character row VCC employ raster scan techniques. The PVTC • Up to 128 character rows per frame CE A2 generates the vertical and horizontal tim- • Programmable horizontal and vertical WR Al ing signals necessary for the display of in- sync generators CTRL1 AO terlaced or non-interlaced data on a CRT • Interlaced or non—interlaced operation monitor. It provides consecutive address- • Up to 16K RAM addressing for multiple CTRL2 LPS ing to a user specified display buffer mem- page operation CTRL3 INTR ory domain and controls the CPU-display • Automatic wraparound of RAM CURSOR DADDO buffer interface for various buffer config- • Addressable incrementable and uration modes. A variety of operating readable cursor DO DADD1 modes, display formats, and timing pro- • Programmable cursor size, position, D1 DADD2 files can be implemented by programming and blink D2 DADD3ILI the control registers in the PVTC. • Split screen and horizontal scroll capability D3 DADD4ILAO A minimum CRT terminal system configur- • Light pen register D4 DADD5ILA1 ation consists of a PVTC, a SCN2671 Key- • Selectable buffer Interface modes board and Communication Controller D5 DADD6ILA2 • Dynamic RAM refresh (PKCC), a SCN2670 Display Character and 013 D ADD7/LA3 • Completely TTL compatible Graphics Generator (DCSG), a SCN2670 • Single +5 volt power supply D7 DADD8ILNZ Video and Attributes Controller (VAC), a • Power on reset circuit CCLK DADD9/LPL single chip microcomputer such as the 8048, a display buffer RAM, and a small APPLICATIONS BLANK DADDIOIUL amount of TTL for miscellaneous address • CRT terminals VSYNC/CSYNC DADD11/BLINK decoding, interface, and control. Typi- • Word processing systems HSYNC DADD12/0DD cally, the package count for a minimum • Small business computers system is between 15 and 20 devices; sys- • Home Computers GND DADDI3ILL tem complexity can be enhanced by up- TOP VIEW grading the microprocessor and expanding via the system address and data busses. BLOCK DIAGRAM

INTERFACE CONTROL CE DISPLAY CTRL1 RD INITIALIZATION READ/ MEMORY CTRL2 AND WR WRITE HANDSHAKE DISPLAY CTRL3 CONTROL LOGIC REGISTERS LOGIC

COMMAND DECODE LOGIC A0-2 ADDRESS INTERRUPT DISPLAY I DADD0-13/> 3 DECODER LOGIC AND ADDRESS STATUS TIMING 14 REGISTER MULTIPLEXERS INTR CURSOR, LIGHT PEN STROBE POINTER AND LIGHT PEN REGISTERS

DATA CURSOR CURSOR < 130-7/ BUS AND DRIVERS COMPARE 8 LOGIC

VCC GND

HSYNC CCLK CLOCK TIMING CHAIN VSYNC/CSYNa BUFFER AND DECODE LOGIC BLANK

TIMING Signetics 2.37 MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC) SCN2672

ORDERING CODE Vcc = 5V -1.- 5%, TA = 0°C to 70°C PACKAGES 4MHz 2.7MHz Ceramic DIP SCN2672AC4140 SCN2672AC3I40 Plastic DIP SCN2672AC4N40 SCN2672AC3N40

PIN DESIGNATION MNEMONIC PIN NO. TYPE NAME AND FUNCTION AO—A2 37-39 I Address Lines: Used to select PVTC internal registers for read /write operations and for commands. DO—D7 8-15 I/O 8—Bit Bidirectional Three—State Data Bus. Bit 0 is the LSB and bit 7 is the MSB. All data, command, and status transfers between the CPU and the PVTC takeplace over this bus. The direction of the transfer is controlled by the RD and WR inputs when the CE input is low. When the CE input is high, the data bus is in the three—state condition. RD 1 I Read Strobe: Active low input. A low on this pin while CE is low causes the contents of the register selected by A0—A2 to be placed on the data bus. The read cycle begins on the leading (falling) edge of RD. WR 3 I Write Strobe: Active low input. A low on this pin while CE is also low causes the contents of the data bus to be transferred to the register selected by A0—A2. The transfer occurs on the trailing (rising) edge of WR. CE 2 I Chip Enable: Active low input. When low, data transfers between the CPU and the PVTC are enabled on DO-07 as controlled by the WR, RD, and AO—A2 inputs. When CE is high, the PVTC is effectively isolated from the data bus and DO—D7 are placed in the three—state condition. CCLK 16 I Character Clock: Timing signal derived from the video dot clock which is used to synchronize the PVTC's timing functions. HSYNC 19 0 Horizontal Sync: Active high output which provides video horizontal sync pulses. The timing parameters are programmable. VSYNC / CSYNC 18 o Vertical Sync/Composite Sync: A control bit selects either vertical or composite sync pulses on this active high output. When CSYNC is selected, equalization pulses are included. The timing parameters are programmable. BLANK 17 0 Blank: This active high output defines the horizontal and vertical borders of the display. Display control signals which are output on DADD3 thru DADD13 are valid on the trailing edge of BLANK. CURSOR 7 0 Cursor Gate: This active high output becomes active fora specified number of scan lines when the address contained in the cursor registers match the address output on DADDO thru DADD13. The first and last lines of the cursor and a blink option are programmable. INTR 35 0 Interrupt Request: Open drain output which supplies an active low interrupt request from any of five maskable sources. This pin is inactive after power on reset or a master reset command. LPS 36 I Light Pen Strobe: Positive edge triggered input indicating a light pen hit. Causes the current value of the display address to be strobed into the light pen register. CTRL 1 4 I/O Handshake Control 1: In independent mode, provides an active low write data buffer (WDB) output which strobes data from the interface latch into the display memory. In transparent and shared modes, this is an active low processor bus request (PBREQ) input which indicates that the CPU desires to access the display memory. This pin must be tied high when operating in row buffer mode. CTRL2 5 0 Handshake Control 2: In independent mode, provides an active low read data buffer (RDB) output which strobes data from the display memory into the interface latch. In transparent and shared modes, this is an active low bus external enable (BEXT) output which indicates that the PVTC has relinquished control of the display memory (DADDO—DADD13 are in the three—state condition) in response to a CPU bus request. BEXT also goes low in response to a 'display off and float DADD' command. In row buffer mode, it is an active low bus request (BREQ) output which halts the CPU during a line DMA.

2.38 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC) SCN2672

PIN DESIGNATION (cont.)

MNEMONIC PIN NO. TYPE NAME AND FUNCTION

CTRL3 6 0 Handshake Control 3: In independent mode, provides the active low buffer chip enable (BCE) signal to the display memory. In transparent and shared modes, provides an active low bus acknowledge (BACK) output which serves as a ready signal to the CPU in response to a processor bus request. In row buffer mode, this is an active high memory bus control (MBC) output which configures the system for the DMA transfer of one row of character codes from system memory to the row display buffer. DADDO—DADD13 34-21 0 Display Address: Used by the PVTC to address up to 16K of display memory. These outputs are floated at various times depending on the buffer mode. Various control signals are multiplexed on DADD3 thru DADD13 and are valid at the trailing edge of BLANK. These control signals are: DADD3/LI Line Interlace: Replaces DADD4 /LAO as the least significant line address for interlaced sync and video applications. A low indicates an even row of an even field or an odd row of an odd field. DADD4—DADD7 /LAO—LA3 Line Address: Provides the number of the current scan line within each character row. DADD8/LNZ Line Zero: Asserted before the first scan line in each character row. DADD9/LPL Light Pen Line: Asserted before the scan line which matches the programmed light pen line position (line 3, 5, 7, or 9). DADD10/UL Underline: Asserted before the scan line which matches the programmed underline position (line 0 thru 15). DADD11 /BLINK Blink frequency: Provides an output divided down from the vertical sync rate. DADD 12 /ODD Odd Field: Active high signal which is asserted before each scan line of the odd field when interlace is specified. DADD13/LL Last Line: Asserted before the last scan line of each character row. VCC 40 I Power Supply: +5 volts ± 5,/o power input. GND 20 I Ground: Signal and power ground input.

FUNCTIONAL DESCRIPTION Table 1 PVTC ADDRESSING As shown on the block diagram, the PVTC A2 Al AO READ (RD=O) WRITE (WR=O) contains the following major blocks: • Data bus buffer 0 0 0 Interrupt register Initialization registers' • Interface Logic 0 0 1 Status register Command register • Operation Control 0 1 0 Screen start address lower register Screen start address lower reg. • Timing 0 1 1 Screen start address upper register Screen start address upper reg. • Display Control 1 0 0 Cursor address lower register Cursor address lower register • Buffer Control 1 0 1 Cursor address upper register Cursor address upper register 1 1 0 Light pen address lower register Display pointer address lower reg. Data Bus Buffer 1 1 1 Light pen address upper register Display pointer address upper reg. The data bus buffer provides the interface NOTE between the external and internal data bus- 1. There are 11 initialization registers which are accessed sequentially via a single address. The PVTC maintains an ses. It is controlled by the operation control internal pointer to these registers which is incremented after each write at this address until the lest register (IRIO, block to allow read and write operations to the split screen register) is accessed. The pointer then continues to point to the split screen register. Upon take place between the controlling CPU and power—up or a master reset commend, the internal pointer is reset to point to the first register (IRO) of the the PVTC. initialization register group. The internal pointer can also be preset to any register of the group via the 'load IR address pointer' command. Interface Logic The interface logic contains address decod- via the data bus buffer. The functions per- ing and read and write circuits to permit formed by the CPU read and write oper- communications with the microprocessor ations are as shown in table 1.

Signetics 2.39

MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC) SCN2672

Operation Control Buffer Control shift register or a small RAM) that is updat- The operation control section decodes con- The buffer control section generates three ed in real time to contain the appropriate figuration and operation commands from the signals which control the transfer of data display data. CPU and generates appropriate signals to between the CPU and the display buffer The user programs bits 0 and 1 of IRO to other internal sections to control the overall memory. Four system configurations requir- select the mode best suited for the system device operation. It contains the timing and ing four different 'handshaking' schemes environment. The CNTRL1-3 outputs per- display registers which configure the dis- are supported. These are described below. form different functions for each mode and play format and operating mode, the inter- are named accordingly in the description of rupt logic, and the status register which pro- SYSTEM CONFIGURATIONS each mode. vides operational feedback to the CPU. Figure 1 illustrates the block diagram of a Independent Mode typical display terminal using the Signetics Timing The CPU to RAM interface configuration for 2670, 2671, 2672, and 2673 CRT terminal The timing section contains the counters this mode is illustrated in figure 2. Transfer devices. In this system, the CPU examines and decoding logic necessary to generate of data between the CPU and display mem- inputs from the data communications line the monitor timing outputs and to control the ory is accomplished via a bidirectional and the keyboard and places the data to be display format. These timing parameters are latched port and is controlled by the signals displayed in the display buffer memory. This selected by programming of the initialization read data buffer (RDB), write data buffer buffer is typically a RAM which holds the registers. (WDB), and buffer chip enable (BCE). This data for a single or multiple screenload mode provides a non—contention type of op- Display Control (page) or for a single character row. The display control section generates linear eration that does not require address addressing for up to 16K bytes of display The PVTC supports four common system multiplexers. The CPU does not address the memory. Internal comparators limit the por- configurations of display buffer memory, memory directly—the read or write oper- tion of the memory which is displayed to designated the independent, transparent, ation is performed at the address contained programmed values. Additional functions shared, and row buffer modes. The first in the cursor address register or the pointer performed in this section include cursor po- three modes utilize a single or multiple page address register as specified by the CPU. sitioning, storage of light pen 'hit' location, RAM and differ primarily in the means used The PVTC enacts the data transfers during and address comparisons required for gen- to transfer display data between the RAM blanking intervals in order to prevent visual eration of timing signals and the split screen and the CPU. The row buffer mode makes disturbances of the displayed data. interrupt. use of a single row buffer (which can be a

2673

GRAPHICS CLOCK LOGIC GENERATOR

CHARACTER VIDEO GENERATOR SHIFT 2672 REGISTER

CHARACTER' VIDEO TIMING SYNC GENERATOR & GRAPHICS CONTROL CHAIN GENERATOR 2670 ATTRIBUTES / LOGIC MONITOR CURSOR MEMORY LOGIC CONTROL H REFRESH RAM TIMING SYNC VIDEO TIMING & ATTRIBUTES

CPU

2671

PROGRAM DATA KEYBOARD DATA COM MEMORY MEMORY INTERFACE INTERFACE

LINE DRIVERS 1 MODEM DATA COMMUNICATIONS LINE KEYBOARD & RECEIVERS

Figure 1. CRT Terminal Block Diagram

2.40 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC) SCN2672

The CPU manages the data transfers by supplying commands to the PVTC. The commands used are: 2672 REFRESH 1. Read/ Write at pointer address. PVTC RAM 2. Read /Write at cursor address (with op- DADD DISPLAY ADDRESS ADR tional increment of address). BCE CTRL3 CE 3. Write from cursor address to pointer ad- Woe CTRL1 ► WR dress. DATA U0 CTRL2 ROB The operational sequence for a write operation is:

1. CPU checks RDFLG status bit to assure TO that any previous operation has been DISPLAY DATA BUS VIDEO completed. /%. LOGIC 2. CPU loads data to be written to display memory into the interface latch. 3. CPU writes address into cursor or pointer \7 registers. op 74LS364 4. CPU issues 'write at cursor with/without increment' or 'write at pointer' command. RD WR— 5. PVTC generates control signals and out- FROM CPU FROM CPU puts specified address to perform re- SYSTEM DATA BUS quested operation. Data is copied from the interface latch into the memory. 6. PVTC sets RDFLG status to indicate that Figure 2. Independent Buffer Mode Configuration the write is completed.

Similarly, a read operation proceeds as follows: 3. CPU writes beginning address of memory play window (defined as first scan line of the 1. Steps 1 and 3 as above. block into cursor address register and first character row to the last scan line of 2. CPU issues 'read at cursor with/without ending address of block into pointer ad- the last character row), the operation takes increment' or 'read at pointer' command. dress register. place during the next horizontal blanking in- 3. PVTC generates control signals and out- 4. CPU issues 'write from cursor to pointer' terval, as illustrated in figure 3. If the com- puts specified address to perform re- command. mand is given during the vertical blanking quested operation. Data is copied from 5. PVTC generates control signals and out- interval, or while the display has been com- memory to the interface latch and PVTC puts block addresses to copy data from manded blanked, the operation takes place sets RDFLG status to indicate that the the interface latch into the specified immediately. In the latter case, the execu- read is completed. block of memory. tion time for the command is approximately 4. CPU checks RDFLG status to see if oper- 6. PVTC sets RDFLG status to indicate that one microsecond plus six (6) character ation is completed. the block write is completed. clocks (see figure 4). 5. CPU reads data from interface latch. Timing for the 'write from cursor to pointer' Loading the same data into a block of dis- Similar sequences can be implemented on operation is shown in figure 5. The BLANK play memory is accomplished via the 'write an interrupt driven basis using the READY output is asserted automatically and re- from cursor to pointer' command: interrupt output to advise the CPU that a previously requested command has been mains asserted until the vertical retrace in- 1. CPU checks RDFLG status bit to assure completed. terval following completion of the command. that any previous operation has been The memory is filled at a rate of one location completed. Two timing sequences are possible for the per two character times, plus a small 2. CPU loads data to be written to display 'read /write at cursor/pointer' commands. If amount of overhead. memory into the interface latch. the command is given during the active dis-

Signetics 2.41

MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC) SCN2672

2 BLANK HORIZONTAL BLANKING INTERVAL

DADC=C=X LAST CURSOR OR ADDRESS POINTER ADDRESS

-.I- REFRESH ADDRESSES 2 2 555

22 rt_ I

NOTE Write waveforms shown in dotted lines.

Figure 3. Read/Write at Cursor/Pointer Command Timing (Command Received During Active Display Window)

BLANK

DAM PVTC READ COMMAND ADDRESS

Via= REFRESH ADDRESSES REFRESH ADDRESSES

555 2

Figure 4. Read/Write at Cursor/Pointer Command Timing (Command Received While Display is Blanked)

2.42 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC) SCN2672

CCLK

2 a Al

BLANK BLANK IS SET UNTIL FIRST VBLNK AFTER LAST WRITE

• ANY CHAR CURSOR 2- POINTER POINTER CURSOR ADDRESS DADD ADDRESS ADDRESS+ 1 ADDRESS — 1 ( ADDRESS

WDB

BCE

RDB Figure 5. Write from Cursor to Pointer Command Timing

Shared and Transparent Buffer Modes In these modes the display buffer RAM is a part of the CPU memory domain and is ad- REFRESH 2672 dressed directly by the CPU. Both modes RAM PVTC DISPLAY ADDRESS ADR use the same hardware configuration with CE the CPU accessing the display buffer via PBREO CTRL1 three—state drivers (see figure 6). The pro- WR CPU BACK .16 CTRL3 DATA I/O cessor bus request (PBREQ) control signal BEXT informs the PVTC that the CPU is requesting CTRL2 access to the display buffer. In response to this request, the PVTC raises bus acknowl- DISPLAY DATA BUS edge (BACK) until its bus external (BEXT) 74LS244 output has freed the display address and 74LS245 data busses for CPU access. BACK, which SELECT can be used as a 'hold' input to the CPU, is RD DECODE CPU LOWER then lowered to indicate that the CPU can WR access the buffer. UPPER In transparent mode, the PVTC delays the SYSTEM ADDRESS BUS granting of the buffer to the CPU until a vertical or horizontal blanking interval, thereby SYSTEM DATA BUS causing minimum disturbance of the display. In shared mode, the PVTC will blank the display and grant immediate access to the CPU. Timing for these modes is illustrated in Figure 6. PVTC Shared or Transparent Buffer Modes figures 7, 8, and 9.

Signetics 2.43

MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC) SCN2672

(0 22- PBRE 2 22 / _/---22 2 2 BERT 22 / (1) (2) -22- BLANK HORIZONTAL BLANKING INTERVAL

PVTC CTRL SIGNALS 1ST CHAR DADD= SYSTEM ADDRE2SSES TO VAC AND DCG ADDRESS

NOTES • 1. PBREQ must be asserted prior to the rising edge of BLANK in order for sequence to begin during that blanking period.

2. If PBREQ is negated after the next to lest CCLK of the horizontal blanking interval, the next scan line will also be blanked.

Figure 7. Transparent Buffer Mode Timing

-22- 22 /

BACK \ 2 22 -22- 22 22 BLANK

DADD SYSTEM PVTC CTRL SIGNALS ADDRESSES TO VAC AND DCG

NOTE 1. If PBREQ is negated after the next to last CCLK of the horizontal blanking interval, the next scan line will also be blanked.

Figure 8. Shared Buffer Mode Timing

2.44 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC) SCN2672

la) (b) -1-1111111PU-111_ -

PBREO PIE111E 22 I Rkel( \--a tkel(

arra BEXT 22 z VBLANK OR DBLANK BLANK

22 DADD SYS.A) SYSTEM PROCESSOR HAS CONTINUOUS BUS CONTROL DADS CDC ?? .-- REFRESH ADDRESSES—. REFRESH ADDRESSES a) During Vertical Blank or after 'display off' command b) After 'display off and 3—state' command

Figure 9. Shared and Transparent Mode Timing

Row Buffer Mode Figures 10 and 11 show the timing and a 2o2111 typical hardware implementation for the 2672 ROW row buffer mode. During the first scan line PVTC LSB's REFRESH > RAM (line 0) of each character row, the PVTC DISPLAY ADDRESS halts the CPU and DMA's the next row of BRED CTRL2 TO CPU character data from the system memory to MSC 74LS244 r WR the row buffer memory. The PVTC then releases the CPU and displays the row buffer CTRL3 data for the programmed number of scan CCLK I DISPLAY DATA BUS lines. The bus request control (BREQ) signal informs the CPU that character ad- SYSTEM ADDRESS BUS dresses and the memory bus control (MBC) 74LS244 signal will start at the next falling edge of BLANK. The CPU must release the address SYSTEM SELECT and data busses before this time to prevent RAM DECODE bus contention. After the row of character data is transferred to the CPU, BREQ re- WR turns high to grant memory control back to the CPU. SYSTEM DATA BUS

Figure 10. Row Buffer Mode Configuration

Figure 11. Row Buffer Mode Timing

Signetics 2.45

MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC) SCN2672

OPERATION groups, the PVTC is ready to control the INITIALIZATION REGISTERS monitor screen. Prior to executing the PVTC After power is applied, the PVTC will be in an There are 11 initialization registers commands which turn on the display and inactive state. Two consecutive 'master (IRO—IR 10) which are accessed sequential- cursor, the user should load the display reset' commands are necessary to release ly via a single address. The PVTC maintains memory with the first data to be displayed. this circuitry and ready the PVTC for oper- an internal pointer to these registers which During operation, the PVTC will sequentially ation. Two register groups exist within the is incremented after each write at this ad- address the display memory within the limits PVTC: the initialization registers and the dis- dress until the last register (IR10, the split programmed into its registers. The memory play control registers. The initialization reg- screen register) is accessed. The pointer outputs character codes to the system isters select the system configuration, moni- then continues to point to the split screen character and graphics generation logic, tor timing, cursor shape, display memory register. Upon power—up or a master reset where they are converted to the serial video domain, and screen format. These are load- command, the internal pointer is reset to stream necessary to display the data on the ed first and normally require no modification point to the first register (IRO) of the CRT. The user effects changes to the dis- except for certain special visual effects. initialization register group. The internal play by modifying the contents of the display The display control registers specify the pointer can also be preset to any register of memory, the PVTC display control and com- memory address of the base character (up- the group via the 'load IR address pointer' mand registers, and the initialization regis- per left corner of screen), the cursor posi- command. These registers are write only ters, if required. Interrupts and status condition, and the pointer address for indepen- and are used to specify parameters such as tions generated by the PVTC supply the dent memory access mode. These usually the system configuration, display format, 'handshaking' information necessary for the require modification during operation. cursor shape, and monitor timing. Register CPU to effect the display changes in the formats are shown in figure 12. After initial loading of the two register proper time frame.

BIT7 BITE • BITS • BIT4 • BITS BITE BIT1 • BITO BIT7 • BITS • BITS • BIT4 • BITS • BITS • BITI • BITO SCAN LINES PER CHARACTER ROW SYNC SUFFER MODE ACTIVE CHARACTERS PER ROW NON-INTERLACED INTERLACED SELECT SELECT 00000010 = 3 CHARACTERS 0000 = 1 LINE 0000 = UNDEFINED 00000011 = 4 CHARACTERS 0001 = 2 LINES 0001 = 5 LINES 0010 = 3 LINES IRS IRO NOT 0010 = 7 LINES 0= VSYNC 00 = INDEPENDENT • USED • 1= CMG 01 = TRANSPARENT 11111110 =•255 CHARACTERS • 10 = SHARED 11111111 = 256 CHARACTERS 1110 = 15 LINES 1110 = 31 LINES 11 = ROW • • 1111 4-- 16 LINES 1111 = UNDEFINED • BIT7 • BITS • BITS • 131,1 BITS • BITS • BITt • BITO FIRST LINE OF CURSOR LAST LINE OF CURSOR BIT) BITB BIT1 • BITO • ' 0000 = SCAN LINED 0000= SCAN LINE INTERLACE 70UA171ZIN:TCONSTAN'r • • "' 0001 = SCAN LINE 1 0001= SCAN LINE 1 ENABLE 0000000=1 CCLK IRO 0000001=2 CCU( CALCULATED FROM: • IR1 1110 = SCAN LINE 14 1110 = SCAN LINE 14 0 =NON-INT • EC = 0.5(HAcT+NFI4 +14SYNC-1114M4 2(HSYNC) 1111= SCAN LINE 15 1111= SCAN LINE 15 1= INTER. 1111110=127 CCLK • • • • 1111111=128 CCLK BIT] • BITS BITS BITO BITS • BIT2 • BITI • BITO LIGHT PEN LINE CURSOR DOUBLE UNDERLINE POSITION BIT] BITS • BITS • 131,1 • arr3 BITE • BIT1 • BITO BLINK HEIGHT OOP, = SCAN LINE 0 HORIZONTAL SYNC WIDTH HORIZONTAL BACK PORCH 00 = SCAN LINE 3 CHAR. 0001 = SCAN LINE 1 0000 = 2 CCLK 000 = 1 CCLK 01 = SCAN LINE 5 0001 = 4 CCLK 001 = 5 CCLK 107 10 = SCAN LINE] O=NO O=NO NOT • IRS • 11 = SCAN LINE 9 1 = YES 1 = YES 1110 =SCAN LINE 14 USED • • 1111 = SCAN LINE 15 1110 = 30 CCLK 110 = 25 CCLK . • • 1111 = 32 CCLK III = 29 CCLK

BIT7 • BITS • BITS • BITS • BITS • BITE • 13I • BITO DISPLAY BUFFER FIRST ADDRESS LSB'S BIT7 • BITS • BITS BIT4 • BITS BIT2 • BIT1 • BITO H'000 =0 VERTICAL FRONT PORCH VERTICAL BACK PORCH H1001' = 000 = 4 SCAN LINES 00000 = 4 SCAN LINES NOTE MSEI'S ARE IN 001 = 8 SCAN LINES 00001 = 6 SCAN LINES IRB • IMO:0j • IRS • H'EFF' = 4,095 110 = 28 SCAN LINES 11110 = 64 SCAN LINES 111 .32 SCAN LINES 11111 = 66 SCAN LINES • • • BIT7 • BITS • SITS • BITO BITS • BIT2 • BITt • BITO DISPLAY BUFFER LAST ADDRESS DISPLAY BUFFER FIRST ADDRESS MSB'S BIT7 SITS • BITS BITS • BITS • BITE • BIT1 • BITO 0000 = 1,023 CHARACTER ACTIVE CHARACTER ROWS PER SCREEN (NOTE 1) 0001 = 2,047 BUNK 0000000 = 1 ROW SEE IRO RATE 0000001 = 2 ROWS IRS IR4 1110 = 15,359 0 =. 1/16 • 1111 = 16,383 VSYNC =1/32 1111110 = 127 ROWS VSYNC 1111111 = 1251 ROWS • BIT7 BITS • BITS • BIT4 • BITS • BITS • BITt • BITO NOTE CURSOR SPLIT SCREEN INTERRUPT ROW 1. In Interlace mode with odd total character rows per Screen the last character BUNK 0000000 = ROW 0 row will be the programmed scan lines per character row minus one. RATE 0000001 = ROW 1 IRIO 0= 1/18 VSYNC • 1 = 1/32 1111110 = ROW 126 VSYNC 1111111 = ROW 127

Figure 12. Initialization Register Formats

2.46 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC) SCN2672

IRO[6:3]—Scan Lines per IR1[6:0]—Equalizing Constant IR5[7:0]—Active Characters Per Character Row This field indirectly defines the horizontal Row Both interlaced and non—interlaced scan- front porch and is used internally to gener- This field determines the number of charac- ning are supported by the PVTC. For inter- ate the equalizing pulses for the RS170 ters to be displayed on each row of the CRT laced mode, two different formats can be compatible CSYNC. The value for this field screen. The sum of this value, the horizontal implemented, depending on the is the total number of character clocks front porch, the horizontal sync width, and interconnection between the PVTC and the (CCLK) during a horizontal line period divid- the horizontal back porch is the horizontal character generator (see IR1[7]). This field ed by two, minus two times the number of scan period in CCLKs. defines the number of scan lines used to character clocks in the horizontal sync compose a character row for each tech- pulse: nique. As scanning occurs, the scan line count is output on the LAO—LA3 and LI pins. HACT+ HFP+ + HBP IR6[7:4], IR6[3:0]—First and Last EC= — 2(H SYNC) 2 Scan Line of Cursor These two fields specify the height and po- IRO[2]—VS/CS Enable The definition of the individual parameters sition of the cursor on the character block. This bit selects either vertical sync pulses is illustrated in figure 14. The minimum The 'first' line is the topmost line when scanning from the top to the bottom of the or composite sync pulses on the value of HFP is two character clocks. screen. VSYNC/CSYNC output (pin 18). The composite sync waveform conforms to EIA Note that when using the 2673 VAC, the RS170 standards, with the vertical interval blank pulse is delayed three CCLKs relative composed of six equalizing pulses, six verti- to the HSYNC pulse. IR7[7:6]—Light Pen Line Position cal sync pulses, and six more equalizing This field defines which of four scan lines of pulses. IR2[6:3]—Horizontal Sync Pulse the character row will be used for the light Width pen strike—thru attribute by the 2673 VAC. The timing signal is multiplexed onto the This field specifies the width of the HSYNC IRO[1:0]—Buffer Mode Select DADD9 /LPL output during the falling edge pulse in CCLK periods. Four buffer memory modes may be selec- of BLANK. tively enabled to accommodate the desired system configuration. See System Configu- IR2[2:0]—Horizontal Back Porch ration. This field defines the number of CCLKs between the trailing edge of HSYNC and the IR7[5]—Cursor Blink Enable trailing edge of BLANK. This bit controls whether or not the cursor IR1[7]—Interlace Enable output pin will be blinked at the selected rate (IR 10[7]). The blink duty cycle for the Specifies interlaced or noninterlaced timing IR3[7:5]—Vertical Front Porch cursor is 50%. operation. Two modes of interlaced oper- Programs the number of scan line periods ation are available, depending on whether between the rising edges of BLANK and LO—L3 or LI, LO—L2 are used as the line VSYNC during a vertical retrace interval. address for the character generator. The re- The width of the VSYNC pulse is fixed at IR7[4]—Double Height Character three scan lines. sulting displays are shown in figure 13. Row Enable For 'interlaced sync' operation, the same IR3[4:0]—Vertical Back Porch If enabled, the number of each scan line will information is displayed in both odd and be repeated twice in succession, causing This field determines the number of scan line even fields, resulting in enhanced the height of the character row to double. periods between the falling edges of the readability. The PVTC outputs successive This bit can be changed at any time but will VSYNC and BLANK outputs. line numbers in ascending order on the only become effective at the beginning of LAO—LA3 lines, one per scan line for each the character row following the time it is field. IR4[7]—Character Blink Rate changed. This allows selected character Specifies the frequency for the character rows to be of double height. The split screen The 'interlaced sync and video' format dou- blink attribute timing. The blink rate can be interrupt can be used to notify the CPU when bles the character density on the screen. specified as 1/ 16 or 1/ 32 of the vertical to effectuate changes to this bit. For each The PVTC outputs successive line numbers field rate. The timing signal has a duty cycle double height row which replaces a normal in ascending order on the LI, LAO—LA2 lines, of 75% and is multiplexed onto the row, one row count should be subtracted one per scan line for each field, but alter- DADD11 /BLINK output at the falling edge of from the 'character rows per screen' field nates beginning the count with even and odd each BLANK. (IR4) to maintain the same total number of line numbers. This displays the odd field scan lines per field. with even scan lines in even character rows and odd scan lines in odd character rows, IR4[6:0]—Character Rows Per and the even field with odd scan lines in Screen even character rows and even scan lines on This field defines the number of character IR7[3:0]—Underline Position odd character rows. This provides balanced rows to be displayed. This value multiplied This field defines which scan line of the beam currents in the odd and even fields, by the scan lines per character row, plus the character row will be used for the underline thus minimizing character variations due to vertical front and back porch values, and the attribute by the 2673 VAC. The timing signal different loading of the CRT anode supply vertical sync pulse width (three scan lines) is multiplexed onto the DADD10 /UL output between fields. is the vertical scan period in scan lines. during the falling edge of BLANK. Signetics 2.47 MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC) SCN2672

- L1

- L2

.4— L3

LINE ADDRESS LINE ADDRESS LINE ADDRESS TO CHAR GEN TO CHAR GEN TO CHAR GEN o 6 8 7 O

1 —• - • - • - • - • 1 —•-•-•- • - • 1-0 0 0 00 1 - 0 0 0 0 0 2 • 2 —• 2 • 9 SCAN 0 2 0 LINES/ 4 • • • 3 —• 3 • ROW 5 0 9 SCAN 17 SCAN 3-0 6 • LINES/ 4 — • •- -• LINES/ 4 • -•-• 7-0 0 0 00 ROW ROW 4 0 0 0 8 5 — • 5 • 0 5 0 6 —• 6 • 2 0 6 0 3 • 7 —• - • - • - • - • 7 • -•-•-•-• 4-0 0 0 7-0-0-0-0-0 5 • 8 8 6 0 7 0 a 1-0-0 0 0 0 0 —•-•-•-•- • • -•-•-•-• 1- 0 0 0 0 0 2 0 2 • 2. —• 2 —• 3 0 3 0 4 • • • 3 • 3 • 5 0 4-0-0-0 6 • 4 — • -• - • 4 — •-•-• 7-0 0 0 00 5 0 8 5 • 5 • 0 6 0 6 —• 6 • 2 0 7-0-0-0-0-0 3 • 7 — • • • • • 7 4-0 0 0 8 5 • a 6 0 7 8

NONINTERLACED INTERLACED SYNC INTERLACED SYNC & VIDEO IRO = 1000; TOTAL LINES/ROW =9 IRO= 0111; TOTAL LINES/ROW =17 IRO= 0011; TOTAL LINES/ROW =9

Figure 13. Interlaced Display Modes

IR9[3:0], IR8[7:0]—Display Buffer screen, the next data is obtained from the Blink is effective only if blink is enabled by First Address address contained in the screen start IR7[5]. register. IR9[7:4]—Display Buffer Last Ad- IR10[6:0]—Split Screen Interrupt dress Note that there is no restriction in displaying The split screen interrupt can be used to data from other areas of the addressable provide special screen effects such as a These two fields define the area within the memory. Normally, the area between these row of double height characters or to buffer memory where the display data will two bounds is used for data which can be change the normal addressing sequence of reside. When the data at the 'display buffer overwritten (e.g., as a result of scrolling), the display memory. The contents of this last address' is displayed, the PVTC will while data that is not to be overwritten would field is compared, in real time, to the current wrap-around and obtain the data to be dis- be contained outside these bounds and character row number. Upon a match, the played at the next screen position from the accessed by means of the split screen inter- PVTC sets the split screen status bit, and 'display buffer first address'. If 'last ad- rupt feature of the PVTC. issues an interrupt request if so pro- dress' is the end of a character row and a grammed. The status change/interrupt re- new screen start address has been loaded IR10[7] — Cursor Blink. Rate quest is made at the beginning of scan line into the screen start register, or if 'last ad- The cursor blink rate can be specified at zero of the split screen character row. dress' is the last character position of the 1/ 16 or 1/ 32 of the vertical scan frequency.

2.48 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC) SCN2672

CHAFUROW (IR5)

HBLANK FRONT PORCH (IRI) BACK PORCH (IR2)

HSYNC HSYNC (IR2) CHAR ROWS/SCREEN (IR4) —4 I.— SCAN LINES PER ROW (IRO)

VBLANK H FRONT PORCH (IR3) BACK PORCH 11R3)

VSYNC VSYNC (FIXED AT 3) EQUALIZING LINESIROW CONSTANT

IRO 1 1 1 1 1 1 RI IIIIIII

HSYNC HBACK VFRONT VBACK WIDTH PORCH PORCH PORCH

IR2 1 1 1 1 1 IR3 1 1 1 1 1 1 1

CHAR ROWS/SCREEN CHARACTERS PER ROW

IR4 LIIIIIIII IR5 1 1 1 1 1 1 1

Figure 14. Horizontal and Vertical Timing

Timing Considerations Table 2 TIMING CONSIDERATIONS Normally, the contents of the initialization PARAMETER TIMING CONSIDERATIONS registers are not changed during operation. However, this may be necessary to imple- First line of cursor These parameters must be estab- ment special display features such as multi- Last line of cursor lished at a minimum of two character ple cursors, smooth scrolling, horizontal Light pen line times prior to their occurence. scrolling, and double height character rows. Underline Table 2 describes timing details for these registers which should be considered when Double height characters Set/reset during the character row implementing these features. prior to the row which is to be/not to be double height

Cursor blink New values become effective within Cursor blink rate one field after values are changed Character blink rate

Split screen interrupt row Change anytime prior to line zero of desired row

Character rows per screen Change only during vertical blanking period

Vertical front porch Change prior to first line of VFP

Vertical back porch Change prior to fourth line after VSYNC

Screen start register Change prior to the horizontal blanking interval of the last line of character row before row where new value is to be used Signetics 2.49 MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC) SCN2672

DISPLAY CONTROL REGISTERS The sequential operation described above refreshing continues from the display buffer There are nine registers in this group, each will be modified upon the occurence of ei- first address. ther of two events. First, if during the incre- with an individual address. Their formats are Cursor Address Registers illustrated in figure 15. The command regis- menting of the memory address counter the The contents of these registers defines the ter is used to invoke one of 16 possible 'display buffer last address' (1R9[7:4]) is buffer memory address of the cursor. If en- PVTC commands as described in the COM- reached, the MAC will be loaded from the abled, the cursor output will be asserted MANDS section of this data sheet. The re- 'display buffer first address' register when the memory address counter matches maining registers in the group store address (IR9[3:0], IR8[7:0]) at the next character the value of the cursor address registers. values which specify the cursor and buffer clock. Sequential operation will then resume The cursor address registers may be read pointer locations, the location of the first starting from this address. This wraparound or written by the CPU or incremented via the character to be displayed on the screen, operation allows portions of the display buff- 'increment cursor address' command. In in- and the location of a light pen 'hit'. With the er to be used for purposes other than stor- dependent buffer mode, these registers de- exception of the light pen register, the user age of displayable data and is completely fine a buffer memory address for PVTC con- initializes these registers after powering on automatic without any CPU intervention (see trolled access in response to 'read / write at the system and changes their values to configure 16a). cursor with/without increment' commands, trol the data which is displayed. The sequential row to row addressing can or the first address to be used in executing Screen Start Registers also be modified under CPU control. If the the 'write from cursor to pointer' command. contents of the screen start register (upper, The screen start registers contain the ad- lower, or both) are changed during any char- Display Pointer Address Registers dress of the first character of the first row acter row (say row 'n'), the starting address These registers define a buffer memory ad- (upper left corner of the active display). At of the next character row (row 'n + 1') will dress for PVTC controlled accesses in re- the beginning of the first scan line of the first be the new value of the screen start register sponse to 'read / write at pointer' com- row, this address is transferred to the row and addressing will continue sequentially mands. They also define the last buffer start register (RSR) and into the memory from there. This allows features such as memory address to be written for the 'write address counter (MAC). The counter is then split screen operation, partial scroll, or sta- from cursor to pointer' command. advanced sequentially at the character rate tus line display to be implemented. The split the number of times programmed into the screen interrupt feature of the PVTC is use- Light Pen Address Registers active characters per row register (IR5), If the light pen input is enabled, these regis- ful in controlling this type of operation. Note thus reaching the address of the last char- ters are used to store the current character that in order to obtain the correct screen acter of the row plus one. At the beginning of display, the screen start register must be address upon receipt of a light pen strobe each subsequent scan line of the first row, input. Several sources of delay between the reloaded with the original value prior to the the MAC is reloaded from the RSR and the display of a character upon the screen and end of the vertical retrace. See figure 16b. above sequence is repeated. At the end of the receipt of a light pen hit can be expected the last scan line of the first row, the con- During vertical blanking the address counter to exist in a system environment. These de- tents of the MAC is loaded into the RSR to operation is modified by stopping the auto- lays include address pipelining in the char- serve as the starting memory address for matic load of the contents of the RSR into acter generation circuits, delays in the video the second character row. This process is the counter, thereby allowing the address generation circuits, and delays in the light repeated for the programmed number of outputs to free—run. This allows dynamic detection circuitry itself. These delays rows per screen. Thus, the data in the dis- memory refresh to occur during the vertical cause the value stored in the light pen regis- play memory is displayed sequentially start- retrace interval. The refresh addressing ter to differ from the actual address of the ing from the address contained in the screen starts at the last address displayed on the character at which the light pen hit actually start register. After the ensuing vertical re- screen and increments by one for each char- was detected. Software must be used to trace interval, the entire process repeats acter clock during the retrace interval. If the correct this condition. again. display buffer last address is encountered,

13117 • BITS • BITS • 1311A • BIT3 • BIT2 • ern • BITS COMMAND CODE

Sot COMMANDS section 1 of command Hod.

• COMMAND REGISTER (WM* only)

BIT7 • BITS • BITS • BIT4 • BIT3 • BIT2 • 13111 • BITO 177 • BITS • BITS • RITA • BITS • 33112 • 13171 • BITO UPPER REGISTER LOWER REGISTER (LSB'el H'0000' = 0 H'0001' = 1 Not us•d MS8'• Note: MS13.• aro In UNA, Register [5:01 H'3FFE' = 16,382 H'3FFF' = 18,383 • • • • • • SCREEN START REGISTERS (READ AND WRITE) CURSOR ADDRESS REGISTERS (READ AND WRITE) POINTER ADDRESS REGISTER (WRITE ONLY) UGHT PEN ADDRESS REGISTER (READ ONLY)

Figure 15. Display Control Register Formats

2.50 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC) SCN2672

INTERRUPT/STATUS REGISTERS The interrupt and status registers provide information to the CPU to allow it to interact with the PVTC to effect desired changes to DISPLAY BUFFER START implement various display operations. The interrupt register provides information on BOTTOM OF SCREEN ...- five possible interrupting conditions, as shown in figure 17. These conditions may be selectively enabled or disabled (masked) from causing interrupts by certain PVTC commands. An interrupt condition which is SCREEN START enabled (mask bit equal to one) will cause the INTR output to be asserted and will MONITOR cause the corresponding bit in the interrupt DISPLAY .- DISPLAY BUFFER END register to be set upon occurrence of the interrupting condition. An interrupt condition which is disabled (mask bit equal to zero) 16K has no effect on either the INTR output or MEMORY the interrupt register. (al DISPLAY MEMORY WRAPAROUND The status register provides six bits of status information: the five possible interrupting conditions plus the NOT BUSY bit. For this register, however, the contents are not DISPLAY BUFFER START effected by the state of the mask bits. BOTTOM OF SCREEN Descriptions of each interrupt /status regis- SCREEN START 1 ter bit follow. Unless otherwise indicated, a bit, once set, will remain set until reset by the CPU by issuing a 'reset interrupt /status SPLIT SCREEN A bits' command. The bits are also reset by a 'master reset' command and upon power—up.

SR[5] — RDFLG SCREEN START 2 This bit is present in the status register only. A zero indicates that the PVTC is currently MONITOR DISPLAY executing the previously issued command. A DISPLAY BUFFER END one indicates that the PVTC is ready to accept a new command. 16K MEMORY I/SR[4] — VBLANK (hi DISPLAY MEMORY SPLIT SCREEN WITH WRAPAROUND Indicates the beginning of a vertical blanking interval. Is set to a one at the beginning of Figure 16. Display Addressing Operation the first scan line of the vertical front porch. I/SR[3] — Line Zero Is set to a one at the beginning of the first scan line (line 0) of each active character BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO row. LINE SPLIT LIGHT I/SR[2] — Split Screen RDFLG VBLANK ZERO SCREEN READY PEN This bit is set when a match occurs between Not used 0 = Busy 0 = No 0 = No 0 = No 0 = Busy 0 = No the current character row number and the always read as 0 1 = Ready 1 = Yes 1 = Yes 1 = Yes 1 = Ready 1 = Yes value contained in the split screen interrupt register, IR10[6:0). The equality condition is only checked at the beginning of line zero of NOTE 'Statue register only. Always 0 when reading interrupt register. each character row. This bit is reset when either of the screen start registers is loaded Figure 17. Interrupt and Status Register Format by the CPU.

I/SR[1] — Ready command should be invoked until the prior register have been updated. This bit will be Certain PVTC commands affect the display command is completed. reset when either of the light pen registers is and may require the PVTC to wait for a read. blanking interval before enacting the com- I/SR[0] — Light Pen mand. This bit is set to one when execution A one indicates that a light pen hit has oc- of the command has been completed. No curred and that the contents of the light pen Signetics 2.51 MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC) SCN2672

COMMANDS Table 3 PVTC COMMAND FORMATS The PVTC commands are divided into two D7 D6 D5 D4 D3 D2 D1 DO COMMAND classes: the instantaneous commands, which are executed immediately after they Instantaneous Commands: are invoked, and the delayed commands 0 0 0 0 0 0 0 0 Master reset which may need to wait for a blanking inter- 000 1 V V VV Load IR pointer with value V (V = 0 to 10) val prior to their execution. Command for- 0 0 1 d d d 1 01 Disable light pen mats are shown in table 3. The commands 0 0 1 d d d 1 12 Enable light pen are asserted by performing a write oper- 0 0 1 d 1 N d 01 Display off. Float DADD bus if N= 1 ation to the command register with the ap- 0 0 1 d 1 N d 12 Display on: Next field (N = 1) or scan line propriate bit pattern as the data byte. (N = 0) Instantaneous Commands 0 0 1 1 d d d 01 Cursor off The instantaneous commands are executed 0 0 1 1 d d d 12 Cursor on immediately after the trailing edge of the WR 0 1 0 N N N N N Reset interrupt /status: Bit reset where N= 1 pulse during which the command is issued. 1 0 0 N N N N N Disable interrupt: Disable where N= 1 These commands do not affect the state of 0 1 1 N N N N N Enable interrupt: Enables interrupts and resets the RDFLG or READY interrupt /status bits. V L S R L the corresponding interrupt/status bits where However, a command should not be invoked B Z S D P N = 1 if the RDFLG bit is low. Delayed Commands: Hex

Master Reset 1 0 1 0 0 1 0 0 A4 Read at pointer address This command initializes the PVTC and may 1 0 1 0 0 0 1 0 A2 Write at pointer address be invoked at any time to return the PVTC to 1 0 1 0 1 0 0 1 A9 Increment cursor address its initial state. Upon power—up, two 1 0 1 0 1 1 0 0 AC Read at cursor address successive master reset commands must 1 0 1 0 1 0 1 0 AA Write at cursor address be applied to release the PVTC's internal 1 0 1 0 1 1 0 1 AD Read at cursor address and increment power on circuits. In transparent and shared address buffer modes, the CNTRL 1 input must be 1 0 1 0 1 0 1 1 AB Write at cursor address and increment high when the command is issued. The com- address mand causes the following: 1 0 1 1 1 0 1 1 BB Write from cursor address to pointer address

1. VSYNC and HSYNC are driven low for the NOTES duration of RESET and BLANK goes high. 1. Any combination of these three commands is valid. BLANK remains high until a 'display on' 2. Any combination of these three commands is valid. command is received. 3. d = don't care. 2. The interrupt and status bits and masks be optionally placed in the three—stale con- are set to zero, except for the RDFLG flag Disable Interrupts dition by setting bit 2 to a '1' when invoking which is set to a one. Sets the interrupt mask to zeros for the des- the command. 3. The transparent mode, cursoroff, display ignated conditions, thus disabling these off, and light pen di:Able states are set. conditions from asserting the INTR output. 4. The initialization register pointer is set to Display On Bit position correspondence is as above. address IRO. Restores normal blanking operation either at the beginning of the next field (bit 2 = 1) Enable Interrupts Load IR Address or at the beginning of the next scan line (bit Resets the selected interrupt and status This command is used to preset the 2 = 0). Also returns the DADDO—DADD13 register bits and writes the associated inter- initialization register pointer with the value drivers to their active state. rupt mask bits to a one. This enables the 'V' defined by D3—D0. Allowable values are corresponding conditions to assert the INTR Oto 10. Cursor Off output. Bit position correspondence is as above. Enable Light Pen Disables cursor operation. Cursor output is placed in the low state. After invoking this command, receipt of a Delayed Commands light pen strobe input will cause the light pen Cursor On This group of commands is utilized for the register to be loaded with the current buffer independent buffer mode of operation, al- Enables normal cursor operation. memory address and the corresponding in- though the 'increment cursor' command can terrupt and status flag to be set. Once load- Reset Interrupt/Status Bits also be used in other modes. With the ex- ed, further loads are inhibited until either ception of the 'write from cursor to pointer' This command resets the designated bits in one of the light pen registers are read or a and 'increment cursor' commands, all the the interrupt and status registers. The bit reset function is performed. commands of this type will be executed im- positions correspond to the bit positions in mediately or will be delayed depending on the registers: Disable Light Pen when the command is invoked. If invoked Light pen hits will not be recognized. Bit 0 — Light pen during the active screen time, the command Bit 1 — Ready is executed at the next horizontal blanking Display Off Bit 2 — Split screen interval. If invoked during a vertical retrace Asserts the BLANK output. The DADDO thru Bit 3 — Line zero interval or a 'display off' state, the command DADD13 display address bus outputs may Bit 4 — Vertical blank is executed immediately.

2-52 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC) SCN2672

The 'increment cursor' and 'write from RDFLG status flag should be used for Read/Write at Cursor and cursor to pointer' commands are executed handshaking control between the PVTC and Increment immediately after they are issued. 'Incre- CPU when using these commands. Transfers data between the display buffer ment cursor' requires approximately three and the bus interface latch using the ad- CCLK periods for completion. 'Write from Read/Write at Pointer dress contained in the cursor register and cursor to pointer' asserts the BLANK output Transfers data between the display buffer then adds one (modulo 16K) to the cursor during its execution. BLANK will not be re- and the bus interface latch using the ad- address register. leased until the beginning of the vertical dress contained in the pointer register. blanking interval following the last write op- Write from Cursor to Pointer eration. A second 'write from cursor to point- Read/Write at Cursor Writes the data contained in the bus inter- er' command should not be issued until this Transfers data between the display buffer face latch into the block of display memory time. and the bus interface latch using the ad- designated by the the cursor address and In all cases, the PVTC will assert the dress contained in the cursor register. pointer address registers, inclusive. After READY /RDFLG status to signify completion completion of the command, the pointer ad- of the command. No other commands should Increment Cursor dress will be unchanged, but the cursor reg- be given until the current command is com- Adds one (modulo 16K) to the cursor ad- ister contents will be equal to the pointer pleted. Therefore, the READY interrupt or dress register. address.

ABSOLUTE MAXIMUM RATINOSI

PARAMETER RATING UNIT

Operating ambient temperature2 0 to +70 oc Storage temperature —65 to +150 °C All voltages with respect to ground, —0.5 to +6.0 V

DC ELECTRICAL CHARACTERISTICS TA = 0 °C to + 70°C, Vcc = 5.0V ± 5%45,6

LIMITS PARAMETER TEST CONDITIONS UNIT Min Typ Max

VIL Input low voltage 0.8 V VIH Input high voltage 2.0 V VOL Output low voltage lot_ = 2.4mA 0.4 V VOH Output high voltage (except INTR output) 10H = — 200pA 2.4 V ill Input leakage current VIN = 0 to VCC —10 10 µA ILL Data bus 3—state leakage current Vo = 0 to VCC —10 10 µA 100 INTR open drain output leakage current Vo = 0 to VCC 10 µA ICC Power supply current 160 mA

NOTES See next page.

Signetics 2.53 MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC) SCN2672

AC ELECTRICAL CHARACTERISTICS TA= 0°0 to + 70°C, Vcc= 5.0V -± 5% 4'5'6'7'8 LIMITS PARAMETER TEST CONDITIONS 2.7MHz 4.0MHz UNIT Min Max Min Max

Bus Timing (Fig. 18)9 tAS A0-A2 setup time to WR, RD low 30 30 ns tAH A0-A2 hold time from WR, RD high 0 0 ns tcs CE setup time to WR, RD low 0 0 ns tcH CE hold time from WR, RD high 0 0 ns tRw WR, RD pulse width 250 250 ns tDD Data valid after RD low 200 200 ns tDF Data bus floating after RD high 100 100 ns tin Data setup time to WR high 150 150 ns tDH Data hold time from WR high 10 5 ns tcc High time from CE to CE1° Consecutive commands 600 600 ns Other accesses 300 300 ns CCLK Timing (Fig. 19) tccp CCLK period 370 250 ns tccH CCLK high time 125 100 ns tccL CCLK low time 125 100 ns tccip Output delay from CCLK edge DADDO-13, MBC 40 175 40 150 ns BLANK, HSYNC, VSYNC/CSYNC, CURSOR, BEXT, BREQ, BACK, BCE, WDB, RDB11 40 225 40 200 ns Other Timings (Fig. 20) tRDL READY/RDFLG low from WR high9 tccp tccp + 30 + 30 ns tBAK BACK high from PBREQ low 225 200 ns twcr BEXT high from PBREQ high 225 200 ns tLpS Light pen strobe setup time to CCLK low 120 120 ns tLpH Light pen strobe hold time from CCLK low — 10 — 10 ns tIRL INTR low from CCLK low 225 200 ns tlfili INTR high from WR, RD high9 600 600 ns NOTES 6. Typical values are at +25°C, typical supply voltages and typical processing 1. Stresses above those listed under Absolute Maximum Ratings may cause perma- parameters. nent damage to the device. This is a stress rating only and functional operation of 7. For testing, all input signals swing between 0.4V and 2.4V with a transition time of the device at these or at any other condition above those in the operation section 2Ons maximum. All time measurements are referenced at input voltages of 0.8V of this specification is not implied. and 2.0V and output voltages of 0.8V and 2.0V as appropriate. 2. For operating at elevated temperatures, the device must be derated based on 8. Test condition for outputs: CL = 150pF. +150°C maximum junction temperature. 9. Timing is illustrated and specified referenced to WR and RD inputs. Device may 3. This product includes circuitry specifically dsigned for the protection of its inter- also be operated with CE as the 'strobing' input. In this case, all timing specifica- nal devices from damaging effects of excessive static charge. Nonetheless, it is tions apply referenced to falling and rising edges of CE. suggested that conventional precautions be taken to avoid applying voltages 10. This specification requires that the CE input be negated (high) between read greater than the rated maxima. and/or write cycles. 4. Parameters are valid over specified temperature range. 11. 13"CT, WDB, and RDB delays track each other within 10nsec. Also, these output 5. All voltage measurements are referenced to ground (GND). delays will tend to follow direction (min/max) of DADDO-13 delays.

2.54 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC) SCN2672

AO-A2 x +V— tAH

H +cc tCS tCH tRW

tOF tDD

DO-D7 FLOAT VALID FLOAT (READ)

tDS tDH

DO-D7 VALID (WRITE)

Figure 18. Bus Timing

CCLK

NOTES 1. DADDO-DADD13, BLANK, HSYNC, CSVNC/VSYNC, CURSOR, MKT. BRED, BCE, OUTPUTS MBC, BACK (NOTE 1) 2. BCE changes state on both CCLK edges—(see Figures 3 and 4).

WDB,C UTP R DUBT, SBCE ).=

Figure 19. CCLK Timing

Signetics 2.55 MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC) SCN2672

VERTICAL BLANK BLANKING INTERVAL

FIRST HSYNC HSYNC OF VBLANK 2 /

MANX STATUS BIT

iFTK

BLANK

DAD03- DADO13

LINE ZERO AND SPLIT SCREEN STATUS BITS

TLPS

LIGHT PEN STATUS BIT

TIRL

INTR

DADOO- CIADDI3

Figure 20. Other Timings

2.56 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC) SCN2672

FOR A DDELAYED COMMAND _TRDL r READY OR RDFLG STATUS BITS

PBREO 22 TBAK 22 TBXT BACK

BEXT —22

WR OR TS WHICH RESETS ---- INTERRUPT TIRH

INTR

Figure 21. Other Timings

EVEN FIELD

LAST FIRST DISPLAYED SCAN DISPLAYED SCAN OF EVEN FIELD VERTICAL FRONT PORCH VERTICAL SYNC PULSE VERTICAL BACK PORCH OF PREVIOUS FIELD HORIZONTAL SYNC /PULSES CSYNCL j1--F

BLANK r--22 VERTICAL BLANKING INTERVAL

ODD FIELD FIRST DISPLAYED SCAN LAST DISPLAYED SCAN OF ODD FIELD BACK PORCH-1/2 H OF EVEN FIELD VERTICAL FRONT PORCH-1 H VERTICAL SYNC PULSE VERTICAL BACK 1/2 Hk—

CSYNC_MIL

1/2 HORIZONTAL SYNC-.- H PERIOD

VERTICAL BLANKING INTERVAL

NOTES HORIZONTAL BLANKING INTERVAL 1. In non-interlaced operation the even field is repeated continuously, and the odd field is not.

2. In interlaced operation the even field alternates with the odd field.

Figure 22. Composite Sync Timing

Signetics 2.57 MICROPROCESSOR DIVISION JANUARY 1983 VIDEO ATTRIBUTES CONTROLLER (VAC) SCB2673

DESCRIPTION FEATURES PIN CONFIGURATION The Signetics 2673A and 2673B Video At- • 25MHz video dot rate tributes Controllers (VAC) are bipolar LSI • Three level current driven (75 ohms) VBB devices designed for CRT terminals and video output VCC display systems that employ raster scan • Three level encoded TTL video outputs D3 02 techniques. Each contains a high speed • Character/field attribute logic D4 D1 video shift register, field and character Reverse video 05 DO attributes logic, attribute latch, cursor for- Character blank mat logic and half dot shift control. Character blink DB CLLR The VAC provides control of visual attri- Underline D7 CCO butes on a field or character by character. Highlight D8 CC1 Light pen strike-thru or graphics Internal logic preserves field attribute data 09 CC2 from character row to character row so control DCLK that an attribute byte is not required at the • Field attributes extend from row to row RESET beginning of each row. The 2673B provides • Light or dark field BKG ND CBLANK • Cursor reverse video logic for reverse video, blank (non-display), ACD TTLVID1 blink, underline and highlight attributes • Up to 10 dots per character AMODE TTLVID2 and a graphics mode attribute to work in • Composite blanking for light field conjunction with the Signetics 2670 Dis- retrace AFLG VIDEO play Character and Graphics Generator • Optional field graphics control output CURSOR HOOT • High speed bipolar design (DCGG). The 2673A substitutes a light pen BLANK ABLANK (strike-thru) attribute for the graphics • 40 pin dual in-line package attribute. • TTL compatible UL ABLINK • Compatible with Signetics 2672 PVTC BLINK AUL The horizontal dot frequency is the basic and 2670 DCGG timing input to the VAC. Internally, this LL AHILT clock is divided down to provide a charac- APPLICATIONS LPUGMD ARVID ter clock output for system synchroniza- • CRT terminals GND ALTPENIAGM tion. Up to ten bits of video dot data are • Word processing systems parallel loaded into the video shift register • Small business computers TOP VIEW on each character boundary. The video data is shifted out on three outputs at the ORDERING CODE dot frequency. On the VIDEO output, the Vcc = 5V ± 5%, TA -, 0°C to 70°C data is presented as a three level signal representing low, medium and high inten- PACKAGES GRAPHICS ATTRIBUTE LIGHT PEN ATTRIBUTE sities. The three intensities are also en- 25MHz 18MHz 25MHz 18MHz coded on two TTL compatible video outputs. Light or dark screen background can Ceramic DIP SCB2673BC5140 SCB2673BC8140 SCB2673AC5140 SCB2673AC8140 be selected. Plastic DIP SCB2673BC5N40 SCB2673BC8N40 SCB2673AC5N40 SCB2673AC8N40 BLOCK DIAGRAM

VIDEO ATTRIBUTES CONTROLLER

CCD CHARACTER CCI CLOCK CCLK CC2 COUNTER

DCLK

10 DOT VIDEO SHIFT DATA 3-LEVEL DO-D9 REGISTER DRIVER VIDEO —12 BITS— VIDEO AND TTL TTLVID1 HDOT ATTRIBUTE DRIVERS TTLVID2 HIERARCHY CURSOR LOGIC ARVID ABLANK BKGND ABLINK CBLANK AHILT AUL ATTRIBUTE AND ALTPENIAGM CURSOR CONTROL AFLG LOGIC AND BLANK AMODE PIPELINE RESET ACD VCC BLINK VBB UL GND LL LPUGMD

2-58 Signetics MICROPROCESSOR DIVISION JANUARY 1983 VIDEO ATTRIBUTES CONTROLLER (VAC) SCB2673

PIN DESIGNATION MNEMONIC PIN NO. TYPE NAME AND FUNCTION DCLK 32 I Dot Clock: Dot frequency input. Video output shift rate. CCLK 36 0 Character Clock: A submultiple of DCLK. The frequency ranges from one sixth to one twelfth of DCLK, as determined by the state of the CCO-CC2 inputs. CC2-CC0 33-35 I Character Clock Control: The logic state on these three static inputs determine the internal divide factor for the CCLK output rate. Character clock rates of 6 thru 12 dots per character may be specified. DO-D9 37-39,2-8 I Dot Data Input: These are parallel inputs corresponding to the character/graphic symbol dot data for a given scan line. These inputs are strobed into the video shift register on the falling edge of each character clock. HDOT 27 I Half Dot Shift: When this input is high, the serial video output is delayed by one half dot time. This input is latched on the falling edge of each character clock. CURSOR 14 I Cursor Timing: This input provides the timing for the cursor video. When high, effectively reverses the intensities of the video and attributes. Cursor position, shape, and blink rate are controlled by this input. BKGND 10 I Background Intensity: Specifies light or dark video during BLANK and character fields. Affects the intensities of all attributes. BLANK 15 I Screen Blank: When high, this input forces the video outputs to the level specified by the BKGND input (either high or low intensity). Not effective when CBLANK is high. CBLANK 31 I Composite Blank: Used with the TTL video outputs only. When high, this input forces the video outputs to a low intensity state for retrace blanking. When BKGND input is low, or when using video outputs, this input may be tied low. ARVID 22 I Reverse Video Attribute: The intensity of the associated character or field video is reversed. All other attributes are effectively reversed. AHILT 23 I Highlight Attribute: All dot video (including underline) of the associated character or field is highlighted with respect to the BKGND input and the reverse video attribute. ABLANK 26 I Blank Attribute: Generates a blank space in the associated character or field. The blank space intensity is determined by the BKGND input, the reverse video attribute, and the CURSOR input. ABLINK 25 I Blink Attribute: The associated character or field video is driven to the intensity determined by BKGND and the reverse video attribute when the BLINK input is high. AUL 24 I Underline Attribute: Specifies a line to be displayed on the character or field. The line is specified by the UL input. All other attributes apply to the underline video. ALTPEN/ AGM 21 I Light Pen Attribute (2673A): Specifies a highlighted fine to be displayed on the character or field. The line is specified by the LPL input. I Attribute Graphics Mode (2673B): This input is latched and synchronized to provide a field GM D output for the 2670 DCGG. AMODE 12 I Attribute Mode: Specifies character (AMODE = 0) or field (AMODE = 1) attributes mode. AFLG 13 I Attributes Flag: The VAC samples and latches the attributes inputs when this input is high. If field attributes are specified (AMODE = 1), the attributes are double buffered on a row basis. Thus, each scan line of every character row will start with the attributes that were valid at the end of the previous row. ACD 11 I Attribute Control Display: In field attributes mode (AMODE = 1), if ACD = 0, the first character in each new attribute field (the attribute control character) will be suppressed and only the attributes will be displayed. If ACD = 1, the first character and the attributes are displayed. This input has no effect in character mode (AMODE = 0).

Signetics 2.59 MICROPROCESSOR DIVISION JANUARY 1983 VIDEO ATTRIBUTES CONTROLLER (VAC) SCB2673

PIN DESIGNATION (continued) MNEMONIC PIN NO. TYPE NAME AND FUNCTION BLINK 17 I Blink: This input is sampled on the falling edge of BLANK to provide the blink rate for the character blink attribute. It should be a submultiple of the frame rate. UL 16 I Underline: Indicates the scan line(s) for the underline attribute. Latched on the falling edge of BLANK. LPL / GMD 19 I Light Pen Line (2673A): Indicates the scan line(s) for the light pen strike-thru attribute. Latched on the falling edge of BLANK. 0 Graphics Mode (2673): This output provides a synchronized, latched, field graphics mode corresponding to the AGM input. This output can be used to control the GM input on the 2670 DCGG. LL 18 I Last Line: Indicates the last scan line of each character row. Used internally to extend field attributes across row boundaries. Latched on the falling edge of BLANK. This input has no effect in character mode (AMODE = 0). VIDEO 28 0 Video: A three level serial video output which corresponds to the composite dot pattern of characters, attributes and cursor. TTLVID1 30 0 TTL Video 1: This output corresponds to the serial, non-highlighted video dot pattern. TTLVID2 29 0 TTL Video 2: This output corresponds to the highlighted serial video dot pattern. Should be used with TTLVID1 to decode a composite video of three intensities. RESET 9 I Manual Reset: This active high input initializes the internal logic and resets the attribute latches. VCC 40 I Power Supply: +5 Volts ± 5./o VBB 1 I Bias Supply: See figure 13. GND 20 I Ground: OV reference

FUNCTIONAL DESCRIPTION CCLK The VAC consists of four major sections (see block diagram). The high speed dot CC2 CC1 CCO DOTS/CHARACTER DUTY CYCLE clock input is divided internally to provide 0 0 0 6 3/3 a character clock for system timing. The 0 0 1 6 3/3 parallel dot data is loaded into the video 0 1 0 7 4/3 shift register on each character boundary 0 1 1 8 4/4 and shifted into the video logic block at 1 0 0 9 5/4 the dot rate. The six attribute inputs are 1 0 1 10 5/5 latched internally and combined with the 1 1 0 11 6/5 serial dot data to provide a three level 1 1 1 12 6/6 video source for the monitor. A separate BLANK input defines the ac- For the latter case, raster retrace video always shifted out before DO. For 12 dots/ tive screen area. When BLANK= 0, the suppression is accomplished by raising character, a 0 is also shifted out after D9. video levels are derived internally by the the BKGND input during horizontal and The serial dot data is shifted into the video combinations of dot data, attributes, cur- vertical retrace intervals. For black back- logic where it is combined with the cursor sor, and the state of the BKGND input. ground, tie BKGND high. Tie CBLANK in- and attributes to encode three levels of Either black or white background can be put low for both cases. video. selected. Symbols (dot data) are normally gray and can be highlighted to white or Character Clock Counter Attribute and Cursor Control black as shown in figure 1. Note that the The character clock counter divides the The VAC visual attributes capabilities in- VIDEO output is inverted as referenced to frequency on the DCLK input to generate clude: reverse video, character blank, the TTL video outputs. the character clock (CCLK). The divide fac- blink, underline, highlight, and light pen During the inactive screen area (BLANK= tor is specified by the clock control inputs strike-thru. The six attributes and the 1), the video level produced by the TTL out- (CCO-CC2) as shown in the table above. three attribute control inputs (AMODE, puts is either white (BKGND= 1) or black AFLG, and ACD) are clocked into the VAC (BKGND = 0). A separate composite blank Video Shift Register on the falling edge of CCLK. If AFLG is (CBLANK) input is provided to suppress On each character boundary, the parallel high, the attributes are latched internally raster retrace video when white back- data (D0-D9) is loaded into the video shift and are effective for either one character ground is specified. During the inactive register. The data is shifted out least time (AMODE= 0) or until another set of screen area (BLANK = 1), the video level significant bit first (DO) by the DCLK. If attributes is latched (AMODE = 1). The at- produced by the VIDEO output is either 11 or 12 dots/character are specified tributes set is double buffered on a row by black (BKGND= 1) or white (BKGND= 0). (CC2-CCO = 110 or 111), a 0 (blank dot) is row basis internally. Using this technique,

2.60 Signetics MICROPROCESSOR DIVISION JANUARY 1983 VIDEO ATTRIBUTES CONTROLLER (VAC) SCB2673

DCLK

CCLK

VIDEO' G B

TTLVIDI

TTLVID2

REVERSE, NORMAL HIGHLIGHTED REVERSE HIGHLIGHTED GRAY ON BLACK WHITE ON BLACK GRAY ON WHITE BLACK ON WHITE

NOTE 1. W = White G = Gray B = Black Figure 1. Encoded Video Outputs

field attributes can extend across charac- TTLVID2 TTLVID1 INTENSITY ter row boundaries thereby eliminating the necessity of starting each row with an 0 0 Black (or CBLANK) attribute set. 0 1 Gray (on black surround) 1 0 Gray (on white surround) When field attribute mode is selected, 1 1 White (AMODE = 1), the VAC will accommodate two attribute storage configurations. In NOTE one configuration, the attribute control The TTLVIDI output can be used Independently to generate a two level non-highlighted video. data is stored in the refresh RAM, taking the place of the first character code in the Video Logic Symbol video is generated from the dot field to be affected. For this mode, the The serial dot data and the pipelined cur- data inputs D0-D9. ACD input is tied low and blank characters sor and attributes are combined to gener- Underline video is enabled by the AUL will be displayed in the screen positions ate the three level current source on the attribute and is generated when the UL occupied by the attribute data (see figure VIDEO output. The three levels (white, timing input is active. Underline and sym- 10). In the second configuration, (ACD =1), gray, and black) are also encoded on the bol video are always the same intensity. the character codes and attribute data are two TTL compatible outputs TTLVID1 and Strike-thru video is enabled by the ALTPEN presented to the VAC in parallel. In this TTLVID2. The three levels are encoded as mode, dot data is displayed at each shown above. attribute and is generated when the LPL character position (see figure 11). timing input is active. This video is always The video is normally shifted out on the highlighted and takes precedence over the The CURSOR and the attribute input sig- leading edge of the DCLK. When the symbol and underline video. This feature nals are pipelined internally to allow for HDOT input is asserted, the correspond. applies to the 2673A only. system propagations (one CCLK for re- ing dot data is delayed by one-half DCLK. fresh RAM, one CCLK for dot generator). This half dot shifting, when used on Surround video is the absence of symbol, The attribute timing signals BLINK, UL, selected lines of character video, can be underline and strike-thru video or the LPL and LL are clocked into the VAC at the used to effect eye-pleasing character presence of the non-display attributes beginning of each scan line by the falling rounding as shown in figure 2. (ABLANK or ABLINK • BLINK). edge of the BLANK input. Thus, these sig- The relative intensities of the four video nals must be in their proper state at the Attribute Hierarchy components are determined by the re- falling edge of BLANK preceding the scan The video of each character block con- maining attributes (AHILT, ABLANK, line at which they are to be active (see sists of four components as shown in ABLINK, ARVID) and the BKGND and figure 4). figure 3. CURSOR inputs as illustrated in table 1. Signetics 2.61 MICROPROCESSOR DIVISION JANUARY 1983 VIDEO ATTRIBUTES CONTROLLER (VAC) SCB2673

1 1 1 1 1 1 H1111 SYMBOL VIDEO 0000 H 0000 SURROUND 0 0 0 0 0 VIDEO 0 00 H 0 0 0

0 0 0 0 0 LIGHT PEN H STRILE THRU 0 0 0 o o 0 VIDEO 0 0 0 0 0 0 o 000 (2673A only) 0 H 0

000 0000 UNDERLINE VIDEO H = LINES SHIFTED

Figure 2. "AT" Symbol with and without Half Dot Shifting Figure 3. Video Components of Character Block

Table 1 ATTRIBUTES HIERARCHY ATTRIBUTES AND CONTROL INPUTS RELATIVE VIDEO INTENSITIES d = don't care W = White, B = Black, G = Gray STRIKE SYMBOL OR NON- THRU UNDERLINE SURROUND BKGND° REVERSEI DISPLAY2 AHILT VIDE03 VIDE03,4 VIDEOS

0 0 0 0 W G B 0 0 1 W W B 0 1 d B B B

0 1 0 0 B G W 1 0 1 B B W

0 1 1 d W W W 0 0 0 B G W 0 0 1 B B W 0 1 d W W W 1 0 0 W G B 1 0 1 W W B 1 1 d B B B

NOTES I. Reverse = ARVID • CURSOR + ARVID • CURSOR 2. Non-display = ABLANK + ABLINK • BLINK 3. See figure 3 4. Symbol and underline video are always the same intensity. 5. Reverse sense for VIDEO output.

ABSOLUTE MAXIMUM RATINGS'

PARAMETER RATING UNIT Operating ambient temperature2 0 to +70 °C Storage temperature —66 to +150 °C All voltages with respect to ground —0.5 to +6.0 V

2.62 Signetics MICROPROCESSOR DIVISION JANUARY 1983 VIDEO ATTRIBUTES CONTROLLER (VAC) SCB2673

DC ELECTRICAL CHARACTERISTICS TA= 0°C to +70°C, Vcc= 5V ± 5%, Vim= See figure 133,45 LIMITS PARAMETER TEST CONDITIONS UNIT Min Typ Max

VIL Input low voltage 0.8 V Viii Input high voltage 2.0 V

VOL Output low voltage IOL= 4mA 0.4 V (except VIDEO) VOH Output high voltage IcH= — 400pEA 2.4 V (except VIDEO)

VB VIDEO black level RL= 150 ohms to GND 0 V VG VIDEO gray level RL= 150 ohms to GND 0.45 V VW VIDEO white level RL= 150 ohms to GND 0.90 V

IL Input low current VIN = 0.4V —400/ µA —80010 IIH Input high current VIN = 2.4V 20/4010 µA

ICC VCC supply current VIN = OV, VCC = max 80 mA IBB VBB supply current VBB = max 120 mA

AC ELECTRICAL CHARACTERISTICS TA = 0°C to +70°C, Vcc = 5V ±5/, VSB = See figure 133,4,5 LIMITS 25MHz 18MHz PARAMETER TEST CONDITIONS UNIT VERSION VERSION Min Max Min Max Dot clock6 to frequency 25 18 MHz tDid high 15 22 ns tDL low 15 22 ns Setup times to CCLK7 tss BLANK 50 50 ns tsc BLINK, UL, LPL, LL (ref to BLANK) 20 20 ns tsA Attributes 45 55 ns t5D Dot data D0-D9 70 70 ns tSK CURSOR 50 50 ns tFS AFLG 50 65 ns ts+i HDOT 45 55 ns Hold times from CCLK tHC BLINK, UL, LPL, LL (ref to BLANK) 20 20 ns tHA Attributes 20 20 ns tHD Dot data D0-D9 30 30 ns tHK CURSOR 20 20 ns tFH AFLG 30 30 ns tHH HDOT 20 20 ns Setup times to DCLK6 tSG BKGND 15 15 ns tuB CBLANK 15 15 ns Hold times from DCLK6 tHG BKGND 15 15 ns tHB CBLANK 15 15 ns Delay times9 CL = 150pF tDGM GMD from DCLK 65 65 ns toot, CCLK from DCLK 65 65 ns tDV TTLVID1 and TTLVID2 from DCLK 45 75 45 80 ns tDV VIDEO from DCLK 240 240 ns NOTES 3. Parameters are valid over operating temperature range unless otherwise specified. 6. See figure 9. 4. All voltage measurements are referenced to ground (VSs). All input signals swing 7. See figures 4, 5, 6, and 9. between 0.4V and 2.4V. All time measurements are referenced at input voltages of 8. See figure 8. 0.8y, 2.OV and at output voltages of 0.8V, 2.OV as appropriate. 9. See figures 6 and 7 . 5. Typical values are at +25°C, typical supply voltages and typical processing parameters. 10. For DCLK input. 11. CL less than 150pF minimum could be faster. Signetics 2.63 MICROPROCESSOR DIVISION JANUARY 1983

VIDEO ATTRIBUTES CONTROLLER (VAC) SCB2673

CCLK tpo 'BS BLANK VIH VIL 'Sc

BLINK, UL LPL,LL

2nd ATTRIBUTES1 CHAR

tHD

DOT DATA2 DO-D9

1st 2nd LAST VIDE03 BKGND4 I CHAR I CHAR I I CHARLAST-1 I CHAR I BKG91D4

NOTES 1. Attributes include: ABLINK, ABLANK, ARVID, AUL, AHILT, and ALTPEN. 2. One CCLK delay for dot data (obtained from delay through character generator). 3. See figure 7 for detail timing of VIDEO, TTLVID1, TTLVID2. 4. Non-active scan time. VIDEO reverts to polarity selected by the BKGND Input.

Figure 4. VAC Pipeline Timing

CCLK

VIH iSKy1-*--tHK

CURSOR

VIDEO

CHARACTER WITH CURSOR

Figure 5. Cursor Pipeline Timing

2.64 Signetics MICROPROCESSOR DIVISION JANUARY 1983

VIDEO ATTRIBUTES CONTROLLER (VAC) SCB2673

CCLK

tFH

AFLG

VIDEO (AMORE = 0) AFF 1

BLANK CHARACTER IF I ACD = 0 VIDEO 7,72 ii q/l A2 (AMODE= 1) Al V Al % Al % \ A2

GMD1 (AMODE =1)

NOTE 1. GMD output in 2673B version only. See figure 7 for detail timing. Figure 6. Character (AMODE = 0), Field (AMODE =1), and GMD Attribute Timing

1,-1/1D 1 1DH I.— tDL

DCLK

tOC CCLK 00H VOL tDV

VIDEO 1st TTLVID1, 2 E311111011 PIXEL 63111

CHARACTER N —1 CHARACTER N

tDGM

GMD1 NOTE (AMODE =1) 1. GMD output in 26738 version only.

Figure 7. Video and GMD Pipeline Timing

Signetics 2.65 MICROPROCESSOR DIVISION JANUARY 1983 VIDEO ATTRIBUTES CONTROLLER (VAC) SCB2673

DCLK

tSG 22 BKGND

tSB 1HB 22 CBLANK

VIDEO GRAY BLACK GRAY BLACK

Figure 8. BKGND and RBLANK Timing During Inactive Scan Time (Blank =1)

DCLK

CHARACTER N

CCLK VOH VOL 1SH tHH

HDOT VIH —

VIDEO

LAST PIXEL / LAST PIXEL CHAR N —1 CHAR N

FIRST PIXEL CHAR N FIRST PIXEL CHAR N +1

NOTE 1. Half dot shift feature 18MH. maximum.

Figure 9. Half Dot Shift Timing

2.66 Signetics MICROPROCESSOR DIVISION JANUARY 1983

VIDEO ATTRIBUTES CONTROLLER (VAC) SCB2673

TO CRT CONTROLLER

CCLK BLANK DCLK BLINK UL LL r FT A E N a 2673 REFRESH 2870 RAM 7 10 CAO DO DO 2K x8 PAGE 1 CA6 D9 D9 VIDEO GMD GMD

AGM ARVID VCC AHILT AUL 11(11 RAM BYTE FORMAT: ABLINK 7 0 ABLANK AMODE CAUSES 0 I CHAR CODE CHARACTER BYTE AFLG ACD ...L ATTRIBUTES BYTE TO BE DISPLAYED AS A BLANK CHARACTER. 1 I 1 1 1 1 ATTRIBUTE BYTE

AFLG --t I I AGM NOT USED ARVID ABLINK AHILT ABLANK AUL

Figure 10. System Block Diagram of the 2673 in Field Attribute Mode Using the Narrow RAM (8 Wide) Configuration

NOT USED

CHARACTER CODE

TO CRT CONTROLLER

7 0 I I CHARACTER CCLK 1 1 " BYTE BLANK DCLK PikaETI — BLINK UL REFRESH LL 2670 2673 RAM 10 CAO DO 10 2K x8 VIDEO CA6 D9 1:9 NOTE 2 PAGE 1 _J GND GMD VCC

AGM 11(S1 ARVID --1•• AHILT ACD FIELD ATTRIBUTES AUL ABLINK ATTRIBUTE ABLANK RAM AMODE 7 AFLG 1 C4) 2K x8 CHARACTER ATTRIBUTES PAGE 1

7 ATTRIBUTE NOTE 1 1 1 1 1 1 1 1 BYTE 1. For operation in character attribute mode, tie AFLG high. NOT USAEFDLG— _11 AGM 2. In character attribute mode, AGM output from RAM should be ARVID connected directly to the 2670 GMD input. ABLINK AHILT ABLANK AUL

Figure 11. System Block Diagram of the 2673 in Field or Character Attribute Mode Using the Wide RAM Configuration

Signetics 2.67 MICROPROCESSOR DIVISION JANUARY 1983

VIDEO ATTRIBUTES CONTROLLER (VAC) SCB2673

PART OF 2673

VCC VCC 752 752

VCC VCC

TTL DRIVER DRIZ V

Zo =752

75D

Figure 12. Video Output Stages of the 2673

2.68 Signetics MICROPROCESSOR DIVISION JANUARY 1983 ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary

DESCRIPTION FEATURES PIN CONFIGURATION The Signetics SCN2674 Advanced Video • 4MHz character rate Display Controller (AVDC) is a program- • 1 to 256 characters per row mable device designed for use in CRT ter- • 1 to 16 raster lines per character row minals and display systems that employ • 1 to 128 character rows per frame RD VCC raster scan techniques. The AVDC gen- • Bit mapped graphics mode CE A2 erates the vertical and horizontal timing • Programmable horizontal and vertical WR Al signals necessary for the display of inter- sync generators laced or non-interlaced data on a CRT — RS170 compatible sync CTRL1 AO monitor. It provides consecutive address- • interlaced or non•interlaced operation CTRL2 ACLL ing to a user specified display buffer • Up to 84K RAM addressing for CTRL3 TRTR memory domain and controls the CPU- multiple page operation DADDOILG display buffer Interface for various buffer • Readable, writable and incrementable CURSOR DADDII configuration modes. A variety of oper- cursor DO DADD14 ating modes, display formats, and timing — Programmable cursor size and blink DADD2I D1 DADD15 profiles can be implemented by program- • AC line lock D2 DADD3ILR ming the control registers In the AVDC. • Automatic wraparound of RAM D3 DADD4ILAO A minimum CRT terminal system configu- • Automatic split screen ration consists of an AVDC, an SCN2671 • Automatic bidirectional soft scrolling D4 DADDS/LA1 — Programmable scan line Increment Keyboard and Communication Controller DO DADEULA2 • Row table addressing mode (PKCC), an SCN2670 Display Character • Double height tops and bottoms D8 DADD7/LA3 and Graphics Generator (DCGG), an • Double width control output 07 DADD8IFL SCB2675 Color/Monochrome Attributes • Selectable buffer interface modes Controller (CMAC), a single chip micro- CCLK DADDEUDW • Dynamic RAM refresh computer such as the 8048, a display buf- DADDIOIUL • Completely TTL compatible BLANK fer RAM, and a small amount of TTL for VSYNCI • Single + 5 volt power supply DADD111 miscellaneous address decoding, inter- CSYNC BLINK • Power on reset circuit face, and control. Typically, the package NSYNC DADD1210DD count for a minimum system is between OND DADD13ILL APPLICATIONS 15 and 20 devices; system complexity can • CRT terminals be enhanced by upgrading the micro- TOP VIEW • Word processing systems processor and expanding via the system • Small business computers address and data busses. • Home computers

ORDERING CODE Vcc = 5V ±5%, TA = 0° to 70°C PACKAGES 4MHz 2.7MHz Ceramic DIP SCN2674BC4140 SCN2674BC3140 Plastic DIP SCN2674BC4N40 SCN2674BC3N40

Signetics 2.69 MICROPROCESSOR DIVISION JANUARY 1983

ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary

BLOCK DIAGRAM

CE INTERFACE CONTROL CTRL1 DISPLAY RD INITIALIZATION, MEMORY CTRL2 READ/ POINTER HANDSHAKE WR WRITE AND LOGIC CONTROL DISPLAY CTRL3 LOGIC REGISTERS

COMMAND DECODE LOGIC DISPLAY

A0.2/ SCROLL AND ADDRESS DOUBLE HEIGHT DECODER LOGIC 3 INTERRUPT DADD0.13 LOGIC STATUS REGISTER 14 ADDRESS TIMING MULTIPLEXERS INTR

CURSOR AND SCREEN START REGISTERS

DO/ DATA CURSOR BUS 8 DRIVERS CURSOR AND COMPARE LOGIC Vcc

GND

ACLL

HSYNC CCLK TIMING CHAIN CLOCK BUFFER AND VSYNC/CSYNC DECODE LOGIC BLANK

TIMING

2.70 Signetics MICROPROCESSOR DIVISION JANUARY 1983 ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary

PIN DESIGNATION PIN MNEMONIC NO. TYPE NAME AND FUNCTION AO-A2 37-39 I Address Lines: Used to select AVDC internal registers for read/write operations and for commands. DO-D7 8-15 I/O 8-Bit Bidirectional Three-State Data Bus: Bit 0 is the LSB and bit 7 is the MSB. All data, command, and status transfers between the CPU and the AVDC take place over this bus. The direc tion of the transfer is controlled by the RD and WR inputs when the CE input is low. When the CE input is high, the data bus is in the three-state condition. RD 1 I Read Strobe: Active low input. A low on this pin while CE is low causes the contents of the register selected by AO-A2 to be placed on the data bus. The read cycle begins on the leading (falling) edge of RD. WR 3 I Write Strobe: Active low input. A low on this pin while CE is also low causes the contents of the data bus to be transferred to the register selected by AO-A2. The transfer occurs on the trailing (rising) edge of WR. CE 2 I Chip Enable: Active low input. When low, data transfers between the CPU and the AVDC are enabled on D0-D7 as controlled by the WR, RD, and AO-A2 inputs. When CE is high, effectively, the AVDC is isolated from the data bus and DO-D7 are placed in the three-state condition. CCLK 16 I Character Clock: Timing signal derived from the video dot clock which is used to synchronize the AVDC's timing functions. HSYNC 19 0 Horizontal Sync: Active high output which provides video horizontal sync pulses. The timing parameters are programmable. VSYNC/CSYNC 18 0 Vertical Sync/Composite Sync: A control bit selects either vertical or composite sync pulses on this active high output. When CSYNC is selected, equalization pulses are included. The timing parameters are programmable. BLANK 17 0 Blank: This active high output defines the horizontal and vertical borders of the display. Display control signals which are output on DADDO and DADD3 thru DADD13 are valid on the trailing edge of BLANK. CURSOR 7 0 Cursor Gate: This output becomes active for a specified number of scan lines when the address contained in the cursor register matches the address output on DADDO through DADD13 for displayable character addresses. The first and last lines of the cursor and a blink option are programmable. When the row table addressing mode is enabled, this output is active for a portion of the blanking interval prior to the first scan line of a character row, while the AVDC is fetching the starting address for that row. I NTR 35 0 Interrupt Request: Open drain output which supplies an active low interrupt request from any of five maskable sources. This pin is inactive after a power on reset or a master reset command. ACLL 36 I AC Line Lock: If this input is low after the programmed vertical front porch interval, the vertical front porch will be lengthened by increments of horizontal scan line times until this input goes high. CTRL1 4 I/O Handshake Control 1: In independent mode, provides an active low write data buffer (WDB) output which strobes data from the interface latch into the display memory. In transparent and shared modes, this is an active low processor bus request (PBREQ) input which indicates that the CPU desires to access the display memory. CTRL2 5 0 Handshake Control 2: In independent mode, provides an active low read data buffer (RDB) output which strobes data from the display memory into the interface latch. In transparent and shared modes, this is an active low bus external enable (BEXT) output which indicates that the AVDC has relinquished control of the display memory (DADDO-DADD13 are in the three-state condition) in response to a CPU bus request. BEXT also goes low in response to a 'display off and float DADD' command. In row buffer mode, it is an active low bus request (BREQ) output which halts the CPU during a line DMA. CTRL3 6 0 Handshake Control 3: In independent mode, provides the active low buffer chip enable (BCE) signal to the display memory. In transparent and shared modes, provides an active low bus acknowledge (BACK) output which serves as a ready signal to the CPU in response to a processor bus request. In row buffer mode, this is an active high memory bus control (MBC) output which configures the system for the DMA transfer of one row of character codes from system memory to the row display buffer. Signetics 2.71 MICROPROCESSOR DIVISION JANUARY 1983 ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary

PIN MNEMONIC NO. TYPE NAME AND FUNCTION DADDO-DADD13 34-21 0 Display Address: Used by the AVDC to address up to 16K of display memory directly, or to 64K of memory by de-multiplexing DADD14 and DADD15. These outputs are floated at various times depending on the buffer mode. Various control signals are multiplexed on DADDO through DADD13 and are valid at the trailing edge of BLANK. These control signals are: DADDO/LG Line Graphics: Output which denotes bit mapped graphics mode. DADD1/DADD14 Display Address 14: Multiplexed address bit used to extend addressing to 64K. DADD2/DADD15 Display Address 15: Multiplexed address bit used to extend addressing to 64K. DADD3/LR Last Row: Output which indicates the last active character row of each field. DADD4-DADD7/LAO-LA3 Line Address: Provides the number of the current scan line count for each character row. DADD8/FL First Line: Asserted during the blanking interval just prior to the first scan line of each character row. DADD9/DW Double Width: Output which denotes a double width character row. DADD1O/UL Underline: Asserted during the blanking interval just prior to the scan line which matches the programmed underline position (line 0 thru 15). DADD11/BLINK Blink Frequency: Provides an output divided down from the vertical sync rate. DADD12/0DD Odd Field: Active high signal which is asserted before each scan line of the odd field when interlace is specified. Replaces DADD4/LAO as the least significant line address for interlaced sync and video applications. DADD13/LL Last Line: Asserted during the blanking interval just prior to the last scan line of each character row.

Vcc 40 I Power Supply: + 5 volts power input. GND 20 I Ground: Signal and power ground input.

FUNCTIONAL DESCRIPTION permit communications with the micro- Operation Control As shown in the block diagram, the AVDC processor via the data bus buffer. The The operation control section decodes contains the following major blocks: functions performed by the CPU read and configuration and operation commands — Data bus buffer write operations are shown in table 1. from the CPU and generates appropriate — Interface Logic — Operation Control Table 1 AVDC ADDRESSING — Timing A2 Al AO READ (RD .0) WRITE (WITI = 0) — Display Control — Buffer Control 0 0 0 Interrupt register Initialization registers1 0 0 1 Status register Command register Data Bus Buffer 0 1 0 Screen start 1 lower register Screen start 1 lower register The data bus buffer provides the interface 0 1 1 Screen start 1 upper register Screen start 1 upper register between the external and internal data 1 0 0 Cursor address lower register Cursor address lower register busses. It is controlled by the operation 1 0 1 Cursor address upper register Cursor address upper register control block to allow read and write 1 1 0 Screen start 2 lower register Screen start 2 lower register operations to take place between the con- 1 1 1 Screen start 2 upper register Screen start 2 upper register trolling CPU and the AVDC. There are 15 initialization registers which are accessed sequentially via a single address. The AVDC maintains an Interface Logic internal pointer to these registers which is Incremented after each write at this address until the last register (IR14) is accessed. The pointer then continues to point to 1R14 for additional accesses. Upon a powerion or a master The interface logic contains address reset command, the internal pointer is reset to point to the first register (IRO) of the Initialization register group. decoding and read and write circuits to The Internal pointer can also be preset to any register of the group via the 'load IR address pointer' command.

2.72 Signetics MICROPROCESSOR DIVISION JANUARY 1983 ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary

signals to other internal sections to con- The user programs bits 0 and 1 of IRO to from memory to the interface latch and trol the overall device operation. It con- select the mode best suited for the sys- AVDC sets RDFLG status to indicate tains the timing and display registers tem environment. The CNTRL1-3 outputs that the read is completed. which configure the display format and perform different functions for each mode 4. CPU checks RDFLG status to see if operating mode, the interrupt logic, and and are named accordingly in the descrip- operation is completed. the status register which provides operation of each mode. 5. CPU reads data from interface latch. tional feedback to the CPU. Independent Mode Loading the same data into a block of 2 Timing The CPU to RAM interface configuration display memory is accomplished via the The timing section contains the counters for this mode is illustrated in figure 2. 'write from cursor to pointer' command: and decoding logic necessary to generate Transfer of data between the CPU and 1. CPU checks RDFLG status bit to the monitor timing outputs and to control display memory is accomplished via a assure that any delayed commands the display format. These timing param- bidirectional latched port and is con- have been completed. eters are selected by programming of the trolled by read data buffer (RDB), write 2. CPU loads data to be written to display initialization registers. data buffer (1NDB), and buffer chip enable memory into the interface latch. (BCE). This mode provides a non- 3. CPU writes beginning address of Display Control contention type of operation that does not memory block into cursor address The display control section generates require address multiplexers. The CPU register and ending address of block linear addressing for up to 16K bytes of does not address the memory directly— into pointer address register. display memory. Internal comparators the read or write operation is performed at 4. CPU issues 'write from cursor to limit the portion of the memory which is the address contained in the cursor ad- pointer' command. displayed to programmed values. Addi- dress register or the pointer address 5. AVDC generates control signals and tional functions performed in this section register as specified by the CPU. The outputs block addresses to copy data include cursor positioning and address AVDC enacts the data transfers during from the interface latch into the speci- comparisons required for generation of blanking intervals in order to prevent fied block of memory. timing signals, double height tops and visual disturbances of the displayed data. 6. AVDC sets RDFLG status to indicate bottoms, smooth scrolling, and the split that the block write is completed. The CPU manages the data transfers by screen interrupts. supplying commands to the AVDC. The Similar sequences can be implemented on Buffer Control commands used are: an interrupt driven basis using the READY The buffer control section generates three 1. Read/write at pointer address. interrupt output to advise the CPU that a signals which control the transfer of data 2. Read/write at cursor address (with previously asserted delayed command has between the CPU and the display buffer optional increment of address). been completed. memory. Four system configurations re- 3. Write from cursor address to pointer quiring four different 'handshaking' address. Two timing sequences are possible for the schemes are supported. These are 'read/write at cursor/pointer' commands. The operational sequence for a write described below. If the command is given during the active operation is: display window (defined as first scan line 1. CPU checks RDFLG status bit to of the first character row to the last scan assure that any delayed commands line of the last character row), the opera- have been completed. SYSTEM CONFIGURATIONS tion takes place during the next horizontal CPU loads data to be written to display Figure 1 illustrates the block diagram of a 2. blanking interval, as illustrated in figure 3. memory into the interface latch. typical display terminal using the If the command is given during the vertical CPU writes address into cursor or Signetics SCN2670, SCN2671, SCN2674, 3. blanking interval, or while the display has and SCB2675 CRT terminal devices. In pointer registers. been commanded blanked, the operation CPU issues 'write at cursor with/ this system, the CPU examines inputs 4. takes place immediately. In the latter without increment' or 'write at pointer' from the data communications line and case, the execution time for the command the keyboard and places the data to be command. is approximately five character clocks (see displayed in the display buffer memory. 5. AVDC generates control signals and figure 4). This buffer is typically a RAM which holds outputs specified address to perform requested operation. Data is copied the data for a single or multiple screen- Timing for the 'write from cursor to from the interface latch into the load (page) or for a single character row. pointer' operation is shown in figure 5. memory. The AVDC supports four common system The memory is filled at a rate of one loca- 6. AVDC sets RDFLG status to indicate configurations of display buffer memory, tion per two character times. The com- that the write is completed. designated the independent, transparent, mand will execute only during blanking in- shared, and row buffer modes. The first Similarly, a read operation proceeds as tervals and may require many horizontal or three modes utilize a single or multiple follows: vertical blanking intervals to complete. page RAM and differ primarily in the 1. Steps 1 and 3 as above. Additional delayed commands can be means used to transfer display data be- 2. CPU issues 'read at cursor with/ asserted immediately after this command tween the RAM and the CPU. The row buf- without increment' or 'read at pointer' has completed. fer mode makes use of a single row buffer command. (which can be a shift register or a small 3. AVDC generates control signals and Immediate commands can be asserted at RAM) that is updated in real time to con- outputs specified address to perform any time regardless of the state of the tain the appropriate display data. requested operation. Data is copied ready status/interrupt. Signetics 2.73 CPU 2674 PROGRAM MEMORY DOUBLE CURSOR HEIGHT TIMING LOGIC CHAIN LOGIC MEMORY GENERATOR DATA TIMING SYNC CONTROL MEMORY SCROLL LOGIC SYNC SOFT KEYBOARD INTERFACE KEYBOARD GENERATOR &GRAPHICS LINE DRIVERS & RECEIVERS DATA COMM CHARACTER GENERATOR INTERFACE GRAPHICS REFRESH LOGIC \ RAM Figure 1.CRTTerminal BlockDiagram I CHARACTER 267 MODEM 2670 ATTRIBUTES GENERATOR REGISTER COLOR CLOCK LOGIC VIDEO SHIFT AND ► DATACOMMUNICATIONSLINE VIDEO TIMING&ATTRIBUTES MODULATION CONTROL DOUBLE WIDTH LOGIC VIDEO AND DOT 2675 MONITOR (t O 5 -v 3 ,

.10 0 41. z (OGAV) 213110211N00 AVldSICIO3 IIACOONVACIV

0966 AdVIINNir NoisiniadOSS3 002.1d02101V1 MICROPROCESSOR DIVISION JANUARY 1983

ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary

AVDC REFRESH RAM

DADD DISPLAY ADDRESS ADR

BCE CTRL3 CE WDB CTRL1 WR DATA 110

CTRL2 RDB

> TO DISPLAY DATA BUS VIDEO Z\ LOGIC

OE cp 74LS364 CP 74LS364

RD WR_ FROM CPU FROM CPU

SYSTEM DATA BUS

Figure 2. Indendent Buffer Mode Configuration

CCLK

2 2

2 2 BLANK HORIZONTAL BLANKING INTERVAL

DADI:===

RDB

22 22 WDB

NOTES 1. Write waveforms shown in dotted lines. 2. If command execution occurs just prior to the first scan line of a character row and row table addressing mode is enabled, execution of the command is delayed by two character clocks from the timing illustrated.

Figure 3. Read/Write at Cursor/Pointer Command Timing (Command Received During Active Display Window)

Signetics 2.75 MICROPROCESSOR DIVISION JANUARY 1983

ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary

CCLK

BLANK

OADD AVDC READ COMMANDT-0—. ADDRESS REFRESH ADDRESSES

ROB

woe

Figure 4. ReadlWrite at Cursor/Pointer Command Timing (Command Received While Display is Blanked)

Shared and Transparent row buffer mode. During the first scan line function of the two MSBs of the second Buffer Modes (line 0) of each character row, the AVDC byte is selected by programming. IRO[7]. halts the CPU and DMA's the next row of They may be used either as row attribute In these modes, the display buffer RAM is character data from the system memory to bits to control double width and double a part of the CPU memory domain and is the row buffer memory. The AVDC then height for that character row, or as an ad- addressed directly by the CPU. Both releases the CPU and displays the row ditional two address bits to extend the modes use the same hardware configura- buffer data for the programmed number of usable display memory to 64K. tion with the CPU accessing the display scan lines. The control signal BREQ in- buffer via three-state drivers (see figure 6). The first address of the row table is desig- forms the CPU that character addresses The processor bus request (PBREQ) con- nated in screen start register two (SSR2). and the MBC signal will start at the next trol signal informs the AVDC that the CPU If row table addressing is enabled via falling edge of BLANK. The CPU must is requesting access to the display buffer. IR2[7], and the display is on, the ADVC release the address and data busses In response to this request, the AVDC fetches the next row's starting address before this time to prevent bus conten- raises bus acknowledge (BACK) until its from the table during the blanking interval tion. After the row of character data is bus external (BEXT) output has freed the prior to the first scan line of each char- transferred to the CPU, BREQ returns high display address and data busses for CPU acter row, while simultaneously incremen- to grant memory control back to the CPU. access. BACK, which can be used as a ting the contents of SSR2 by two so as to `hold' input to the CPU, is then lowered to Row Table Addressing Mode point to the next table entry. The fetching indicate that the CPU can access the of the row starting address from the row In this mode, each character row in the buffer. screen image memory has a unique start- table is indicated by the assertion of the. CURSOR output during BLANK. The ad- In transparent mode, the AVDC delays the ing address. This provides greater flexibil- granting of the buffer to the CPU until a ity with respect to screen operations, dress read from the table by the AVDC vertical or horizontal blanking interval, such as editing, than the sequential ad- is loaded into screen start register 1 thereby causing minimum disturbance of dressing mode. The row table, figure 12, is (SSR1) for use internally. Since the con- the display. In shared mode, the AVDC will a list of starting addresses for each char- tents of SSR2 changes as the table entries are fetched, it must be re-initialized to blank the display and grant immediate ac- acter row and may reside anywhere in the cess to the CPU. Timing for these modes AVDC's addressable memory space. Each point to the first table entry during each is illustrated in figures 7, 8, and 9. entry in the table consists of two bytes: vertical retrace interval. the first byte contains the 8 LSBs of the Row table addressing is intended primari- Row Buffer Mode row starting address and the second byte ly for use in conjunction with the row buf- Figures 10 and 11 show the timing and a contains, in its 6 least significant bits, the fer mode of operation and requires no typical hardware implementation for the 6 MSBs of the row starting address. The additional circuitry in that case. It may

2.76 Signetics

T\ £866 1W 1W 210 10 1c 02. 2JOSS30 NOISIAIG

NT NT AdVI

ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) 3 3 a CD W 1=k R O D R o t A 1s SIGNALS SIGNALS AVDC CONTROL 3 RF+4 RF +5 (AVDC CONTROL SIGNALS RF + AVDC CONTROL RF +2 Command Timing COI C11111211 +2 RF RF Pointer to +1 RF Cursor POINTER ADDRESS COMMAND COMPLETION from D / Write CURSOR POINTER ADDRESS +1 ADDRESS —1 Figure 5. HFP = ODD / CURSOR CURSOR ADDRESS ADDRESS+ N LAST ADDR HFP = EVEN LAST LAST ADDR ADDR 0 =1

= WR BCE RDB WDB CCLK DADD DADD DADD BLANK BLANK HSYNC HSYNC BLANK HSYNC NOTE If command execution occurs just priori° the first scan line of a character row and row table addressing mode is enabled, execution of the command is delayed by two character clocks from the timing illustrated. row and row table addressing mode is enabled, execution of the command is delayed by two character clocks from the timing If command execution occurs just priori° the first scan line of a character MICROPROCESSOR DIVISION JANUARY 1983 ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary

REFRESH 2674 RAM AVDC DISPLAY ADDRESS ADR \ CE PERK) CTR L1 CPU WR BACK CTRL3 DATA 110

BEXT CTRL2

DISPLAY DATA BUS 74LS244

74LS245 SELECT FIE) DECODE CPU { LOWER WR

UPPER SYSTEM ADDRESS BUS

SYSTEM DATA BUS S Figure 6. AVDC Shared or Transparent Buffer Modes

(1) i2- PBRE (2) 2 22

22 -22- SEXT (3,4) 22 (1) (2) 22 -22- BLANK HORIZONTAL BLANKING INTERVAL

AVDC CTRL SIGNALS DADD SYSTEM KOORESSESI TO CMAC AND DCG

NOTES t. PBREO must be asserted prior to the rising edge of BLANK in order for sequence to begin during that blanking period.

2 If PBREO is negated after the next to last CCLK of the horizontal blanking interval, the next scan line will also be blanked. 3. Accesses during vertical blank or "display off" are granted only at the beginning of the horizontal front porch. 4. If row table addressing is enabled, CPU access is delayed by two character clocks prior to the first scan line of each character row.

Figure 7. Transparent Buffer Mode Timing

2.78 Signetics MICROPROCESSOR DIVISION JANUARY 1983

ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary

'111111-1._ -22- 22 _J

22 -22- _ I 22 (1) I 22 - ---1 DADD ANYADDRESS CHAR ADDRESSESSYSTEM AVDCTO CMAC CTRL AND SIGNALS DCG 1STADDRESS CHAR.

NOTE 1. If P8RECI is negated after the next to last CCLK of the horizontal blanking interval, the next scan line will also be blanked.

Figure 8. Shared Buffer Mode Timing

lot lbl -1111111-\_PLIII1_ PBFIE PB(irD 22 -22 I I I

WI< B-TI,C1( BERT BERT 22 I VBLANK OR DBLANK BLANK 22

22 SVS ADD SYSTEM PROCESSOR HAS CONTINUOUS BUS CONTROL )— (TC DADA 22 Y.— REFRESH REFRESH ADDRESSES—P.- ADDRESSES a) During Vertical Blank or after 'display off' command in b) After 'display off and 3—state' command shared mode only. See Figure 7 for transparent timing.

Figure 9. Shared and Transparent Mode Timing

Signetics 2.79 MICROPROCESSOR DIVISION JANUARY 1983 ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary

2X2111

2874 ROW AVDC LSBs REFRESH DISPLAY ADDRESS RAM BREO CTRL2 OD TO CPU MBC 4LS244 Wri CTRL3 i>. CCLK DISPLAY DATA BUS

SYSTEM ADDRESS BUS 74LS244

SYSTEM SYSTEM RAM DECODE

RD WR

SYSTEM DATA BUS

Figure 10. Row Buffer Mode Configuration

BLANK

BREQ 22

22 MBC 2

NOTE If row table addressing Is enabled, BREQ will be asserted at the middle of the last scan line of the prior row, and MBC will be asserted at the beginning of BLANK.

Figure 11. Row Buffer Mode Timing

also be used with the other modes, but cir- OPERATION scrolling area or an alternate memory. cuitry must be added to route the data After power is applied, the AVDC will be in These may require modification during from the display memory to the data bus an inactive state. Two consecutive 'master operation. inputs of the AVDC. Additionally, when reset' commands are necessary to release After initial loading of the two register not operating in row buffer mode, care this circuitry and ready the AVDC for groups, the AVDC is ready to control the must be taken to assure that the CPU does operation. Two register groups exist monitor screen. Prior to executing the not attempt to access the AVDC while it is within the AVDC: the initialization regis- AVDC commands which turn on the reading the row table. One way of prevent- ters and the display control registers. The display and cursor, the user should load ing this is to latch the last line output initialization registers select the system the display memory with the first data to which is multiplexed on DADD13 and to configuration, monitor timing, cursor be displayed. During operation, the AVDC test this latch prior to reading or writing shape, display memory domain, pointer will sequentially address the display the AVDC. The AVDC should only be address, scrolling region, double height memory within the limits programmed in- accessed if the latch is low, indicating and width condition, and screen format. to its registers. The memory outputs char- that the last line of the row is not active. These are loaded first and normally re- acter codes to the system character and quire no modification except for certain graphics generation logic, where they are Figure 13 illustrates a typical hardware special visual effects. The display control converted to the serial video stream implementation for use in conjunction registers specify the memory address of necessary to display the data on the CRT. with independent and transparent modes, the base character (upper left corner of The user effects changes to the display by and figure 14 shows the timing for row screen), the cursor position, and the split modifying the contents of the display table operation. screen addresses associated with the memory, the AVDC display control and

2.80 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary IR0[7] — Double Height/ even fields, resulting in enhanced readability. The AVDC outputs successive line SSR2 Width Enable When this bit is set, the value in IR14[7:6] numbers in ascending order on the is used to control the double height and LAO-LA3 lines, one per scan line for each A width conditions of each character row. field. Assertion of this bit also allows IR14[7:61 The 'interlaced sync and video' format ROW TABLE to be programmed in two ways: doubles the character density on the IN MEMORY D } 1. By the CPU writing to IR14 directly. screen. The AVDC outputs successive line F } 2. When the contents of screen start numbers in ascending order on the odd register 1 (SSR1) upper are changed, and LAO-LA2 lines, one per scan line for either by the CPU writing to this regis- each field. ter or by the automatic loading of SSR1 1st CHAR when operating in row table mode, the IR1[6:0] — Equalizing Constant 2nd CHAR two MSBs of SSR1 upper are copied in- This field indirectly defines the horizontal 0 THIRD to IR14[7:6]. Thus, the MSBs of each front porch and is used internally to gen- DATA ROW O erate the equalizing pulses for the RS170 0 row table entry can be used to control compatible CSYNC. The value for this field LAST CHAR double height and double width attributes on a row by row basis. is the total number of character clocks (CCLKs) during a horizontal line period IR14[5:4] are not active when this bit is set. divided by two, minus two times the 1st CHAR When this bit is reset, the double height number of character clocks in the hori- 2nd CHAR and width attributes operate as described zontal sync pulse: FIRST 0 in IR[14]. DATA ROW 0 HAcT+ FiFp+ HSYNC+ HBP EC- 2(HsyNc) 0 IRO[6:3] — Scan Lines per 2 LAST CHAR Character Row The definition of the individual parameters Both interlaced and non-interlaced scan- is illustrated in figure 17. The minimum 1st CHAR ning are supported by the AVDC. For inter- value of HFp is two character clocks. laced mode, two different formats can be 2nd CHAR Note that when using the 2675 CMAC, it implemented, depending on the intercon- SECOND, 0 will delay the blank pulse three CCLKs DATA ROW nection between the AVDC and the char- O relative to the HSYNC pulse. 0 acter generator (see IR1[7]). This field LAST CHAR defines the number of scan lines used to compose a character row for each tech- IR2[7] — Row Table Mode Enable Figure 12. Row Table Address Format nique. As scanning occurs, the scan line Assertion/negation of this bit causes the AVDC to begin/terminate operating in row count is output on the LAO- LA3 and ODD table mode starting at the next character pins. command registers, and the initialization row. See Row Table Addressing Mode sec- registers, if required. Interrupts and status IR0121 — VSYNC/CSYNC Enable tion. By using the split interrupt capability conditions generated by the AVDC supply of the AVDC, this mode can be enabled This bit selects either vertical sync pulses the 'handshaking' information necessary and disabled on a particular character row. or composite sync pulses on the for the CPU to effect real time display This allows a combination of row table VSYNC/CSYNC output (pin 18). The com- changes in the proper time frame if and sequential addressing to be utilized to posite sync waveform conforms to EIA required. provide maximum flexibility in generating RS170 standards, with the vertical interval the display. INITIALIZATION REGISTERS composed of six equalizing pulses, six There are 15 initialization registers vertical sync pulses, and six more equaliz- IR2[6:31 — Horizontal Sync (IRO-IR14) which are accessed sequen- ing pulses. tially via a single address. The AVDC main- Pulse Width This field specifies the width of the tains an internal pointer to these registers IRO[1:0] — Buffer Mode Select which is incremented after each write at Four buffer memory modes may be selec- HSYNC pulse in CCLK periods. this address until the last register (IR14) is tively enabled to accommodate the de- accessed. The pointer then continues to sired system configuration. See System IR2[2:0] — Horizontal Back Porch point to IR14 for further accesses. Upon a Configurations. This field defines the number of CCLKs power-on or a master reset command, the IR1[7] — Interlace Enable between the trailing edge of HSYNC and internal pointer is reset to point to the first Specifies interlaced or noninterlaced tim- the trailing edge of BLANK. register (IRO) of the initialization register ing operation. Two modes of interlaced group. The internal pointer can also be operation are available, depending on preset to any register of the group via the IR3[7:51 — Vertical Front Porch whether LO-L3 or ODD, LO-L2 are used as 'load IR address pointer' command. These Specifies the number of scan line periods the line address for the character gener- registers are write only and are used to between the rising edges of BLANK and ator. The resulting displays are shown in specify parameters such as the system VSYNC during the vertical retrace interval. figure 16. configuration, display format, cursor The vertical front porch will be extended in shape, and monitor timing. Register for- For 'interlaced sync' operation, the same increments of scan lines if the ACLL input mats are shown in figure 15. information is displayed in both odd and is low at the end of the programmed value. Signetics 2.81 MICROPROCESSOR DIVISION JANUARY 1983

ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary

CCLK

RAM

DADD DISPLAY ADDRESS ADD 2674 AVDC DATA DBLNK > 0 CCLK ZN BLANK 7474 7474 RD CURSOR WR CURSOR CE DO 07

70 DISPLAY DATA BUS RD

SELECT DECODE

CE CE 74LS245 SIR w

.\7 SYSTEM DATA BUS

Figure 13. Row Table Mode Configuration (non-Row Buffer Modes)

IR3[4:0] — Vertical Back Porch IR5[7:0] — Active Characters Per rate (IR7[4]). The blink duty cycle for the This field determines the number of scan Row cursor is 50%. line periods between the falling edges of This field determines the number of char- IR7(4) — Cursor Blink Rate the VSYNC and BLANK outputs. acters to be displayed on each row of the The cursor blink rate can be specified at CRT screen. The sum of this value, the 1/32 or 1/64 of the vertical scan frequency. horizontal front porch, the horizontal sync Blink is effective only if blink is enabled by IR4[7] — Character Blink Rate width, and the horizontal back porch is the Specifies the frequency for the character I R7[5]. horizontal scan period in CCLKs. blink attribute timing. The blink rate can be specified as 1/64 or 1/128 of the vertical IR6[7:4], IR6[3:0] — First and IR7[3:0] — Underline Position field rate. The timing signal has a duty cy- This field defines which scan line of the cle of 50% and is multiplexed onto the Last Scan Line of Cursor character row will be used for the under- These two fields specify the height and DADD11/BLINK output at the falling edge line attribute by the 2675 CMAC. The tim- position of the cursor on the character of each BLANK. ing signal is multiplexed onto the block. The 'first' line is the topmost line DADD1O/UL output during the falling edge when scanning from the top to the bottom of BLANK. of the screen. IR4[6:0] — Character Rows Per IR9[3:0], IR8[7:0] — Display Screen IR7[7:6] — Vertical Sync Pulse This field defines the number of character Width Buffer First Address rows to be displayed. This value multiplied This field specifies the width of the IR9[7:4] — Display Buffer Last by the scan lines per character row, plus VSYNC pulse in scan line periods. Address . the vertical front porch, the vertical back These two fields define the area within the porch values, and the vertical sync pulse IR7[5] — Cursor Blink Enable buffer memory where the display data will width is the vertical scan period in scan This bit controls whether or not the cursor reside. When the data at the 'display buf- lines. output pin will be blinked at the selected fer last address' is displayed, the AVDC

2.82 Signetics MICROPROCESSOR DIVISION JANUARY 1983

ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary

CCLK

BLANK LAST LINE OF ROW FIRST LINE OF ROW

HSYNC H.- EC + 2 HSW CCLKs-•-.1

BRED ROW",,,FZZ' SSR2 MBC SSR2 +1 REFRESH / DADD LAST LINE ADDRESSES I A FIRST LINE ADDRESSES REFRESH I A IA I

CURSOR r POSSIBLE CURSORS POSSIBLE CURSORS I FETCH CONTROL INTERVAL DADD I \ I I FIRST LINE ADDRESSES 3-STATE1 I A I 3.STATE BRED I I NO FETCH BUS TRANSPARENT BUS REQUEST in REQUEST BUFFER MODE DURING BACK FETCH CYCLE I I—

BEXT (CURSOR OR POINTER ADDRESSES FOR DELAYED COMMANDS)

DADD FIRST LINE ADDRESSES II '. 1 A I

INDEPENDENT RDB BUFFER MODE

BCE

= MULTIPLEXED CONTROL SIGNALS EC = EQUALIZING CONSTANT HSW = HORIZONTAL SYNC WIDTH

Figure 14. Row Table Mode Timing

Signetics 2.83 MICROPROCESSOR DIVISION JANUARY 1983

ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary

BIT7 BITE • BITS • SITU • BIT3 SITU BIT1 • BITO BIT7 • BITE • BITS • BIT4 • BIT3 • BIT2 • BITS • BITO DOUBLE SCAN LINES PER CHARACTER ROW SYNC BUFFER MODE DISPLAY BUFFER FIRST ADDRESS LSB S HTIWD NON-INTERLACED INTERLACED SELECT SELECT H000 = 0 0000 = 1 LINE 0000=2 LINES H001 = 0001 = 2 LINES • NOTE: MSS'S ARE IN 0001 =4 LINES 0010 = 3 LINES IRB • IR9(301 IRO 0= OFF 0010=6 LINES 0 = VSYNC 00 = INDEPENDENT H FFE = 4,094 1 =ON • 1 = CSYNC 01 = TRANSPARENT • 10 = SHARED H'FFF' = 4.095 • 1110 = 15 LINES 1110=30 LINES 11 = ROW • • 1111 = 18 LINES 1111 = UNDEFINED • •

BIT] • BITE • BITS • BIT4 BITS • BITS • BIT1 • BITO DISPLAY BUFFER LAST ADDRESS DISPLAY BUFFER FIRST ADDRESS MOB'S BIT7 BITS • BIT5 • BIT4 • BITS • BIT2 • BIT1 • BITS INTERLACE EQUALIZING CONSTANT 0000 = 1,023 ENABLE 0001 = 2,047 0000000=1 CCLK • SEE IRB 0000001=2 CCLK CALCULATED FROM: IR9 • 1110 = 15,359 0 =NON-INT • EC = 0.501 40T+HFR+HSYNC+.30 -2(HSYNC) 1111 = 16,383 1= INTER. 1111110=127 CCLK • • • • 1111111=128 CCLK • BIT7 • BITS • BITS • BIT4 • BIT3 • BIT2 • BIT1 • BITO BIT7 SITS • BITS • BIT4 • BITS BITS • BITS • BITO DISPLAY POINTER ADDRESS LOWER ROW HORIZONTAL SYNC WIDTH HORIZONTAL BACK PORCH TABLE 0000 = 2 CCLK 000= NOT ALLOWED SEE IRIS 0001 = 4 CCLK 001= 3 CCLK IR2 • IR10 0= OFF • • 1= ON • 1110 = 30 CCLK 110 = 23 CCLK 1111 = 32 CCLK 111 = 27 CCLK • • • •

BITS BIT4 • BIT3 • BITS • BIT1 • BITO 67/;RTI;AL BFIFTI:NT VERTICAL BACK PORCH BIT7 • BITS • BIT5 • BIT4 • BIT3 • BIT2 • BITS • BITO 000 = 4 SCAN LINES 00000 = 4 SCAN LINES LZ DOWN LZ UP DISPLAY POINTER ADDRESS UPPER 001 = 8 SCAN LINES 00001 = 6 SCAN LINES I-00000' = 0 83 • 0 = OFF 0 = OFF • • 1 = ON 1 = ON 5'0001' = 1 110 = 28 SCAN LINES 11110 = 64 SCAN LINES IRII III = 32 SCAN LINES 11111 = 66 SCAN LINES • • • • • • H'3FFF' = 16,383

BIT7 BITS • BITS • BIT4 • BITS • BIT2 • BIT1 • BITO • CHARACTER ACTIVE CHARACTER ROWS PER SCREEN BLINK 0000000 = 1 ROW RATE 0000001 = 2 ROWS IRA BIT7 • BITE • BIT5 • BIT4 • BIT3 • BITS • BIT1 • BITO 0 = 1/64 • • VSYNC SCROLL SPLIT REGISTER 1 1111110= 127 ROWS 1=1/128 1111111 = 128 ROWS START 0000000 = ROW 1 VSYNC • • • • • 0 = OFF 0000001 = ROW 2 IRIS = ON

BIT7 • BITE • BITS • BIT4 • BIT3 • BITS • BITS • BITS 1111111= ROW 128 ACTIVE CHARACTERS PER ROW 00000010 = 3 CHARACTERS 00000011 = 4 CHARACTERS • IRS • 11111110 = 255 CHARACTERS 11111111 = 256CHARACTERS BIT7 • BITE • BITS • B1T4 • BIT3 • BIT2 • BITS • BITO • SCROLL SPLIT REGISTER 2

END 0000000 = ROW 1 0 = OFF 0000001 = ROW 2 BITS • BITS • BITS • BIT4 BIT3 • BITS • BITS • BITO IR13 1 = ON FIRST LINE OF CURSOR LAST LINE OF CURSOR 0000 = SCAN LINE 0 0000 = SCAN LINE 0 1111111 = ROW 128 0001 = SCAN LINE 1 0001 = SCAN LINE 1 • • IRS • • 1110 = SCAN LINE 14 1110= SCAN LINE 14 1111 = SCAN LINE 15 1111 =SCAN LINE 15 • • • • BIT7 • BITS BITS • BIT4 BIT3 BIT2 • 8171 • BITO DOUBLES DOUBLE 2 LINES TO SCROLL 511T7 • BITE BITS BIT4 BITS • BIT2 • BITS • BITO VSYNC WIDTH CURSOR CURSOR UNDERLINE POSITION 00 = NORMAL 00 = NORMAL 0000 = 1 01 = DOUBLE WIDTH 01 = DOUBLE WIDTH 2 BLINK RATE 0000 = SCAN LINE 0 0001 = 00=3 SCAN LN 0001 = SCAN LINER IR14 10= DB WD & TOPS 10 = DB WD & TOPS 01=1 SCAN LN 11 = DB WD & BOTS 11 = DB WD & BOTS • IR7 10=5 SCAN LN 0 = OFF 0= 1132 • 1110 = 15 11=7 SCAN LN 1= ON 1=1164 1110 = SCAN LINE 14 1111 = 16 1111 = SCAN LINE 15 • • • • • .

Figure 15. Initialization Register Formats

2.84 Signetics MICROPROCESSOR DIVISION JANUARY 1983

ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary

ODD

LINE ADDRESS LINE ADDRESS LINE ADDRESS TO CHAR GEN TO CHAR GEN TO CHAR GEN S 6 0 Lt 7 8

1 - • - • - • • • 1 • • • - • IIII 1 -0 0 0 0 0 I - 0-0-0- 0- 0 2 • 2 • 2 • 10 SCAN 3 0 2 0 LINES/ 4 • • • 3 3 • ROW 5 0 9 SCAN 18 SCAN 3 0 6 • LINES/ 4 • • • LINES/ 4 • - • - • 7 - 0 0 0 0 0 ROW ROW 4 0 0 0 5 • 5 • 9 5 0 0 6 • 6 • 1 - 0 0 0 0 0 6 0 2 • 7 - • - • - • - • - • 7 • - • -• - • - • 3 0 7 - 0- 0-0- 0- 0 4 • • • 8 18 6 o 8 6 • 0 0 7 - 0 0 0 0 0 0 8 I —•-•-•-•- • I —•-•-•-•-• 9 1 - 0- 0- 0- 0- 0 0 2 • 2 • 1 - 0 0 0 0 0 2 0 2 • 3 • 3 • 3 0 3 -0 4 • • • 4 • • • 4 • -• • 5 0 4 0 o o 6 • 5 • 5 • 7 - 0 0 0 0 0 5 0 8 6 6 • 9 6 o 0 7 - • - • - • - • - • 7 • • • • • 1 - 0 0 0 0 0 7 -0-0-0-0-0 2 • 8 3 0 a 4 - • • • 5 o 6 •

NON INTERLACED INTERLACED SYNC INTERLACED SYNC AND VIDEO IRO = 1000; TOTAL LINES/ROW =9 IRO= 1000; TOTAL LINES/ROW = 16 IRO = 0100; TOTAL LINES/FIOW = 10

Figure 16. Interlaced Display Modes

Signetics 2.85 MICROPROCESSOR DIVISION JANUARY 1983

ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary

CHAR ROW (IRS)

H BLANK H FRONT PORCH (1111) BACK PORCH (IR2) I.—

HSYNC —I 1 HSYNC (IR2) CHAR ROWS/SCREEN (IR4)

HI SCAN LINES PER ROW (IRO)

VBLANK

FRONT PORCH (IR3) BACK PORCH (IR3)

VSYNC VSYNC (IR7)

EQUALIZING LINES/ROW CONSTANT

IRO 1 1 1 IRI

HSYNC HBACK VFRONT VBACK VSYNC WIDTH PORCH PORCH PORCH WIDTH

IR2 IR3 IR7

CHAR ROWS/SCREEN CHARACTERS PER ROW

IR4 1111111 IRS 1111111

Figure 17. Horizontal and Vertical Timing

will wraparound and obtain the data to be response to 'read/write at pointer' com- IR12171 — Scroll Start displayed at the next screen position from mands. They also define the last buffer This bit is asserted when soft scroll is to the 'display buffer first address'. If 'last memory address to be written for the take place. The scrolling area begins at address' is the end of a character row and 'write from cursor to pointer' command. the row specified in split register 1 a new screen start address has been load- (IR12[6:0]). If set, the first row to scroll ed into the screen start register, or if 'last scan line count will be reduced by the address' is the last character position of IR11171 — Scan Line Zero During value in the lines to scroll register the screen, the next data is obtained from Scroll Down (IR14[3:0]). The scan line count of this row the address contained in the screen start This field specifies normal scan line count will start at the programmed offset value. register. of all scan line zero counts for the new When this bit is asserted, scroll end character row that occurs at the top of the Note that there is no restriction in display. IR13[7] must be set before split 2. scrolling area during soft scroll down ing data from other areas of the address- operation. If the character generator pro- able memory. Normally, the area between IR12[6:0] — Split Register 1 vides blanks during scan line zero, this will Split register 1 can be used to provide these two bounds is used for data which cause the new row to be automatically special screen effects such as soft (scan can be overwritten (e.g., as a result of blanked on the display. This feature can line by scan line) scrolling, double height/ scrolling), while data that is not to be over- be used, if necessary, to blank the new width rows, or to change the normal ad- written would be contained outside these row until the CPU places 'blank data' into dressing sequence of the display memory. bounds and accessed by means of the the display buffer. The contents of this field is compared, in automatic split screen or split screen real time, to the current row number. Upon interrupt feature of the AVDC. a match, the AVDC sets the split screen 1 IR10[7:0] — Display Pointer IR11161 — Scan Line Zero status bit, and issues an interrupt request Address Lower During Scroll Up if so programmed. The status change/ This field specifies normal scan line count interrupt request is made at the beginning IR11[5:0] — Display Pointer of all scan line zero counts for the new of scan line zero of the split screen char- Address Upper character row that occurs at the bottom of acter row. If enabled by the SPL1 bit of These two fields define a buffer memory the scrolling area during soft scroll up screen start register 2, an automatic split address for AVDC controlled accesses in operation. See above. screen to the address specified in screen

2.86 Signetics MICROPROCESSOR DIVISION JANUARY 1983 ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary

start register 2 will be made for the desig- toggling between tops and bottoms is the second character row. This process is nated character row. During a scroll opera- disabled. repeated for the programmed number of tion, this field defines the first character rows per screen. Thus, the data in the row of the scrolling area. 1R14[5:41 — Double 2 display memory is displayed sequentially This field specifies the conditions (double starting from the address contained in the IR13[7] — Scroll End width/height or normal) of the row desig- screen start register. After the ensuing This field specifies that the row pro- nated in split register 2 (IR13[6:0). Not vertical retrace interval, the entire process grammed in split register 2 (I R13[6:0]) is to used when IRO[7]= 1. repeats again. be the last scrolling row of the scrolling During vertical blanking, the address area. Note that this bit must be asserted IR14[3:0] — Lines to Scroll counter operation is modified by stopping for a valid row only when the scroll start This field defines the scan line increment the automatic load of the contents of the bit IR12[7] is also asserted. to be used during a soft scroll operation. RSR into the counter, thereby allowing the This value will only be used when scroll address outputs to free-run. This allows start (IR12[7]) and scroll end (IR13[7]) are IR13[6:0] — Split Register 2 dynamic memory refresh to occur during This field is similar to the split register 1 enabled. the vertical retrace interval. The refresh field except for the following: addressing starts at the last address 1. Split screen 2 status bit is set. Timing Considerations displayed on the screen and increments Normally, the contents of the initialization 2. During a scroll operation, this field by one for each character clock during the registers are not changed during normal defines the last character row of the retrace interval. If the display buffer last operation. However, this may be neces- scrolling area. This row will be followed address is encountered, refreshing con- sary to implement special display features by a partial row. The LTSR (IR14) value tinues from the display buffer first such as multiple cursors and horizontal replaces the normal scan lines/row address. value for the partial row, thus keeping scrolling. Table 2 describes timing details for these registers which should be con- the total scan lines/screen the same. The sequential operation described above sidered when implementing these 3. If enabled by the SPL2 bit of screen will be modified upon the occurrence of features. start register 2, an automatic split to any one of three events. First, if during the the address contained in screen start incrementing of the memory address DISPLAY CONTROL REGISTERS register 2 will occur in one of two ways: counter the 'display buffer last address' There are seven registers in this group, a) If not scrolling an automatic split will (IR9[7:4]) is reached, the MAC will be each with an individual address. Their for- occur for the next character row. b) If loaded from the 'display buffer first mats are illustrated in figure 15. The com- scrolling, the automatic split will occur address' register (IR9[3:0] and IR8[7:0]) at mand register is used to invoke one of 19 after the partial row being scrolled onto the next character clock. Sequential oper- possible AVDC commands as described in or off the screen. ation will then resume starting from this the COMMANDS section of this data 4. The specified double width and height address. This wraparound operation sheet. The remaining registers in the conditions (IR14) are also asserted in allows portions of the display buffer to be group store address values which specify two possible ways: a) Automatic split used for purposes other than storage of the cursor location, the location of the will assert the programmed condition displayable data and is completely auto- first character to be displayed on the for the current row. b) During soft scroll matic without any CPU intervention (see screen, and any split screen address loca- operation the programmed conditions figure 19a). are asserted for the partial row scroll- tions. The user initializes these registers after powering on the system and changes ing onto or off the screen. The sequential row to row addressing can their values to control the data which is also be modified via split register 1 (IR12) displayed. IR14[7:6] — Double 1 and split register 2 (IR13), under CPU con- This field specifies the conditions (double trol, or by enabling the row table address- width/height or normal) of the row desig- Screen Start Registers 1 and 2 ing mode. If bit 6 of screen start register 2 nated in split register 1 (IR12[6:0]). When The screen start 1 registers contain the upper (SPL1) is set, the screen start regis- double height tops or bottoms has been address of the first character of the first ter 2 contents will be loaded automatically specified, the AVDC will automatically row (upper left corner of the active into the RSR at the beginning of the first toggle between tops and bottoms until display). At the beginning of the first scan scan line of the row designated by split another split 1 or 2 occurs which changes line of the first row, this address is trans- register 1 (IR12[6:0]). If bit 7 of screen start the double height/width condition. If a ferred to the row start register (RSR) and 2 upper (SPL2) is set, the screen start reg- double height tops row is specified, the into the memory address counter (MAC). ister 2 contents is automatically loaded scan line count will start at zero and incre- The counter is then advanced sequentially into the RSR at the end of the last scan ment the scan line count every other scan at the character clock rate for the number line of the row designated by split register line. If a double height bottom row is of times programmed into the active char- 2 (11913[6:0]). SPL1 and SPL2 are write only specified, the AVDC will start at one half acters per row register (IR5), thus reaching bits and will read as zero when reading the normal scan line total. If double width the address of the last character of the screen start register 2. is specified, the AVDC will assert the row plus one. At the beginning of each DADD9/DW output at the falling edge of subsequent scan line of the first row, the If the contents of screen start register 1 blank. This condition will also remain ac- MAC is reloaded from the RSR and the (upper, lower, or both) are changed during tive until the next split 1 or 2. When above sequence is repeated. At the end of any character row (e.g., row 'n'), the start- IRO[7]= 1, the values written into bits 7 the last scan line of the first row, the con- ing address of the next character row (row and 6 of screen start 1 upper will also be tents of the MAC is loaded into the RSR to 'n+ 1') will be the new value of the screen written into IR14[7:6] and the automatic serve as the starting memory address for start register and addressing will continue Signetics 2.87 MICROPROCESSOR DIVISION JANUARY 1983

ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Prelimmary Table 2 TIMING CONSIDERATIONS sequentially from there. This allows features such as split screen operation, par- PARAMETER TIMING CONSIDERATIONS tial scroll, or status line display to be First line of cursor These parameters must be established at a implemented. The split screen interrupt Last line of cursor minimum of two character times prior to their feature of the AVDC is useful in control- Underline line occurrence ling the CPU initiated operations. Note that in order to obtain the correct screen Double height character rows Set/reset prior to the row specified in split 1 display, screen start register 1 must be Double width character rows or 2 registers reloaded with the original (origin of dis- Rows to scroll play) value prior to the end of the vertical Cursor blink New values become effective within one field retrace. See figure 19b. Cursor blink rate after values are changed When row table addressing mode is en- Character blink rate abled, the first address of the row table is Split register 1 Change anytime prior to line zero of desired designated in SSR2. The AVDC fetches Split register 2 row the next row's starting address from the table during the blanking interval prior to Character rows per screen Change only during vertical blanking period the first scan line of each character row Vertical front porch Change prior to first line of VFP and loads it into SSR1 for use as the start- Vertical back porch Change prior to fourth line after VSYNC ing address of the next row. Since the contents of SSR2 changes as the table entries Screen start register 1 Change prior to the horizontal blanking are fetched, it must be re-initialized to Row table mode enable interval of the last line of character row point to the first table entry during each before row where new value is to be used vertical retrace interval. The values in the two MSBs of SSR1 upper are multiplexed onto the DADD1/DADD14 and DADD2/DADD15 outputs during the

BIT7 BITS BITS BIT4 BITS BITS BIT1 BITO COMMAND CODE

SEE COMMANDS SECTION FOR COMMAND CODES

COMMAND REGISTERS (WRITE ONLY)

BIT7 BITS BITS BIT4 BITS BIT2 BIT1 BIT() BIT7 BITE BITS BIT4 BIT3 BIT2 BIT1 BIT() UPPER REGISTER LOWER REGISTER (LSB) 6'00017 = 0 NOTE: MSB's ARE IN H.0001' = 1 UPPER REGISTER [5:01 DADD15 DADD14 MSB's THRU H'3FFE. =16,382 H'3FFF. = 16,383 NOTES: 1. Bits 7 and 6 of upper register are not used in the cursor address registe . 2. Bits 7 and 6 of upper register are always zero when read by the CPU. 3. When IRO[7]. 1, the values written into bits 7 and 6 of screen start 1 upper will also be written Into IR14[7:6] to control the double width and double height attributes of the display as follows: 7 6 Attribute 0 0 None 0 1 Double width only 1 0 Double width and double height tops 1 1 Double width and double height bottoms

SCREEN START 1 REGISTERS (READ AND WRITE) CURSOR ADDRESS REGISTERS (READ AND WRITE)

BIT7 BITS BITS BIT4 BITS BITS BIT1 BITO BIT7 BITS BITS BIT4 BIT3 BIT2 BIT1 BITO UPPER REGISTER LOWER REGISTER (LSB) SPL2 SPL1 6'0000' = 0 NOTE: MSB's ARE IN 0=OFF 0 =OFF 1.1.0001' = 1 UPPER REGISTER [5:01 1=ON 1=ON MSB's THRU H'3FFE' =16,3132 H'3FFF' =16,383

NOTE: Bit 7 and bit 6 are always zero when read by CPU. SCREEN START 2 REGISTERS (READ AND WRITE) Figure 18. Display Control Register Formats

2.88 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary falling edge of BLANK. If IRO[7] = 0, these two bits act as memory page select bits 0 which may be used to extend the display memory addressing range of the AVDC up to 64K. In that case, these two bits act as a DISPLAY BUFFER START two-bit counter which is incremented each time that 'wraparound' occurs (see above). BOTTOM OF SCREEN'. Note that the counter is incremented at the falling edge of BLANK and that for proper display operation the wraparound address should be programmed to occur at the last character position of a row. SCREEN START-► Also, the first address accessed in the MONITOR new page will be the address contained in DISPLAY the display buffer first address register DISPLAY BUFFER END (I R9[3:0] and I R8[7:0]).

Cursor Address Registers 16K The contents of these registers define the MEMORY buffer memory address of the cursor. The (a) DISPLAY MEMORY WRAPAROUND cursor output will be asserted when the memory address counter matches the value of the cursor address registers for the scan lines specified in IR6. The cursor DISPLAY BUFFER START address registers can be read or written by the CPU or incremented via the 'increment -•- BOTTOM OF SCREEN cursor address' command. In independent SCREEN START 1.- buffer mode, these registers define a buffer memory address for AVDC controlled access in response to 'read/write at cursor with/without increment' commands, or the SPLIT SCREEN first address to be used in executing the 'write from cursor to pointer' command.

SCREEN START 2 INTERRUPT/STATUS REGISTERS The interrupt and status registers provide MONITOR DISPLAY information to the CPU to allow it to inter- DISPLAY BUFFER END act with the AVDC to effect desired changes that implement various display 16K operations. The interrupt register provides MEMORY information on five possible interrupting (b) DISPLAY MEMORY SPLIT SCREEN WITH WRAPAROUND conditions, as shown in figure 20. These conditions can be selectively enabled or Figure 19. Display Addressing Operation disabled (masked) from causing interrupts by certain AVDC commands. An interrupt condition which is enabled (mask bit equal to one) will cause the INTR output to be asserted and will cause the corresponding reset by the CPU by issuing a 'reset inter- I/SR[3] — Line Zero bit in the interrupt register to be set upon rupt/status bits' command. The bits are Set to one at the beginning of the first the occurrence of the interrupting condi- also reset by a 'master reset' command scan line (line 0) of each active character tion. An interrupt condition which is dis- and upon power-up. row. abled (mask bit equal to zero) has no effect on either the INTR output or the SR[5] — RDFLG I/SR[2] — Split Screen 1 interrupt register. This bit is present in the status register This bit is set when a match occurs be- only. A zero indicates that the AVDC is The status register provides six bits of tween the current character row number currently executing the previously issued status information: the five possible inter- and the value contained in split register 1, delayed command. A one indicates that rupting conditions plus the RDFLG bit. IR12[6:0). The equality condition is only For this register, however, the contents the AVDC is ready to accept a new delayed checked at the beginning of line zero of command. are not affected by the state of the mask each character row. bits. I/SR[4] — VBLANK Descriptions of each interrupt/status reg- Indicates the beginning of a vertical blank- USR[1] — Ready ister bit follow. Unless otherwise indi- ing interval. Set to one at the beginning of The delayed commands affect the display cated, a bit, once set, will remain set until the first scan line of the vertical front porch. and may require the AVDC to wait for a Signetics 2.89 MICROPROCESSOR DIVISION JANUARY 1983 ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary

Cursor Off BITT BIT6 BITS BITS BITS BITS BIT1 BITS Disables cursor operation. Cursor output LINE RDFLG VBLANK ZERO SPLIT 1 READY SPLIT 2 is placed in the low state. NOT USED ALWAYS READ ASO 0 = BUSY O=NO O=NO O=NO P = BUSY O=NO Cursor On 1= READY 1= YES 1= YES 1= YES 1= READY 1= YES Enables normal cursor operation.

16 STATUS REGISTER ONLY. ALWAYS 0 WHEN READING INTERRUPT REGISTER. Reset Interrupt/Status Bits Figure 20. Interrupt and Status Register Format This command resets the designated bits in the interrupt and status registers. The bit positions correspond to the bit posi- blanking interval before enacting the com- 2. The interrupt and status bits and tions in the registers: mand. This bit is set to one when execu- masks are set to zero, except for the Bit 0 — Split 2 tion of a delayed command has been com- RDFLG flag which is set to a one. Bit 1 — Ready pleted. No other delayed command should 3. The row buffer mode, cursor-off, Bit 2 — Split 1 be invoked until the prior delayed com- display-off, and line graphics disable Bit 3 — Line zero mand is completed. states are set. Bit 4 — Vertical blank 4. The initialization register pointer is set Disable Interrupts I/SR[0] — Split Screen 2 to address IRO. Sets the interrupt mask to zeros for the This bit is set when a match occurs be- 5. IR2[7] is reset. tween the current character row number designated conditions, thus disabling and the value contained in split register 2 Load IR Address these conditions from being set in the in- (IR13[6:0]) when you are not scrolling. It is This command is used to preset the initial- terrupt register and asserting the INTR set for the value contained in (split screen ization register pointer with the value 'V' output. Bit position correspondence is as register 2) +1 when scrolling. defined by D3-D0. Allowable values are 0 above. to 14. COMMANDS Enable Interrupts The AVDC commands are divided into two Enable Graphics This command writes the associated inter- classes: the instantaneous commands After invoking this command, the AVDC rupt mask bits to a one. This enables the which are executed immediately after they will increment the MAC to the next con- corresponding conditions to be set in the are invoked, and the delayed commands secutive memory address for each scan interrupt register and asserts the INTR which may need to wait for a blanking in- line even if more than one scan line per output. Bit position correspondence is as terval prior to their execution. Command row is programmed. This mode can be above. formats are shown in table 3. The com- used for bit-mapped graphics where each mands are asserted by performing a write location in the display buffer within the Delayed Commands operation to the command register with defined area contains the bit pattern to be This group of commands is utilized for the the appropriate bit pattern as the data displayed. This command is row buffered independent buffer mode of operation, al- byte. and should be asserted during the though the 'increment cursor' command character row prior to the row where this can also be used in other modes. With the Instantaneous Commands feature is required. This allows the user to exception of the `write from cursor to The instantaneous commands are ex- enter and exit graphics mode on character pointer' and 'increment cursor' com- ecuted immediately after the trailing edge row boundaries. mands, all the commands of this type will of the WR pulse during which the com- To perform split screen operations while be executed immediately or will be mand is issued. These commands do not in graphics mode use SSR2 only. delayed depending on when the command affect the state of the RDFLG or READY is invoked. If invoked during the active interrupt/status bits and can be invoked at DADDO/LG is asserted during the trailing screen time, the command is executed at edge of BLANK for each scan line while any time. the next horizontal blanking interval. If this mode is active. Master Reset invoked during a vertical retrace interval or This command initializes the AVDC and can Disable Graphics a 'display off' state, the command is ex- be invoked at any time to return the AVDC Normal addressing resumes at the next ecuted immediately. to its initial state. Upon power-up, two row boundary. The 'increment cursor' command is exe- successive master reset commands must cuted immediately after it is issued and re- be applied to release the AVDC's internal Display Off Asserts the BLANK output. The DADDO quires approximately three CCLK periods power on circuits. In transparent and for completion. The `write from cursor to shared buffer modes, the CNTRL1 input through DADD13 display address bus outputs can be optionally placed in the three- pointer' command executes during blank- must be high when the command is issued. ing intervals. The AVDC will execute as The command causes the following: state condition by setting bit 2 to a '1' when invoking the command. many writes as possible during each 1. VSYNC and HSYNC are driven low for blanking interval. If the command is not the duration of the command and Display On completed during the current blanking in- BLANK goes high. After command Restores normal blanking operation either terval, the command will be held in sus- completion, HSYNC and VSYNC will at the beginning of the next field (bit 2= 1) pension during the next active portion of begin operation and BLANK will remain or at the beginning of the next scan line the screen and continues during the next high until a 'display on' command is (bit 2=0). Also returns the DADDO-DADD13 blanking interval until the command is received. drivers to their active state. completed.

2.90 Signetics MICROPROCESSOR DIVISION JANUARY 1983 ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary

In all cases, the AVDC will assert the Table 3 AVDC COMMAND FORMATS READY/RDFLG status to signify comple- D7 D6 D5 D4 D3 D2 tion of the delayed command. No other D1 DO COMMAND delayed command should be given until Instantaneous Commands: the previous delayed command has com- 0 0 0 0 0 0 0 0 Master reset pleted. Therefore, the READY interrupt 0 0 0 1V V V V Load IR pointer with value V or RDFLG status flag should be used (V=0 to 14) for handshaking control between the 0 0 1 d d d 1 01 Disable graphics AVDC and CPU when using the delayed 0 0 1 d d d 1 12 Enable graphics commands. 0 0 1 d 1 N d 01 Display off. Float DADD bus if N= 1 0 0 1 d 1 N d 12 Display on: Next field (N = 1) or scan Read/Write at Pointer line (N =0) Transfers data between the display buffer 0 0 1 1 d d d 01 Cursor off and the bus interface latch using the ad- 0 0 1 1 d d d 12 Cursor on dress contained in the pointer registers. 0 1 0 N N N N N Reset interrupt/status: Bit reset where N= 1 Read/Write at Cursor 1 0 0 N N N N N Disable interrupt: Disable where Transfers data between the display buffer N = 1 and the bus interface latch using the ad- 0 1 1 N N N N N Enable interrupt: Enables interrupts dress contained in the cursor registers. where N = 1 V LSRS Interrupt Bit Increment Cursor BZPDP Assignments Adds one (modulo 16K) to the cursor ad- 1 Y 2 dress registers. Delayed Commands: Hex Read/Write at Cursor and 1 0 1 0 0 1 0 0 A4 Read at pointer address Increment 1 0 1 0 0 0 1 0 A2 Write at pointer address Transfers data between the display buffer 1 0 1 0 1 0 0 1 A9 Increment cursor address and the bus interface latch using the ad- 1 0 1 0 1 1 0 0 AC Read at cursor address dress contained in the cursor registers 1 0 1 0 1 0 1 0 AA Write at cursor address and then adds one (modulo 16K) to the cur- 1 0 1 0 1 1 0 1 AD Read at cursor address and sor address registers. increment address 1 0 1 0 1 0 1 1 AB Write at cursor address and Write from Cursor to Pointer increment address Writes the data contained in the bus inter- 1 0 1 1 1 0 1 1 BB Write from cursor address to pointer face latch into the block of display mem- address ory designated by the cursor address and 1 0 1 1 1 1 0 1 BD Read from cursor address to pointer pointer address registers, inclusive. After address completion of the command, the pointer NOTES: 2. Any combination of these three commands in valid. address will be unchanged, but the cursor 1. Any combination of these three commands is valid. 3. d= don't care. register contents will be equal to the pointer address. ABSOLUTE MAXIMUM RATINGS1 PARAMETER RATING UNIT Operating ambient temperature2 0 to + 70 °C Storage temperature —65 to + 150 °C All voltages with respect to ground3 —0.5 to + 6.0 V

DC ELECTRICAL CHARACTERISTICS TA = 0°C to +70°C, Vcc= 5.0V ± 5% 45'6 LIMITS PARAMETER TEST CONDITIONS UNIT Min Typ Max VIS Input low voltage 0.8 V VIH Input high voltage 2.0 V VOL Output low voltage Ion = 2.4mA 0.4 V VOH Output high voltage (except INTR output) I0H = — 200µA 2.4 V 'IL Input leakage current VIN = 0 to Vcc — 10 10 itA ILL Data bus 3-state leakage current Vo = 0 to Vcc — 10 10 µA Ion INTR open drain output leakage current Vo = 0 to Vcc 10 µA 'cc Power supply current 160 mA Signetics 2.91 MICROPROCESSOR DIVISION JANUARY 1983 ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary

AC ELECTRICAL CHARACTERISTICS TA = 0°C to + 70°C, Vcc = 5.0V ± 5%4'5'67'8 TENTATIVE LIMITS PARAMETER TEST CONDITIONS 2.7MHz 4.0MHz UNIT Min Max Min Max Bus Timing (Fig. 21)9 tAS A0-A2 setup time to WR, RD low 30 30 ns t AH A0-A2 hold time from WR, RD high 0 0 ns tcs CE setup time to WR, RD low 0 0 ns t„ CE hold time from WR, RD high 0 0 ns t ew WR, RD pulse width 250 200 ns IDD Data valid after RD low 200 200 ns tDF Data bus floating after RD high 100 100 ns t„ Data setup time to WR high 150 150 ns IDH Data hold time from WR high 10 5 ns t„ High time from CE to CE Consecutive commands tCCP tCCP ns Other accesses 300 300 ns CCLK Timing (Fig 22, 23, 24) tCCP CCLK period 370 10,000 250 10,000 ns tCCH CCLK high time 125 100 ns tcci_ CCLK low time 125 100 ns Output delay from CCLK edge tccot DADDO-13, MBC 40 175 40 150 ns tCCD2 BLANK, HSYNC, VSYNC/CSYNC, CURSOR, BEXT, BREQ, BACK, BCE, WDB, RDB19 40 225 40 200 ns Other Timings (Fig 23) tRDL READY/RDFLG low from WR high9 tCCP tCCP + 30 + 30 ns t BAK BACK high from PBREQ low 225 200 ns t BXT BERT high from PBREQ high 225 200 ns tIRL INTR low from CCLK low 225 200 ns tIRH INTR high from WR, RD high9 600 600 ns tAC ACLL from HSYNC 3xtccp 3xtcop ns Row Table Input Timing (Fig. 24) tDsRT Data setup time to CCLK low 100 60 ns tDHRT Data hold time from CCLK low 60 60 ns

NOTES 5 All voltage measuremen s are referenced to ground (GND). 1. Stresses above those listed under Absolute Maximum Ratings may cause perma- 6. Typical values are at +25°C, typical supply voltages, and typical processing nent damage to the device. This is a stress rating only and functional operation of parameters. the device at these or at any other condition above those in the operation section 7. For testing, all input signals swing between 0.4V and 2.4V with a transition time of of this specification is not implied. 20ns maximum. All time measurements are referenced at input voltages of 0.8V 2. For operating at elevated temperatures, the device must be derated based on and 2.0V and output voltages of 0.8V and 2.0V as appropriate. + 150°C maximum junction temperature. 8. Test condition for outputs: CL = 150pF. 3. This product includes circuitry specifically designed for the protection of its inter- 9. Timing is illustrated and specified referenced to WR and RD inputs. Device may nal devices from damaging effects of excessive static charge. Nonetheless, it is also be operated with CE as the 'strobing' input. In this case, all timing specifica- suggested that conventional precautions be taken to avoid applying any voltages tions apply referenced to falling and rising edges of CE. larger than the rated maxima. 10 BCE, WDB, and RDB delays track each other within 1Onsec. Also, these output 4. Parameters are valid over specified temperature range. delays will tend to follow direction (min/max) of DADDO-13 delays.

2.92 Signetics MICROPROCESSOR DIVISION JANUARY 1983 ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary

AO-A2

to tAH

tCS tCH

1RW

tDF

DO-D7 FLOAT VALID FLOAT (READ)

tDH

DO-D7 VALID (WRITE)

NOTE 1. Any two must be high for tcc. Figure 21. Bus Timing

CCLK

OUTPUTS (NOTE 1)

NOTES OUTPUTS 1. DADDO-DADD13, BLANK, HSYNC, CSYNCNSYNC, CURSOR, BERT, BRED, WDB, RDB, BCE BCE, MBC, BACK. 2. BCE CHANGES STATE ON BOTH CCLK EDGES —(see Figures 3 and 4)

Figure 22. CCLK Timing

Signetics 2.93 MICROPROCESSOR DIVISION JANUARY 1983

ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary

BLANK VERTICAL BLANKING /-? INTERVAL

1st HSYNC HSYNC OF VBLANK 2 /

VBLANK STATUS BIT

INTR

CCLK

tpCO2

BLANK HORIZONTAL BLANKING INTERVAL

IccD1 DADDO- MULTIPLEXED ADDRESS OF 1st CHARACTER DADD13 SIGNALS VALID OF ROW

LINE ZERO AND SPLIT SCREEN STATUS BITS

tiRL1

INTR

HSYNC

BLANK VFp = n SCAN LINES NORMAL I VSYNC (ACLL =1) ?? 1_- IAC

ACLL ?2

DELAYED VSYNC

A VFp — n + 3 SCAN LINES

Figure 23. Other Timings

2.94 Signetics MICROPROCESSOR DIVISION JANUARY 1983

ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preliminary

1/74 FOR A DELAYED COMMAND

130\1 r— READY OR RDFLG STATUS BITS

PBREQ 22

22 tBXT BACK

BEXT —22

WR OR RD WHICH RESETS INTERRUPT tIRH

INTR /

Figure 23. Other Timings (Continued)

LATCH DO-D7 INTO LATCH DO-D7 INTO SSRI LOWER SSRI UPPER

CCLK

BLANK /

MBC

IC= 1-.—

CURSOR /

DS R tDHRT-4.-ItDSRTI-m— tDHRT--.-1

DO-07

Figure 24. Row Table Fetch 110 Timing

Signetics 2.95 MICROPROCESSOR DIVISION JANUARY 1983

ADVANCED VIDEO DISPLAY CONTROLLER (AVDC) SCN2674

Preview

EVEN FIELD LAST DISPLAYED FIRST DISPLAYED SCAN SCAN OF OF EVEN FIELD VERTICAL FRONT PORCH VERTICAL SYNC PULSE VERTICAL BACK PORCH PREVIOUS FIELD / HORIZONTAL SYNC _WES CSYNC1 :Le

BLANK VERTICAL BLANKING INTERVAL

ODD FIELD FIRST DISPLAYED LAST DISPLAYED SCAN OF SCAN OF H VERTICAL FRONT PORCH-1/2 H VERTICAL SYNC PULSE VERTICAL BACK PORCH -1l2 H ODD FIELD EVEN FIELD 112 H CSYNC 1n n

1/2 HORIZONTAL SYNC H PERIOD

BLANKILS-2 VERTICAL BLANKING INTERVAL

HORIZONTAL BLANKING INTERVAL NOTES 1. In non.interlaced operation the even field is repeated continuously. 2. In Interlaced operation the even field alternates with the odd field.

Figure 25. Composite Sync Timing

2.96 Signetics MICROPROCESSOR DIVISION JANUARY 1983 COLOR/MONOCHROME ATTRIBUTES CONTROLLER (CMAC) SCB2675

Preliminary

DESCRIPTION FEATURES PIN CONFIGURATION The Signetics SCB2675 Color/Mono- • 25 and 18MHz video dot rate versions* chrome Attributes Controller (CMAC) is a • Four video intensities encoded on two bipolar LSI device designed for CRT ter- TTL outputs (monochrome mode) minals and display systems that employ • Eight foreground and background raster scan techniques. It contains a pro- colors encoded on three TTL outputs Vee Vcc grammable dot clock divider to generate a (color mode) 131 DO character clock, a high speed shift regis- • Internally latched character attributes: D3 D2 ter to serialize input dot data into a video — Reverse video stream, latches and logic to apply visual — Blank D5 D4 attributes to the resulting display, and — Blink D7 D6 logic to display a cursor on the display. — Underline D8 C1 — Highlight The CMAC provides control of visual attri- RBLANK CO — Two general purpose butes on a character by character basis for — Eight foreground colors CURSOR CCLK two operating modes: monochrome and — Eight background colors CMODE DCLK color. The monochrome mode provides — Dot width control reverse video, blank, highlight and two DOTS DOTM — Double width characters general purpose user definable attributes. • VT100 compatible attributes BLINK M/C In this mode, the display characters can • Reverse video cursor with optional BLANK BLUE/TTLV2 be specified to appear on either a light or white cursor in color mode dark screen background. Retrace video UL RED/TTLV1 • Up to 10 dots per character suppression can be automatically or exter- ADOUBLE GREEN/GPI • Light or dark background in nally controlled. The color mode provides monochrome mode RESET LU MIG P2 eight colors for foreground (character) — Automatic retrace blanking ABLINK AREDF/AHILT video and eight colors for background • Programmable dot stretching AGREENF, video together with a luminance output for ADOTM • Compatible with SCN2674 AVDC and BKGND external color set selection or to simul- AG REEN BI ABLUEF/ SCN2670 DCGG ABLANK taneously drive a monochrome monitor. ARVID • TTL compatible AUL ABLUEB/AGP2 Additionally, both modes provide double • 40.pin dual in-line package width, underline, blink, dot stretching and GND AREDB1AGP1 dot width attributes. In monochrome APPLICATIONS mode, the SCB2675 emulates the attribute TOP VIEW • CRT terminals characteristics of Digital Equipment Cor- • Word processing systems poration's VT100 terminal. • Small business computers The horizontal dot frequency is the basic timing input to the CMAC. This clock is 'For faster versions consult factory. divided internally to provide a character clock output for system synchronization. ORDERING CODE Up to ten bits of dot data are parallel Vcc =5V-2:5%, 0°C to +70°C loaded into the video shift register on DOTS PER each character boundary. The two TTL PACKAGES video data outputs in monochrome mode CHARACTER 25MHz 18MHz are encoded to provide four video inten- Ceramic DIP SCB2675BC5I40 SCB2675BC8140 sities (black, gray, white and highlight). 7, 8, 9 , 10 The video data in color mode is encoded Plastic DIP SCB2675BC5N40 SCB2675BC8N40 to provide eight foreground colors and Ceramic DIP SCB2675CC5140 SCB2675CC8140 shifted out on three TTL outputs, together 6, 8, 9 , 10 Plastic DIP SCB2675CC5N40 SC B2675CC8N40 with the luminance output.

Signetics 2.97 MICROPROCESSOR DIVISION JANUARY 1983 COLOR/MONOCHROME ATTRIBUTES CONTROLLER (CMAC) SCB2675

Preliminary

PIN DESIGNATION MNEMONIC PIN NO. TYPE NAME AND FUNCTION Vcc 40 I Power Supply: + 5VDC

VBB 1 i Bias Supply: See figure 5 GND 20 I Ground: OV reference DCLK 32 I Dot Clock: Dot frequency input. Video output shift rate. CCLK 33 0 Character Clock: An output which is a submultiple of DCLK. The period ranges from 7 to 10 DCLK periods per cycle and is determined by the state of the CO-Cl inputs. RED/TTLV1 28 0 Red/TTL Video 1: In color mode, this output provides the red gun serial video. In monochrome mode, it should be used with the blue/TTL video 2 output to decode four video intensities. BLUE/TTLV2 29 0 Blue/TTL Video 2: In color mode, this output provides the blue gun serial video. In monochrome mode, it should be used with the red/TTL video 1 output to decode four video intensities. GREEN/GP1 27 0 Green/General Purpose 1: In color mode, this output provides the green gun serial video. In monochrome mode, it is a general purpose TTL output which is asserted if the AREDB/AGP1 input is asserted when the corresponding character dot data is loaded into the video shift register. LUM/G P2 26 0 Luminance/General Purpose 2: In color mode, this output is the logical-OR of the RGB foreground video. It is low during a blanking interval and during the foreground portion of the cursor display. In monochrome mode, it is a general purpose TTL output which is asserted if the ABLUEB/AGP2 input is asserted when the corresponding character dot data is loaded into the video shift register. UL 13 I Underline Timing: Indicates the scan line(s) for the underline attribute. Latched on the falling edge of BLANK. BLINK 11 I Blink Timing: This input is sampled on the falling edge of BLANK to provide the blink rate for the blink attribute. Should be a submultiple of the frame rate. BLANK 12 I Screen Blank: When high, this input forces the video outputs to the specified background color in color mode and to the level specified by the BKGND input (either black or gray) in monochrome mode. RBLANK 7 I Retrace Blank: This input is used to force the video outputs to a low during retrace periods. If pulled high, it will automatically suppress video during the retrace periods when BLANK is high. The user may also pulse this input while BLANK is high to selectively suppress raster video. AGREENF/BKGND 17 I Green Foreground/Background Intensity: In color mode, this input activates the GREEN! GP1 output during the foreground (character video) portion of the associated character block. In monochrome mode, this input specifies gray or black screen background. ABLUEF/ABLANK 23 I Blue Foreground/Blank Attribute: In color mode, this input activates the BLUE/TTLV2 output during the foreground (character video) portion of the associated character block. In monochrome mode, this input generates a blank space for the associated character. The blank space intensity is controlled by the AGREENF/BKGND input, the reverse video attribute and cursor input. AREDF/AHILT 25 I Red Foreground/Highlight Attribute: In color mode, this input activates the RED/TTLV1 output during the foreground (character video) portion of the associated character block. In monochrome mode, this input highlights the associated character (including underline). CURSOR 8 I Cursor Timing: This input provides the timing for the cursor video. In color mode, with CURSOR and CMODE high, the RGB outputs are driven high (white cursor). If CMODE is low, or in monochrome mode, this input reverses the intensities of the video and attributes. Cursor position, shape, and blink rate are controlled by this input. CMODE 9 I Cursor Mode: Used in color mode only. When CURSOR and CMODE are high, the RGB outputs are driven high (white cursor). When CURSOR is high and CMODE is low, the RGB outputs are logically inverted (reverse video cursor). AUL 19 I Underline Attribute: Specifies a line to be displayed in the character block. The specific line(s) are specified by the UL input. All other attributes apply to the underline video.

2.98 Signetics MICROPROCESSOR DIVISION JANUARY 1983

COLOR/MONOCHROME ATTRIBUTES CONTROLLER (CMAC) SCB2675

Preliminary

PIN DESIGNATION (Continued) MNEMONIC PIN NO. TYPE NAME AND FUNCTION ABLINK 16 I Blink Attribute: In color mode, this active high input will drive the foreground RGB combination to the background RGB combination. In monochrome mode, the associated character or background is driven to the intensity determined by BKGND, reverse video attribute and the cursor input. ADOUBLE 14 I Double Width Attribute: This active high input causes the associated character video to be shifted out of the serial shift register at one half the dot frequency (DCLK). The CCLK output is not affected. AREDB/AGP1 21 I Red Background/General Purpose Attribute 1: In color mode, this input activates the RED/TTLV1 output during the background portion of the associated character block. In monochrome mode, it activates the GREEN/GP1 output for the associated character block. ABLUEB/AGP2 22 I Blue Background/General Purpose Attribute 2: In color mode, this input activates the BLUE/TTLV2 output during the background portion of the associated character block. In monochrome mode, it activates the LUM/GP2 output for the associated character block. AGREENB/ARVID 18 I Green Background/Reverse Video Attribute: In color mode, this input activates the GREENIGP1 output during the background portion of the associated character block. In monochrome mode, it causes the associated character block video intensities to be reversed. D0-D8 36-39, I Dot Data Input: These are parallel inputs corresponding to the character/graphic symbol 2-6 dot data for a given scan line. These inputs are strobed into the video shift register on the trailing (falling) edge of each character clock (CCLK). CO-C1 34-35 I Character Clock Control: The states of these two static inputs determine the internal divide factor for the CCLK output rate. RESET 15 I Reset: This active high input initializes the internal logic and resets the attribute latches. M/C 30 I Monochrome/Color Mode: This input selects whether the CMAC operates in monochrome or color mode. A low selects color mode and a high selects monochrome mode. ADOTM 24 I Dot Modulation Attribute: When DOTM and this input are high, the active dot width of the associated character video is one DCLK. When DOTM is high and this input is low, the active dot width of the associated character video is two DCLKs. DOTM 31 I Dot Width Modulation: When this input is high, two DCLKs are used for each dot shifted through the shift register. When this input is low, one DCLK is used.

DOTS 10 I Dot Stretching: Sampled at the falling edge of BLANK. When this input is high, one extra dot is appended to individual dots or groups of dots of the input parallel data and then transferred through the shift register. When this input is low, normal transfer of input parallel data results.

Signetics 2.99 MICROPROCESSOR DIVISION JANUARY 1983 COLOR/MONOCHROME ATTRIBUTES CONTROLLER (CMAC) SCB2675

Preliminary

BLOCK DIAGRAM

DCLK

C1 —I.- CHARACTER DOUBLE CLOCK 11-111-1 WIDTH ADOUBLE CO COUNTER LOGIC

VIDEO SHIFT DOT DOTM DO-D8 REGISTER MODULATION DOTS — 10 BITS LOGIC ADOTM

CCLK

UL RBLANK

BLINK VIDEO CURSOR —P.- AND CMODE ATTRIBUTE RED/TTLV1 MONOCHROME HIERARCHY ABLINK TTL BLUE/TTLV2 AND COLOR LOGIC AOL ATTRIBUTE DRIVERS GREENIGP1 MIC AND LUMIGP2 ABABLUEF/ABLANK CURSOR LOGIC AGREENFIBKGND BLANK AREDFIAHILT RESET ABLUEBIAGP2 -NI- VCC AGREENBIARVID -.11- Vae AREDBIAGP1 GND

FUNCTIONAL DESCRIPTION In color mode, eight colors for the charac- foreground and background are a function The CMAC consists of seven major sec- ter (foreground) and eight colors for the of the attribute and BKGND inputs, i.e., tions (see block diagram). The high speed background (area other than character) characters may be black, gray, white, or dot clock input is applied to a program- can be selected by the attribute inputs. In highlight (very white) while background mable divider to provide a character clock monochrome mode, the intensities of may be black, gray, or white (see Table 1). output for system timing. Parallel dot data is loaded into the video shift register on character boundaries and shifted into the Table 1 MONOCHROME MODE ATTRIBUTE CHARACTERISTICS video logic block at the dot rate specified by the dot modulation section. The appro- FOREGROUND BACKGROUND REV1 AHILT ABLINK2 priate attribute control inputs are selected VIDEO VIDEO by the mode select logic, latched inter- 0 0 0 W B nally on character boundaries, and com- 0 0 1 W/G B bined with the serial dot data to provide 0 1 0 H B monochrome or color video outputs. 0 1 1 H/W B 1 0 0 B G The BLANK input defines the active 1 0 1 B/W G/B screen area. In color mode, the video out- 1 1 0 B W puts are forced to the specified back- 1 1 1 B/H W/B ground color when this signal is asserted; in monochrome mode the video outputs NOTES 1. REV= (BKGND) XOR (ARVID): are forced to the states defined by the BKGND ARVID REV BKGND input, i.e., black if dark back- 0 o 0 ground is selected and gray if light back- o 1 1 ground is selected. A separate RBLANK 1 0 1 1 1 0 input allows the user to select the amount 2. For blinking, the video outputs are shown as 0/1, where 0 and 1 are the blink timing input states. of border around the active area when 3. Foreground includes underline when underlining is specified by AUL= 1. operating in color mode or in mono- 4. When ABLANK= 1, foreground component becomes same as background component chrome mode with light background. This 5. Codes for video outputs are as follows: CODE TTLV2 TTLV1 BEAM INTENSITY input can be tied high, in which case the 130 0 Black area outside the active area will be dark, or 0 1 Gray it may be pulsed during BLANK periods to 0 White externally control the border widths. H 1 Highlight

2.100 Signetics MICROPROCESSOR DIVISION JANUARY 1983

COLOR/MONOCHROME ATTRIBUTES CONTROLLER (CMAC) SCB2675

Preliminary

Character Clock Counter other attributes (e.g., overscore) into the foreground and background components The character clock counter divides the video stream. The color mode provides of the character block in monochrome DCLK input to generate the character RGB foreground and background color mode. attributes. Both modes provide double clock (CCLK). The divide factor is speci- In color mode, the colors of the fore- width characters, blink, underline, dot fied by the clock control inputs (C1-00) as ground and background components are width control and dot stretching. follows: specified by the corresponding attribute The cursor and attribute inputs are pipe- inputs; AREDF, AGREENF and ABLUEF 2 SCB2675B lined internally to allow for system pipe- dictate the color of the foreground compo DOTS/ CCLK line propagations. The cursor input signal nent while AREDB, AGREENB and Cl CO CHAR. DUTY CYCLE* is delayed internally by two CCLKs (one ABLUEB do the same for the background for RAM and one for the character genera- component. In this mode, the serial dot 0 0 10 5/5 tor), while the attribute inputs are delayed data and pipelined cursor and attributes 0 1 7 4/3 for one CCLK to account for the delay of are combined to generate four video out- 1 0 8 4/4 the character data through the character puts. The RED, GREEN and BLUE outputs 1 1 9 5/4 generator latches. The attribute timing separately contain the corresponding 'High/low inputs (BLINK, UL and DOTS) are clocked foreground and background components. into the 2675 at the beginning of each The LUM output is the logical-OR of the scan line time by the falling edge of foreground colors and can be used to SCB2675C BLANK. Thus, these inputs must be in drive a separate monochrome monitor or to select a different set of colors for the DOTS/ CCLK their proper state at the falling edge of Cl CO foreground. CHAR. DUTY CYCLE* BLANK preceding the scan line where they are required to be active. The BLANK 0 0 10 5/5 signal itself is also delayed internally to 0 1 6 3/3 provide for the RAM and character genera- 1 0 8 4/4 tor delays (see figures 6 and 7). Internal 1 1 9 5/4 delays cause the video outputs to be SYMBOL VIDEO • High/low delayed relative to CCLK as illustrated in BACKGROUND figure 8. VIDEO The number of dot clocks/character is normally the number of dots/character as Video Logic listed above. However, when dot width Each character block consists of the three control is specified, the DCLK input is components shown in figure 1. Symbol divided by two before it is applied to the UNDERLINE video is generated from the dot data in- VIDEO character clock counter resulting in the puts D0-D8. Underline video is enabled by number of dot clocks/character being the AUL attribute and is generated during double those listed above, although the the scan lines for which the UL input is number of displayed dots/character re- active. Underline and symbol video are Figure 1. Character Block Definition mains the same. See Dot Modulation sec- always the same intensity or color, and tion 'of this data sheet. other attributes (e.g., ABLINK) apply to them equally. The combination of under- Video Shift Register line and symbol video is also referred to as On each character boundary, the parallel foreground video. Background video is the input dot data (D0-D8) is loaded into the area of the character block corresponding video shift register. The data is shifted out to the absence of foreground video. The least significant bit first (DO) at the DCLK assertion of the non-display attribute rate. If 10 dots/character are specified (ABLANK) causes the entire character (C1-C0=00), the tenth dot will be the block to be displayed as background. same as D8. The serial dot data from the In monochrome mode, the serial dot data video shift register is routed to the video and pipelined cursor and attributes are logic where it is combined with the cursor combined to generate four video intensi- and attribute control bits to produce the ties (black, gray, white and highlight) video data outputs. which are encoded on the TTLV1 and TTLV2 outputs as follows: Mode Select, Attribute and Cursor Control TTLV2 TTLV1 VIDEO INTENSITY The mode select logic multiplexes the 0 0 Black monochrome and color attribute inputs 0 1 Gray and outputs as specified by the M/C input. 1 0 White The monochrome mode provides blank, 1 1 Highlight reverse video, highlight and two general purpose attributes. The latter may be Table 1 describes the relationship be- used, with external logic, to combine tween attributes and video intensity of the Signetics 2.101

MICROPROCESSOR DIVISION JANUARY 1983 COLOR/MONOCHROME ATTRIBUTES CONTROLLER (CMAC) SCB2675

Preliminary

Dot Modulation Logic which enables the feature on the entire 1. Make horizontal lines and vertical lines The dot modulation logic controls the display, or low, which disables the feature. appear the same brightness on the video shift register to supply dot stretch- With ADOTM high, the dot width of display. ing and dot width control. characters can be selectively controlled 2. Provide two different brightness levels by assertion of the ADOTM attribute input. for characters without requiring a moni- Dot stretching is controlled by the DOTS When operating in this mode, the dot tor with analog brightness inputs. input which is sampled each scan line at clock input is divided by two before being the trailing (falling) edge of BLANK. If However, note that the effects produced applied to other circuits in the CMAC. This DOTS is asserted at that time, all charac- by this feature are highly dependent on affects the CCLK output. ters on the following scan line will have the video amplifier characteristics of the dot stretching applied. Dot stretching When dot width control is enabled as monitor used. causes an extra dot to be added to in- above, two DCLKs are used for each video dividual dots or groups of dots as shown dot period. Asserting ADOTM for a partic- Double Width Logic in figures 2 and 3. Dot stretching can be ular character will cause each active video The double width logic controls the rate at used to: dot of the displayed character to be turned which dots are shifted through the video on for one DCLK and off for the other shift register. When the ADOUBLE input is 1. Compensate for low video bandwidth DCLK, while if ADOTM is negated for that asserted, the associated character video monitors (since the minimum active displayed segment with dot stretching character, the active video dot for that will be shifted at one half the DCLK rate, is two DCLKs). character will be turned on (black back- and the dot information for the next ground) or off (white background) for both 2. Assure crisp black characters when character will be loaded into the shift DCLK times (see figures 2 and 4). Only the operating in white background mode. register two CCLKs later. The CCLK out- character video component of the charac- 3. Provide thick characters as a means of put is not affected. If a double width ter block is modulated. Underline video distinguishing areas of the display. character is specified at the last location and background are not affected by on- of a character row, the second half of the Dot width is controlled by the DOTM and time modulation. Width control can be double width character (one CCLK) will ex- ADOTM inputs. DOTM is tied either high, used to: tend into the horizontal front porch.

DOT STRETCHING DOT CLOCK

NORMAL

STRETCHED

DISPLAYED ON MONITOR NORMAL _-

STRETCHED

DOT WIDTH CONTROL DOT CLOCK

WIDTH ADOTM = 0

WIDTH ADOTM -1

DISPLAYED ON MONITOR WIDTH ADOTM = 0

WIDTH ADOTM =1 • • •

Figure 2. Dot Modulation Timing

2.102 Signetics MICROPROCESSOR DIVISION JANUARY 1983

COLOR/MONOCHROME ATTRIBUTES CONTROLLER (CMAC) SCB2675

Preliminary

CHARACTER AS STORED ACTUAL CHARACTER DISPLAYED IN CHARACTER GENERATOR WITH DOT STRETCHING EMPLOYED 0 0 0 ) 0 0 0 0 0 0 o 0000008 0 0 § 8 0 0

Figure 3. Dot Stretching

NORMAL CHARACTER DISPLAY ACTUAL CHARACTER DISPLAY WITHOUT WIDTH CONTROL WITH WIDTH CONTROL §)00000

Figure 4. Dot Width Control

ABSOLUTE MAXIMUM RATINGS1 PARAMETER RATING UNIT Operating ambient temperature2 0 to + 70 °C Storage temperature — 65 to + 150 °C All voltages with respect to ground3 —0.5 to + 6.0 V

DC ELECTRICAL CHARACTERISTICS TA= 0°C to +70°C, Vcc= 5V 5%, VBB = figure 545'6 LIMITS PARAMETER TEST CONDITIONS UNIT Min Typ Max VIL Input low voltage 0.8 V VIH Input high voltage 2.0 V VOL Output low voltage IOL = 4mA 0.4 V VOH Output high voltage 106 = —400µA 2.4 V in_ Input low current VIN= 0.4V DCLK —800 i.,A All other inputs — 400 µA IIH Input high current VN = 2.4V DCLK 40 µA All other inputs 20 AA

'cc Vcc supply current VIN = OV, Vcc = max 80 mA !Be Vee supply current Figure 5 120 mA Signetics 2.103 MICROPROCESSOR DIVISION JANUARY 1983

COLOR/MONOCHROME ATTRIBUTES CONTROLLER (CMAC) SCB2675

Preliminary

AC ELECTRICAL CHARACTERISTICS TA = 0°C to + 70°C, Vcc= 5V ± 5%, VBB= figure 54'5'6 TENTATIVE LIMITS PARAMETER TEST CONDITIONS 25MHz VERSION 18MHz VERSION UNIT Min Max Min Max Dot clock timing7 fp Frequency 25 18 MHz t DH High time 15 22 ns tDL Low time 15 22 ns Setup times8 tSB BLANK to CCLK 40 50 ns tSA Attributes to CCLK 40 50 ns ISD D0-D9 to CCLK 60 70 ns tSK CURSOR to CCLK 40 50 ns tBD CO, Cl to DCLK 20 20 ns tSR RBLANK to DCLK 20 20 ns tsm BLINK, UL, DOTS to BLANK 20 20 ns Hold times8 the BLANK from CCLK 20 20 ns tHA Attributes from CCLK 20 20 ns tHD DO-D8 from CCLK 30 30 ns tHK CURSOR from CCLK 20 20 ns tHC CO, Cl from DCLK 20 20 ns tHR RBLANK from DCLK 20 20 ns tHM BLINK, UL, DOTS from BLANK 20 20 ns Delay times7 CL = 50pF IDC CCLK from DCLK 55 70 ns toy Other outputs from DCLK 30 60 35 70 ns NOTES 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature. 3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying voltages greater than the rated maxima. 4. Parameters are valid over operating temperature range unless otherwise specified. 5. All voltage measurements are referenced to ground. For testing, all input signals swing between 0.4V and 2.4V with a transition time of 3ns maximum. All time measurements are referenced at input voltages of 0.8V and 2.0V and at output voltages of 0.8V and 2.0V as appropriate. 6. Typical values are at +25°C, typical supply voltages and typical processing parameters. 7. See figure 8. 8. See figures 6, 7, 9, and 10.

Figure 5. Recommended VBB Test Circuit

2.104 Signetics MICROPROCESSOR DIVISION JANUARY 1983

COLOR/MONOCHROME ATTRIBUTES CONTROLLER (CMAC) SCB2675

Preliminary

CCLK

riSBH

BLANK

BLINK, UL, DOTS

tHA

ATTRIBUTES.'

DOT DATA2 DO-D8

I 1st I 2nd I LAST -1 LAST I BKOND4 VIDE02 BKOND4 CHAR CHAR CHAR CHAR

NOTES, 1. Attributes include: ABLINK, ABLANK, ARVID, AUL, AHILT, ADOUBLE, ADOTM, two general purpose, and foreground/background colors. 2. One CCLK delay for dot data (obtained from delay through character generator). 3. See figure 8 for detail timing of video outputs. 4. Non-active scan time. VIDEO reverts to polarity selected by the BKGND input in monochrome mode.

Figure 6. CMAC Pipeline Timing

CCLK

CURSOR tHK

VIDEO

CHARACTER WITH CURSOR

Figure 7. Cursor Pipeline Timing

Signetics 2.105 MICROPROCESSOR DIVISION JANUARY 1983

COLOR/MONOCHROME ATTRIBUTES CONTROLLER (CMAC) SCB2675

Preliminary

tOH IDL

DCLK

tDC

CCLK

.0— toy

OTHER LAST — 1 OUTPUTS PIXEL

CHARACTER N — 1 CHARACTER N

Figure 8. Output Pipeline Timing

MONOCHROME MODE

DCLK

t8A-1 H "1/ 22 BKGND

tHR ISR 22 RBLANK

VIDEO GRAY BLACK GRAY BLACK 22

Figure 9. BKGND and RBLANK Timing During Inactive Scan Time (Blank =1)

DCLK

CCLKI

tsc H .4—tSC CO, Cl

NOTE 1. The high and low times of CCLK may be controlled independently. Figure 10. Clock Divider Timing

2.106 Signetics MICROPROCESSOR DIVISION JANUARY 1983

COLOR/MONOCHROME ATTRIBUTES CONTROLLER (CMAC) SCB2675

Preliminary

OSC

DCLK

- R 2670 DO CHARACTER - G CHARACTER RAM MONITOR GENERATOR - B D7 - LUM

2675 CMAC

LAY ADDR ATTRIBUTE INPUTS

ATTRIBUTE RAM

Figure 11. System Block Diagram of SCB2675 in Color Mode

OSC

DCLK

- TTLVI ) 2670 MONITOR CHARACTER - TTLV2 CHARACTER RAM GENERATOR > 07 O PURPOSE - OUTPUTS a 2675 CMAC

ATTRIBUTE INPUTS

ATTRIBUTE RAM

Figure 12. System Block Diagram of SCB2675 in Monochrome Mode

Signetics 2.107

Section 3 Single Chip Microcomputers

Signetics

MICROPROCESSOR DIVISION JANUARY 1983 SINGLE CHIP 8-BIT MICROCOMPUTERS SCN80 SERIES

Preliminary DESCRIPTION FEATURES PIN CONFIGURATION The Signetics SCN80 Series microcom- 8-bit CPU, ROM, RAM, I/O in a 40-pin puters are self-contained, 8-bit processors package which contain the system timing, control 24 quasi bidirectional I/O lines TO Vcc logic, RAM data memory, ROM program Two test inputs memory (8048/49/50 only), and I/O lines XTAL1 T1 Internal counter/timer necessary to implement dedicated control XTAL2 P27 functions. All SCN80 Series devices are Single•level vectored interrupts: exter- RESET P26 pin and program compatible, differing nal, counter/timer only in the size of the on-board program Over 90 instructions, 70% single byte ss P25 ROM and data RAM, as follows: 1,36µs or 2.5µs instruction cycle, all in- INT P24

structions one or two cycles EA P17 TYPE RAM SIZE ROM SIZE Expandable memory and I/O RD P16 SCN8048 64 x 8 1Kx 8 Low voltage standby PSEN P15 SCN8049 128 x 8 2K x 8 TTL compatible inputs and outputs SCN 8050 256 x 8 4K x 8 WR P14 Single + 5V power supply SCN8035 64 x 8 — ALE P13 SCN8039 128 x 8 — DBO P12 SCN8040 256 x 8 — Del P11

Program memory can be expanded exter- DB2 P10 nally up to a maximum total of 4K bytes DB3 VDD without paging. Data memory can also be DB4 PROG expanded externally. I/O capabilities can DB5 P23 be expanded using standard devices or the 8243 I/O expander. FUNCTIONAL DESCRIPTION DB6 P22 P21 The SCN80 Series processors are designed The following is a general functional de- DB7 to be efficient control processors as well scription of the SCN80 Series microcom- v55 P20 as arithmetic processors. They provide an puters. Refer to the block diagram. instruction set which allows the user to TOP VIEW directly set and reset individual lines within its I/O ports as well as test individual bits within the accumulator. A large variety of branch and table look-up instructions make these processors very efficient in implementing standard logic functions. Also, special attention has been given to ORDERING CODE code efficiency. Over 70% of the instructions are a single byte long and all others SCN80 m AO ❑ ❑ 40 (CPxxxx) are only 2 bytes long. L CUSTOM ROM PATTERN NUMBER An on-chip 8-bit counter is provided which Applies to masked ROM versions only. Number will be can count, under program control, either assigned by Signetics. Contact Signetics sales office internal clock pulses (with a divide by 32 for ROM pattern submission requirements. prescaler) or external events. The counter can be programmed to cause an interrupt 40 Pin on terminal count. PACKAGE N = Plastic DIP I =Ceramic DIP

SPEED 6 = 6MHz clock B= 11MHz clock

OPERATING TEMPERATURE RANGE C= Cr to + 70°C

ROM/RAM (bytes) 35 = EXT/64 48 = 1K/64 39= EXT/128 49= 2K/128 40 = EXT/256 50 = 4K/256

Signetics 3.1 MICROPROCESSOR DIVISION JANUARY 1983 SINGLE CHIP 8-BIT MICROCOMPUTERS SCN80 SERIES

Preliminary

PIN DESIGNATION MNEMONIC PIN NO. TYPE NAME AND FUNCTION DBO-DB7 12-19 I/O Bus. Bidirectional I/O port can be read from or written into using the RD or WR strobes. This port can also be statically latched. Contains the 8 lower address bits during an access of external memory and receives the addressed instruction under control of PSEN. PSEN, ALE, RD, and WR determine whether the access is an instruction fetch or a RAM read/write. P1O-P17 27-34 I/O Port 1. 8-bit quasi-bidirectional I/O port.1 P20-P27 21-24, I/O Port 2. 8-bit quasi-bidirectional I/O port.1 P20-P23 contain the 4 higher order address bits during an 35-38 access of external program memory and also serve as a 4-bit I/O expander bus for the 8243. PROG 25 I/O Output strobe (active low) for the 8243 I/O expander. TO 1 I/O Input pin sensed using the JTO and JNTO instructions. Clock output pin when designated as such by the ENTO CLK instruction. T1 39 I Input pin sensed using the JT1 and JNT1 instructions. Can be designated as the timer/counter input by the STRT CNT instruction. INT 6 I Interrupt input pin. When low causes interrupt if interrupt is enabled. Can also be used as an input which is testable with the JNI instruction. Interrupt is disabled during and after a RESET. RESET 4 I Reset input pin is that used to initialize the microcomputer. Active low. Internal pullup - 75k02. During program verification the address is latched by a "0" to "1" transition on RESET and the data at the addressed location is output on BUS. ALE 11 0 Address latch enable. Occurs each clock cycle and is useful for clocking and sampling. During external program or data memory access, ALE is used to strobe the address information multiplexed on the DBO-DB7 outputs. RD 8 0 Read strobe. Active low strobe used to gate data onto BUS lines when reading from an external source. WR 10 0 Write strobe. Active low strobe used to write data from BUS lines to an external destination. EA 7 I External access input. When high forces instruction fetches from external memory. Internal pullup - 10M0. PSEN 9 0 Program store enable. Active low strobe that occurs only during a fetch from external program memory. SS 5 I Single step. Active low input which is used with ALE to cause the microcomputer to execute a single instruction. Internal pullup - 300ka XTAL1 2 I One side of crystal (or L) input for internal oscillator. Can also be used as an input for an external timing source2. XTAL2 3 I Other side of crystal. Vss 20 I Circuit ground. Vcc 40 I Power input, + 5VDC.

VDD 26 I RAM power input; low power standby pin. NOTES 1. Each pin on these ports can be assigned, under program control, to be an input or an output. A pin is designated as an input by writing a logic "1" to the pin. RESET sets all pins to the input mode. Each pin has an internal pullup of approximately 50kft. 2. Non-standard TTL

3.2 Signetics MICROPROCESSOR DIVISION JANUARY 1983

SINGLE CHIP 8-BIT MICROCOMPUTERS SCN80 SERIES

Preliminary BLOCK DIAGRAM

P20 DBO

P27 DB7 () EXPANSION TO 18 MORE I/O AND MEMORY

PORT 2 BUS BUFFER BUS BUFFER

PORT 2 LATCH BUS LATCHES 8 HIGH PROGRAM (LOW 4) AND RESIDENT AND LOW PORT 2 LATCH COUNTER EXPANDER ROM PC TEMP REG (HIGH 4) (4) PORT I/O (8048/49/50 ONLY)

DECODE

BY FREDC'RE 3 5 TIMER EVENT LOWER PROGRAM COUNTER PROGRAM STATUS TEST 1 (8) COUNTER (8) WORD

PORT 1 P10 BUS (8) BUFFER AND P17 LATCH

ACCUMULATOR INSTRUCTION RAM ADDRESS TEMP REG (8) FLAGS (8) REGISTER REGISTER AND DECODER \.7 MULTIPLEXER

REGISTER 0 ACCUMULATOR LATCH ARITHMETIC REGISTER 1 LOGIC a-- TEST 0 UNIT REGISTER 2 (8) TEST 1 INT REGISTER 3 W FLAG 0 CONDITIONAL REGISTER 4 VDD FLAG 1 RAM SUPPLY BRANCH LOGIC REGISTER 5 POWER _ Vc0 FA + 5V MAIN SUPPLY CARRY SUPPLY REGISTER 6 V., DEC MAL -a— ACC ADJUST REGISTER 7 ECODER

ACC BIT TEST D 8 LEVEL STACK (VARIABLE LENGTH) OPTIONAL SECOND REGISTER BANK

CONTROL AND TIMING DATA STORE

TO INT RESET PROG EA XTAL1 XTAL2 ALE PSEN SS RD WR L

RESIDENT RAM ARRAY 1 1 1 TIMING INTERRUPT INITIALIZE EXPANDER CPU OSCILLATOR PROGRAM SINGLE READ/WRITE OUTPUT STROBE MEMORY XTAL MEMORY STEP STROBES SEPARATE ENABLE ADDRESS LATCH ENABLE

Signetics 3.3 MICROPROCESSOR DIVISION JANUARY 1983 SINGLE CHIP 8-BIT MICROCOMPUTERS SCN80 SERIES

Preliminary

PROGRAM MEMORY either of two RAM pointer registers at An interrupt or CALL to a subroutine Resident program memory consists of up locations 0 and 1. The first eight locations causes the contents of the program to 4K bytes of ROM. The program memory of RAM (0-7) are designated as working counter to be stored in one of the 8 regis- is divided into pages of 256 bytes each. As registers and are directly addressable by ter pairs of the program counter stack. The shown in the memory map, figure 1, pro- several instructions. pair to be used is determined by a 3-bit stack pointer which is part of the Program gram memory is also divided into two By selecting register bank 1, RAM loca- Status Word (PSW). Data RAM locations 8 2048-byte banks, MBO and MB1. 4096 tions 24-31 become the working registers, through 23 are available as stack registers bytes can be addressed directly. If more replacing those in register bank 0 (0-7). memory is required, an I/O port can be and are used to store the program counter used to address locations over 4095. RAM locations 8-23 are designated as the and 4 bits of PSW. The stack pointer, when stack. Two locations (bytes) are used per initialized to 000, points to RAM locations There are three locations in program mem- CALL, allowing nesting of up to eight sub- 8 and 9. The first subroutine jump or inter- ory of special importance. These locations routines. rupt results in the program counter con- contain the first instruction to be ex- tents being transferred to locations 8 and ecuted upon the occurrence of one of If additional RAM is required, up to 256 9 of the RAM array. The stack pointer is three events. bytes may be added and addressed direct- then incremented by one to point to loca- ly using the MOVX instructions. If more LOCATION EVENT tions 10 and 11 in anticipation of another RAM is required an I/O port can be used to CALL. Nesting of subroutines within sub- 0 Activation then deactiva- select one (256-byte) bank of external routines can continue up to eight times tion of the RESET line. memory at a time. without overflowing the stack. If overflow 3 Activation of the INT line does occur the deepest address stored when the external inter- PROGRAM COUNTER AND (location 8 and 9) will be overwritten and rupt is enabled. STACK lost since the stack pointer overflows 7 An overflow of the timer/ from 111 to 000. It also underflows from The Program Counter (PC) is a 12-bit counter if the T/C interrupt 000 to 111. is enabled. counter/register that points to the location from which the next instruction is to The end of a subroutine, which is sig- be fetched. The 8048 and 8049 will auto- nalled by a return instruction (RET or DATA MEMORY matically address exernal memory when RETR), causes the stack pointer to be Resident data memory, as shown in figure the boundary of their internal memory is decremented and the contents of the re- 2, consists of up to 256 bytes of RAM. All exceeded. All processors access external sulting register pair to be transferred to locations are indirectly addressable by memory if EA is high. the program counter.

4095 255 .1( 8040/8050 USER RAM 128 x 8 128 127 8039/8049 USER RAM 64 x 8 64 2048 SEL MB1 63 2047 8035/8048 SEL MBO USER RAM 32 32 x 8 31 BANK 1 WORKING DIRECTLY REGISTERS ADDRESSABLE Lol 1024 8 x 8 WHEN BANK 1 1023 R1' IS SELECTED O 24 RO O is 23

O 8 LEVEL STACK ADDRESSED INDIRECTLY z 8 LOCATION 7 —TIMER OR O THROUGH 54' INTERRUPT VECTORS USER RAM R1 OR RO PROGRAM HERE 16 x 8 (RO' OR R1 O 5 z 4 0 LOCATION 3— EXTERNAL 7 3 BANK 0 INTERRUPT VECTORS WORKING 2 PROGRAM HERE DIRECTLY REGISTERS ADDRESSABLE RESET VECTORS 8 x 8 WHEN BANK 0 PROGRAM HERE R1 IS SELECTED ADDRESS RO •

Figure 1. Program Memory Map Figure 2. Data Memory Map

3.4 Signetics MICROPROCESSOR DIVISION JANUARY 1983 SINGLE CHIP 8-BIT MICROCOMPUTERS SCN80 SERIES

Preliminary

OSCILLATOR AND CLOCK divided by 32 before they are input to the Ports 1 and 2 8-bit counter. External events are input The processor contains its own internal Ports 1 and 2 are each 8 bits wide and have directly to the counter. The maximum fre- oscillator and clock driver. A crystal, in- identical characteristics. Data written to quency that can be counted is one third of ductor, or external pulse generator may be these ports is statically latched and re- the frequency of the cycle counter. The used to determine the oscillator frequency mains unchanged until rewritten. As input minimum positive duty cycle that can be (see figure 3). The output of the oscillator ports these lines are non-latching, i.e., in- detected is 0.2 Icy. The counter is under is divided by three and can be output on puts must be present until read by an in- program control and can be made to gen- the TO pin by executing the ENTO CLK input instruction. Inputs are fully TTL com- erate an interrupt to the processor when it struction. This CLK signal is divided by patible and outputs will drive one standard overflows. five to define a machine (instruction) TTL load. cycle. It is available on pin 11 as ALE. INTERRUPT The lines of ports 1 and 2 are called quasi- bidirectional because of a special output TIMER/EVENT COUNTER An interrupt may be generated by either an external input (TNT, pin 6) or the overflow circuit structure which allows each line to An internal counter is available which can of the internal counter, when enabled. In serve as an input, an output, or both even count either external events or machine either case, the processor completes exe- though outputs are statically latched. Fig- cycles (+32). The machine cycles are cution of the present instruction and then ure 4 shows the circuit configuration. does a CALL to the interrupt service rou- Each line is continuously pulled up to tine. After service, a RETR instruction +5V through a resistive device of rela- restores the machine to the state it was tively high impedance (--50K). This pullup prior to the interrupt. The external inter- is sufficient to provide the source current ,s 1 11.112 XTAL1 rupt has priority over the internal inter- for a TTL high level yet can be pulled low MHz rupt. by a standard TTL gate thus allowing the 'T = same pin to be used for both input and 3 INPUT/OUTPUT output. To provide fast switching times in XTAL2 C = 15-25pF The processor has 27 lines which can be a "0" to "1" transition a relatively low im- (INCLUDES SOCKET, I C used for input or output functions. These pedance device (-5k0) is switched in STRAY) lines are grouped as 3 ports of 8 lines each momentarily (— 500ns) whenever a "1" is SERIES RESONANT, AT CUT CRYSTAL which serve as either inputs, outputs or written to the line. When a "0" is written to bidirectional ports and 3 "test" inputs the line, a low impedance (-3000) device which can alter program sequences when overcomes the light pullup and provides DRIVING tested by conditional jump instructions. TTL current sinking capability. FROM EXTERNAL SOURCE

+ 5V

ORL, ANL XTAL1

+ 5V

XTAL2 +5V

BOTH X1 AND X2 SHOULD BE DRIVEN. RESISTORS TO VCC ARE NEEDED TO ENSURE INTERNAL 5K 1/0 .1= 3.8V IF TTL CIRCUITRY IS USED. BUS D =50K THE MINIMUM HIGH AND THE MINIMUM LOW TIMES ARE 45%. D FLIP 110 PIN FLOP PORT 1 LC AND 2 OSCILLATOR MODE CLK 0 L C NOMINAL 1 45,H 2OpF WRITE 120,,H 2OpF 27r NIC' PULSE XTAL1 C + 3Cpp C' 2 INPUT Cpp = 5-10pF BUFFER XTAL2 PIN.TO.PIN CAPACITANCE IN EACH C SHOULD BE APPROXIMATELY 20pF, INCLUDING STRAY CAPACITANCE.

Figure 3. Crystal Oscillator Mode Figure 4. "Quasi Bidirectional" Port Structure

Signetics 3.5 MICROPROCESSOR DIVISION JANUARY 1983 SINGLE CHIP 8-BIT MICROCOMPUTERS SCN80 SERIES

Preliminary

Since the pulldown transistor is a low im- is at ground and only VDD is maintained at pedance device a "1" must first be written its specified voltage. Applying RESET to to any line which is to be used as an input. the processor through the RESET pin in- Reset initializes all lines to the high hibits any access to the RAM by the pro- impedance "1" state. This structure cessor and guarantees that RAM cannot allows input and output on the same pin be inadvertently altered as power is and also allows a mix of input lines and ACTIVE removed from Vcc• PULLUP output lines on the same port. The quasi- A typical power down sequence occurs as bidirectional port in combination with the shown in figure 6. ANL and ORL logical instructions provide External Reset an efficient means for handling single line INSTRUCTION SET inputs and outputs within an 8-bit processor. The SC80 Series instruction set consists of over 90 one and two byte instructions BUS (see table 1). Program code efficiency is BUS is also an 8-bit port which is a true high because: (1) working registers and bidirectional port with associated input program variables are stored in RAM, and output strobes. If the bidirectional AF which require only one byte to address 10VI feature is not needed, BUS can serve as and (2) program memory is divided into either a statically latched output port or pages of 256 bytes each, which means non-latching input port. Input and output Power on Reset that branch destination addresses require lines on this port cannot be mixed. one byte.

As a static port, data is written and Figure 5. Reset Circuits The instruction set efficiently manipulates latched using the OUTL instruction and in- and tests bits in addition to performing put using the INS instruction. The INS and logical and arithmetic operations upon OUTL instructions generate pulses on the SINGLE STEP and the testing of bytes. A set of move in- corresponding RD and WR output strobe structions operates indirectly upon either lines; however, in the static port mode By proper control of the SS line, the micro- RAM or ROM, which permits efficient ac- they are generally not used. As a bidirec- computer can be made to execute one in- cess of pointers and data tables. The indi- tional port, the MOVX instructions are struction and then pause or wait until the rect jump instruction performs a multi (up used to read and write to the port. A write single step switch is activated again. to 256) way branch upon the content of the accumulator to addresses stored in a look- to the port generates a pulse on the WR POWER DOWN MODE output line and output data is valid at the up table. The "decrement register and trailing edge of WR. A read of the port gen- The SC80 Series devices permit power to jump if not zero" instruction saves a byte erates a pulse on the RD output lineand in- be removed from all but the data RAM every time it is used versus using separate put data must be valid at the trailing edge array for low power standby operation. In increment and test instructions. of RD. When not being written or read, the the power down mode the contents of The on-chip counter enables either exter- BUS lines are in a high impedance state. data RAM can be maintained while draw- nal events or time to be counted off-line ing typically 5% of normal operating from the main program. The processor can Test and INT Inputs power. either test the counter (under program Three pins serve as inputs and are test- Vcc serves as the 5V supply pin for the control) or cause its overflow to generate able with the conditional jump instruction. bulk of the circuitry while the VDD pin sup- an interrupt. These features are highly These are TO, T1, and INT. These pins plies only the RAM array. In normal opera- desirable for real time applications. See allow inputs to cause program branches tion both pins are at + 5V. In standby, Vcc table 2 for instruction timing. without the necessity to load an input port into the accumulator. The TO, T1, and INT pins have other possible functions as well.

RESET INPUT The reset input provides a means for ini- POWER SUPPLY PROCESSOR tialization for the processor. This Schmitt- INTERRUPTED I I trigger input has an internal pullup resis- POWER SUPPLY I NORMAL POWER tor which in combination with an external FAIL SIGNAL -l— ON SEQUENCE I FOLLOWS 1µF capacitor provides an internal reset I pulse of sufficient length to guarantee all RESET circuitry is reset. If the reset pulse is generated externally, the reset pin must DATA SAVE ACCESS TO be held at ground (0.5V) for at least 10 ROUTINE DATA RAM milliseconds after the power supply is EXECUTED INHIBITED within tolerance. Only five machine cycles (12.5ps @ 6MHz) are required if power is already on and the oscillator has stabil- Figure 6. Power Down Sequence ized. Typical circuitry is shown in figure 5

3.6 Signetics MICROPROCESSOR DIVISION JANUARY 1983 SINGLE CHIP 8-BIT MICROCOMPUTERS SCN80 SERIES

Preliminary

Table 1 INSTRUCTION SET

INSTRUCTION CODE FLAGS MNEMONIC FUNCTION DESCRIPTION D7 D6 D5 04 D3 D2 D1 Do CYCLES BYTES C AC FO F1 BS

ACCUMULATOR

ADD A, if data (A).- (A) + data Add immediate the specified data to the 0 0 0 0 0 0 1 1 2 2 • • accumulator. d7 d6 d5 d4 d3 d2 d 1 do

ADD A, Rr (A).- (A) + (Rr) Add contents of designated register to 0 1 1 0 1 r r r 1 1 • • for r = 0 - 7 the accumulator. ADD A, @ Rr (A).- (A) + ((Rr)) Add indirect the contents the data 0 1 1 0 0 0 0 r 1 1 • • for r = 0 - 1 memory location to the accumulator. ADDC A, tt data (A).- (A) + (C) + data Add immediate with carry the specified 0 0 0 1 0 0 1 1 2 2 • • data to the accumulator. d7 d6 d5 d4 d3 d2 di d0 ADDC A, Rr (A) w- (A) + (C) + (Rr) Add with carry the contents of the 0 1 1 1 1 r r 1 1 1 • • for r = 0 - 7 designated register to the accumulator. ADDC A, @ Rr (A).- (A) + (C) + ((Rr)) Add indirect with carry the contents of 0 1 1 1 0 0 0 r 1 1 • • for r = 0 - 1 data memory location to the accumulator. ANL A, tt data (A).- (A) AND data Logical AND specified immediate data 0 t 0 1 0 0 1 1 2 2 with accumulator. d7 d6 d5 d4 d3 d2 di d0 ANL A, Rr (A).- (A) AND (Rr) Logical AND contents of designated 0 1 0 1 1 r r r 1 1 for r = 0 - 7 register with accumulator. ANL A, @ Rr (A).- (A) AND ((Rr)) Logical AND indirect the contents of 0 1 0 1 0 0 0 r for r = 0 - 1 data memory with accumulator. CPL A (A)w- NOT (A) Complement the contents of the 00110111 1 1 accumulate, CLR A (A).- 0 Clear the contents of the accumulator. 00100111 DA A Decimal adjust the contents of the 0 1 0 t 0 1 1 1 1 1 • • accumulator. DEC A (A).- (A) - 1 Decrement the accumulator's 0 0 0 0 0 1 contents by 1. INC A (A).- (A) + 1 Increment the accumulator's contents 0 0 0 1 0 1 1 1 1 1 by 1. ORL A, S data (A).- (A) OR data Logical OR specified immediate data 0 1 0 0 0 0 1 1 2 2 with accumulator. d7 d6 d5 d4 d3 d2 d1 do ORL A, Rr (A).- (A) OR (Rr) Logical OR contents of designated 0 1 0 0 1 r r r for r = 0 - 7 register with accumulator. ORL A, @ Rr (A).- (A) OR ((Rr)) Logical OR indirect the contents of data 0 1 0 0 0 0 0 r for r = 0 - 1 memory location with accumulator. RL A (An + 1) -,- (An) Rotate accumulator left by 1.bit without 1 1 1 0 0 1 (A0) -•- (57) carry. for N = 0 w- 6 RLC A (An + 1) .- (An); n= 0- 6 Rotate accumulator left by 1-bit through 1 1 1 1 0 1 1 1 1 1 • (it).- (C) carry. (C).- (A7) RR A (An).- (An + 1); n= 0- 6 Rotate accumulator right by 1-bit 011101 (A7) (A0) without carry. RRC A (An).- (An + 1); n= 0- 6 Rotate accumulator right by 1-bit 0 1 1 0 0 1 1 1 1 1 • (A7)'-- (C) through carry. (C).- (A0) SWAP A (A4_7).-."(A0 - 3) Swap the 2 4-bit nibbles in the 0 1 0 0 0 1 accumulator. XRL A, $1 data (A).- (A) XOR data Logical XOR specified immediate data 1 1 0 1 0 0 1 1 2 2 with accumulator. d7 d6 ds 44 d3 d2 d1 d0 XRL A, Rr (A).- (A) XOR (Rr) Logical XOR contents of designated 1 1 0 1 1 r r r for r = 0 - 7 register with accumulator. XRL A, @ Rr (A).- (A) XOR ((13r)) Logical XOR indirect the contents of data 1 1 0 1 0 0 0 r for r = 0 - 1 memory location with accumulator.

Signelics 3.7 MICROPROCESSOR DIVISION JANUARY 1983 SINGLE CHIP 8-BIT MICROCOMPUTERS SCN80 SERIES

Preliminary Table 1 INSTRUCTION SET (Continued) INSTRUCTION CODE FLAGS MNEMONIC FUNCTION DESCRIPTION D7 D6 D6 D4 D3 D2 Di Do CYCLES BYTES C AC FO Fl BS DATA MOVES (cont'd)

MOVP A, @ A (A) '.- ((A)) Move date in the current page into the 1 0 1 0 0 0 1 1 2 accumulator. MOVP3 A, 0 A (A).— ((A)) Move data in page 3 into the 1 1 1 0 0 0 1 1 2 in page 3 accumulator. MOVX A, @ Rr (A).— ((Rr)); r= 0— 1 Move indirect the contents of 1 0 0 0 0 0 0 r 2 1 external memory location into the accumulator. MOVX 0 Rr, A ((Rr)) -..— (A); r= 0— 1 Move indirect the contents of 1 0 0 1 0 0 0 r 2 1 the accumulator into external memory. XCH A, Rr (A).-"-(Rr); r= 0— 7 Exchange the accumulator and 0 0 1 0 1 r r r 1 designated register's contents. XCH A, @ Rr (A)*"((11r)); r= 0— 1 Exchange indirect contents of accumu- 0 0 1 0 0 0 0 r 1 lator and location in data memory. XCHD A, 0 Rr (A 0 — 3) '"°'(Rr) (0 — 3); Exchange indirect 4-bit contents of 0 0 1 1 0 0 0 r 1 r = 0 — 1 accumulator and data memory. FLAGS

CPL C (C) -0-- NOT (C) Complement content of carry bit. 1 0 1 0 0 1 1 1 1 1 • CPL FO (FO) .— NOT (F0) Complement content of flag FO. 1 0 0 1 0 1 0 1 1 1 • CPL F1 (F1) -0— NOT (F1) Complement content of flag Fl. 10110101 i 1 • CLR C (C) -0— 0 Clear content of carry bit to 0. 1 0 0 1 0 1 1 1 1 1 • CLR FO (FO) -0— 0 Clear content of flag 0 to 0. 1 0 0 0 0 1 0 1 1 1 • CLR F1 (F1).— 0 Clear content of flag 1 to O. 1 0 1 0 0 1 0 1 1 1 • INPUT/OUTPUT

ANL BUS, # data (BUS).— (BUS) AND Logical AND immediate 1 0 0 1 1 0 0 0 2 2 data specified data with BUS. d7 de <16 44 d3 d2 di do ANL Pp, # data (Pp) -.0— (Pp) AND data Logical AND immediate specified data 1 0 0 1 1 0 p p 2 2 p = 1 — 2 with designated port (1 or 2). d7 d5 d6 d4 d3 d2 d1 do ANLD Pp, A (Pp) -0— (Pp) AND (A 0 — 3) Logical AND contents of accumulator 1 0 0 1 1 1 p p 2 p = 4 — 7 with designated port (4 — 7). IN A, Pp (A).— (Pp); p = 1 — 2 Input data from designated port (1 — 2) 0 0 0 0 1 0 p p 2 into accumulator. INS A, BUS (A) -00— (BUS) Input strobed BUS data into 0 0 0 0 1 0 0 0 1 2 accumulator. MOVD A, Pp (A 0 — 3) .— (Pp); p = 4 — 7 Move contents of designated port (4 — 7) 0 0 0 0 1 1 p p 2 (A 4 — 7) -0— 0 into accumulator. MOVD Pp, A (Pp).— A 0— 3; p= 4— 7 Move contents of accumulator to 0 0 1 1 1 1 p p 1 designated port (4 — 7). ORLD Pp, A (Pp).— (Pp) OR (A 0— 3) Logical OR contents of accumulator with 1 0 0 0 1 1 p p 1 p = 4 — 7 designated port (4 — 7). ORL BUS, # data (BUS).—(BUS) OR Logical OR immediate 1 0 0 0 1 0 0 0 2 2 data specified data with BUS. dy d6 d5 44 d3 d2 di do ORL Pp, # data (Pp).— (Pp) OR data Logical OR immediate specified data with 1 0 0 0 1 0 p p 2 2 p = 1 — 2 designated port (1 — 2). dy r16 d5 44 d3 d2 d1 d0 OUTL BUS, A (BUS).— (A) Output contents of accumulator onto 0 0 0 0 0 0 1 0 1 2 BUS. OUTL Pp, A (Pp).— (A); p= 1— 2 Output contents of accumulator to 0 0 1 1 1 0 p p designated port (1 — 2). REGISTERS

DEC Rr (Rr)'— (Rr) — 1; r= 0— 7 Decrement contents of designated 1 1 0 0 1 r r r 1 1 register by 1. INC Rr (Rr).— (Rr) + 1; r= 0— 7 Increment contents of designated 0 0 0 1 1 r r r register by 1. INC @ Rr ((Rr)).— ((Rr)) + 1; Increment indirect the contents of 0 0 0 1 0 0 0 r 1 r = 0 — 1 data memory location by 1.

3.8 Signetics MICROPROCESSOR DIVISION JANUARY 1983 SINGLE CHIP 8-BIT MICROCOMPUTERS SCN80 SERIES

Preliminary Table 1 INSTRUCTION SET (Continued) INSTRUCTION CODE FLAGS

MNEMONIC FUNCTION DESCRIPTION D7 D6 05 D4 D3 D2 D1 Do CYCLES BYTES C AC FO F1 BS

BRANCH DJNZ Rr, addr (Pr).- (Rr) - 1; r= 0- 7 Decrement the specified register and 1 1 1 0 1 r r r 2 2 If (Rr) A 0; test contents. a7 a6 as .4 .3 .2 at a0 (PC 0 - 7).- addr JBb addr (PC 0 - 7).- addr if Bb = 1 Jump to specified address if b2 b1 60 1 0 0 1 0 2 2 (PC).- (PC) + 2 if Bb = 0 accumulator bit is set. a7 a6 .5 a4 a3 02 01 .0 JC addr (PC 0 - 7).- addr if C = 1 Jump to specified address if carry flag 1 1 1 1 0 1 1 0 2 2 (PC).- (PC) + 2 if C = 0 is set. a7 a6 a5 54 a3 a2 a1 .0 JFO addr (PC 0 - 7).- addr if FO = I Jump to specified address if flag FO is 1 0 1 1 0 1 1 0 2 2 (PC).- )(PC) + 2 if FO = 0 set. a7 .6 a5 a4 a3 .2 01 .0 JF1 addr (PC 0 - 7).-- addr if F1 = 1 Jump to specified address if flag Fl is 0 1 1 1 0 1 1 0 2 2 (PC).- (PC) + 2 if F1 = 0 set. a7 06 a5 a4 03 02 a1 .0 JMP addr (PC 8 - 10).- addr 8 - 10 Direct jump to specified address within 010 09 a8 0 0 1 0 0 2 2 (PC 0 - 7).- addr 0 - 7 the 2K address block. a7 06 .5 04 .3 a2 01 a0 (PC11).- (DBF) JMPP @ A (PC 0- 7)a- ((A)) Jump indirect to specified address 1 0 1 1 0 0 1 1 2 within address page. JNC addr (PC 0 - 7).- addr if C = 0 Jump to specified address if carry flag is 1 1 1 0 0 1 1 0 2 2 (PC).- (PC) + 2 if C = 1 low. .7 06 a5 04 e3 .2 .1 a° JNI (PC 0 - 7).- addr if INT = 0 Jump to specified address if INT 1 0 0 0 0 1 1 0 2 2 (PC).- (PC) + 2 if INT = 1 input is low. 07 a6 a5 a4 .3 a2 .1 .0 JNTO addr (PC 0 - 7).- addr if TO = 0 Jump to specified address if test 0 is low. 0 0 1 0 0 1 1 0 2 2 (PC).- (PC) + 2 if TO = 1 a7 06 05 a4 93 a2 al 00 JNT1 addr (PC 0 - 7).- addr if T1 = 0 Jump to specified address if test 1 is low. 0 1 0 0 0 1 1 0 2 2 (PC).- (PC) + 2 if T1 = 1 .7 06 a5 .4 a3 .2 .1 a0 JNZ addr (PC 0- 7).- addr if A 0 0 Jump to specified address if accumulator 1 0 0 1 0 1 1 0 2 2 (PC).- (PC) + 2 if A = 0 is non-zero. 07 06 05 .4 03 a2 .1 00 JTF addr (PC 0 - 7).- addr if TF = 1 Jump to specified address if timer flag 0 0 0 1 0 1 1 0 2 2 (PC).- (PC) + 2 if TF = 0 is set to 1. a7 06 a5 .4 .3 .2 al a0 JTO addr (PC 0 - 7).- addr if TO = 1 Jump to specified address if test 0 is a 1. 0 0 1 1 0 1 1 0 2 2 (PC).- (PC) + 2 if TO = 0 a7 a6 a5 .4 a3 02 .1 a0 JTI addr (PC 0 - 7).- addr if T1 = 1 Jump to specified address if test 1 is a 1. 0 1 0 1 0 1 1 0 2 2 (PC).- (PC) + 2 if T1 = 0 .7 a6 85 .4 .3 02 a1 00 JZ addr (PC 0- 7).- addr if A= 0 Jump to specified address if accumulator 1 1 0 0 0 1 1 0 2 2 (PC)..-- (PC) + 2 if A * 0 is 0. .7 a6 .5 a4 .3 .2 a1 a0 CONTROL

EN I Enable the external own interrupt. 0 0 0 0 0 1 0 1 1 1 DIS I Disable the external (INT) interrupt. 0 0 0 1 0 1 0 1 SEL RBO (BS).- 0 Select bank 0 (locations 0- 7) of data 1 1 0 0 0 1 0 1 1 1 • memory. SEL RB 1 (BS).- I Select bank 1 (locations 24 - 31) of 1 1 0 1 0 1 0 1 1 1 • data memory. SEL MBO (DBF) .- 0 Select program memory bank 1 1 1 0 0 1 0 1 0, addresses 0 - 2047. SEL MBI (DBF).- 1 Select program memory bank 1 1 1 1 0 1 0 1 1 I 1, addresses 2048 - 4095 ENTO CLK Enable clock output on TO 0 1 1 1 0 1 0 1 pin.

DATA MOVES

MOV A, SS data (A).- data Move immediate the specified data into 0 0 1 0 0 0 1 1 2 2 the accumulator. d7 d6 d5 d4 d3 d2 d1 do MOV A, Rr (A).- (Rr); r = 0 - 7 Move the contents of the designated 1 1 1 1 1 r r r register into the accumulator. MOV A, @ Rr (A).- ((Rn)); r= 0- 1 Move indirect the contents of data 1 1 1 1 0 0 0 r memory location into the accumulator. MOV A, PSW (A).- (PSW) Move contents of the program status 1 1 0 0 0 1 1 1 1 1 word into the accumulator. MOV Rr, 8 data (Rr).- data; r = 0 - 7 Move immediate the specified data into 1 0 1 1 1 r rr 2 2 the designated register. d7 d6 d5 d4 d3 d2 d1 d0 MOV Rr, A (Rr).- (A); r= 0- 7 Move accumulator contents into the 1 0 1 0 1 r r r 1 designated register. MOV @ Rr, A ((Rr)) '.- (A); r= 0- I Move indirect accumulator contents 1 0 1 0 0 0 0 r 1 I into data memory location. MOV @ Rr, S data ((Rr)) .- data; r= 0- 1 Move indirect the specified data into 1 0 1 1 0 0 0 r 2 2 data memory. d7 d6 d5 d4 d3 d2 d1 do MOV PSW, A (PSW). - (A) Move contents of accumulator into the 1 1 0 1 0 1 1 1 1 1 • • • • program status word. Signetics 3.9 MICROPROCESSOR DIVISION JANUARY 1983 SINGLE CHIP 8-BIT MICROCOMPUTERS SCN80 SERIES

Preliminary

Table 1 INSTRUCTION SET (Continued)

INSTRUCTION CODE FLAGS

MNEMONIC FUNCTION DESCRIPTION 07 D6 D5 04 D3 Do D 1 DO CYCLES BYTES C AC FO F/ BS

SUBROUTINE

CALL addr ((SP)).- (PC), (PSW 4 - 7) Call designated subroutine. .10 .9 .8 1 0 1 0 0 2 2 (SP).- (SP) + 1 .7 a6 .5 .4 a3 .2 .1 .0 (PC 8 - 10)•- addr 8 - 10 (PC 0 - 7) .- addr 0 - 7 (PC 11) .- DBF RET (SP) •- (SP) - 1 Return from subroutine without 1 0 0 0 0 0 1 1 2 (PC)•- ((SP)) restoring program status word. RETR (SP).- (SP) - 1 Return from subroutine restoring 1 0 0 1 0 0 1 1 2 (PC)•- ((SP)) program status word. (PSW 4 - 7)•- ((SP))

TIMER/COUNTER

EN TCNTI Enable timer/counter interrupt. 0 0 1 0 0 1 0 1 DIS TCNTI Disable timer/counter interrupt. 00 1 1 0 1 0 1 1 1 MOV A, T (A).- (T) Move contents of timer/counter into 0 1 0 0 0 0 1 0 1 1 accumulator. MOV T, A (T)-.- (A) Move contents of accumulator into 0 1 1 0 0 0 1 0 1 timer/counter. STOP TCNT Stop count for event counter or timer. 0 1 1 0 0 1 0 1 1 1 STRT CNT Start count for event counter. 0 1 00 0 1 0 1 STRT T Start count for timer. 0 1 0 1 0 1 0 1 1 1 MISCELLANEOUS

NOP No operation performed. 0 0 0 0 0 0 0 0 1 1

NOTES 1. Instruction code designations r and p form the binary representation of the registers and ports involved. 2. The dot under the appropriate flag bit indicates that its content is subject to change by the instruction it appears in. 3. Numerical subscripts appearing in the FUNCTION column reference the specific bits affected.

SYMBOL DEFINITIONS SYMBOL DESCRIPTION SYMBOL DESCRIPTION A The accumulator P "In-Page" operation designator AC The auxiliary carry flag Pp Port designator (p = 1, 2 or 4 — 7) addr Program memory address (11 bits) PSW Program status word Bb Bit designator (b = 0 — 7) Rr Register designator (r = 0, 1 or 0 — 7) BS The bank switch SP Stack pointer C Carry flag T Timer CLK Clock signal TF Timer flag CNT Event counter TO, T1 Testable inputs 0,1 D Nibble designator (4 bits) # Prefix for immediate data

DBF Program memory bank flip-flop @ Prefix for indirect address data Number or expression (8 bits) $ Program counter's current value F0, F1 Flags 0,1 -.— Replaced by

I Interrupt --,- Exchanged with INT External interrupt

3.10 Signetics MICROPROCESSOR DIVISION JANUARY 1983 SINGLE CHIP 8-BIT MICROCOMPUTERS SCN80 SERIES

Preliminary

Table 2 INSTRUCTION TIMING**

CYCLE 1 CYCLE 2

INSTRUCTION S1 S2 S3 54 S5 S1 S2 S3 S4 S5 Fetch Increment Increment IN A,P — — — Read Port • — — — Instruction Program Counter Timer

Fetch Increment Increment Output • OUTL RA — — — — — Instruction Program Counter Timer To Port Fetch • Increment increment Fetch • Increment Output ANL R # DATA — Read Port — Instruction Program Counter Timer Immediate Data Program Counter To Port —

Fetch • Increment Increment Fetch • increment Output ORL P, 4 DATA — Read Port — Instruction Program Counter Timer Immediate Data Program Counter To Port —

Fetch Increment Increment • INS A, BUS — — — Read Port — — — Instruction Program Counter Timer

Fetch Increment increment Output • — OUTL BUS, A — — — — — Instruction Program Counter Timer To Port Fetch • increment increment Fetch • Increment Output — ANL BUS, 4 DATA — Read Port — Instruction Program Counter Timer Immediate Data Program Counter To Port Fetch Increment Increment Fetch • increment Output — ORL BUS, 4 DATA — Read Port — Instruction Program Counter Timer immediate Data Program Counter To Port

Fetch Increment Output RAM Increment Output • — MOVX (§)R,A — — — Instruction Program Counter Address Timer Data To RAM

Fetch Increment Output RAM increment • MOVX A,CSR — — Read Data — — — instruction Program Counter Address Timer

Fetch increment Output Increment Read • — MOVD A, Pi — — — — Instruction Program Counter Opcode/Address Timer P2 Lower

Fetch Increment Output increment Output Data • — MOVD Pi, A — — — — Instruction Program Counter Opcode/Address Timer TO P2 Lower

ANLD P, A Fetch increment Output increment Output _ _• _ — Instruction Program Counter Opcode/Address Timer Data

ORLD P, A Fetch Increment Output Increment Output _ • _ — — — Instruction Program Counter Opcode/Address Timer Data Fetch • increment Sample increment Fetch Update J (CONDITIONAL) — — • — — Instruction ProgramCounter Condition Timer immediate Data • Program Counter

Fetch • increment Start STRT CNT/STRT T — — instruction Program Counter Counter Fetch Increment Stop STOP TCNT — — Instruction Program Counter Counter Fetch • increment Enable — EN I — Instruction Program Counter interrupt Fetch • increment Disable — DISI — Instruction Program Counter interrupt

Fetch • Increment Enable — ENTO CLK — Instruction Program Counter Clock

NOTES *Valid instruction address are output at this time if external program memory is being accessed. **See Figures 11 and 12 for instruction cycle and cycle timing.

Signelics 3.11 MICROPROCESSOR DIVISION JANUARY 1983 SINGLE CHIP 8-BIT MICROCOMPUTERS SCN80 SERIES

Preliminary

ABSOLUTE MAXIMUM RATINGS1 PARAMETER RATING UNIT Operating ambient temperature2 0 to +70 °C Storage temperature -65 to +150 oc Input voltages with respect to VSS3 -0.5 to +7 V Power Dissipation 1.5 W

DC ELECTRICAL CHARACTERISTICS TA= CrC to 70°C, Vcc = Vcs= 5V ± 10%, Vss=0V43 6 LIMITS PARAMETER TEST CONDITIONS UNIT Min Typ Max

VIL Input low voltage All except XTAL1, XTAL2 -0.5 0.8 V XTAL1, XTAL2 - 0.5 0.6 V VIH Input high voltage All except RESET, XTAL1, XTAL2 2.0 Vcc V RESET, XTAL1, XTAL2 3.0 Vcc V VOL Output low voltage la_ = 2.0mA 0.4 V VOH Output high voltage All except BUS ICH = - 125AA 2.4 V BUS i OH = - 400µA 2.4 V II Input leakage current Port 1, Port 2, EA, SS Vss+ 0.45 s VIII s VCC - 500 AA T1, INT Vss + 0.45 5 VIN '.- VCC ±10 µA loL Output leakage current BUS, TO (high impedance state) Vss+ 0.45 .5. VIN -'5 VCC ±10 µA IDD Standby supply current RESET 5 VII_ 8035/8048 All inputs =0V 2.5 mA 8039/8049 V00 = 0V 4.5 mA 8040/8050 8.5 mA

IDD + ICC Total supply current RESET 5 VII_ 8035/8048 1 40 75 mA 8039/8049 6 MHz versions 45 85 mA 8040/8050 50 95 mA 8035/8048 45 80 mA 8039/8049 11 MHz versions 50 95 mA 8040/8050 60 110 mA VDD Standby power supply 2.2 V

NOTES 1. Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated In the operation NORMALIZED TOTAL section of this specification is not implied. SUPPLY CURRENT 2. For operating at elevated temperatures, the device must be derated based on vs. TEMPERATURE (TYPICAL) + 150°C maximum junction temperature. 3. This product includes circuitry specifically designed for the protection of its inter- 1.2 nal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. (,) 1.1 4. Parameters are valid over operating temperature range unless otherwise specified. 5. All voltage measurements are referenced to ground (V55). For testing, all input 1.0 signals swing between 0.4V and 2.4V with a transition time of 2Ons maximum. All time measurements are referenced at input voltages of 0.8V and 2.0V and output voltages of 0.8V and 2.0V as appropriate. 0.9 6. Typical values are at + 25°C, typical supply voltages and typical processing pararn- eters. 0.8

0.7 - 25 0 25 50 75 100 NTEMPERATURE, °C

3.12 Signetics MICROPROCESSOR DIVISION JANUARY 1983 SINGLE CHIP 8-BIT MICROCOMPUTERS SCN80 SERIES

Preliminary

AC ELECTRICAL CHARACTERISTICS TA = 0 °C to 70°C, Vcc= VDD= 5V± 10%, Vss= OV4'5'6 TENTATIVE LIMITS PARAMETER TEST CONDITIONS7 11 MHz 6 MHz UNIT VERSIONS VERSIONS (Refer to figures 7, 8 and 9) Min Max Min Max

ILL ALE pulse width 150 400 ns tAL Address setup to ALE 70 150 ns ILA Address hold from ALE 50 80 ns tcc Control pulse width (PSEN, RD, WR) 300 700 ns tpw Data set-up before WR 250 500 ns

two Data hold after WR 40 120 ns tcy Cycle time 1.36 3.75 2.5 15.0 iLs tDR Data hold 0 100 0 200 ns tRD PSEN, RD to data in 200 500 ns tAw Address setup to WR 200 230 ns tAD Address setup to data in 400 950 ns tAFC Address float to RD, PSEN — 10 0 ns tCA Control pulse to ALE 10 10 ns (Refer to figure 10)

tCP Port control setup before falling 100 110 ns edge of PROG tpc Port control hold after falling edge 60 130 ns of PROG tpR PROG to time P2 input must be valid 650 810 ns

tDp Output data setup time 200 250 ns tpo Output data hold time 20 65 ns tpF Input data hold time 0 150 0 150 ns

tpp PROG pulse width 700 1200 ns tpL Port 2 I/O data setup 250 350 ns tLP Port 2 I/O data hold 20 150 ns

NOTES 4, 5, 6. See DC Electrical Characteristics 7. Control outputs: CL =80pF Bus outputs: CL = 150pF tcy=1.36µs for 11 MHz versions tcy= 2.5its for 6 MHz versions

Signetics 3.13 MICROPROCESSOR DIVISION JANUARY 1983 SINGLE CHIP 8-BIT MICROCOMPUTERS SCN80 SERIES

Preliminary TIMING DIAGRAMS

icy - ILL

ALE

tAFC tcc ICA

PSEN

ILA

BUS FLOATING

IRO IAD

Figure 7. Instruction Fetch from External Program Memory

ALE j / \_

ICA

RD / tApo top

BUS FLOATING 41=> CID CI FLOATING

tAD

Figure 8. Read from External Data Memory

Figure 9. Write to External Data Memory

3.14 Signetics MICROPROCESSOR DIVISION JANUARY 1983 SINGLE CHIP 8-BIT MICROCOMPUTERS SCN80 SERIES

Preliminary

TIMING DIAGRAMS (cont'd)

EXPANDER PORT OUTPUT

EXPANDER PORT INPUT

PROG

Figure 10. Port 2 Timing

Icy

S5 S1 S2 S3 S4 S1 INPUT INST. DECODE EXECUTION INPUT

OUTPUT ADDRESS INC. PC OUTPUT ADDRESS I I I

Figure 11. Instruction Cycle

S1 S2 S3 S4 55 51 S2 53 S4 S5

CLOCK OUT ON TO

ALE

PSEN

RD WR

PROG

Figure 12. Instruction Cycle Timing

Signetics 3.15 MICROPROCESSOR DIVISION JANUARY 1983 CMOS SINGLE CHIP 8-BIT MICROCOMPUTERS SCC80 SERIES

PRODUCT BRIEF, contact your Signetics sales office for additional information.

DESCRIPTION FEATURES PIN CONFIGURATION The Signetics SCC80 Series microcom- • 8•bit CPU, ROM, RAM, I/O in a 40-pin puters are low power, CMOS versions of package the popular SCN80 series NMOS equiva- • 24 quasi bidirectional I/O lines lents. They are self-contained, 8-bit pro- • Two test inputs TO Vcc cessors which contain the system timing, • Internal counter/timer XTAL1 T1 control logic, RAM data memory, ROM • Single-level vectored interrupts: program memory (80C48/C49/C50 only), external, counter/timer XTAL2 P27 and I/O lines necessary to implement dedi- • Over 90 instructions, 70% single byte RESET P26 cated control functions. All SCC80 Series • 1.36ps instruction cycle, all instructions Ss P25 devices are pin and program compatible, one or two cycles INT P24 differing only in the size of the on-board • Expandable memory and I/O program ROM and data RAM, as follows: • Low voltage standby EA P17 • TTL compatible inputs and outputs RD P16 TYPE RAM SIZE ROM SIZE • Single + 5V power supply PSEN P15 Pin-to-pin compatible with SCN80 SCC80C48 64 x 8 1K x 8 • Series WR P14 SCC80C49 128 x 8 2K x 8 • Ability to maintain operation during AC ALE P13 SCC80C50 256 x 8 4K x 8 power line interruptions SCC80C35 64 x 8 — DBO P12 Exit Idle mode with an external or SCC80C39 128 x 8 — • internal interrupt signal DB1 P11 SCC80C40 256x 8 — • Battery operation DB2 P10

• 3 power consumption selections DB3 V00 Program memory can be expanded exter- — Normal operation: DB4 PROG nally up to a maximum total of 4K bytes 15mA @ 11MHz a 6V without paging. Data memory can also be — Idle mode: 500µA @ 11MHz @ 6V DB5 P23 expanded externally. I/O capabilities can — Power down: 10pA @ 2.0V DB6 P22 be expanded using standard devices or 11MHz, TTL compatible operation; • DB7 P21 the 8243 110 expander. Vcc = 5V ±10% vss P20 The SCC80 Series processors are de- CMOS compatible operation; Vcc = 5V ±20% signed to be efficient control processors TOP VIEW as well as arithmetic processors. They provide an instruction set which allows the user to directly set and reset individual lines within its I/O ports as well as test individual bits within the accumulator. A prescaler) or external events. The counter large variety of branch and table look-up can be programmed to cause an interrupt instructions make these processors very on terminal count. efficient in implementing standard logic The CMOS design of the SCC80 Series functions. Also, special attention has opens new application areas that require been given to code efficiency. Over 70% battery operation, low power standby, of the instructions are a single byte long wide voltage range, and the ability to main- and all others are only 2 bytes long. tain operation during AC power line inter- An on-chip 8-bit counter is provided which ruptions. These applications include por- can count, under program control, either table and hand-held instruments, telecom- internal clock pulses (with a divide by 32 munications, consumer, and automotive.

3.16 Signetics MICROPROCESSOR DIVISION JANUARY 1983 SINGLE CHIP 8-BIT MICROCOMPUTERS SCN8031, SCN8051

Advance Information DESCRIPTION FEATURES PIN CONFIGURATION The Signetics SNC8031/8051 is a stand- • 4K x 8 ROM (SCN8051) alone, high-performance single-chip • 128 x 8 RAM computer fabricated with Signetics' • Four 8-bit ports, 32 I/O lines P1.0 Vcc highly-reliable +5 volt, depletion-load, • Two 16-bit timer/event counters P1.1 P0.0 ADO N-Channel, silicon-gate MOS technology • High-performance full-duplex serial P1.2 P0.1 AD1 and packaged in a 40-pin DIP. It provides channel P1.3 P0.2 AD2 the hardware features, architectural • External memory expandable to 128K enhancements and new instructions that • Boolean processor P1.4 P0.3 AD3 are necessary to make it a powerful and • SCN80 series architecture enhanced P1.5 P0.4 AD4 cost effective controller for applications with: P1.6 P0.5 AD5 requiring up to 64K bytes of program - Non-paged jumps memory and/or up to 64K bytes of data - Direct addressing P1.7 P0.6 ADO storage. - Four 8-register banks RST/VPD P0.7 AD7 - Stack depth up to 128-bytes The SCN8051 contains a 4K x 8 read-only RxD P3.0 EA - Multiply, divide, subtract, compare program memory; a 128 x 8 read/write data • Most instructions execute in 11,s TxD P3.1 ALE memory; 32 I/O lines; two 16-bit timer/ • 4µs multiply and divide INTO P3.2 PSEN counters; a five-source, two-priority-level, nested interrupt structure; a serial I/O port INTI P3.3 P2.7 A15 for either multi-processor communica- TO P3.4 P2.6 A14 tions, I/O expansion, or full duplex UART; T1 P3.5 P2.5 A13 and on-chip oscillator and clock circuits. and BCD arithmetic and excels in bit- The SCN8031 is identical, except that it WR P3.6 P2.4 Al2 handling capabilities. Efficient use of pro- lacks the program memory. For systems RD P3.7 P2.3 All gram memory results from an instruction that require extra capability, the SCN8051 set consisting of 44% one-byte, 41% two- XTAL2 P2.2 A10 can be expanded using standard TTL com- byte, and 15% three-byte instructions. P2.1 A9 patible memories and byte oriented XTAL1 With a 12MHz crystal, 58% of the instruc- peripheral controllers. Vss P2.0 AS tions execute in 1µs, 40% in 2µ5 and multi- The SCN8051 microcomputer, like its ple and divide require only 4µs. Among the TOP VIEW SCN8048 predecessor, is efficient both as many instructions added to the standard a controller and as an arithmetic proces- SCN8048 instruction set are multiply, sor. It has extensive facilities for binary divide, subtract and compare.

ORDERING CODE LOGIC SYMBOL

SCN80 ❑❑ AO ❑ ❑ 40 (CPxxxx) -r CUSTOM ROM PATTERN NUMBER RST/VPD Vss Vcc Applies to masked ROM versions only. Number CO will be assigned by Signetics. Contact Signetics XTAL1 < sales office for ROM pattern submission requirements. 0 2 40-PIN XTAL2 a Ul PACKAGE EA N = Plastic DIP 0 I = Ceramic DIP PSEN ALE SPEED C= 12MHz clock

• RxD- OPERATING TEMPERATURE RANGE C=0° to +70°C

T1-.- ROM/RAM (bytes) W R-.-- ADDRESS BUS 31 = EXT/256 g RD 51 = 4K/256 N

Signetics 3.17 MICROPROCESSOR DIVISION JANUARY 1983 SINGLE CHIP 8-BIT MICROCOMPUTERS SCN8031, SCN8051

Advance Information

PIN DESIGNATION MNEMONIC PIN NO. TYPE NAME AND FUNCTION Vss 20 I Ground Vcc 40 I Power Supply: + 5VDC P0.0-P0.7 39-32 I/O Port 0: An 8-bit open drain bidirectional I/O port. It is also the multiplexed low-order address and data bus when using external memory. It is used for data output during program verification. Port 0 can sink/source eight LS TTL loads. P1.0-P1.7 1-8 I/O Port 1: An 8-bit quasi-bidirectional I/O port. It is used for the low-order address byte during program verification. Port 1 can sink/source four LS TTL loads. P2.0-P2.7 21-28 I/O Port 2: An 8-bit quasi-bidirectional I/O port. It also emits the high-order address byte when accessing external memory. It is used for the high-order address and the control signals during program verification. Port 2 can sink/source four LS TTL loads. P3.0-P3.7 10-17 I/O Port 3: An 8-bit quasi-directional I/O port. It also contains the interrupt, timer, serial port and RD and WR pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. Port 3 can sink/source four LS TTL loads. The secondary functions are assigned to the pins of port 3 as follows: RXD/data (P3.0): Serial port's receiver data input (asynchronous) or data input/output (synchronous). TXD/clock (P3.1): Serial port's transmitter data output (asynchronous) or clock output (synchronous). INTO (P3.2): Interrupt 0 input or gate control input for counter 0. INTI (P3.3): Interrupt 1 input or gate control input for counter 1. TO (P3.4): Input to counter 0. T1 (P3.5): Input to counter 1. WR (P3.6): The write control signal latches the data byte from port 0 into the external data memory. RD (P3.7): The read control signal enables external data memory to port 0. RST/VPD 9 I Reset/Standby Power: A high level on this pin resets the SCN8051. A small internal pulldown resistor permits power-on reset using only a capacitor connected to Vcc. If VPD is held within its specification while Vcc drops below specification, VPD will provide standby power to the RAM. When VPD is low, the RAM's current is drawn from Vcc. ALE 30 0 Address Latch Enable: Provides address latch enable output used for latching the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access. PSEN 29 0 Program Store Enable: The program store enable output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods, except during external data memory accesses. Remains high during internal program execution. EA 31 I Instruction Execution Control: When held at a TTL high level, the 8051 executes instructions from the internal ROM when the PC is less than 4096. When held at a TTL low level, the 8051 fetches all instructions from external program memory. XTAL1 19 I Crystal 1: Input to the oscillator's high gain amplifier. Required when a crystal is used. Connect to Vss when external source is used on XTAL2. XTAL2 18 0 Crystal 2: Output from the oscillator's amplifier. Input to the internal timing circuitry. A crystal or external source can be used.

ABSOLUTE MAXIMUM RATINGS1 PARAMETER RATING UNIT Operating ambient temperature2 0 to + 70 °C Storage temperature —65 to + 150 °C All voltages with respect to ground3 —0.5 to + 7.0 V

3.18 Signetics MICROPROCESSOR DIVISION JANUARY 1983

SINGLE CHIP 8-BIT MICROCOMPUTERS SCN8031, SCN8051

Advance Information BLOCK DIAGRAM

FREQUENCY REFERENCE COUNTERS

4096 BYTES TWO 16-BIT OSCILLATOR PROGRAM 128 BYTES AND MEMORY DATA MEMORY TIMER/EVENT TIMING (8051) COUNTERS

PROGRAMMABLE 64K-BYTE BUS SERIAL PORT EXPANSION PROGRAMMABLE I/O • FULL DUPLEX CONTROL UART • SYNCHRONOUS INTERRUPTS SHIFTER L

INTERRUPTS CONTROL PARALLEL PORTS, SERIAL SERIAL ADDRESS/DATA BUS, IN OUT AND I/O PINS

DC ELECTRICAL CHARACTERISTICS TA = 0 °C to + 70°C, Vcc= 4.75 to 5.25V, Vss= OV4'5'6 LIMITS PARAMETER TEST CONDITIONS UNIT Min Typ Max

V IL Input low voltage —0.5 0.8 V Input high voltage VIH 2.0 V (except RST/VPD and XTAL2) Vcc+ 0.5 Input high voltage to RST/ VIH1 XTAL1 to Vss 2.5 V VPD for reset, XTAL2

VPD Power down voltage to RST/VPD Vcc= OV 4.5 5.5 V VOL Output low voltage ports 1, 2, 37 loL = 1.6mA 0.45 V Output low voltage port 0, VOL1 0.45 V ALE, PSEN7 loL= 3.2mA VoH Output high voltage ports 1, 2, 3 'OH = —80µA 2.4 V Output high voltage port 0, VOH1 1 0H = —400µA 2.4 V ALE, PSEN Logical 0 input current XTAL1 at Vss IlL — 800 µA XTAL2, ports 1, 2, 3 VIL= 0.45V Input high current to lint in = Vcc — 1.5V 500 µA RST/VPD for reset V

ILI Input leakage current to port 0, EA 0 < V,n < Vcc 10 µA Icc Power supply current 125 160 mA IF,D Power down current 10 20 mA

CIO Capacitance of I/O buffer fc = 1MHz 10 pF Signetics 3.19 MICROPROCESSOR DIVISION JANUARY 1983 SINGLE CHIP 8-BIT MICROCOMPUTERS SCN8031, SCN8051

Advance Information

AC ELECTRICAL CHARACTERISTICS TA = 0°C to + 70°C, Vcc= 5V ± 5%, Vss= OV45 6 8

12MHz CLOCK VARIABLE CLOCK PARAMETER Min Max Units 1Mtum.=1.2MHz to 12MHz Min Max Units Program memory char (fig 1) tLHLL ALE pulse width 127 ns 2tcLcL — 40 ns tAVLL Address setup to ALE 53 ns tCLCL — 30 ns tLLAX9 Address hold after ALE 48 ns ICLDL — 35 ns twv ALE to valid instr in 233 ns 4tcLcL— 100 ns tLLPL ALE to PSEN 58 ns tcLcL — 25 ns tpLPH PSEN pulse width 215 ns 3tcLci. — 35 ns tpLiv PSEN to valid instr in 125 ns 3tcLcL— 125 ns tpxix Input instr hold after PSEN 0 ns 0 ns tpx1z1° Input instr float after PSEN 63 ns tcLcL — 20 ns tpxAvl° Address valid after PSEN 75 ns tCL0L — 8 ns t Aviv Address to valid instr in 302 ns 6tcLcL— 115 ns tAzpL Address float to PSEN 0 ns 0 ns External data memory char (fig 2 and 3)

IFILRH RD pulse width 400 ns 6tcLcL — 100 ns tWLWH WR pulse width 400 ns 6tcLcL — 100 ns tu_Ax9 Address hold after ALE 132 ns 2tcLcL — 35 ns tRLDV RD to valid data in 250 ns 5tcLcL — 165 ns tRHDX Data hold after RD 0 ns 0 ns tRHDZ Data float after RD 97 ns 2tcLcL — 70 ns tLLDV ALE to valid data in 517 ns 8tcLcL — 150 ns tAvDv Address to valid data in 585 ns 0tcLcL — 165 ns tam_ ALE to WR or RD 200 300 ns 3tcLcL— 50 3tcLa+ 50 ns tAVWL Address to WR or RD 203 ns 4tcLcL — 130 ns tWHLH WR or RD high to ALE high 43 123 ns tcLcL — 40 tCLOL + 40 ns tDVWX Data valid to WR transition 33 ns tcLci. — 50 ns tOVWH Data setup before WR 433 ns 7tcLa. — 150 ns tWHQX Data hold after WR 33 ns tCLCL — 50 ns t RLAZ Address float after RD 0 ns 0 ns External clock (fig 4) tcLci_ Oscillator period 83.3 833.3 ns tCHCx High time 20 tcLcL — tcLcx ns tucx Low time 20 tcLcL— tCHCX ns tCLCH Rise time 20 ns 'CHCL Fall time 20 ns

NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. For operating at elevated temperatures, the device must be derated based on + 150°C maximum junction temperature. 3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying voltages greater than the rated maxima. 4. Parameters are valid over operating temperature range unless otherwise specified. 5. All voltage measurements are referenced to ground. For testing, all input signals swing between 0.45V and 2.4V with a transition time of 2Ons maximum. All time measurements are referenced at input voltages of 0.8V and 2.0V and at output voltages of 0.8V and 2.0V as appropriate. 6. Typical values are at +25°C, typical supply voltages and typical processing parameters. 7. VOL is degraded when the SCN8051 rapidly discharges external capacitance. This AC noise is most pronounced during emission of address data. When using external memory, locate the latch or buffer as close to the SCN8051 as possible. Emitting Time Degraded • Datum Ports Interval 110 Lines VOL (Peak Max) Address P2, PO T3, T9 P1, P3 0.8V Write data PO T6 P1, P3, ALE 0.8V 8. CL= 100pF for port 0, ALE and PSEN outputs; CL= 80pF for all other ports. 9. tLLAX for access to program memory is different from 1LLAX for access to data memory. 10. Interfacing the SCN8051 devices with float times up to 75ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. 3.20 Signetics MICROPROCESSOR DIVISION JANUARY 1983 SINGLE CHIP 8-BIT MICROCOMPUTERS SCN8031, SCN8051

Advance Information

tce

tLHLL LLIV tLLPL ALE 1PLPH

1PXAV PSEN LLAX—P- tAvLL ""— tPX1Z —w tAzpi 4€1 , INSTR IN A7-A0 PORT 0 1AVIV ADDRESS ADDRESS A15-A8 ADDRESS A15-A8 PORT 2 OR SFR-P2

Figure 1. Program Memory Read Cycle

twEILH —". tLLDV ALE

PSEN tLLwL RD 1RLRH tAVWL tRHOZ iRLOV tp,HDx—p-

A7-A0 ATA IN PORT 0 )<>\/ ..>•' - 2),( tFILAZ ADDRESS PORT 2 OR SFR.P2 ADDRESS A15-A8 OR SFR-P2 Figure 2. Data Memory Read Cycle

twHLH Ire ALE

PSEN tLLWL tWLWI1 WR

tAVWL tOVWX tOVWH tWHOX PORT 0 DATA OUT

ADDRESS X PORT 2 OR SFR-P2 ADDRESS A15-A8 OR SFR.P2

Figure 3. Data Memory Write Cycle

tcHex_pl tcIcH tCHCL

2.5 2.5 2.5

0.8 0.8

tCLCX--P-1

tcLcL

Figure 4. External Clock Drive XTAL2 Signetics 3.21 MICROPROCESSOR DIVISION JANUARY 1983 SINGLE CHIP 8-BIT MICROCOMPUTERS SCN8031, SCN8051

Advance Information

INPUT/OUTPUT FLOAT

FLOAT 2.4 2.4 2.4 2.0 2.0

0.8 0.8 0.45 0.45 0 45

Figure 5. AC Testing Input, Output, Float Waveforms

NOTES: 1. AC testing inputs are dirven at 2.4V for a logic "1" and 0.45V for a logic "0". 2. Timing measurements are made at 2.0V for a logic "1" and 0.8V for a logic "0". 3. For timing purposes, the float state is defined as the point at which a PO pin sinks 3.2mA or sources 400µA at the voltage test levels.

S4P1 S4P2 S5P1 S5P2 S6P1 S6P2 S1P1 S1P2 S2P1 S2P2 S3P1 S3P2 S4P1 S4P2 S5P1 XTAL2

ALE

PSEN

BUS (P0) DATA FLOAT FLOAT I FLOAT FLOAT FLOAT ADDRESS I DATA ADDRESS DATA ADDRESS SAMPLED OUTPUT SAMPLED OUTPUT SAMPLED OUTPUT FOR EXTERNAL PROGRAM MEMORY FETCH P2 (EXT) INDICATES ADDRESS TRANSITIONS

PORT OUT OLD DATA NEW DATA

PORT IN SAMPLING TIME OF I/0 PORT PINS DURING INPUT (INCLUDING INTO AND INTI)

SERIAL PORT CLK (SHIFT MODE)

Figure 6. Timing Waveforms

NOTE All internal timing is referenced to the internal time states shown at the top of the page. This waveform represents the signal on the X2 input of the oscillator. This diagram represents when these signals are actually clocked within the chip. However, the time it takes a signal to propagate to the pins is in the range of 50-150ns. Pro- pagation delays are dependent on many variables, such as temperature and pin loading. Even the different signals vary. Typically though, RD and WR have propagation delays of approximately 5Ons and the other timing signals approximately 85ns. At room temperature, fully loaded, these differences in propagation delays between signals have been integrated into the timing specs.

3-22 Signetics MICROPROCESSOR DIVISION JANUARY 1983 SINGLE CHIP 8-BIT MICROCOMPUTERS SCN8031, SCN8051

Advance Information TABLE 1 Instruction Set Description

ARITHMETIC OPERATIONS DATA TRANSFER (Continued) Mnemonic Description Byte Cycles Mnemonic Description Byte Cycles ADD A,Rn Add register to accumulator MOV DPTR,#data16 Load data pointer with a 16-bit constant 3 2 ADD A,direct Add direct byte to accumulator 2 1 MOVC A,5A + DPTR Move code byte relative to DPTR to A 1 2 ADD kw Ri Add indirect RAM to accumulator 1 1 MOVC A,@ A + PC Move code byte relative to PC to A 1 2 ADD A,R#data Add immediate data to accumulator MOVX A,W Ri Move external RAM (8-bit addr) to A 1 2 ADDC A,Rn Add register to accumulator with carry MOVX A,0 DPTR Move external RAM (16-bit addr) to A 1 2 ADDC A,direct Add direct byte to A with carry flag 2 MOVX a Ri,A Move A to external RAM (8-bit addr) 2 ADDC AA, Ri Add indirect RAM to A with carry flag 1 MOVX ISDPTR,A Move A to external RAM (16-bit addr) 2 ADDC A,#data Add immediate data to A with carry flag 2 PUSH direct Push direct byte onto stack 2 2 SUBB A,Rn Subtract register from A with borrow 1 POP direct Pop direct byte from stack 2 2 SUBB A,direct Subtract direct byte from A with borrow 2 XCH A,Rn Exchange register with accumulator 1 1 SUBB A,a Ri Subtract indirect RAM from A wlborrow 1 XCH A,direct Exchange direct byte with accumulator 2 1 SUBB A,#data Subtract immed. data from A wlborrow 2 XCH A,g Ri Exchange indirect RAM with A INC A Increment accumulator 1 XCHD A,W Ri Exchange low-order digit ind. RAM wIA 1 1 INC Rn Increment register 1 INC direct Increment direct byte 2 BOOLEAN VARIABLE MANIPULATION INC SRi Increment indirect RAM Mnemonic Description Byte Cycles DEC A Decrement accumulator CLR C Clear carry flag 1 1 DEC Rn Decrement register 1 CLR bit Clear direct bit 2 1 DEC direct Decrement direct byte 12 SETS C Set carry flag 1 1 DEC WM Decrement indirect RAM 1 SETS bit Set direct bit 2 1 INC DPTR Increment data pointer 2 CPL C Complement carry flag 1 1 MUL AB Multiply A & B 4 CPL bit Complement direct bit 2 1 DIV AB Divide A by 13 4 ANL C,bit AND direct bit to carry flag 2 2 DA A Decimal adjust accumulator 1 ANL C,/bit AND complement of direct bit to carry 2 2 ORL C,bit OR direct bit to carry flag 2 2 LOGICAL OPERATIONS ORL C,/bit OR complement of direct bit to carry 2 2 Mnemonic Destination Byte Cycles MOV C,bit Move direct bit to carry flag 2 1 ANL A,Rn AND register to accumulator 1 1 MOV bit,C Move carry flag to direct bit 2 2 ANL A,direct AND direct byte to accumulator 2 1 ANL A,5 RI AND indirect RAM to accumulator 1 1 PROGRAM AND MACHINE CONTROL. ANL A,Irdata AND immediate data to accumulator 2 1 Mnemonic Description Byte Cycles ANL direct,A AND accumulator to direct byte 2 1 ACALL addr11 Absolute subroutine call 2 2 ANL direct,#data AND immediate data to direct byte 3 2 LCALL addr16 Long subroutine call 3 2 ORL A,Rn OR register to accumulator 1 RET Return from subroutine 1 2 ORL A,direct OR direct byte to accumulator 2 RETI Return from interrupt 1 2 ORL A,@Ri OR indirect RAM to accumulator 1 1 AJMP addr11 Absolute jump 2 2 ORL A,#data OR immediate data to accumulator 2 1 LJMP addrl6 Long jump 3 2 ORL direct, A OR accumulator to direct byte 2 1 SJMP rel Short jump (relative addr) 2 2 ORL direct,#data OR immediate data to direct byte 3 JMP aA+ DPTR Jump indirect relative to the DPTR 1 2 XRL A,Rn Exclusive-OR register to accumulator 1 JZ rel Jump if accumulator is zero 2 2 XRL A,direct Exclusive-OR direct byte toaccumulator 2 1 JNZ rel Jump if accumulator is not zero 2 2 XRL Airy Ri Exclusive-OR indirect RAM to A 1 1 JC rel Jump if carry flag is set 2 2 XRL A,#data Exclusive-OR immediate data to A 2 JNC rel Jump if no carry flag 2 2 XRL direct,A Exclusive-OR accumulator to direct byte 2 1 JB bit,rel Jump if direct bit set 3 2 XRL direct,#data Exclusive-OR immediate data to direct 3 JNB bit,rel Jump if direct bit not set 3 2 CLR A Clear accumulator 1 JBC bit,rel Jump if direct bit is set & clear bit 3 2 CPL A Complement accumulator 1 1 CJNE A,direct,rel Compare direct to A & jump if not equal 3 2 RL A Rotate accumulator left 1 1 CJNE A,#data,rel Comp. immed. to A & jump if not equal 3 2 RLC A Rotate A left through the carry flag 1 1 CJNE Rn,#data,rel Comp. immed. to reg. &jump if not equal 3 2 RR A Rotate accumulator right 1 1 CJNE @Ri,#data,rel Comp. immed. to ind. &jump if not equal 3 2 RRC A Rotate A right through carry flag 1 DJNZ Rn,rel Decrement register & jump if not zero 2 2 SWAP A Swap nibbles within the accumulator 1 DJNZ direct, rel Decrement direct & jump if not zero 3 2 NOP No operation 1 1 DATA TRANSFER

Mnemonic Description Byte Cycles Notes on data addressing modes: MOV A,Rn Move register to accumulator 1 1 Rn —Working register RO-R7 MOV A,direct Move direct byte to accumulator 2 1 direct —128 internal RAM locations, any I/O port, control or status register MOV A,5 Ri Move indirect RAM to accumulator 1 1 5 Ri —Indirect internal RAM location addressed by register RO or R1 MOV A,#data Move immediate data to accumulator 2 1 #data —8-bit constant included in instruction MOV Rn,A Move accumulator to register 1 1 #datal6 —16-bit constant included as bytes 2 & 3 of instruction MOV Rn,direct Move direct byte to register 2 2 bit —128 software flags, any I/O pin, control or status bit MOV Rn,#data Move immediate data to register 2 1 MOV direct,A Move accumulator to direct byte 2 1 Notes on program addressing modes: MOV direct,Rn Move register to direct byte 2 2 addr16 —Destination address for LCALL & LJMP may be anywhere within the MOV direct,direct Move direct byte to direct 3 2 64-kilobyte program memory address space. MOV direct,5Ri Move indirect RAM to direct byte 2 2 addr11 —Destination address for ACALL & AJMP will be within the same MOV direct,#data Move immediate data to direct byte 3 2 2-kilobyte page of program memory as the first byte of the following MOV a Ri,A Move accumulator to indirect RAM 1 1 instruction. MOV @RLdirect Move direct byte to indirect RAM 2 2 rel —SJMP and all conditional jumps include an 8-bit offset byte. Range is MOV RiAdata Move immediate data to indirect RAM 2 1 + 127— 128 bytes relative to first byte of the following instruction.

Signetics 3.23

MICROPROCESSOR DIVISION JANUARY 1983

CMOS SINGLE CHIP 8-BIT MICROCOMPUTERS SCC80C31 , SCC80C51

PRODUCT BRIEF, contact your Signetics sales office for additional information. DESCRIPTION FEATURES PIN CONFIGURATION The Signetics SCC80C31/80C51 is a stand- • 4K x 8 ROM (SCN8051) alone, high performance single-chip corn- • 128 x 8 RAM puter fabricated with Signetics' highly- • Four 8-bit ports, 32 I/O lines P1.0 Vcc reliable CMOS technology and packaged • Two 16-bit timer/event counters P1.1 P0.0 ADO in a 40-pin DIP. It provides the hardware • High-performance full-duplex serial P1.2 P0.1 AD1 features, architectural enhancements and channel P1.3 P0.2 AD2 new instructions that are necessary to • External memory expandable to 128K make it a powerful and cost effective con- • Boolean processor P1.4 P0.3 AD3 troller for applications requiring up to 64K • SCN80 series architecture enhanced P1.5 P0.4 AD4 bytes of program memory and/or up to 64K with: P1.6 P0.5 AD5 bytes of data storage. - Non-paged jumps - Direct addressing P1.7 P0.6 AD6 The SCC80051 contains a 4K x 8 read-only - Four 8-register banks program memory; a 128 x 8 read/write data RST/VPD P0.7 AD7 - Stack depth up to btract,128-bytes memory; 32 I/O lines; two 16-bit timer/ RXD P3.0 ENVoo - Multiply, divide, subtract, compare counters; a five-source, two-priority-level, • Most instructions execute in 1µs TxD P3.1 ALE/PROG nested interrupt structure; a serial I/O port • tips multiply and divide INTO P3.2 PSEN for either multi-processor communications, I/O expansion, or full duplex UART; rThI, P3.3 P2.7 A15 and on-chip oscillator and clock circuits. TO P3.4 binary and BCD arithmetic and excels in P2.6 A14 The SCC80C31 is identical, except that it bit-handling capabilities. Efficient use of T1 P3.5 P2.5 A13 lacks the program memory. For systems program memory results from an instruc- that require extra capability, the WR P3.8 P2.4 Al2 tion set consisting of 44% one-byte, 41% SCC80C51 can be expanded using stand- RD P3.7 P2.3 A11 two-byte, and 15% three-byte instruc- and TTL compatible memories and byte tions. With a 12MHz crystal, 58% of the in- XTAL2 P2.2 A10 oriented peripheral controllers. structions execute in 1µs, 40% in 2µs and XTAL1 P2.1 A9 The SCC80051 microcomputer, like its multiple and divide require only 4µ5. Vss P2.0 A8 SCC80C48 predecessor, is efficient both Among the many instructions added to as a controller and as an arithmetic pro- the standard SCC8OC48 instruction set TOP VIEW cessor. It has extensive facilities for are multiply, divide, subtract and compare.

BLOCK DIAGRAM LOGIC SYMBOL

FREQUENCY REFERENCE COUNTERS

RST/VPD 1 Vss Vcc XTAL1 4096 BYTES OSCILLATOR PROGRAM 128 BYTES TWO 16.81T AND TIMER/EVENT MEMORY DATA MEMORY TIMING (8051) COUNTERS XTAL2

EANDD 8051 a CPU PSEN

ALE/PROG

PROGRAMMABLE 64K.BYTE BUS SERIAL PORT • FULL DUPLEX EXPANSION PROGRAMMABLE 110 UART CONTROL S • SYNCHRONOUS INTERRUPTS SHIFTER Z\ 4\ ADDRESS BU INTERRUPTS V V CONTROL PARALLEL PORTS, SERIAL SERIAL ADDRESS/DATA BUS, IN OUT AND 110 PINS

3.24 Signetics Section 4 S68000 16-Bit Family

Signetics

MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

DESCRIPTION FEATURES PIN CONFIGURATION1 The Signetics SCN68000 combines state- • 32-bit data and address registers of-the-art semiconductor technology and • 16 megabyte direct addressing range advanced circuit design techniques with • 56 powerful instruction types computer sciences to achieve an architec- • Operations on five main data types D4 E EI D5 turally advanced 16-bit microprocessing • Memory mapped I/O D3 1 ED6 unit. As shown in the programming model, figure 1, the SCN68000 offers seventeen • 14 addressing modes D2 62 D7 32-bit registers in addition to a 32-bit pro- • Multilevel Interrupt structure D1 ED8 gram counter and a 16-bit status register. • Signed and unsigned multiply and The first eight registers (DO-D7) are used DO 60 D9 divide as data registers for byte (8-bit), word AS E ED10 • User and supervisor modes (16-bit), and long word (32-bit) data opera- E UDS D11 tions. The second set of seven registers • Support for high level languages LDS E M D12 (AO-A6) and the system stack pointer can • Testing and debugging support be used as software stack pointers and R/W 56 013 base address registers. In addition, these DTACK 10 55 D14 registers can be used for word and long BG 11 E015 word address operations. All 17 registers BGACK 12 53 GND can be used as index registers. ETA E E A23 Vcc 14 51 A22 CLK 15 E3 A21 31 1615 87 0 GND 16 DO E vcc I HALT a 48 A20 I D1 D2 RESET a 47 A19 D3 Eight VMA 19 E A18 Data D4 E 20 E All Registers VPA E E A16 D5 D6 BERR g E A15 r-- D7 IPL2 g E A14 31 1615 0 IPL1 24 E A13 AO WiTi 25 El Al2 Al FC2 26 E All A2 Seven FC1 E E MO A3 Address FCO 28 E A9 Registers A4 Al a E A8 A5 A2 /I E A7 A6 A3 E E A6 User Stack Pointer Two Stack A4 a E A5 A7 Supervisor Stack Pointer 1 Pointers L 31 0 TOP VIEW Program Counter 15 87 0 Status System Byte; User Byte Register

Figure 1. Programming Model

ORDERING CODE VDD= 5V -±- 5%, TA = CI° to 70°C PACKAGES 4MHz 6MHz 8MHz 10MHz

Ceramic DIP SCN68000C4164 SCN68000C6164 SCN68000C8164 SCN68000CAI64 1ln this data sheet, barring signal names loeerscore) to Plastic DIP SCN68000C4N64 SCN68000C6N64 SCN68000C8N64 SCN68000CAN64 Indicate low is done only for the pin configuration diagram, signal description headings, tables and figures.

Signetics 4.1 MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

SIGNAL DESCRIPTION Address Bus (A1-A23) rupt cycles. During interrupt cycles, address lines Al, A2, and A3 provide infor- The input and output signals can be func- This 23-bit, unidirectional, three-state bus mation about what level interrupt is being tionally organized into the groups shown is capable of addressing eight megawords serviced while address lines A4-A23 are in figure 2. The I/O signal characteristics of data. It provides the address for bus all set to a logic high. are summarized in table 1. operation during all cycles except inter Data Bus (DO-D15) This 16-bit, bidirectional, three state bus is the general purpose data path. It can transfer and accept data in either word or VC 21 Address byte length. During an interrupt acknowl- ON D(2) Bus >A1-A23 edge cycle, an external device supplies CLK the interrupt vector on data lines DO-D7.

AS Asynchronous Bus Control SCN68000 R/W Asynchronous data transfers are handled FCO Microprocessor UDS Asynchronous Bus using the following control signals: Processor FC1 LDS Control Status FC2 DTACK Address Strobe (AS) — This signal indicates that there is a valid address on the BR M6800 { address bus. Peripheral VMA BG `Bus Arbitration Control Control VPA BGACK Read/Write (RIW) — This signal defines the data bus transfer as a read or write BEAR -to IPLO cycle. The R/W signal also works in con- Interrupt System RESET - IPL1 junction with the upper and lower data Control Control HALT IPL2 } strobes as explained in the next paragraph.

Upper and Lower Data Strobes (UDS, LDS) Figure 2. Input and Output Signals — These signals control the data on the bus as shown in table 2. When the R/W line is high, the processor will read from the data bus as indicated. When the R/W Table 1 SIGNAL SUMMARY line is low, the processor will write to the data bus as shown. Three Signal Name Mnemonic Input/Output Active State State Data Transfer Acknowledge (DTACK) — Address Bus A1-A23 output high yes This input indicates that the data transfer Data Bus DO-D15 input/output high yes is completed. When the processor recog- Address Strobe To.: output low yes nizes DTACK during a read cycle, data is latched and the bus cycle is terminated. read-high Read/Write R/W output yes When DTACK is recognized during a write write-low cycle, the bus cycle is terminated. An ac- Upper and Lower Data Strobes 13177S , t output low yes tive transition of DTACK indicates the ter- Data Transfer Acknowledge DTACK input low — mination of a data transfer on the bus. Bus Request U17 input low — If the system must run at a maximum rate Bus Grant BG output low no determined by RAM access times, the Bus Grant Acknowledge BGACK input low — relationship between the times at which Interrupt Priority Level 1PLO, IPL1, n input low — DTACK and data are sampled is important. All control and data lines are sampled dur- Bus Error BERR input low — ing the SCN68000's clock high time. The Reset RESET input/output low no* clock is internally buffered, which results Halt HALT input/output low no* in some slight differences in the sampling Enable E output high — and recognition of various signals. The Valid Memory Address VMA output low yes DTACK signal, like other control signals, is Valid Peripheral Address VPA input low — internally synchronized to allow for valid operation in an asynchronous system. If Function Code Output FCO, FC1, FC2 output high yes the required setup time (#47)1 is met dur- Clock CLK input high no ing S4, DTACK will be recognized during Power Input VCC input — Ground GND input — 1 Number references (#1 can be found in the AC Electrical Characteristics section and corresponding timing *open drain diagrams located towards the end of this data sheet. 4.2 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

Table 2 DATA STROBE CONTROL OF DATA BUS ternally generated reset (result of a RESET instruction) causes all external devices to Otig LDS R/W D8-D15 DO-D7 be reset and the internal state of the pro- High High — No valid data No valid data cessor is not affected. A total system Valid data bits Valid data bits reset (processor and external devices) is Low Low High 8-15 0-7 the result of external HALT and RESET Valid data bits signals applied at the same time (see High Low High No valid data 0-7 Reset Operation for additional information). Valid data bits Low High High No valid data 8-15 Halt (HALT) — When this bidirectional line Valid data bits Valid data bits Low Low Low is driven by an external device, it will 8-15 0-7 cause the processor to stop at the com- Valid data bits Valid data bits High Low Low pletion of the current bus cycle. When the 0-7 0-7 processor has been halted using this in Valid data bits Valid data bits put, all control signals are inactive and all Low High Low 8-15 8-15* three-state lines are put in their high- 4 impedance state. When the processor has *These conditions are a result of current implementation and may stopped executing instructions, such as not appear on future devices. in a double bus fault condition, the halt line is driven by the processor to indicate to external devices that the processor has S5 and S6, and data will be captured dur- 3. Data transfer acknowledge is inactive, stopped (see Bus Error and Halt Operation ing S6. The data must meet the required indicating that another device is not for additional information). setup time (#27). If an asynchronous con- using the bus. trol signal does not meet the required set- 4. Bus grant acknowledge is inactive, indi- Peripheral Control up time, it is possible that it may not be cating that no other device is still These control signals are used to allow recognized during that cycle. Because of claiming bus mastership. the interfacing of synchronous peripheral this, asynchronous systems must not al- devices with the asynchronous SCN68000: low DTACK to precede data by more than parameter #31. Interrupt Control (IPLO,IPL1,IPL2) Enable (E) — This signal is the enable Asserting DTACK (or BERR) on the rising These inputs indicate the encoded priority signal for synchronous type peripheral edge of a clock (such as S4) after the level of the device requesting an interrupt. devices. The period for this output is ten assertion of address strobe will allow an Level seven is the highest priority while SCN68000 clock periods (six clocks low; SCN68000 system to run at its maximum level zero indicates that no interrupts are four clocks high). bus rate. If setup times #27 and #47 are requested. The least significant bit is guaranteed, #31 may be ignored. given in IPLO and the most signficant bit is Valid Peripheral Address (VPA) — This in- contained in IPL2. put indicates that the device or region ad- Bus Arbitration Control dressed is a synchronous device and that These three signals forma bus arbitration System Control data transfer should be synchronized with circuit to determine which device will be The system control inputs are used to the enable (E) signal. This input also indi- the bus master device: either reset or halt the processor and to in- cates that the processor should use automatic vectoring for an interrupt (see Inter- dicate to the processor that bus errors Bus Request (BR) — This input is wire have occurred. face with Synchronous Peripherals for ad- ORed with all other devices that could be ditional information). bus masters. It indicates to the processor Bus Error (BERR) — This input informs the Valid Memory Address (VMA) — This out- that some other device desires to become processor that there is a problem with the put is used to indicate to synchronous the bus master. cycle currently being executed. Problems peripheral devices that there is a valid ad- may be the result of nonresponding de- Bus Grant (BG) — This output indicates to dress on the address bus and the proces- vices, interrupt vector acquisition failure, all other potential bus master devices that illegal access request as determined by a sor is synchronized to enable. This signal the processor will release bus control at is issued only in response to a valid memory management unit, or other appli- the end of the current bus cycle. peripheral address (VPA) input which in- cation dependent errors. The bus error sig- dicates that the peripheral is a synchro- nal interacts with the halt signal to deter- Bus Grant Acknowledge (BGACK) — This nous device. input indicates that some other device has mine if exception processing should be performed or the current bus cycle should become the bus master. This signal can- Processor Status (FC0,FC1,FC2) not be asserted until the following four be retried (see Bus Error and Halt Opera- conditions are met: tion for additional information). These function code outputs indicate the state (user or supervisor) and the cycle 1. A bus grant has been received. Reset (RESET) — This bidirectional signal type currently being executed (see table 2. Address strobe is inactive, indicating line acts to reset the processor (initiate a 3). The information indicated by the func- that the microprocessor is not using system initialization sequence) in re- tion code is valid whenever address strobe the bus. sponse to an external reset signal. An in- (AS) is active.

Signetics 4.3

MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

Table 3 FUNCTION CODE Data Registers — Each data register is zero (Z), overflow (V), and carry (C). Addi- OUTPUTS 32-bits wide. Byte operands occupy the tional status bits indicate that the pro- low order 8-bits, word operands the low cessor is in a trace (T) mode and/or in a FC2 FC1 FCO Cycle Type order 16-bits, and long word operands the supervisor (S) state. entire 32-bits. The least significant bit is Low Low Low (Undefined, Reserved) addressed as bit 0; the most significant bit Data Organization in Memory Low Low High User Data is addressed as bit 31. When a data regis- Bytes are individually addressable with Low High Low User Program ter is used as either a source or destina- the high order byte having an even ad- Low High High (Undefined, Reserved) tion operand and the operand size is not dress the same as the word, as shown in High Low Low (Undefined, Reserved) 32 bits, only the appropriate low-order por- figure 3. The low order byte has an odd High Low High Supervisor Data tion is changed; the remaining high-order address that is one count higher than the High High Low Supervisor Program portion is neither used nor changed. word address. Instructions and multibyte High High High Interrupt Acknowledge data are accessed only on word (even Address Registers — Each address byte) boundaries. If a long word data is register and the stack pointer are 32-bits Clock (CLK) located at address n (n even), then the sec- wide and hold a full 32-bit address. Ad- ond word of that data is located at address The clock input is a TTL-compatible signal dress registers do not support byte sized n + 2. that is internally buffered for development operands. Therefore, when an address reg- The data types supported by the SCN68000 of the internal clocks needed by the pro- ister is used as a source operand, either are: bit data, integer data of 8, 16, or 32 cessor. The clock input is a constant fre- the low order word or the entire long word bits, 32-bit addresses and binary coded quency. operand is used depending on the operation size. When an address register is decimal data. Each of these data types is used as the destination operand, the en- put in memory as shown in figure 4. REGISTER DESCRIPTION AND tire register is affected regardless of the DATA ORGANIZATION operation size. If the operation size is BUS OPERATION word, any other operands are sign ex- The following is an explanation of control Operand Size tended to 32-bits before the operation is signal and bus operation during data performed. Operand sizes are defined as follows: a transfer operations, bus arbitration, bus byte equals 8-bits,a word equals 16-bits, Status Register error and halt conditions, and reset opera- and a long word equals 32-bits. The oper- tion. and size for each instruction is either ex- The status register contains the interrupt plicitly encoded in the instruction or im- mask (eight levels available) as well as the Data Transfer Operations plicitly defined by the instruction opera- condition codes: extend (X), negative (N), Transfer of data between devices involves tion. All explicit instructions support byte, address bus A1-A23, data bus D0-D15 and word or long word operands. Implicit in- control signals. The address and data structions support some subset of all STATUS REGISTER buses are separate parallel buses used to three sizes. System Byte User Byte transfer data using an asynchronous bus structure. In all cycles, the bus master Data Organization in Registers 3 10 8 assumes responsibility for deskewing all The eight data registers support data 0ZEIM11113\ NEGILIGla signals it issues at both the start and end Trace Mode Extend operands of 1, 8, 16, or 32 bits. The seven of a cycle. In addition, the bus master is Supervisor Negative address registers together with the active Zero responsible for deskewing the acknowl- State Interrupt stack pointer support address operands of Mask Overflow edge and data signals from the slave 32 bits. Carry device.

15 14 13 12 11 10 9 8 7 Word 000000 Byte 000000 Byte 000001 Word 000002 Byte 000002 Byte 000003

• • Word FFFFFE Byte FFFFFE Byte FFFFFF

Figure 3. Word Organization in Memory

4.4 Signetics MICROPROCESSOR DIVISION JANUARY 1983

16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

Bit Data 1 Byte= 8 Bits

7 6 5 4 3 2 1 0

Integer Data 1 Byte =8 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0

Byte 0 Byte 1 MSB LSB

Byte 2 Byte 3

1 Word= 16 Bits

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Word 0 MSB LSB

Word 1

Word 2

1 Long Word= 32 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSB High Order — — Long Word 0 Low Order LSB

— —Long Word 1

— — Long Word 2

Addresses 1 Address= 32 Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 MSB High Order — — Address 0 Low Order LSB

— — Address 1

— — Address 2

MSB= Most Significant Bit LSB = Least Significant Bit Decimal Data 2 Binary Coded Decimal Digits= 1 Byte 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSD BCD 0 BCD 1 LSD BCD 2 BCD 3

BCD 4 BCD 5 BCD 6 BCD 7 MSD= Most Significant Digit LSD= Least Significant Digit

Figure 4. Data Organization in Memory

Signetics 4.5 MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

NOTE specifies byte operation, the processor peripheral device. The processor writes The terms assertion and negation are used uses an internal AO bit to determine which bytes of data in all cases. If the instruction extensively to avoid confusion when deal- byte to read and then issues the data specifies a word operation, the processor ing with a mixture of 'active low' and strobe required for that byte: when the AO writes both bytes simultaneously. When 'active high' signals. Assert or assertion is bit equals zero, the upper data strobe is the instruction specifies a byte operation, used to indicate that a signal is active or issued; when the AO bit equals one, the the processor uses an internal AO bit to true independent of whether that voltage lower data strobe is issued. When the data determine which byte to write and then is low or high. Negate or negation is used is received, the processor correctly posi- issues the data strobe required for that to indicate that a signal is inactive or false. tions it internally. byte: when the AO bit equals zero, the upper data strobe is issued; when the AO Flow charts for word and byte read cycles bit equals one, the lower data strobe is Read Cycle — During a read cycle, the pro- are shown in figures 5 and 6 respectively. issued. cessor receives data from memory or a Figure 7 illustrates read and write cycle peripheral device. The processor reads timing and figure 8 illustrates the timing Flow charts for word and byte write cycles bytes of data in all cases. If the instruction for word and byte read cycles. are shown in figures 9 and 10 respectively. specifies a word (or double word) opera- Figure 11 illustrates the timing for both tion, the processor reads both bytes Write Cycle — During a write cycle, the cases. simultaneously. When the instruction processor sends data to memory or a

BUS MASTER SLAVE BUS MASTER SLAVE

Address Device Address Device 1) Set R/W to Read 11 Set R/W to Read 21 Place Function Code on FCO-FC2 21 Place Function Code on FCO-FC2 3) Place Address on A1-A23 31 Place Address on A1-A23 41 Assert Address Strobe (A7) 41 Assert Address Strobe (ASI 51 Assert Upper Data Strobe IUDSI or Lower 51 Assert Upper Data Strobe IUDS/ and Low- Data Strobe (LDS) (based on AO) er Data Strobe (LDS)

Input Data 11 Decode Address Input Data 2) Place Data on DO-D7 or D8-D15 (based on 11 Decode Address UDS or LDS) 21 Place Data on DO-D15 3) Assert Data Transfer Acknowledge 31 Assert Data Transfer (DTACK) Acknowledge (DTACK)

Acquire Data Acquire Data 1) Latch Data 11 Latch Data 2) Negate UDS or LDS 21 Negate UDS and LDS 3) Negate AS 31 Negate T.,§

Terminate Cycle Terminate Cycle 1) Remove Data from DO-D7 or D8-D15 1) Remove Data from DO-D15 2) Negate DTACK 2) Negate DTACK

Start Next Cycle Start Next Cycle

Figure 5. Word Read Cycle Flow Chart Figure 6. Byte Read Cycle Flow Chart

4.6 Signetics MICROPROCESSOR DIVISION JANUARY 1983

46-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

SO S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 w w w w S5 S6 S7 CLK

Al-A23 AS UDS LDS RAM

DTACK D8-015 DO-D7 FCO-2

— -Read- -Write — — -Slow Read— —

Figure 7. Read and Write Cycle Timing

SO S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 S5 S6 S7 CLK

A1-A23 111111111•11MMIM 01111111111111111•111. 1111111111111•111•11111 AO*

R/W DTACK D8-D15

DO-D7 >-______< FCO-2 * Internal Signal Only

— - Word Read- - — Odd Byte Read- 3▪ 0- —Even Byte Read — 3P.1

Figure 8. Word and Byte Read Cycle Timing

Signetics 4-7 MICROPROCESSOR DIVISION JANUARY 1983

16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

BUS MASTER SLAVE BUS MASTER SLAVE

Address Device Address Device 11 Place Function Code on FCO-FC2 11 Place Function Code on FCO-FC2 2) Place Address on A1-A23 21 Place Address on A1-A23 3) Assert Address Strobe (A7) 3) Assert Address Strobe (ASI 4/ Set R/W/ to Write 41 Set R/W to Write 5) Place Data on DO-D15 51 Place Data on DO-D7 or D8-D15 (according to AO) 6) Assert Upper Data Strobe (UDS) and 6) Assert Upper Data Strobe (UDS) or Lower Lower Data Strobe (LDS) Data Strobe (LDS) (based on AO)

Input Data Input Data 1) Decode Address 11 Decode Address 21 Store Data on DO-D7 if LDS is asserted 21 Store Data on DO-D15 Store Data on D8-D15 if UDS is asserted 31 Assert Data Transfer 3) Assert Data Transfer Acknowledge Acknowledge (DTACK) IDTACKI

Terminate Output Transfer Terminate Output Transfer 1) Negate UDS and LDS 2) Negate AS 1) Negate UDS and LDS 3) Remove Data from DO-D15 21 Negate AS 4) Set R/W to Read 3) Remove Data from DO-D7 or D8-D15 4) Set R/W to Read

Terminate Cycle Terminate Cycle 11 Negate DTACK 11 Negate DTACK

Start Next Cycle Start Next Cycle

Figure 9. Word Write Cycle Flow Chart Figure 10. Byte Write Cycle Flow Chart

SO S1 S2 S3 S4 S5 S6 S7 SO 51 52 S3 S4 S5 S6 S7 SO Si S2 S3 S4 S5 S6 S7 CLK

At-A23 a 1E1111 MI 1E11111111 11111111/1111111 111111D AO* AS UDS

R/W

DTACK

D8-D15

DO-D7

FCO-2

*Internal Signal Only

- Word Write-- Odd Byte Write - Even Byte Write -- i+

Figure 11. Word and Byte Write Cycle Timing

4.8 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

Read-Modify-Write Cycle — The read- Bus Arbitration device. Figure 15 is a timing diagram for modify-write cycle performs a read, modi- the same operations. The technique used Bus arbitration is a technique used by fies the data in the arithmetic-logic unit, allows processing of bus requests during master type devices to request, be and writes the data back to the same ad- data transfer cycles. granted, and acknowledge bus master- dress. In the SCN68000, this cycle is indi- ship. In its simplist form, it consists of: The timing diagram shows that the bus re- visible in that the address strobe is assert- quest is negated at the time that an 1. Asserting a bus mastership request. ed throughout the entire cycle. The test acknowledge is asserted. This type of and set (TAS) instruction uses this cycle 2. Receiving a grant that the bus is avail- operation would be true for a system con- to provide meaningful communication be- able at the end of the current cycle. sisting of the processor and one device tween processors in a multiple processor capable of bus mastership. In systems environment, and is the only instruction 3. Acknowledging that mastership has having a number of devices capable of that uses it. The read-modify-write cycle is been assumed. mastership, the bus request line from always a byte operation. The flow chart is Figure 14 is a flow chart showing the each device is wire-ORed to the processor. given in figure 12 and a timing diagram is detail involved in a request from a single In this system, there could be more than shown in figure 13. 4

BUS MASTER SLAVE Address Device 11 Set R/W to Read 21 Place Function Code on FCO-FC2 Input Data 31 Place Address on A1-A23 1) Decode Address 41 Assert Address Strobe (TAS1 2) Place Data on DO-D7 or D8-D15 51 Assert Upper Data Strobe (UDS) or 3) Assert Data Transfer Acknowledge Lower Data Strobe (LDS) (DTACK)

Acquire Data 1) Latch Data 2) Negate UDS or LDS I 3) Start Data Modification Terminate Cycle 1) Remove Data from DO-D7 or D8-D15 2) Negate DTACK

Start OutputI Transfer 1) Set R/W to Write 2) Place Data on DO-D7 or D8-D15 Input Data 3) Assert Upper Data Strobe IUDSI or Lower 1) Store Data on DO-D7 or D8-D15 Data Strobe (LDS) 2) Assert Data Transfer Acknowledge (DTACK)

Terminate Output Transfer 1) Negate UDS or LDS 2) Negate AS 31 Remove Data from DO-D7 or D8-D15 4) Set R/W to Read Terminate Cycle 1) Negate DTACK

Start Next Cycle

Figure 12. Read-Modify-Write Cycle Flow Chart

Signetics 4.9 MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

SO S1 S2 S3 S4 S5 S6 S7 S8 S9 SlOS11S12S13S14S 5S16S17S18S19 CLK Al-A23 D—( )-- AS \ /

UDS or LDS / \ / R/W \ / DTACK \ / \ / )------( D8-D15 ---( ).----

FCO-2 D( C

Indivisible Cycle - 14 Figure 13. Read-Modify-Write Cycle Timing

one bus request being made. The timing PROCESSOR REQUESTING DEVICE diagram shows that the bus grant signal is Request the Bus negated a few clock cycles after the tran- 1) Assert Bus Request (BR) sition of the acknowledge (BGACK) signal. However, if the bus requests are still pending, the processor will assert another bus grant within a few clock cycles after it was Grant Bus Arbitration negated. This additional assertion of bus 11 Assert Bus Grant (BG) grant allows external arbitration circuitry to select the next bus master before the current bus master has completed its requirements. Acknowledge Bus Mastership 1) External arbitration determines next bus Requesting the Bus — External devices, master capable of becoming bus masters, request 2) Next bus master waits for current cycle to the bus by asserting the bus request (BR) complete signal. This is a wire-ORed signal (al- 3) Next bus master asserts Bus Grant though it need not be constructed from Acknowledge (BGACK) to become new open collector devices) that indicates to master the processor that some external device 4) Bus master negates BR requires control of the external bus. The processor is effectively at a lower bus priority level than the external device and Terminate Arbitration will relinquish the bus after it has com- 1) Negate BG (and wait for BGACK to be pleted the last bus cycle it has started. negated) When no acknowledge is received before the bus request signal goes inactive, the Operate as Bus Master processor will continue processing when it detects that the bus request is inactive. 1) Perform Data Transfers (Read and Write This allows ordinary processing to con- cycles) according to the same rules the processor uses. tinue if the arbitration circuitry inadvertently responded to noise.

Release Bus Mastership Receiving the Bus Grant — The processor 1) Negate BGACK asserts bus grant (BG) as soon as possible. Normally this is immediately after internal synchronization. The only exception to this occurs when the processor has Re-Arbitrate or Resume Processor made an internal decision to execute the next bus cycle but has not progressed far enough into the cycle to have asserted the Figure 14. Bus Arbitration Cycle Flow Chart address strobe (AS) signal. In this case, bus grant will not be asserted until one 4-10 Signetics MICROPROCESSOR DIVISION JANUARY 1983

16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

CLK

A1-A23

I‘ LDS/UDS

R/W DTACK DO-D15

FCO-2

BR BG BGACK

Processor— )0+4 —DMA Device— -044— — -Processor — — —11441F— -DMA Device' —

Figure 15. Bus Arbitration Cycle Timing

clock after address strobe is asserted to knowledge is asserted. If bus request is shown in figure 18. The bus arbitration se- indicate to external devices that a bus still asserted after bus grant acknowledge quence while the bus is inactive (i.e., ex- cycle is being executed. is negated, the processor performs an- ecuting internal operations such as a other arbitration sequence and issues The bus grant signal may be routed multiply instruction) is shown in figure 19. another bus grant. Note that the proces- through a daisy-chained network or If a bus request is made at a time when the sor does not perform any external bus through a specific priority-encoded net- MPU has already begun a bus cycle but AS cycles before it reasserts bus grant. work. The processor is not affected by the has not been asserted (bus state SO), BG external method of arbitration as long as Bus Arbitration Control—The bus arbitra- will not be asserted on the next rising the protocol is obeyed. tion control unit in the SCN68000 is imple- edge following its internal assertion. This mented with a finite state machine whose sequence is shown in figure 20. Acknowledgement of Mastership — Upon state diagram is shown in figure 16. All receiving a bus grant, the requesting asynchronous signals to the SCN68000 are Bus Error and Halt Operation device waits until address strobe, data synchronized before being used inter- transfer acknowledge, and bus grant In a bus architecture that requires a hand- nally. This synchronization is accom- acknowledge are negated before issuing shake from an external device, the possi- plished in a maximum of one cycle of the its own BGACK. The negation of the ad- bility exists that the handshake might not system clock, assuming that the asyn- dress strobe indicates that the previous occur. Since different systems will require chronous input setup time (#47) has been master has completed its cycle, and the a different maximum response time, a bus met (see figure 17). The input signal is error input is provided. External circuitry negation of bus grant acknowledge indi- sampled on the falling edge of the clock cates that the previous master has re- must be used to determine the duration and is valid internally after the next falling leased the bus. A device is not allowed to between address strobe and data transfer edge. 'break into' a cycle while address strobe is acknowledge before issuing a bus error asserted. The negation of data transfer As shown in figure 16, input signals signal. When a bus error signal is re- acknowledge indicates that the previous labeled R and A are internally synchro- ceived, the processor has the option of slave has terminated its connection to the nized on the bus request and bus grant either initiating a bus error exception previous master. Note that in some appli- acknowledge pins respectively. The bus sequence or trying to run the bus cycle cations, data transfer acknowledge might grant output is labeled G and the internal again. not enter into this function. General pur- three-state control signal T. If T is true, the Exception Sequence — When the bus pose devices would then be connected address, data, and control buses are error signal is asserted, the current bus such that they were only dependent on ad- placed in a high-impedance state when AS cycle is terminated. If BERR is asserted dress strobe. When bus grant acknowl- is negated. All signals are shown in posi- before the falling edge of S4, AS will be edge is issued, the device remains the bus tive logic (active high) regardless of their negated in S7 in either a read or write master until it negates bus grant acknowl- true active voltage level. cycle. As long as BERR remains asserted, edge. Bus grant acknowledge should not State changes (valid outputs) occur on the the data and address buses will be in the be negated until after the bus cycle(s) is next rising edge after the internal signal is high-impedance state. When BERR is neg- completed. valid. ated, the processor will begin stacking for The bus request from the granted device A timing diagram of the bus arbitration the exception sequence. Figure 21 is a should be dropped when bus grant ac- sequence during a processor bus cycle is timing diagram for the exception se- Signetics 4.11 MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

TT, quence which is composed of the following elements: 1. Stacking the program counter and status register. 2. Stacking the error information. 3. Reading the bus error vector table entry. 4. Executing the bus error handling routine. The stacking of the program counter and the status register is the same as if an interrupt had occurred. Several additional items are stacked when a bus error occurs to determine the nature of the error and to correct it, if possible. The bus error vector is vector number two located at address $000008. The processor loads the program counter from this location and a software bus error handler routine is then executed by the processor. Refer to Exception Pro- cessing for additional information.

Rerunning the Bus Cycle — When the processor receives a bus error signal and the halt pin is being driven by an external device, the processor enters the rerun R= Bus Request Internal RA sequence illustrated in figure 22. A= Bus Grant Acknowledge Internal The processor completes the bus cycle, G= Bus Grant then puts the address, data, function T = Three-State Control to Bus Control Logic code, and control leads in the high- X= Don't Care impedance state. The processor remains * State machine will not change state if bus is in SO.. Refer to 'halted' and will not run another bus cycle BUS ARBITRATION CONTROL for additional information. until the halt signal is removed by external Figure 16. State Diagram of SCN68000 Bus Arbitration Unit logic. The processor will then rerun the previous bus cycle using the same address, the same function codes, the same data (for a write operation), and the same Internal Signal Valid controls. The bus error signal should be removed before the halt signal is removed. External Signal Sampled —4 NOTE CLK The processor will not rerun a read-modify- write cycle. This restriction is made to guarantee that the entire cycle runs correctly and that the write operation of a test-and-set operation is performed without ever releasing AS. If BERR and HALT BR (External) are asserted during a read-modify-write cycle, a bus error operation results.

The processor terminates the bus cycle, then puts the address, data and function BR (Internal) code output lines in the high-impedance state. The processor remains 'halted' and will not run another bus cycle until the halt signal is removed by external logic. Then Asychronous the processor will rerun the previous bus Input Delay* cycle using the same address, the same *This delay time is equal to parameter # 33,tcHGL. function codes, the same data (for a write operation), and the same controls. The Figure 17. Timing Relationship of External Inputs to Internal Signals bus error signal should be removed before the halt signal is removed. 4.12 Signetics MICROPROCESSOR DIVISION JANUARY 1983

16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

Bus three stated Bus released from three state and BG asserted Processor starts next bus cycle BR valid internal BGACK negated internal BR sampled BGACK sampled BR asserted-1 BGACK negated

CLK SC S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 S5 S6 S7 SO S1 BR

BGACK A1 A23 ) AS /-‘ UDS

LDS

FCO-FC2

R/W

DTACK

DO-D15 ) Processor Alternate Bus Master Processor

Figure 18. Bus Arbitration During Processor Bus Cycle

Bus released from three state and processor starts next bus cycle BGACK negated BG asserted and bus three stated BR valid internal BR asserted

CLK SO S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4

BGACK

A1-A23

UDS r

LDS

FCO-FC2

R/W

DTACK

D0-D15 ) Processor Bus Inactive Alternate Bus Master Processor

Figure 19. Bus Arbitration with Bus Inactive

Signetics 4.13

MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

BR asserted Bus released from three state and BR sampled Processor starts next bus cycle Bus th ee stated BGACK negated internal BG asserted BGACK sampled BR valid internal BGACK negated

V CLK SO S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 S5 S6 S7 SO S1 BR

BGACK A1 A23 ( ) C=iiD- —C AS

UDS LDS \ 1-` /--- \ /------F CO- F C3 —X ( R /7V

DTACK

DO D15 Processor Alternate Bus Master Processor 1 4

Figure 20. Bus Arbitration During Processor Bus Cycle Special Case

CLK A1-A23 D---( N AS \ / Lositir)- s IR/ \TY N—\ DTACK N DO D15 FCO-2 N BERR HALT Inivatee Initiate Bus -Response Failure— —1014-- — — Bus Error Detection _ k Read Error Stacking

Figure 21. Bus Error Timing

4.14 Signetics MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

CLK A1-A23 al11111111MIIIM

LDS/UDS • R/W DTACK • DO-D15 FCO-2

BERR

HALT

— — Read— — ) 4— Halt— — — — — Rerun— —

Figure 22. Rerun Bus Cycle Timing

CLK

Al-A23 D--'( 1111111111111111111=1.1 4,7 LDS/ UDS • • R/W DTACK • • DO D15

FCO-2 HALT • — —Read-- — — 144— — — Halt — — — — — Read — —

Figure 23. Halt Signal Timing

Halt Operation with No Bus Error — The cycle, then changing to the 'halt' mode. When the processor completes a bus halt input signal to the SCN68000 can be Thus, the single step mode allows the cycle after recognizing that the halt signal used to perform a halt/run/single-step user to proceed through (and therefore is active, most three-state signals are put function. The halt and run modes are debug) processor operations one bus in the high-impedance state. These in- somewhat self explanatory in that, when cycle at a time. clude address lines and data lines. This is the halt signal is constantly active, the Figure 23 shows the timing required for required for correct performance of the processor 'halts' (does nothing) and when correct single-step operations. Some care rerun bus cycle operation. the halt signal is constantly inactive, the must be exercised to avoid harmful inter- While the processor is honoring the halt processor 'runs' (does something). actions between the bus error signal and request, bus arbitration performs as usual. The single-step mode is derived from cor- the halt pin when using the single cycle That is, halting has no effect on bus arbi- rectly timed transitions on the halt signal mode as a debugging tool. This is also tration. It is the bus arbitration function input. It forces the processor to execute a true of interactions between the halt and that removes the control signals from the single bus cycle by entering the 'run' reset lines since these can reset the pro- bus. mode until the processor starts a bus cessor. Signetics 4.15 MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

The halt function and the hardware trace execution. If a bus error occurs while Halt termination: HALT is asserted at the capability allow the hardware debugger to reading the vector table (or at any time same time, or precedes DTACK (no BERR) trace single bus cycles or single instruc- before the first instruction is executed), cases 2 and 3. tions at a time. These processor capabil- the processor reacts as if a double bus ities, along with a software debugging fault has occurred and it halts. Only an ex- Bus error termination: BERR is asserted in package, give total debugging flexibility. ternal reset will start a halted processor. lieu of, at same time, or preceding DTACK (case 4); BERR negated at same time, or Double Bus Faults — When a bus error ex- Relationship of DTACK, BERR, after DTACK. ception occurs, the processor will attempt and HALT to stack several words containing informa- Rerun termination: HALT and BERR tion about the state of the processor. If a In order to properly control termination of asserted at the same time, or before bus error exception occurs during the a bus cycle for a rerun or a bus error condi- DTACK (cases 6 and 7); HALT must be stacking operation, there have been two tion, DTACK, BERR, and HALT should be negated at least one cycle after BERR. bus errors in a row, which is commonly asserted and negated on the rising edge Case 5 indicates BERR can precede HALT referred to as a double bus fault. When a of the SCN68000 clock. This will assure which allows fully asynchronous asser- double bus fault occurs, the processor will that when two signals are asserted simul- tion. halt. Once a bus error exception has oc- taneously, the required setup time (#47) curred, any bus error exception occurring for both of them will be met during the Table 4 details the resulting bus cycle ter- before the execution of the next instruc- same bus state. mination under various combinations of tion constitutes a double bus fault. This, or some equivalent precaution, control signal sequences. The negation of should be designed external to the these same control signals under several Note that a bus cycle which is rerun does SCN68000. Parameter #48 is intended to conditions is shown in table 5 (DTACK is not constitute a bus error exception, and ensure this operation in a totally asyn- assumed to be negated normally in all does not contribute to a double bus fault. chronous system, and may be ignored if cases; for best results, both DTACK and This means that as long as the external the above conditions are met. BERR should be negated when address hardware requests it, the processor will strobe is negated). continue to rerun the same bus cycle. The preferred bus cycle terminations can be summarized as follows (case numbers The bus error pin also has an effect on the refer to table 4): Example A: A system uses a watch-dog processor operation after the processor timer to terminate accesses to un- receives an external reset input. The pro- populated address space. The timer cessor reads the vector table after a reset Normal termination: DTACK occurs first asserts DTACK and BERR simultaneousl to determine the address to start program (case 1). after time-out (case 4). Table 4 DTACK, BERR, HALT ASSERTION RESULTS Asserted on Rising Case Control Edge of State Result No. Signal N N + 2 DTACK A S Normal cycle terminate and continue. 1 BERR NA X HALT NA X DTACK A S Normal cycle terminate and halt. Continue when HALT removed. 2 BERR NA X HALT A S DTACK NA A Normal cycle terminate and halt. Continue when HALT removed. 3 BERR NA NA HALT A S DTACK X X Terminate and take bus error trap. 4 BERR A S HALT NA NA DTACK NA X Terminate and re-run. 5 BERR A S HALT NA A DTACK X X Terminate and re-run. 6 BERR A S HALT A S DTACK NA X Terminate and re-run when HALT removed. 7 BERR NA A HALT A S Legend: N — he number of the current even bus state le.g S4, S6, etc.l A — signal is asserted in this bus state NA — signal is not asserted in this state X — don't care S — signal was asserted in previous state and remains asserted in this state 4.16 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

Example B: A system uses error detection the reset vector table entry (vector number PROCESSING STATES on RAM contents. Designer can (a) delay zero, address $000000) and loads it into The SCN68000 is always in one of three DTACK until the data is verified, and return the supervisor stack pointer (SSP). Vector processing states: normal, exception, or BERR and HALT simultaneously to rerun table entry number one at address halted. The normal processing state is error cycle (case 6), or if valid, return $000004 is read next and loaded into the that associated with instruction execu- DTACK; (b) delay DTACK until data is program counter. The processor initializes tion; the memory references are to fetch verified, and return BERR at the same time the status register to an interrupt level of instructions and operands, and to store as DTACK if data is in error (case 4); (c) seven. No other registers are affected by results. A special case of the normal state return DTACK prior to data verification, as the reset sequence. is the stopped state which the processor described in the previous section. If data When a RESET instruction is executed, enters when a STOP instruction is exe- is invalid, BERR is asserted (case 1) in the the processor drives the reset pin for 124 cuted. In this state, no further memory ref- next cycle. Error handling software must clock pulses. In this case, the processor is erences are made. know how to recover the error cycle. trying to reset the rest of the system. The exception processing state is asso- Therefore, there is no effect on the inter- ciated with interrupts, trap instructions, Reset Operation nal state of the processor and its internal tracing and other exceptional conditions. The reset signal is a bidirectional signal registers and the status register are unaf- The exception may be internally generated that allows either the processor or an ex- fected. All external devices connected to 4 by an instruction or by an unusual condi ternal signal to reset the system. Figure 24 the reset line should be reset at the com- Hon arising during the execution of an in- illustrates reset timing. Both the halt and pletion of the RESET instruction. struction. Externally, exception process- the reset lines must be applied to ensure Asserting the RESET and HALT pins for ing can be forced by an interrupt, by a bus total reset of the processor. ten clock cycles will cause a processor error, or by a reset. Exception processing When the reset and halt lines are driven by reset, except when Vcc is initially applied is designed to provide an efficient context an external device, it is recognized as an to the processor. In this case, an external switch so that the processor can handle entire system reset, including the proces- reset must be applied for 100 millisec- unusual conditions. sor. The processor responds by reading onds. The halted processing state is an indication of catastrophic hardware failure. For Table 5 BERR AND HALT NEGATION RESULTS example, if during the exception processing of a bus error another bus error oc- Conditions of Negated on Rising curs, the processor assumes that the sys- Control Termination in Edge of State Results — Next Cycle tem is unusable and halts. Only an exter- Signal Table A N N + 2 nal reset can restart a halted processor. BERR • or • Takes bus error trap. Note that a processor in the stopped state Bus Error HALT • or • is not in the halted state, nor vice versa. BEAR • or • Illegal sequence; usually traps to Re-run HALT • vector number 0. Privilege States BERR • Re-runs the bus cycle. Re-run The processor operates in one of two HALT • states of privilege: the 'user' state or the BERR • May lengthen next cycle. Normal 'supervisor' state. The privilege state HALT • or • determines which operations are legal, is BERR • If next cycle is started it will Normal used by the external memory management HALT • or none be terminated as a bus error. device to control and translate accesses,

CLK

Plus 5 Volts

VCC t— >100 Milliseconds RESET 1

HALT 1 t < 4 IE 1—>I Bus Cycles )000001000 00(000 CDCD=== 2 3 4 5 6 NOTES: 1) Internal start-up time 4) PC High read in here Bus State Unknown:X)00(X 21 SSP High read in here 5) PC Low read in here All Control Signals Inactive. 31 SSP Low read in here 6) First instruction fetched here Data Bus In Read Mode: Figure 24. Reset Operation Timing

Signetics 4.17 MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary and is used to choose between the super- pointer (MOVE and USP) instructions are new context is obtained, and the pro- visor stack pointer and the user stack also privileged. cessor switches to instruction process- pointer in instruction references. ing. The bus cycles generated by an instruc- The privilege state is a mechanism for pro- tion executed in user state are classified Exception Vectors — Exception vectors viding security in a computer system. Pro- as user state references. This allows an are memory locations from which the programs should access only their own code external memory management device to cessor fetches the address of a routine and data areas, and ought to be restricted translate the address and to control ac- which will handle that exception. All ex- from accessing information which they do cess to protected portions of the address ception vectors are two words in length not need and must not modify. space. While the processor is in the user (see figure 25), except for the reset vector, privilege state, those instructions which The privilege mechanism provides secur- which is four words. All exception vectors use either the system stack pointer im- ity by allowing most programs to execute lie in the supervisor data space, except for plicitly, or address register seven explic- in user state. In this state, their accesses the reset vector which is in the supervisor ity, access the user stack pointer. are controlled, and the effects on other program space. A vector number is an parts of the system are limited. The oper- 8-bit number which, when multiplied by Privilege State Changes — Once the pro- ating system executes in the supervisor four, gives the address of an exception cessor is in the user state and executing state, has access to all resources, and per- vector. Vector numbers are generated in- instructions, only exception processing forms the overhead tasks for the user ternally or externally, depending on the can change the privilege state. During ex- state programs. cause of the exception. In the case of in- ception processing, the current setting of terrupts, during the interrupt acknowledge the S-bit of the status register is saved Supervisor State — The supervisor state bus cycle, a peripheral provides an 8-bit and the S-bit is asserted, putting the pro- is the higher state of privilege. For instruc- vector number (see figure 26) to the processor in the supervisor state. Therefore, tion execution, the supervisor state is de- cessor on the data bus lines DO through when instruction execution resumes at termined by the S-bit of the status regis- D7. The processor translates the vector the address specified to process the exter: it is asserted (high), the processor is in number into a full 24-bit address, as ception, the processor is in the supervisor the supervisor state. All instructions can shown in figure 27. The memory layout for privilege state. be executed in the supervisor state. The exception vectors is given in table 7. bus cycles generated by instructions executed in the supervisor state are classified Reference Classification — When the pro- As shown in table 7, the memory layout is as supervisor references. While the processor makes a reference, it classifies the 512 words long (1024 bytes). It starts at ad- cessor is in the supervisor privilege state, kind of reference being made, using the dress 0 and proceeds through address those instructions which use either the encoding on the three function code out- 1023. This provides 255 unique vectors; system stack pointer implicitly or address put lines. This allows external translation some of these are reserved for traps and register seven explicitly access the super- of addresses, control of access, and dif- other system functions. Of the 255, there are 192 reserved for user interrupt vectors. visor stack pointer. ferentiation of special processor states, such as an interrupt acknowledge. Table 6 However, there is no protection on the All exception processing is done in the lists the classification of references. first 64 entries, so the user interrupt vec- supervisor state, regardless of the setting tors may overlap at the discretion of the of the S-bit. The bus cycles generated dur- systems designer. ing exception processing are classified as Exception Processing General supervisor references. All stacking opera- Description Kinds of Exceptions — Exceptions can be tions during exception processing use the The processing of an exception occurs in generated by either internal or external supervisor stack pointer. four steps, with variations for different ex- causes. The externally generated excep- ception causes. During the first step, a tions are the interrupts and the bus error User State — The user state is the lower temporary copy of the status register is and reset requests. The interrupts are re- state of privilege. For instruction execu- made, and the status register is set for ex- quests from peripheral devices for proces- tion, the user state is determined by the ception processing. In the second step sor action while the bus error and reset in- S-bit of the status register: it is negated the exception vector is determined, and puts are used for access control and pro- (low), the processor is executing instruc- the third step is the saving of the current cessor restart. The internally generated tions in the user state. processor context. In the fourth step a exceptions come from instructions, or Most instructions execute the same in user state as in the supervisor state. Table 6 REFERENCE CLASSIFICATION However, some instructions which have Function Code Output Reference Class important system effects are made privi- FC2 FC1 FCO leged. User programs are not permitted to 0 0 0 (Unassigned) execute the STOP instruction, or the RESET instruction. To ensure that a user 0 0 1 User Data program cannot enter the supervisor state 0 1 0 User Program except in a controlled manner, the instruc- 0 1 1 (Unassigned) tions which modify the whole status regis- 1 0 0 (Unassigned) ter are privileged. To aid in debugging pro- 1 0 1 Supervisor Data grams which are to be used as operating systems, the move to user stack pointer 1 1 0 Supervisor Program (MOVE to USP) and move from user stack 1 1 1 Interrupt Acknowledge

4.18 Signetics MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

Word 0 New Program Counter (High) A0=0, Al =0

Word 1 New Program Counter (Low) A0=0, Al =1

Figure 25. Exception Vector Format

D15 D8 D7 DO

Ignored v7 v6 v5 v4 v3 v2 vl v0

Where: v7 is the MSB of the Vector Number v0 is the LSB of the Vector Number

Figure 26. Peripheral Vector Number Format

A23 A10 A9 A8 A7 A6 A5 A4 A3 A2 Al AO

All Zeroes v7 v6 v5 v4 v3 v2 vl v0 0 0

Figure 27. Address Translated from 8-Bit Vector Number

from address errors or tracing. The trap processor fetch, classified as an interrupt The instruction at the address given in the (TRAP), trap on overflow (TRAPV), check acknowledge. For all other exceptions, in- exception vector is fetched, and the nor- register against bounds (CHK) and divide ternal logic provides the vectored number. mal instruction decoding and execution is (DIV) instructions all can generate excep- This vector number is then used to gener- started. tions as part of their instruction execu- ate the address of the exception vector. tion. In addition, illegal instructions, word Multiple Exceptions — The following fetches from odd addresses and privilege The third step is to save the current pro- describes the processing which occurs violations cause exceptions. Tracing be- cessor status, except in the case of the when multiple exceptions arise simultane- haves like a very high priority, internally reset exception. The current program ously. Exceptions can be grouped accord- generated interrupt after each instruction counter value and the saved copy of the ing to their occurrence and priority. The execution. status register are stacked using the group 0 exceptions are reset, bus error, supervisor stack pointer. The program and address error. These exceptions Exception Processing Sequence — Ex- counter value stacked usually points to cause the instruction currently being exe- ception processing occurs in four identifi- the next unexecuted instruction, however cuted to be aborted and the exception pro- able steps. In the first step, an internal for bus error and address error, the value cessing to commence at the next minor copy is made of the status register. After stacked for the program counter is unpre- cycle of the processor. The group 1 excep- the copy is made, the S-bit is asserted put- dictable, and may be incremented from tions are trace and interrupt, as well as the ting the processor into the supervisor priv- the address of the instruction which privilege violations and illegal instruc- ilege state. Also, the T-bit is negated caused the error. Additional information tions. These exceptions allow the current which will allow the exception handler to defining the current context is stacked for instruction to execute to completion, but execute unhindered by tracing. For the the bus error and address error excep- preempt the execution of the next instruc- reset and interrupt exceptions, the inter- tions. tion by forcing exception processing to rupt priority mask is also updated. The last step is the same for all excep- occur (privilege violations and illegal in- In the second step, the vector number of tions. The new program counter value is structions are detected when they are the the exception is determined. For inter- fetched from the exception vector and the next instruction to be executed). The rupts, the vector number is obtained by a processor resumes instruction execution. group 2 exceptions occur as part of the Signetics 4.19 MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary Table 7 EXCEPTION VECTOR ASSIGNMENT sumes, however, the interrupt exception is also processed, and instruction process- Vector Address ing commences finally in the interrupt Assignment Number(s) Dec Hex Space handler routine. A summary of exception 0 0 000 SP Reset: Initial SSP grouping and priority is given in table 8. 4 004 SP Reset: Initial PC 2 8 008 SD Bus Error Exception Processing Detailed 3 12 DOC SD Address Error Discussion 4 16 010 SD Illegal Instruction Exceptions have a number of sources, and 5 20 014 SD Zero Divide each exception has processing which is 6 24 018 SD CHK Instruction peculiar to it. 7 28 01C SD TRAPV Instruction Reset — The reset input provides the 8 32 020 SD Privilege Violation highest exception level. The processing of 9 36 024 SD Trace the reset signal is designed for system in- 10 40 028 SD Line 1010 Emulator itiation and recovery from catastrophic 11 44 02C SD Line 1111 Emulator failure. Any processing in progress at the time of the reset is aborted and cannot be 12" 48 030 SD (Unassigned, reserved) recovered. The processor is forced into 13* 52 034 SD (Unassigned, reserved) the supervisor state, and the trace state is 14* 56 038 SD (Unassigned, reserved) forced off. The processor interrupt priority 15 60 03C SD Uninitialized Interrupt Vector mask is set at level seven. The vector num- 16-23" 64 04C SD (Unassigned, reserved) ber is internally generated to reference the reset exception vector at location 0 in the 95 05F supervisor program space. Because no as- 24 96 060 SD Spurious Interrupt sumptions can be made about the validity 25 100 064 SD Level 1 Interrupt Autovector of register contents, in particular the 26 104 068 SD Level 2 Interrupt Autovector supervisor stack pointer, neither the pro- 27 108 06C SD Level 3 Interrupt Autovector gram counter nor the status register is 28 112 070 SD Level 4 Interrupt Autovector saved. The address contained in the first two words of the reset exception vector is 29 116 074 SD Level 5 Interrupt Autovector fetched as the initial supervisor stack 30 120 078 SD Level 6 Interrupt Autovector pointer, and the address in the last two 31 124 07C SD Level 7 Interrupt Autovector words of the reset exception vector is 32-47 128 080 SD TRAP Instruction Vectors fetched as the initial program counter. 191 OBE — Finally, nstruction execution is started at the address in the program counter. The 48-63' 192 OCO SD (Unassigned, reserved) power-up/restart code should be pointed 255 OFF to by the initial program counter. 64-255 256 100 SD User Interrupt Vectors The RESET instruction does not cause 1023 3FF — loading of the reset vector, but does *Vector numbers 12, 13, 14, 16 through 23 and 48 through 63 are assert the reset line to reset external reserved for future enhancements. No user peripheral devices devices. This allows the software to reset should be assigned these numbers. the system to a known state and then continue processing with the next instruction.

Interrupts — Seven levels of interrupt priorities are provided. Devices may be normal processing of instructions. The struction can be executed at a time, there chained externally within interrupt priority TRAP, TRAPV, CHK, and zero divide ex- is no priority relation within group 2. levels, allowing an unlimited number of peripheral devices to interrupt the pro- ceptions are in this group. For these ex- The priority relation between two excep- cessor. Interrupt priority levels are ceptions, the normal execution of an in- tions determines which is taken, or taken numbered from one to seven, level seven struction may lead to exception process- first, if the conditions for both arise being the highest priority. The status ing. simultaneously. Therefore, if a bus error register contains a three-bit mask which Group 0 exceptions have highest priority, occurs during a TRAP instruction, the bus indicates the current processor priority, while group 2 exceptions have lowest pri- error takes precedence, and the TRAP in- and interrupts are inhibited for all priority ority. Within group 0, reset has highest struction processing is aborted. In levels less than or equal to the current pro- priority, followed by bus error and then ad- another example, if an interrupt request cessor priority. dress error. Within group 1, trace has pri- occurs during the execution of an instruc- ority over external interrupts, which in tion while the T-bit is asserted, the trace An interrupt request is made to the pro- turn takes priority over illegal instruction exception has priority, and is processed cessor by encoding the interrupt request and privilege violation. Since only one in- first. Before instruction processing re- level on the interrupt request lines; a zero

4.20 Signetics MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

Table 8 EXCEPTION GROUPING AND PRIORITY indicates no interrupt request. Interrupt requests arriving at the processor do not Group Exception Processing force immediate exception processing, Reset Exception processing begins but are made pending. Pending interrupts 0 Bus Error within two clock cycles. are detected between instruction execu- Address Error tions. If the priority of the pending inter- Trace rupt is lower than or equal to the current Interrupt Exception processing begins before 1 processor priority, execution continues Illegal the next instruction with the next instruction and the interrupt Privilege exception processing is postponed. (The TRAP, TRAPV, recognition of level seven is slighly dif- Exception processing is started by 2 CHK, ferent, as explained in a following para- normal instruction execution Zero Divide graph.)

If the priority of the pending interrupt is greater than the current processor priority, the exception processing sequence is 4 started. First a copy of the status register is saved, and the privilege state is set to PROCESSOR INTERRUPTING DEVICE supervisor, tracing is suppressed, and the processor priority level is set to the level of the interrupt being acknowledged. The Request Interrupt processor fetches the vector number from the interrupting device, classifying the reference as an interrupt acknowledge and displaying the level number of the interrupt being acknowledged on the ad- Grant Interrupt dress bus. If external logic requests an 11 Compare interrupt level in status register automatic vectoring, the processor inter- and wait for current instruction to complete nally generates a vector number which is 21 Place interrupt level on Al, A2, A3 determined by the interrupt level number. 3) Set R/VV to read If external logic indicates a bus error, the 41 Set function code to interrupt acknowledge interrupt is taken to be spurious, and the 5) Assert address strobe IASI generated vector number references the 61 Assert lower data strobe ILDS) spurious interrupt vector. The processor then proceeds with the usual exception processing, saving the program counter and status register on the supervisor Provide Vector Number stack. The saved value of the program 1) Place vector number of D0-D7 counter is the address of the instruction 2) Assert data transfer acknowledge IDTACKI which would have been executed had the interrupt not been present. The content of the interrupt vector whose vector number was previously obtained is fetched and loaded into the program counter, and nor- Acquire Vector Number mal instruction execution commences in the interrupt handling routine. A flow 1) Latch vector number 2) Negate LDS chart for the interrupt acknowledge se- 3) Negate AS quence is given in figure 28, a timing diagram is given in figure 29 and the interrupt exception timing sequence is shown in figure 30.

Release Priority level seven is a special case. Level 1) Negate DTACK seven interrupts cannot be inhibited by the interrupt priority mask, thus providing a `non-maskable interrupt' capability. An interrupt is generated each time the interrupt request level changes from some Start Interrupt Processing lower level to level seven. Note that a level seven interrupt may still be caused by the level comparison if the request level is a Figure 28. Interrupt Acknowledge Sequence Flow Chart seven and the processor is set to a lower level by an instruction.

Signetics 4.21 MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

CLK A4-A23 )-( A1-A3 >-( AS \ / UDS

LDS

DTACK

D8 D15 ( >--\r

DO-D7--‹ >-----N < i>---

FCO-2 \

IPLO-2

Last Bus Cycle of Instruction Stack IACK Cycle Stack and (Read or Write) PCL (Vector Number Acquisition) Vector Fetch Itt F ISSPI >ir(

Figure 29. Interrupt Acknowledge Sequence Timing Diagram

Last Bus Cycle IACK of Instruction Stack Stack Stack Cycle (During Which PCL Status PCH (Vector Number Interrupt Was ISSPI ISSPI ISSPI Acquisition) Recognized)

Read Read Fetch First Word Vector -711. Vector of Instruction High Low of Interrupt (A16-A23) (AO-A15) Routine

Figure 30. Interrupt Exception Timing Sequence

4-22 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

Uninitialized Interrupt — An interrupting STOP the processor was not between instruc- device asserts VPA or provides an inter- RESET tions when the bus error exception re- rupt vector during an interrupt acknowl- RTE quest was made, the context of the pro- edge cycle to the SCN68000. If the vector MOVE to SR cessor is more detailed. To save more of register has not been initialized, the re- AND (word) immediate to SR this context, additional information is sponding SCN68000 family peripheral will EOR (word) immediate to SR saved on the supervisor stack. The pro- provide vector 15, the uninitialized inter- OR (word) immediate to SR gram counter and the copy of the status rupt vector. This provides a uniform way to MOVE USP register are of course saved. The value recover from a programming error. saved for the program counter is advanced Tracing — To aid in program development, by some amount, two to ten bytes beyond Spurious Interrupt — If during the inter- the SCN68000 includes a facility to allow the address of the first word of the in- rupt acknowledge cycle no device re- instruction by instruction tracing. In the struction which made the reference caus- sponds by asserting DTACK or VPA, the trace state, after each instruction is ex- ing the bus error. If the bus error occurred bus error line should be asserted to ter- ecuted, an exception is forced allowing a during the fetch of next instruction, the minate the vector acquisition. The pro- debugging program to monitor the execu- saved program counter has a value in the cessor separates the processing of this er- tion of the program under test. vicinity of the current instruction, even if ror from the bus error by fetching the The trace facility uses the T-bit in the the current instruction is a branch, a jump 4 spurious interrupt vector instead of the supervisor portion of the status register. If or a return instruction. Besides the usual bus error vector. The processor then pro- the T-bit is negated (off), tracing is dis- information, the processor saves its inter- ceeds with the usual exception process- abled and instruction execution proceeds nal copy of the first word of the instruc- ing. from instruction to instruction as normal. tion being processed, and the address If the T-bit is asserted (on) at the begin- which was being accessed by the aborted Instruction Traps — Traps are exceptions ning of the execution of an instruction, a bus cycle. Specific information about the caused by instructions. They arise either trace exception will be generated after the access is also saved: whether it was a read from processor recognition of abnormal execution of that instruction is com- or a write, whether the processor was pro- conditions during instruction execution, pleted. If the instruction is not executed, cessing an instruction or not, and the clas- or from use of instructions whose normal either because an interrupt is taken, or the sification displayed on the function code behavior is trapping. instruction is illegal or privileged, the outputs when the bus error occurred. The processor is processing an instruction if it Some instructions are used specifically to trace exception does not occur. The trace is in the normal state or processing a generate traps. The TRAP instruction exception also does not occur if the in- group 2 exception; the processor is not always forces an exception, and is useful struction is aborted by a reset, bus error, processing an instruction if it is process- for implementing system calls for user or address error exception. If the instruc- ing a group 0 or group 1 exception. Figure programs. The TRAPV and CHK instruction is indeed executed and an interrupt is 31 illustrates how this information is orga- tions force an exception if the user pro- pending on completion, the trace excep- nized on the supervisor stack. Although gram detects a runtime error, which may tion is processed before the interrupt ex- this information is not sufficient in gen- be an arithmetic overflow or a subscript ception. If, during the execution of the in- eral to effect full recovery from the bus out of bounds. The signed divide (DIVS) struction, an exception is forced by that error, it does allow software diagnosis. and unsigned divide (DIVU) instructions instruction, the forced exception is pro- Finally, the processor commences in- will force an exception if a division opera- cessed before the trace exception. struction processing at the address con- tion is attempted with a divisor of zero. As an extreme illustration of the above tained in the vector. It is the responsibility rules, consider the arrival of an interrupt of the error handler routine to clean up the Illegal and Unimplemented Instructions — during the execution of a TRAP instruc- stack and determine where to continue Illegal instruction is the term used to refer tion while tracing is enabled. First the trap execution. to any of the word bit patterns which are exception is processed, then the trace ex- not the bit pattern of the first word of a ception, and finally the interrupt excep- If a bus error occurs during the exception legal instruction. During instruction ex- tion. Instruction execution resumes in the processing for a bus error, address error, ecution, if such an instruction is fetched, interrupt handler routine. or reset, the processor is halted, and all an illegal instruction exception occurs. processing ceases. This simplifies the Bus error exceptions occur detection of catastrophic system failure, Word patterns with bits 15 through 12 Bus Error — since the processor removes itself from equaling 1010 or 1111 are distinguished as when external logic requests that a bus the system rather than destroying all unimplemented instructions and separate error be processed by an exception. The memory contents. Only the RESET pin can exception vectors are given to these pat- current bus cycle which the processor is restart a halted processor. terns to permit efficient emulation. This making is then aborted. Whether the pro- facility allows the operating system to cessor was doing instruction or exception detect program errors, or to emulate processing, that processing is terminated, Address Error unimplemented instructions in software. and the processor immediately begins ex- Address error exceptions occur when the ception processing. processor attempts to access a word or a Privilege Violations — In order to provide Exception processing for bus error long word operand or an instruction at an system security, various instructions are follows the usual sequence of steps. The odd address. The effect is much like an in- privileged. An attempt to execute one of status register is copied, the supervisor ternally generated bus error, so that the the privileged instructions while in the state is entered, and the trace state is bus cycle is aborted, and the processor user state will cause an exception. The turned off. The vector number is gener- ceases whatever processing it is currently privileged instructions are: ated to refer to the bus error vector. Since doing and begins exception processing. Signetics 4.23 MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Lower Address R/W I/N Function Code

High — — Access Address — - Low

Instruction Register

Status Register

High -- Program Counter - - Low

R/W (read/write): write= 0, read= 1. I/N (instruction/not): instruction= 0, not= 1

Figure 31. Supervisor Stack Order

SO S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 S5

CLK Al-A23 AS UDS LDS

R/7)1- DTACK

DO-D15

Aerr Approx. 8 Clocks Read tvi Write Stack Write Idle

Figure 32. Address Error Timing

After exception processing commences, chronous cycle requirements whenever a The synchronous cycle timing diagrams the sequence is the same as that for bus synchronous device address is detected. and corresponding AC electrical charac- error including the information that is Figure 33 is a flow chart of the interface teristics table are located towards the end stacked, except that the vector number operation between the processor and syn- of this data sheet. At state zero (SO) in the refers to the address error vector instead. chronous devices. cycle, the address bus and function codes Likewise, if an address error occurs during are in the high-impedance state. One half the exception processing for a bus error, Data Transfer Operation clock later, in state 1, the address bus and address error, or reset, the processor is Three signals on the processor provide function code outputs are released from halted. As show in figure 32, an address the synchronous interface. They are: the high-impedance state. error will execute a short bus cycle fol- enable (E), valid memory address (VMA), During state 2, the address strobe (AS) is lowed by exception processing. and valid peripheral address (VPA). The asserted to indicate that there is a valid bus frequency is one tenth of the incom- address on the address bus. If the bus INTERFACE WITH SYNCHRO- ing SCN68000 clock frequency. Enable cycle is a read cycle, the upper and/or NOUS PERIPHERALS has a 60/40 duty cycle; that is, it is low for lower data strobes are also asserted in six input clocks and high for four input state 2. If the bus cycle is a write cycle, the To interface synchronous peripherals with clocks. This duty cycle allows the pro- read/write (R/W) signal is switched to low the asynchronous SCN68000, the proces- cessor to do successive VPA accesses on (write) during state 2. One half clock later, sor modifies its bus cycle to meet the syn- successive E pulses. in state 3, the write data is placed on the

4.24 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

During a read cycle, the processor latches the peripheral data in state 6. For all cycles, the processor negates the address PROCESSOR SLAVE and data strobes one half clock cycle later Initiate Cycle in state 7, and the enable signal goes low 11 The processor starts a normal Read or at this time. Another half clock later, the Write cycle address bus is put in the high-impedance state. During a write cycle, the data bus is put in the high-impedance state and the read/write signal is switched high at this Define Synchronous Cycle time. The peripheral logic must remove 11 External hardware asserts Valid Peripheral VPA within one clock after address strobe Address (VPA) is negated. DTACK should not be asserted while VPA is asserted. The SCN68000 VMA is active low, while the VMA of the synchronous device should be active high. This allows Synchronize With Enable the processor to put its buses in the high- 11 The processor monitors Enable IEI until it is impedance state on DMA requests with- low (Phase 1) out inadvertently selecting peripherals. 2) The processor asserts Valid Memory Ad- dress (VMA) Interrupt Operation During an interrupt acknowledge cycle while the processor is fetching the vector, if VPA is asserted, the SCN68000 will as- Transfer Data sert VMA and complete a synchronous 1) The peripheral waits until E is active and read cycle as shown in figure 34. The pro- then transfers the data cessor will then use an internally generated vector that is a function of the interrupt being serviced. This process is known as autovectoring. The seven auto- vectors are vector numbers 25 through 31 (decimal). Terminate Cycle There are six normal interrupt vectors and 11 The processor waits until E goes low. (On a Read cycle the data is latched as E goes one NMI type vector. As with the low internally) SCN68000's normal vectored interrupt, the 21 The processor negates VMA interrupt service routine can be located 31 The processor negates AS, UDS, and LDS anywhere in the address space. This is due to the fact that while the vector numbers are fixed, the contents of the vector table entries are assigned by the user. Start Next Cycle Since VMA is asserted during autovectoring, the synchronous peripheral address Figure 33. Synchronous Interfacing Flow Chart decoding should prevent unintended accesses.

data bus, and in state 4 the data strobes After the recognition of VPA, the pro DATA TYPES AND ADDRESSING are issued to indicate valid data on the cessor assures that enable (E) is low, by MODES data bus. waiting if necessary, and subsequently Five basic data types are supported: asserts VMA. Valid memory address is The processor now inserts wait states un- then used as part of the chip select equa- • Bits til it recognizes the assertion of VPA. The tion of the peripheral. This ensures that • BCD digits (8-bits) VPA input signals the processor that the the synchronous peripherals are selected • Bytes (8-bits) address on the bus is the address of a syn- and deselected at the correct time. The • Word (16-bits) chronous device (or an area reserved for peripheral now runs its cycle during the • Long words (32-bits) synchronous devices) and that the bus high portion of the E signal. Cycle timing should conform to the synchronous trans- diagrams depicting best and worst cases In addition, operations on other data types fer characteristics of the synchronous are located towards the end of this data such as memory addresses, status word bus. Valid peripheral address is derived by sheet. The cycle length is dependent data, etc. are provided for in the instruc- decoding the address bus, conditioned by strictly on when VPA is asserted in relation set. The 14 addressing modes (see the address strobe. tionship to the E clock. table 9) include six basic types:

Signetics 4-25 MICROPROCESSOR DIVISION JANUARY 1983

416-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

SO S2 S4 S6 SO S2 S4 w w w w w w w w w w S6 SO S2 CLK

A1-A3 A4-A23 AS

UDS LDS

R/W

DTACK

D8-D15

DO-D7 FCO-2 Nc_

VPA

V MA

Fr... Normal —Autovector Operation— — — — Cycle

Figure 34. Autovector Operation Timing

• Register direct Program/Data References Implicit reference — the definition of • Register indirect certain instructions implies the use of The SCN68000 separates memory refer- • Absolute ences into two classes: program refer- specific registers. • Immediate ences and data references. Program refer- • Program counter relative ences, as the name implies, are references Register Specification • Implied to that section of memory that contains The register field within an instruction Included in the register indirect address- the program being executed. Data refer- specifies the register to be used. Other ing modes is the capability to do post- ences refer to that section of memory that fields within the instruction specify incrementing, pre-decrementing, offset. contains data. Generally, operand reads whether the register selected is an ad- ting and indexing. Program counter rela- are from the data space. All operand dress or data register and how the register tive mode can also be modified via index- writes are to the data space. is to be used. ing and offsetting. Addressing Effective Address Instruction Format Instructions for the SCN68000 contain two kinds of information; the type of function Most instructions specify the location of Instructions are from one to five words in to be performed and the location of the an operand by using the effective address length, a shown in figure 35. The length of operand(s) on which to perform the func- field in the operation word. For example, the instruction and the operation to be tion. Instructions specify an operand loca- figure 36 shows the general format of the performed are specified by the first word tion in one of three ways: single effective address instruction opera- of the instruction which is called the tion word. The effective address is com- operation word. The remaining words fur- Register specification — the number of posed of two 3-bit fields: the mode field, ther specify the operands. These words the register is given in the register field and the register field. The value in the are either immediate operands or exten- of the instruction. mode field selects the different address sions to the effective address modes Effective address — use of the different modes. The register field contains the specified in the operation word. effective address modes. number of a register.

4.26 Signetics MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

Table 9 DATA ADDRESSING MODES The effective address field may require additional information to fully specify the Mode Generation operand. This additional information, Register Direct Addressing called the effective address extension, is Data Register Direct EA= Dn contained in a following word or words Address Register Direct EA= An and is considered part of the instruction, Absolute Data Addressing as shown in figure 35. The effective ad- Absolute Short EA= (Next Word) dress modes are grouped into three cate- Absolute Long EA= (Next Two Words) gories: register direct, memory addressing, and special. Program Counter Relative Addressing Relative with Offset EA = (PC) + d16 Relative with Index and Offset EA= (PC1+ (Xnl+dg Register Direct Modes Register Indirect Addressing These effective addressing modes specify Register Indirect EA = (An) that the operand is in one of the 16 multi Postincrement Register Indirect EA = (An), An ..— An + N function registers. Predecrement Register Indirect An 4—i An—N, EA= lAn) Register Indirect with Offset EA=1,An)+d16 Data Register Direct — The operand is in Indexed Register Indirect with Offset EA= (An)+ (Xn1+ dg the data register specified by the effective Immediate Data Addressing address register field. Immediate DATA= Next Wordlsl Quick Immediate Inherent Data Address Register Direct — The operand is in the address register specified by the Implied Addressing effective address register field. Implied Register EA=SR, USP, SP, PC NOTES: Memory Address Modes EA = Effective Address dg= Eight-bit Offset An= Address Register (displacement) These effective addressing modes specify Dn= Data Register diig= Sixteen-bit Offset that the operand is in memory and provide Xn= Address or Data Register used (displacement) • the specific address of the operand. as Index Register N=1 for Byte, 2 for SR = Status Register Words and 4 for Long Address Register Indirect — The address PC= Program Counter Words • of the operand is in the address register I 1= Contents of = Replaces specified by the register field. The reference is classified as a data reference with the exception of the jump and jump to subroutine instructions.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Operation Word (First Word Specifies Operation and Modes) Immediate Operand (If Any, One or Two Words) Source Effective Address Extension (If Any, One or Two Words) Destination Effective Address Extension (If Any, One or Two Words)

Figure 35. Instruction Format

15 14 13 12 11 10 9 8 7 6 5 3 2 1 0 Effective Address X X X X X X X X X X Mode I Register

Figure 36. Single Effective Address Instruction Operation Word General Format

Signetics 4.27 MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

Address Register Indirect with Postincre- Absolute Long Address — This address Byte operation — operand is low order ment — The address of the operand is in mode requires two words of extension. byte of extension word. the address register specified by the reg- The address of the operand is developed Word operation — operand is extension ister field. After the operand address is by the concatenation of the extension word. used, it is incremented by one, two, or four words. The high-order part of the address depending on whether the size of the oper- is the first extension word; the low order Long word operation — operand is in and is byte, word, or long word. If the ad- part of the address is the second exten- the two extension words, high-order 16 dress register is the stack pointer and the sion word. The reference is classified as a bits are in the first extension word, low- operand size is byte, the address is in- data reference with the exception of the order 16 bits are in the second exten- cremented by two rather than one to keep jump and the jump to subroutine instruc- sion word. the stack pointer on a word boundary. The tions. Condition Codes or Status Register — A reference is classified as a data reference. selected set of instructions may reference Program Counter with Displacement — the status register by means of the effec- Address Register Indirect with Predecre- This address mode requires one word of tive address field. These are: ment — The address of the operand is in extension. The address of the operand is ANDI to CCR the address register specified by the reg- the sum of the address in the program ister field. Before the operand and the ad- counter and the sign-extended 16-bit ANDI to SR EORI to SR dress is used, it is decremented by one, displacement integer in the extension ORI to CCR two or four depending on whether the word. The value in the program counter is ORI to SR operand size is byte, word, or long word. If the address of the extension word. The the address register is the stack pointer reference is classified as a program and the operand size is byte, the address reference. Effective Address Encoding is decremented by two rather than one to Summary keep the stack pointer on a word bound- Program Counter with Index — This ad- Table 10 is a summary of the effective ad- ary. The reference is classified as a data dress mode requires one word of exten- dressing modes. reference. sion. The address is the sum of the address in the program counter, the sign- Address Register Indirect with Displace- extended displacement integer in the Implicit Reference ment — This address mode requires one lower eight bits of the extension word, and Some instructions make implicit refer- word of extension. The address of the the contents of the index register. The ence to the program counter (PC), the operand is the sum of the address in the value in the program counter is the ad- system stack pointer (SP), the supervisor address register and the sign-extended dress of the extension word. This refer- stack pointer (SSP), the user stack pointer 16-bit displacement integer in the exten- ence is classifed as a program reference. (USP), or the status register (SR). sion word. The reference is classified as a data reference with the exception of the Immediate Data — This address mode jump and jump to subroutine instructions. requires either one or two words of exten- System Stack sion depending on the size of the opera- The system stack is used implicitly by Address Register Indirect with Index — tion. many instructions; user stacks and This address mode requires one word of extension. The address of the operand is the sum of the address in the address register, the sign-extended displacement Table 10 EFFECTIVE ADDRESS ENCODING SUMMARY integer in the low order eight bits of the extension word, and the contents of the Addressing Mode Mode Register index register. The reference is classified Data Register Direct 000 register number as a data reference with the exception of Address Register Direct 001 register number the jump and jump to subroutine instruc- Address Register Indirect 010 register number tions. Address Register Indirect with Special Addressing Modes Postincrement 011 register number Address Register Indirect with The special address modes use the effec- Predecrement 100 register number tive address register field to specify the special addressing mode instead of a reg- Address Register Indirect with ister number. Displacement 101 register number Address Register Indirect with Absolute Short Address — This address Index 110 register number mode requires one word of extension. The Absolute Short 111 000 address of the operand is in the extension Absolute Long 111 001 word. The 16-bit address is sign extended Program Counter with before it is used. The reference is classi- Displacement 111 010 fied as a data reference with the exception Program Counter with Index 111 011 of the jump and jump to subroutine instructions. Immediate 111 100

4.28 Signetics MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary queues may be created and maintained INSTRUCTION SET OVERVIEW types, data types, and addressing modes, through the addressing modes. Address over 1000 useful instructions are provided. register seven (A7) is the stack pointer The SCN68000 instruction set is summa- These instructions include signed and un- (SP). The SP is either the SSP or the USP, rized in table 11. Some additional instruc- signed multiply and divide, `quick' arith- depending on the state of the S-bit in the tions are variations, or subsets, of these metic operations, BCD arithmetic and ex- status register. If the S-bit indicates and appear in table 12. Special emphasis panded operations (through traps). supervisor state, SSP is the active system has been given to the instruction set's stack pointer, and the USP cannot be support of structured high-level languages The instructions form a set of tools that in- referenced as an address register. If the to facilitate ease of programming. Each include all machine functions to perform the S-bit indicates user state, the USP is the struction, with few exceptions, operates following operations: active system stack pointer, and the SSP on bytes, words, and long words, and cannot be referenced. Each system stack most instructions can use any of the 14 Data movement fills from high memory to low memory. addressing modes. Combining instruction Integer arithmetic

Table 11 INSTRUCTION SET SUMMARY Mnemonic Description Mnemonic Description Mnemonic Description ABCD Add Decimal with Extend EOR Exclusive Or PEA Push Effective Address ADD Add EXG Exchange Registers RESET Reset External Devices AND Logical And EXT Sign Extend ROL Rotate Left without Extend ASL Arithmetic Shift Left JMP Jump ROR Rotate Right without Extend ASR Arithmetic Shift Right JSR Jump to Subroutine ROXL Rotate Left with Extend BCC Branch Conditionally LEA Load Effective Address ROXR Rotate Right with Extend BCHG Bit Test and Change LINK Link Stack RTE Return from Exception BCLR Bit Test and Clear LSL Logical Shift Left RTR Return and Restore BRA Branch Always LSR Logical Shift Right RTS Return from Subroutine BSET Bit Test and Set MOVE Move SBCD Subtract Decimal with Extend BSR Branch to Subroutine MOVEM Move Multiple Registers SCC Set Conditional BTST Bit Test MOVEP Move Peripheral Data STOP Stop CHK Check Register Against Bounds MULS Signed Multiply SUB Subtract CLR Clear Operand MULU Unsigned Multiply SWAP Swap Data Register Halves CMP Compare NBCD Negate Decimal with Extend TAS Test and Set Operand DBCC Test Condition, Decrement and NEG Negate TRAP Trap Branch NOP No Operation TRAPV Trap on Overflow DIVS Signed Divide NOT One's Complement TST Test DIVU Unsigned Divide OR Logical Or UNLK Unlink

Table 12 VARIATIONS OF INSTRUCTION TYPES

Instruction Instruction Variation Description Variation Description Type Type ADD ADD Add MOVE MOVE Move ADDA Add Address MOVEA Move Address ADDQ Add Quick MOVEQ Move Quick ADDI Add Immediate MOVE from SR Move from Status Register ADDX Add with Extend MOVE to SR Move to Status Register AND AND Logical And MOVE to CCR Move to Condition Codes ANDI And Immediate MOVE USP Move User Stack Pointer CMP CMP Compare NEG NEG Negate CM PA Compare Address NEGX Negate with Extend CMPM Compare Memory OR OR Logical Or CMPI Compare Immediate ORI Or Immediate EOR EOR Exclusive Or SUB SUB Subtract EORI Exclusive Or Immediate SUBA Subtract Address SUBI Subtract Immediate SUBQ Subtract Quick SUBX Subtract with Extend Signetics 4.29 MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

Logical Table 13 DATA MOVEMENT OPERATIONS Shift and rotate Instruction Operand Size Bit manipulation Operation Binary coded decimal EXG 32 Rx.-.Ry Program control LEA 32 EA-.An System control An --.SP@- The complete range of instruction capa- LINK SP-.An bilities, combined with the variety of ad- SP+d-.SP dressing modes described previously, pro- MOVE 8, 16, 32 (EAls -.. EAd vide a very flexible base for program lEA1--. An, Dn MOVEM 16, 32 development. An, Dn --. EA (EAI-.Dn MOVEP 16, 32 Data Movement Operations Dn-` EA The basic method of data acquisition MOVEQ 8 #xxx-.Dn (transfer and storage) is provided by the PEA 32 EA- SP@ - move (MOVE) instruction. The move in- SWAP 32 Dn[31:161 Dn[15:01 struction and the effective addressing modes allow both address and data An -* Sp UNLK SP@ + -.An manipulation. Data move instructions NOTES: allow byte, word, and long word operands s= source @ - = indirect with predecrement to be transferred from memory to memory, d= destination @+ = indirect with postdecrement memory to register, register to memory, 1= bit numbers and register to register. Address move instructions allow word and long word operand transfers and ensure that only legal address manipulations are executed. tended (SUBX), sign extended (EXT), and Bit Manipulation Operations In addition to the general move instruc- negate binary with extend (NEGX). tion, there are several special data move- Bit manipulation operations are accom- A test operand (TST) instruction that will ment instructions: move multiple register plished using bit test (BTST), bit test and set the condition codes as a result of a (MOVEM), move peripheral data (MOVEP), set (BSET), bit test and clear (BCLR), and compare of the operand with zero is avail- exchange registers (EXG), load effective bit test and change (BCHG). Table 17 is a able. Test and set (TAS) is a synchroniza- address (LEA), push effective address summary of the bit manipulation operation instruction useful in multiprocessor (PEA), link stack (LINK), unlink stack tions (bit 2 of the status register is Z). systems. Table 14 is a summary of the in- (UNLK), and move quick (MOVEQ). Table teger arithmetic operations. 13 is a summary of the data movement operations. Binary Coded Decimal Logical Operations Operations Integer Arithmetic Operations Logical operation instructions AND, OR, Multiprecision arithmetic operations on The arithmetic operations include the four EOR, and NOT are available for all sizes of binary coded decimal numbers are ac- basic operations of add (ADD), subtract integer data operands. A similar set of complished using add decimal with ex- (SUB), multiply (MUL), and divide (DIV) as immediate instructions (ANDI, ORI, and tend (ABCD), subtract decimal with extend well as arithmetic compare (CMP), clear EORI) provide these logical operations (SBCD), and negate decimal with extend (CLR), and negate (NEG). The add and sub- with all sizes of immediate data. Table 15 (NBCD). Table 18 is a summary of the tract instructions are available for both ad- is a summary of the logical operations. binary coded decimal operations. dress and data operations, with data operations accepting all operand sizes. Shift and Rotate Operations Address operations are limited to legal ad- Program Control Operations Shift operations in both directions are pro- dress size operands (16 or 32 bits). Data, Program control operations are accom- vided by the arithmetic instructions ASR address, and memory compare operations plished using a series of conditional and and ASL and logical shift instructions LSR are also available. The clear and negate in- unconditional branch instructions and and LSL. The rotate instructions (with and structions can be used on all sizes of data return instructions (see table 19). The con- without extend) available are ROXR, operands. ditional instructions provide setting and ROXL, ROR, and ROL. All shift and rotate The multiply and divide operations are branching for the following conditions: operations can be performed in either available for signed and unsigned oper- registers or memory. Register shifts and CC-carry clear ands using word multiply to produce a rotates support all operand sizes and CS-carry set long word product, and a long word divi- allow a shift count specified in the instruc- EQ-equal dend with word divisor to produce a word tion of one to eight bits, or 0 to 63 F-never true quotient with a word remainder. specified in a data register. Memory shifts GE-greater or equal Multiprecision and mixed size arithmetic and rotates are for word operands only GT-greater than can be accomplished using a set of ex- and allow only single-bit shifts or rotates. HI-high tended instructions. These instructions Table 16 is a summary of the shift and LE-less or equal are: add extended (ADDX), subtract ex- rotate operations. LS-low or same

4.30 Signetics MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

LT-less than Table 15 LOGICAL OPERATIONS MI-minus Instruction Operand Size Operation NE-not equal PL-plus DnAlEA) --• Dn T-always true AND 8, 16, 32 (EA)ADn -. EA VC-no overflow (EA)A#xxx-ti EA VS-overflow Dn v (EAI-it Dn OR 8, 16, 32 IEAI v Dn-EA System Control Operations (EA) v #xxx -. EA (EA) a Dy--. EA System control operations are accom- EOR 8, 16, 32 plished by using priviledged instructions, (EA) e #xxx -. EA trap generating instructions, and instruc- NOT 8, 16, 32 - (EAl•-•: EA tions that use or modify the status regis- NOTE: - = invert ter. These instructions are summarized in table 20.

INSTRUCTION SET Table 16 SHIFT AND ROTATE OPERATIONS Instruc.. Operand The following provides information about Operation tion Size the addressing categories and instruction set of the SCN68000. ASL 8, 16, 32 X/C < 14-0 Addressing Categories ASR 8, 16, 32 > X/C Effective address modes can be categorized by the ways in which they may be LSL 8, 16, 32 X/C 4 }4-0

LSR 8, 16, 32 0 > X/C

Table 14 INTEGER ARITHMETIC OPERATIONS ROL 8, 16, 32 C t1-4-1 Instruction Operand Size Operation 8, 16, 32 Dn + (EN -. Dn ROR 8, 16, 32 > C (EAI+ Dn --. EA ADD (EAI+ #xxx:-. EA ROXL 8, 16, 32 C < X 16, 32 An + (EA) --. An 8, 16, 32 Dx+Dy+X-.Dx ADDX ROXR 8, 16, 32 X > C 16, 32 Ax@- Ay@ - + X --. Ax@ CLR 8, 16, 32 0-EA 8, 16, 32 On - (EA) (EA)-#xxx CMP Table 17 BIT MANIPULATION OPERATIONS Ax@+ - Ay@ + 16, 32 An - (EA) Instruction Operand Size Operation DIVS 32+16 Dn/IEA)-On BTST 8, 32 -bit of (EA)-fiZ DIVU 32+16 Dn/(EA) -.Dn -bit of (EA)-`Z BSET 8, 32 1- bit of EA 8-.16 (Dn18- EXT ' Dn16 16-.32 (Dn)16--x Dn32 -bit of (EA)-.Z BCLR 8, 32 MULS 16'16-.32 Dn'(EA)--x Dn 0-bit of EA -bit of (EA)--. Z MULU 16'16-.32 Dn'IEA) --. Dn BCHG 8, 32 -bit of IEA)--'bit of EA NEG 8, 16, 32 0- (EA) --x EA NEGX 8, 16, 32 0- (EA) - X- EA 8, 16, 32 Dn- (EA)-fi Dn (EA) - Dn -.: EA Table 18 BINARY CODED DECIMAL OPERATIONS SUB (EA) - #xxx:-. EA Operand 16, 32 An- (EA) --fi An Instruction Operation Size Dx-Dy- X -. Dx SUBX 8, 16, 32 Dx10+ Dm+ X-. Dx Ax@ - - Ay@ - - X •-• Ax@ ABCD 8 Ax@ - 10+ Ay@ - 10 + X-• Ax@ TAS 8 (EA) - 0, 1 --ti EA[7] Dx10 - DM- X -"Dx TST 8, 16, 32 (EA) - 0 SBCD 8 Ax@ - 10- Ay@ -10 - X-Ax@ NBCD 8 0- (EA)10 -. EA NOTE: 1= bit number - X Signetics 4.31 MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary used. The following classifications are 3. The last fetch from the instruction 5. The program counter usually points to used in the instruction definitions: stream is made when the operation the last word fetched from the instruc- word is discarded and decoding is tion stream. Data If an effective address mode started on the next instruction. may be used to refer to data operands, it is considered a 4. If the instruction is a single word in- data addressing effective ad- struction causing a branch, the second INSTRUCTION EXECUTION dress mode. word is not used. But because this TIMES word is fetched by the preceding in- Memory If an effective address mode The following contains listings of the instruction, it is impossible to avoid this may be used to refer to memory struction execution times in terms of the superfluous fetch. In the case of an in- operands, it is considered a external clock (CLK) periods. In this timing terrupt or trace exception, both words memory addressing effective data, it is also assumed that the memory are not used. address mode. cycle time is no greater than four periods Alterable If an effective address mode may be used to refer to alterable (writable) operands, it is con- Table 19 PROGRAM CONTROL OPERATIONS sidered an alterable addressing Instruction Operation effective address mode. Conditional Control If an effective address mode BCC Branch conditionally (14 conditions/ may be used to refer to memory 8- and 16-bit displacement operands without an associated DBCC Test condition, decrement, and branch size, it is considered a control 16-bit displacement addressing effective address mode. SCC Set byte conditionally (16 conditions/ Unconditional Table 21 shows the various categories to which each of the effective address BRA Branch always modes belongs. Table 22 shows the in- 8- and 16-bit displacement struction set. BSR Branch to subroutine 8- and 16-bit displacement The status register addressing mode is JMP Jump not permitted unless it is explicitly mentioned as a legal addressing mode. JSR Jump to subroutine Returns These categories may be combined, so that additional, more restrictive, classifi- RTR Return and restore condition codes cations may be defined. For example, the RTS Return from subroutine instruction descriptions use such classifications as alterable memory or data alterable. The former refers to those address- Table 20 SYSTEM CONTROL OPERATIONS ing modes which are both alterable and memory addresses, and the latter refers to Instruction Operation addressing modes which are both data Privileged and alterable. RESET Reset external devices Instruction Prefetch RTE Return from exception STOP Stop program execution The SCN68000 uses a two word tightly coupled instruction prefetch mechanism ORI to SR Logical OR to status register to enhance performance. This mechanism MOVE USP Move user stack pointer is described in terms of the microcode ANDI to SR Logical AND to status register operations involved. If the execution of an EORI to SR Logical EOR to status register instruction is defined to begin when the MOVE EA to SR Load new status register microroutine for that instruction is entered, some features of the prefetch Trap Generating mechanism can be described. TRAP Trap 1. When execution of an instruction TRAPV Trap on overflow begins, the operation word and the CHK Check register against bounds word following have already been Status Register fetched. The operation word is in the in- ANDI to CCR Logical AND to condition codes struction decoder. EORI to CCR Logical EOR to condition codes 2. In the case of multiword instructions, MOVE EA to CCR Load new condition codes as each additional word of the instruc- ORI to CCR Logical OR to condition codes tion is used internally, a fetch is made MOVE SR to EA Store status register to the instruction stream to replace it.

4-32 Signetics MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary Table 21 EFFECTIVE ADDRESSING MODE CATEGORIES Effective Addressing Categories Address Modes Mode Register Data Memory Control Alterable Dn 000 register number X X An 001 register number — X An@ 010 register number X X X X An@ + 011 register number X X X An@ — 100 register number X X X An@id) 101 register number X X X X An@id, ix) 110 register number X X X X xxx.W 111 000 X X X X xxx.L 111 001 X X X X PC@(d) 111 010 X X X PC@Id, ix) 111 011 X X X #xxx 111 100 X X

of the external processor clock input, must be added to those of the effective ad- tions. The number of bus read and write which prevents the insertion of wait states dress calculated where indicated. cycles is shown in parenthesis as (r/w). in the bus cycle. The number of bus read In table 26, the headings have the follow- The number of clock periods plus the and write cycles for each instruction is ing meanings: An = address register oper- number of read and write cycles must be also included with the timing data. This and, Dn = data register operand, ea= an added to those of the effective address data is enclosed in parenthesis following operand specified by an effective address, calculation where indicated. the execution periods and is shown as and M = memory effective address oper- (r/w), where r is the number of read cycles and. and w is the number of write cycles. The Bit Manipulation Instruction number of periods includes instruction Immediate Instruction Clock Clock Periods fetch and all applicable operand fetches Periods and stores. Table 30 indicates the number of clock The number of clock periods shown in periods for the bit manipulation instruc- Effective Address Operand table 27 includes the time to fetch immedi- tions. The number of bus read and write Calculation Timing ate operands, perform the operations, cycles is shown in parenthesis as (r/w). store the results, and read the next opera- The number of clock periods plus the Table 23 lists the number of clock periods tion. The number of bus read and write number of read and write cycles must be required to compute an instruction's ef- cycles is shown in parenthesis as (r/w). added to those of the effective address fective address. It includes fetching of any The number of clock periods plus the calculation where indicated. extension words, the address computa- number of read and write cycles must be tion, and fetching the memory operand. added to those of the effective address The number of bus read and write cycles is calculation where indicated. Conditional Instruction Clock shown in parenthesis as (r/w). Note that there are no write cycles involved in pro- In table 27, the headings have the follow- Periods ing meanings: # immediate operand, cessing the effective address. Table 31 indicates the number of clock Dn = data register operand, M = memory periods required for the conditional in- operand, and SR = status register. Move Instruction Clock Periods structions. The number of bus read and Table 24 and 25 indicate the number of write cycles is shown in parenthesis as Single Operand Instruction Clock (r/w). The number of clock periods plus the clock periods for the move instruction. Periods This data includes fetch, operand reads, number of read and write cycles must be and operand writes. The number of bus Table 28 indicates the number of clock added to those of the effective address read and write cycles is shown in paren- periods for the single operand instruc- calculation where indicated. thesis as (r/w). tions. The number of bus read and write cycles is shown in parenthesis as (r/w). Standard Instruction Clock The number of clock periods plus the JMP, JSR, LEA, PEA, MOVEM Periods number of read and write cycles must be Instruction Clock Periods added to those of the effective address The number of clock periods shown in calculation where indicated. Table 32 indicates the number of clock table 26 indicates the time required to per- periods required for the jump, jump to form the operations, store the results, and Shift/Rotate Instruction Clock subroutine, load effective address, push read the next instruction. The number of effective address, and move multiple reg- bus read and write cycles is shown in Periods isters instructions. The number of bus parenthesis as (r/w). The number of clock Table 29 indicates the number of clock read and write cycles is shown in paren- periods plus the number of read cycles periods for the shift and rotate instruc- thesis as (r/w). Signetics 4.33 MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

Table 22 INSTRUCTION SET

Condition Mnemonic Description Operation Codes XNZVC ABCD Add Decimal with Extend (Destinationlio+ (Source110-.Destination • U U • ADD Add Binary (Destination)+ (Source) -* Destination ADDA Add Address (Destination)+ (Source)-. Destination - - - - - ADDI Add Immediate (Destination)+ Immediate Data-.Destination • ADDQ Add Quick (Destination)+ Immediate Data-.Destination * ADDX Add Extended (Destination)+(Source)+X-.Destination • • AND AND Logical (Destination) A (Source)-.Destination - • 0 0 ANDI AND Immediate (Destination) A Immediate Data-. Destination 0 0 ASL, ASR Arithmetic Shift (Destination) Shifted by -.Destination BCC Branch Conditionally If CC then PC+ d-* PC ------(< bit number>) OF Destination-.Z BCHG Test a Bit and Change - l< bit number>) OF Destination-. - - • - - OF Destination -() OF Destination--.Z BCLR Test a Bit and Clear • - - 0-. -.OF Destination BRA Branch Always PC+d-.PC -() OF Destination-.Z BSET Test a Bit and Set - - * - - 1-. OF Destination BSR Branch to Subroutine PC -.SP@-; PC+d-.PC BTST Test a Bit - (< bit number>) OF Destination-.Z - - • - - CHK Check Register against Bounds If Dn <0 or Dn> 1 I then TRAP -•UUU CLR Clear an Operand 0— Destination - 0 1 0 0 CMP Compare (Destination) - (Source) CMPA Compare Address (Destination)-(Source) • • CMPI Compare Immediate (Destination)-Immediate Data - • CMPM Compare Memory (Destination)-(Source) - • DBCC Test Condition, Decrement and Branch If-CC then Dn- 1 -. Dn; if Dn*-1 then PC+ d-• PC - - - - - DIVS Signed Divide (Destination)/(Source)-.Destination DIVU Unsigned Divide (Destination)/(Source)-.Destination - • 0 EOR Exclusive OR Logical (Destination) e (Source)-. Destination - • * 0 0 EORI Exclusive OR Immediate (Destination)® Immediate Data-.Destination - • 0 0 EXG Exchange Register Rx.-.Ry - - - - - EXT Sign Extend (Destination) Sign-extended-.Destination 0 0 JMP Jump Destination-.PC JSR Jump to Subroutine PC -. SP@ - ; Destination -. PC - - - - - LEA Load Effective Address Destination-.An LINK Link and Allocate An-.SP@-; SP-•An; SP+ d-.SP LSL, LSR Logical Shift (Destination) Shifted by -.Destination MOVE Move Data from Source to Destination (Source)-.Destination - • 0 0 MOVE to CCR Move to Condition Code (Source)-'CCR • • • • MOVE to SR Move to the Status Register (Source)-. SR • affected 0 cleared U defined - unaffected 1 set

4.34 Signetics MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

Table 22 INSTRUCTION SET (Continued) Condition Mnemonic Description Operation Codes XNZVC MOVE from SR Move from the Status Register SR-- Destination — — — — — MOVE USP Move User Stack Pointer USP —.An; An USP — — — — — MOVEA Move Address (Source) —. Destination Registers —. Destination MOVEM Move Multiple Registers (Source)—. Registers MOVEP Move Peripheral Data (Source) —. Destination MOVEQ Move Quick Immediate Data —. Destination — • 0 0 MULS Signed Multiply (Destinationr (Source) —. Destination 0 0 MULU Unsigned Multiply (Destinationr(Source) —. Destination — • 0 0 NBCD Negate Decimal with Extend 0— (Destinationlio— X —. Destination • U U NEG Negate 0— (Destination)—. Destination NEGX Negate with Extend 0— (Destination) — X —. Destination NOP No Operation — — — — — NOT Logical Complement — (Destination) —. Destination — 0 0 OR Inclusive OR Logical (Destination) v (Source)—. Destination — • 0 0 ORI Inclusive OR Immediate (Destination) v Immediate Data—' Destination — • • 0 0 PEA Push Effective Address Destination —. SP@ — RESET Reset External Devices — — — — — ROL, ROR Rotate (Without Extend) (Destination) Rotated by —.Destination ROXL, ROXR Rotate with Extend (Destination) Rotated by —.Destination RTE Return from Exception SP@ + —.SR; SP@ + —.PC RTR Return and Restore Condition Codes SP@ + —.CC; SP@ + —.PC • FITS Return from Subroutine SP@ + —.PC — — — — SBCD Subtract Decimal with Extend (Destination) ig — (Sourcelig — X —. Destination U U SCC Set According to Condition If CC then l's—. Destination else O's—. Destination STOP Load Status Register and Stop Immediate Data —' SR; STOP SUB Subtract Binary (Destination) — (Source)—. Destination SUBA Subtract Address (Destinationl— (Sourcel--. Destination SUBI Subtract Immediate (Destination)—Immediate Data—. Destination SUBQ Subtract Quick (Destinationl— Immediate Data —. Destination • • • SUBX Subtract with Extend (Destinationl— (Source) — X—. Destination • • SWAP Swap Register Halves Register [31:161 Register [15:0] — • 0 0 TAS Test and Set an Operand (Destination) Tested —.CC; 1—. [7] OF Destination — • 0 0 TRAP Trap PC —. SSP@ — SR —. SSP@ — (Vector) —'• PC TRAPV Trap on Overflow If V then TRAP — — — — — TST Test an Operand (Destination) Tested —. CC 0 0 UNLK Unlink An' SP; SP@+ —.An — — — — —

[ ]=bit number

affected 0 cleared U defined — unaffected 1 set

Signetics 4.35 MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

Table 23 EFFECTIVE ADDRESS OPERAND CALCULATION TIMING

Addressing Mode Byte, Word Long Register Dn Data Register Direct 010/01 010/01 An Address Register Direct 010/01 010/0) Memory An@ Address Register Indirect 411/01 812/01 An@ + Address Register Indirect with Postincrement 411/01 812/01 An@ — Address Register Indirect with Predecrement 611 /0) 1012/01 An@ld) Address Register Indirect with Displacement 812/01 1213/01 An@ld, ix)* Address Register Indirect with Index 10(2/0) 1413/01 xxx.W Absolute Short 8)2/0) 1213/01 xxx.L Absolute Long 1213/01 1614/01 PC@1d) Program Counter with Displacement 812/01 1213/01 PC@1d, ix)* Program Counter with Index 1012/01 1413/01 #xxx Immediate 411/01 812/01

'The size of the index register (ix) does not affect execution time.

Table 24 MOVE BYTE AND WORD INSTRUCTION CLOCK PERIODS Destination Source Dn An An@ An@ + An@ — An@ld) An@ld,ix)* xxx.W xxx.L Dn 411/01 411/01 811/1) 811/11 811/11 1212/11 1412/1) 1212/1) 1613/11 An 411/0) 411/01 8(1/1) 811/11 811/11 1212/11 1412/11 1212/1) 1613/1) An@ 812/0) 812/01 1212/1) 1212/1) 1212/11 160/1) 1813/11 1613/11 2014/1) An@ + 812/01 812/01 1212/1) 1212/11 1212/11 1613/11 1813/1) 16(3/ 1) 2014/1) An@ — 1012/01 1012/0/ 1412/ 11 1412/1) 14(2/1) 1813/1) 2013/11 1813/1) 2214/1) An@ld) 1213/01 1213/01 1613/11 1613/1) 1613/11 2014/1) 2214/1) 2014/11 2415/11 An@ld, ix)* 1413/0) 1413/01 1813/1) 1813/1) 1813/11 2214/1) 2414/11 2214/1/ 2615/1) xxx.W 1213/0) 1213/01 1613/11 1613/11 1613/1) 2014/1/ 2214/11 2014/1) 2415/ 1) xxx.L 1614/01 1614/0) 2014/1) 2014/11 2014/11 24(5/1) 2615/11 2415/11 2816/1) PC@Idl 1213/01 1213/01 1613/11 1613/1) 1613/11 2014/11 2214/11 2014/ 11 2415/11 PC@1d, ixr 1413/0) 1413/01 1813/1) 1813/1) 1813/11 2214/11 2414/11 2214/11 2615/1) #xxx 8(2/0) 812/01 1212/1) 1212/11 12(2/ 11 1613/11 1813/11 1613/1) 20(4/11

The size of the index register (ix) does not affect execution time.

Table 25 MOVE LONG INSTRUCTION CLOCK PERIODS

Destination Source Dn An An@ An@ + An@ — An@ld) An@ld,ix)* xxx.W xxx.L Dn 411/01 411/01 1211/21 1211/21 1411/21 1612/21 1812/21 16(2/2) 2013/2) An 411/01 411/0) 1211/21 1211/21 1411/21 1612/21 1812/21 1612/2) 2013/2) An@ 1213/0) 1213/01 2013/21 20(3/2) 2013/21 2414/21 2614/2) 2414/21 2815/21 An@ + 1213/01 1213/0) 2013/2) 2013/21 200/21 2414/2) 2614/21 2414/21 2815/21 An@ — 1413/0) 1413/0) 2213/2) 2213/2) 2213/2) 2614/21 2814/2) 2614/2) 30(5/2) An@ld) 1614/01 1614/01 2414/21 2414/21 2414/21 2815/2) 3015/21 2815/2) 3216/21 An@ld, ix)* 1814/0) 1814/01 2614/21 2614/21 2614/21 3015/21 3215/2) 3015/21 3416/21 xxx.W 1614/0) 1614/0) 24(4/2) 2414/2) 2414/21 2815/21 3015/21 2815/2) 3216/21 xxx.L 2015/01 2015/0) 2815/2) 28(5/2) 2815/2) 32(6/2) 3416/2) 3216/2) 36(7/2) PC@Id) 1614/01 1614/0) 2414/21 2414/21 2414/21 2815/2) 3015/21 2815/2) 3215/21 PC@1d, ix)* 1814/01 1814/0) 2614/21 2614/21 2614/21 3015/2) 3215/21 3015/2) 3416/21 #xxx 1213/0) 1213/0) 20(3/2) 2013/2) 2013/21 2414/21 2614/2) 2414/2) 2815/21

'The size of the index regis er (ix) does not affect execution time.

4.36 Signetics MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

Table 26 STANDARD INSTRUCTION CLOCK PERIODS

Instruction Size op , An op , Dn op Dn, Byte, Word 8(1/01+ 4(1/01+ 8(1/11+ ADD Long 611/01+•• 611/01+*" 1211/21+ Byte, Word — 411/01+ 811/11+ AND Long — 611/01+” 1211/21+ Byte, Word 611/01+ 411/01+ — CMP Long 6(1/01+ 611/01+ — DIVS — — 15811/01+ • DIVU — — 14011/01+ • — Byte, Word — 411/01*** 811/11+ EOR Long — 811/01*** 1211/21+ MULS — — 70(1/01+ • — MULU — — 7011/01+ • — Byte, Word — 411/01+ 811/11+ OR Long — 6(1/01+ " 12(1/11+ Byte, Word 811/01+ 411/01+ 811/11+ SUB Long 6(1/01+•• 611/01+'"' 12(1/21+

+ add effective address calculation time •• total of 8 clock periods for instruction if the effective address is register direct • indicates maximum value ••• only available effective address mode is data register direct

Table 27 IMMEDIATE INSTRUCTION CLOCK PERIODS

Instruction Size op #, Dn op #, An op #, M Byte, Word 812/01 — 1212/11+ ADDI Long 1613/01 2013/ 21+ Byte, Word 411/01 811/01' 811/11+ ADDQ Long 811/01 811/01 1211/21+ Byte, Word 812/01 1212/11+ ANDI Long 1613/01 2013/11+ Byte, Word 812/01 812/01 812/01+ CMPI Long 1413/01 14(3/0/ 12(3/01+ Byte, Word 812/01 — 12(2/ 11+ EORI Long 1613/01 — 2013/21+ MOVEQ Long 411/0) — Byte, Word 812/01 1212/11+ ORI Long 16(3/01 20(3/21+ Byte, Word 812/01 — 1212/11+ SUBI Long 1613/01 2013/21+ Byte, Word 411/0) 811/01' 811/11+ SUBQ Long 8(1/01 811 /0) 12(1/21+

+ add effective address calculation time *word only

Signetics 4.37 MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

Table 28 SINGLE OPERAND INSTRUCTION CLOCK PERIODS

Instruction Size Register Memory Byte, Word 411/01 811/11+ CLR Long 611/01 1211/21+ NBCD Byte 611 /01 811/11+ Byte, Word 411/01 811/11+ NEG Long 611/01 1211/21+ Byte, Word 411/01 811/11+ NEGX Long 611/01 1211/21+ Byte, Word 411/01 811/11+ NOT Long 611/01 1211/21+ Byte, False 411/01 811/11+ SCC Byte, True 611/01 811/11+ TAS Byte 411/01 1011/11+ Byte, Word 411/01 411/0/ TST Long 411/01 411/01+ + add effective address calculation time

Table 29 SHIFT AND ROTATE INSTRUCTION CLOCK PERIODS

Instruction Size Register Memory Byte, Word 6 + 21111/01 811/11+ ASR, ASL Long B + 2n11/01 — Byte, Word 6 + 2n11/01 811/11+ LSR, LSL Long 8 + 2n11/01 Byte, Word 6 + 2n11/0/ 811/11+ ROR, ROL Long 8 + 2n11/01 Byte, Word 6 + 2n11/01 811/11+ ROXR, ROXL Long 8 + 21111/01 —

Table 30 BIT MANIPULATION INSTRUCTION CLOCK PERIODS

Dynamic Static Instruction Size Register Memory Register Memory Byte 8(1 / 11+ 1212/11+ BCHG Long 811/01* 1212/01* Byte — 811/11+ — 1212/11+ BCLR Long 1011/01* 1412/01* Byte — 811/ 11+ — 1212/11+ BSET Long 811/01* — 1212/01k Byte — 4(1/01+ — 812/01+ BTST Long 611/01 — 1012/01

+ add effective address calculation time indicates maximum value

4.38 Signetics MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

Multi-Precision Instruction Clock Exception Processing Clock Periods Periods the time for all stacking, the vector fetch, and the fetch of the first instruction of the Table 33 indicates the number of clock Table 35 indicates the number of clock handler routine. The number of bus read periods required for the multi-precision in- periods required for exception process- and write cycles is shown in parenthesis structions. The number of clock periods ing. The number of clock periods includes as (r/w). include the time to fetch both operands, perform the operations, store the results, Table 31 CONDITIONAL INSTRUCTION CLOCK PERIODS and read the next instructions. The number of bus read and write cycles is shown Trap or Branch Trap or Branch Instruction Displacement in parenthesis as (r/w). Taken Not Taken 811/01 In table 33, the headings have the follow- BCC Byte 1012/01 ing meaning: Dn -,- data register operand Word 1012/01 1212/01 and M = memory operand. Byte 1012/01 — BRA Word 1012/01 — Miscellaneous Instructions Clock Byte 1812/21 — BSR Periods Word 1812/21 — Table 34 indicates the number of clock cc true — 1212/01 DBCC periods required for miscellaneous in- CC false 1012/01 1413/01 structions. The number of bus read and CHK — 4015/31+ * 811/01+ write cycles is shown in parenthesis as TRAP — 3414/31 — (r/w). The number of clock periods plus the TRAPV 34(5/31 411/01 number of read and write cycles must be — added to those of the effective address + add effective address calculation time calculation where indicated. * indicates maximum value

Table 32 JMP, JSR, LEA, PEA, MOVEM INSTRUCTION CLOCK PERIODS Instr Size An@ An@ + An@ - An@ld) An@ld, ix)* xxx.W xxx.L PC@1d1 PC@1d, ixl* JMP - 812/01 - - 1012/01 1413/01 1012/01 12(3/01 10(2/0) 14(3/01 JSR - 16(2121 - - 18(2/2) 2212/2) 1812/21 2013/21 18112) 22(2/2) LEA - 411/01 - - 812/01 1212/0) 812/0) 12(3/0) 8(2/0) 112/0) PEA - 12(1/21 - - 1612/2) 20(2/2) 16(2/21 20(3/2) 16(2/2) 2012/21 MOVEM Word 12+4n 12+4n 16 + 4n 18+4n 16 + 4n 20 + 4n 16+4n 18 + 4n 13+n/01 (3+n/01 14 + n/01 (4 + n/01 (4+n/0) 15 + n/01 14 + n/0) 14 + n/01 16+8n 18+8n M —R Long 12 + 8n 12 + 8n - 16 + 8n 18+8n 16 + 8n 20+8n 13+2n/01 13+2n/01 (4+2n/01 (4 + 2n/01 (4 + 2n/01 (5+2n/0) 14 + 2n/01 14 + 2n/0) 16 + 5n - - MOVEM Word 8 + 5n - 8+5n 12 + 5n 14+5n 12 + 5n 12/n) - (2/n) 13/n) 13/n) 13/n) 14/n) R -..-M Long 8+10n - 8+10n 12+10n 14 + 10n 12 + 10n 16+10n - - (2/2n1 - 12/2n) 13/2n) (3/2n1 (3/2n) 14/2n( - n is the number of registers to move * the size of the index register (ix) does not affect the instruction's execution time

Table 33 MULTI-PRECISION INSTRUCTION CLOCK PERIODS

Instruction Size op Dn, Dn op M, M Byte, Word 411/01 1813/11 ADDX Long 811/0) 3015/21 Byte, Word 1213/01 CMPM Long — 2015/01 Byte, Word 411/01 1813/ 11 SUBX Long 811/01 3015/21 ABCD Byte 611/01 1813/ 1) SBCD Byte 6(1/0) 1813/11 Signetics 4.39 MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

Table 34 MISCELLANEOUS INSTRUCTIONS CLOCK PERIODS Instruction Size Register Memory Register -.-- Memory Memory -..-- Register MOVE from SR 6(1/01 811/11+ — — MOVE to CCR — 1212/01 1212/01+ — — MOVE to SR — 1212/0) 1212/01+ — — Word — — 16(2/21 16(4/01 MOVEP Long — — 24(2/41 24(6/01 EXG 611/01 — — Word 411/01 — — — EXT Long 411/0) — — LINK 1612/21 — — — MOVE from USP — 4(1/01 — — — MOVE to USP — 4(1/01 — — NOP — 4(1/0) — — — RESET — 132(1/0) — — — RTE — 2015/01 — — RTR — 2015/01 — — RTS — 16(4/01 — — — STOP — 410/0) — — — SWAP 411/01 — — UNLK 1213/01 — — — + add effective address calculation time

Table 35 EXCEPTION PROCESSING CLOCK PERIODS Exception Periods Address Error 5014/7) Bus Error 5014/7) Interrupt 4415/31* Illegal Instruction 3414/31 Privileged Instruction 3414/31 Trace 3414/31 *The interrupt acknowledge bus cycle is assumed to take four external clock periods

4.40 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

ABSOLUTE MAXIMUM RATINGS1

PARAMETER RATING UNIT

Supply voltage -0.3 to + 7.0 V Input voltage3 - 0.3 to + 7.0 V Operating temperature range2 0 to + 70 °C Storage temperature - 55 to + 150 °C

DC ELECTRICAL CHARACTERISTICS Vcc = 5.0V 5%, Vss = OV; TA = 0°C tO + 70°C (see figures 37-39)46

LIMITS PARAMETER TEST CONDITIONS UNIT Min Max

VH Input high voltage 2.0 Vcc V

VIL Input low voltage V00-0.75 0.8 V 1,, Input leakage current 5.25V BERR, BGACK, BR, DTACK, CLK, IP00-1PL2, VPA 2.5 µA HALT, RESET 20 µA

i-rsi Three-state (off state) input current 2.4V/0.4V AS, A1-A23, D0-D15, FCO-FC2, LDS, R/W, UDS, VMA 20 µA

VON Output high voltage 10H ,..- -400µA E6 Vcc-O-75 V AS, A1-A23, BG, DO-D15, FCO-FC2, LDS, R/W, UDS, VMA 2.4 V

Vol_ Output low voltage HALT IOL = 1.6mA 0.5 V A1-A23, BG, FCO-FC2 lc _= 3.2mA 0.5 V RESET loL= 35.0mA 0.5 V E, AS, DO-D15, LDS, R/W, UDS, VMA loL= 5.3mA 0.5 V 130 Power dissipation Clock frequency = *MHz 1.5 W

Cl„ Capacitance V,,= OV, TA = 25°C, 10.0 pF frequency = 1MHz NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operation section of this specification is not implied. 2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature. 3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. 4. Parameters are valid over specified temperature range. 5. All voltage measurements are referenced to ground (GND). For testing, all input signals swing between 0.4V and 2.4V with a transition time of 20ns maximum.All time measurements are referenced at input voltages of 0.8V and 2.0V and output voltages of 0.8V and 2.0V as appropriate. 6. With external pullup resistor of 470 ohms. 7. For a loading capacitance of less than or equal to 500pF, subtract 5ns from the values given in these columns. 8. Actual value depends on clock period. 9. If #47 is satisfied for both DTACK and BERR, #48 can be Ons. 10 After VCC has been applied for 100ms. 11 If the asynchronous setup time (#47) requirements are satisfied, the DTACK low-to-data setup time (#31) requirements can be ignored. The data must only satisfy the data-in to clock-low setup time (#27) for the following cycle.

Signetics 4.41 MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

AC ELECTRICAL SPECIFICATIONS VA = 5VDC, TA = 0°C to 70°C (see figures 41-45)4,8 TENTATIVE LIMITS NUMBER CHARACTERISTIC SYMBOL 4MHz 6MHz 8MHz 10MHz UNIT Min Max Min Max Min Max Min Max 1 Clock period tcy, 250 500 167 500 125 500 100 500 ns 2 Clock width low to_ 115 250 75 250 55 250 45 250 ns 3 Clock width high tCH 115 250 75 250 55 250 45 250 ns 4 Clock fall time tv 10 10 10 10 ns 5 Clock rise time tor 10 10 10 10 ns

6 Clock low to address ICLAV 90 80 70 55 ns 6A Clock high to FC valid tcHFcv 90 80 70 60 ns Clock high to address data high 7 120 100 80 70 ns impedance (maximum) tcHAZx Clock high to address/FC invalid 8 0 0 0 0 ns (minimum) tcRAzn 97 Clock high to AS, DS low (maximum) tcHsLx 80 70 60 55 ns

10 Clock high to AS, DS low (minimum) tCHSLn 0 0 0 0 ns

118 Address to AS, DS (read) low/AS write tAVSL 55 35 30 20 ns 11A8 FC valid to AS, DS (read) low/AS write tFcvsi_ 80 70 60 50 ns 127 Clock low to AS, DS high tcLsH 90 80 70 55 ns 138 AS, DS high to address/FC invalid tSHAZ 60 40 30 20 ns 148 AS, DS width low (read)/AS write tsL 535 337 240 195 ns 14A8 DS width low (write) 285 170 115 95 ns 157 AS, DS width high tsR 285 180 150 105 ns

16 Clock high to AS, DS high impedance ICHSZ 120 100 80 70 ns 178 AS, DS high to R/W high tSHRH 60 50 40 20 ns 187 Clock high to R/W high (maximum) tcHRrix 90 80 70 60 ns

19 Clock high to R/W high (minimum) tCHRHn 0 0 0 0 ns

207 Clock high to RIW low tCHRL 90 80 70 60 ns

218 Address valid to R/W low tAVRL 45 25 20 0 ns

21A8 FC valid to RIW low tFCVRL 80 70 60 50 ns

228 R/W low to DS low (write) tRLSL 200 140 80 50 ns

23 Clock low to data out valid tCLDO 90 80 70 55 ns 24 Clock high to R/W, VMA high impedance LcHFIz 120 100 80 70 ns

258 DS high to data out invalid tSHDO 60 40 30 20 ns 268 Data out valid to DS low (write) thost. 55 35 30 20 ns 2711 Data in to clock low (setup time) tDICL 30 25 15 15 ns

288 AS, DS high to DTACK high tSHDAH 0 240 0 160 0 120 0 90 ns 29 DS high to data invalid (hold time) tSHDI 0 0 0 0 ns 30 AS, DS high to BERR high tsRBER 0 0 0 0 ns

318 DTACK low to data in (setup time) tDALDI 180 120 90 65 ns

32 HALT and RESET input transition time tRHrf 0 200 0 200 0 200 0 200 ns

33 Clock high to BG low tCHGL 90 80 70 60 ns

34 Clock high to BG high tCHGH 90 80 70 60 ns 35 BR low to BG low tBRLGL 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 Clk Per

35 BR low to BG low (figure 43) tBRLGL 1.5 3.5 1.5 3.5 1.5 3.5 1.5 3.5 Clk Per

4.42 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

AC ELECTRICAL SPECIFICATIONS (Continued) VA = 5VDC, TA = 0 °C to 70°C (see figures 41-45)4,5 TENTATIVE LIMITS NUMBER CHARACTERISTIC SYMBOL 4MHz 6MHz 8MHz 10MHz UNIT Min Max Min Max Min Max Min Max 36 BR high to BG high tBRHGH 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 Clk Per 37 BGACK low to BG high tGALGH 1.5 3.0 1.5 3.0 1.5 3.0 1.5 3.0 Clk Per 38 BG low to bus high impedance (AS high) tmz 120 100 80 70 ns 39 BG width high tGH 1.5 1.5 1.5 1.5 Clk Per

40 Clock low to VMA low 1cLynit. 90 80 70 70 ns 41 Clock low to E transition tux 100 85 70 55 ns 42 E output rise and fall time tErf 25 25 25 25 ns 43 VMA low to E high tVMLEH 325 240 200 150 ns 44 AS, DS high to VPA high tSHVPH 0 240 0 160 0 120 0 90 ns 45 E low to address/VMA/FC invalid tELAI 55 35 30 10 ns 46 BGACK width tem_ 1.5 1.5 1.5 1.5 Clk Per 4711 Asynchronous input setup time tAsi 30 25 20 20 ns 489 BERR low to DTACK low tBELDAL 50 50 50 50 ns 49 E low to AS, DS Invalid tELSI -80 -80 -80 -80 ns 50 E width high tEH 900 600 450 350 ns 51 E width low tEL 1400 900 700 550 ns 52 E extended rise time tCIEHx 80 80 80 80 ns 53 Data hold from clock high tcHoo 0 0 0 0 ns 54 Data hold from E low (write) tELGoz 60 40 30 20 ns 55 R/W to data bus Impedance change tRLDo 55 35 30 20 ns 5610 Halt/RESET pulse width tHRpw 10 10 10 10 Clk Per

CLOCK TIMING (see figure 40) 4MHz 6MHz 8MHz 10MHz CHARACTERISTIC SYMBOL UNIT Min Max Min Max Min Max Min Max Frequency of Operation F 2.0 4.0 2.0 6.0 2.0 8.0 2.0 10.0 MHz Cycle Time tcyc 250 500 167 500 125 500 100 500 ns 115 250 75 250 55 250 45 250 Clock Pulse Width tcL ns tcH 115 250 75 250 55 250 45 250 - 10 - 10 - 10 - 10 Rise and Fall Times tCr ns tcf - 10 - 10 - 10 - 10

POWER CONSIDERATIONS PINT. ICC X Vcc, Watts - Chip Solving equations 1 and 2 for K gives: Internal Power The average chip-junction temperature, TJ, K= PD.,(TA + 2734C)+ OJA•PD2 (3) in °C can be obtained from: Pm= Power Dissipation on Input and Output Pins - User Determined Where K is a constant pertaining to the Tj = TA ± (PD•0 JA) (1) particular part. K can be determined from 110 For most applications P PINT and can equation 3 by measuring pp (at equili- Where: be neglected. TA.-- Ambient Temperature, °C brium) for a known TA. Using this value of 0 JA m Package Thermal Resistance, An approximate relationship between P0 K the values of P0 and TJ can be obtained Junction-to-Ambient, °C/W and TJ (if P110 is neglected) is: by solving equations (1) and (2) iteratively for any value of TA. PO' PINT + PI/0 (2) Pt) = K+. (Tj + 273°C) Signetics 4.43 MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

+5V

R =740 0 MMD6150 Test Point or Equivalent

MM07000 Or Equivalent

CL= 130 pF (Includes all Parasitics) RL=6.0 kit for A1-A23, BG, D0-D15, E FC0-FC2, LDS, RAW, UDS, VMA •R = 1.22 kit for A1-A23, BG, E, FC0-FC2

Figure 39. Test Loads

All timing diagrams should only be referenced in regard to the edge-to-edge measurement of the timing specifications. They are not intended as a functional description of the input and output signals. Refer to other functional descriptions and their related diagrams for device operation.

tcyc

- tCL tCH--)low

2.0 V

0.8 VI

tCr._

Figure 40. Input Clock Timing

4.44 Signetics MICROPROCESSOR DIVISION JANUARY 1983

16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

DSO S1 S2 S3 S4 S5 S6 S7

CLK

04' 411 .10 Al-A23 0

12 ati LDS/LTE7)

R/W mm l

FCO-FC2 clt

Asynchronous Inputs (Note 1)

HALT/RESET

.11-0 CD 47 BERR/BR (Note 21 +t-07

DTACK fl y Data In

NOTES:

1. Setup time for the asynchronous inputs BGACK, IPLO-IPL2, and VPA guarantees their recognition at the next falling edge of the clock. 2. BR need fall at this time only in order to insure being recognized at the end of this bus cycle.

Figure 41. Read Cycle Timing

Signetics 4.45

MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

SO S1 S2 S3 S4 S5 S6 S7 SO...

CLK

Al -A23 F 10

al—C) 0 AS 0 10 —3A. 15 0

LDS/ UDS

23 R /TR €t) cp,

Data Out CD FCO-FC2

Asynchronous Inputs

HALT/ RESET > 47

.1(—C)

BERR / BR

DTACK

Figure 42. Write Cycle Timing

4.46 Signetics MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR SCN68000 SERIES

Preliminary

Strobes and RAN

BGACK

CLK

NOTES, 1. Setup time for the asynchronous inputs BERR, BGACK, BR, DTACK, IPLO-IPL2, and VPA guarantees their recognition at the next falling edge of the clock.

Figure 43. AC Electrical Timing—Bus Arbitration

Signetics 4.47 Data Out At-A23 Data In NOTE: Thisfigurerepresentsthebest casesynchronoustimingwhereVPAfallsbeforethethirdsystemclock cycleafterthefallingedgeofE. VMA VPA CLK AS SO < Si

S2 S3 S4 w Figure 44.Synchronous Timing—BestCase w w ,ne a a. , - A

w S5S6S7SO a

.4 / a- O >

rAmmiElz

S31213S00099NOS 210SS30021d02101104 118-9 cog AdVIINVr NOISIAIC dOSS300dd021011A1 R/W Write UDS/ LDS UDS/LDS Data Out AI-A23 Data In (Read) Write Read R/W VMA VPA CLK AS

SO SIS2S3S4wwwwS5S6S7 4t— Figure 45.Synchronous Timing—WorstCase 4 52 .4-- 42 J O

a 3

S31213S00099N OS 2IOSS30021d021011A1118-91.

£866 AdVfINVr NOISIAIGdOS S300ddOdaltAl

MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR WITH 8-BIT BUS SCN68008

PRODUCT BRIEF, contact your Signetics sales office for complete information.

DESCRIPTION The SCN68008 has full code compatibility PIN CONFIGURATION The SCN68008 is a member of the S68000 (source and object) with the SCN68000 Family of advanced microprocessors. This which allows programs to be run on either device allows the design of cost effective MPU depending on performance require- A3E A2 systems using 8-bit data buses while pro- ments and cost objectives. E viding the benefits of a 32-bit micro- A4 C E Al The programmer's model is identical to processor architecture. The performance that of the SCN68000, as shown in figure A51 E AO of the SCN68008 is greater than any 8-bit 1, with seventeen 32-bit registers, a 32-bit A6 E 45 FC0 microprocessor and superior to several program counter, and a 16-bit status regis- 16-bit microprocessors. A7 C E FC1 ter. The first eight registers (DO-D7) are A8 (8 FC2 The resources available to the SCN68008 used as data registers for byte (8-bit), word E user consist of the following: (16-bit), and long word (32-bit) operations. A9 E IPL2/0 • 17 32-bit data and address registers The second set of seven registers (AO-A6) A10 E 41 IPL1 • 56 basic instruction types and the system stack pointer (A7) may be Alli EBERR • Extensive exception processing used as software stack pointers and base Al2 10 EVPA • Memory mapped I/O address registers. In addition, the • 14 addressing modes registers may be used for word and long Ala E EE • Complete code compatibility with the word operations. All of the 17 registers A14 12 E RESET may be used as index registers. SCN68000 Vcc 13 E HALT A system implementation based on an FEATURES Al 5 E E GND 8-bit data bus reduces system cost in • 32-bit data and address registers comparison to 16-bit systems due to a GND 15 34 CLK • 1-megabyte direct addressing range more effective use of components and the Alb BR • 56 powerful instruction types E E fact that byte-wide memories and periph- • Operations on five main data types A17 E E BG erals can be used much more effectively. • Memory mapped I/O In addition, the non-multiplexed address A18 18 31 DTACK • 14 addressing modes and data buses eliminate the need for ex- Al 9 E ERIW • Source and object compatible with ternal demultiplexers, thus further simpli- SCN68000 07 a EDS fying the system. • 48-pin DIP D8 E 28 AS D5 g EDO 31 16 15 8 7 0 D4 g 26 D1 DO D3 E E D2 01

D2 TOP VIEW D3 EIGHT DATA D4 REGISTERS D5 D6

DI 31 16 15 AO Al

A2 SEVEN A3 ADDRESS REGISTERS A4

USER STACK POINTER TWO STACK SUPERVISOR STACK POINTER 1Al POINTERS

31 PROGRAM COUNTER 15 8 7 STATUS SYSTEM BYTE USER BYTE REGISTER

Figure 1. Programming Model

4.50 Signetics MICROPROCESSOR DIVISION JANUARY 1983 16-BIT MICROPROCESSOR WITH 8-BIT BUS SCN68008

The 1-megabyte non-segmented linear ad- FUNCTIONAL DIAGRAM dress space of the SCN68008 allows large modular programs to be developed and executed efficiently. A large linear address Ycc ADDRESS AO-A19 space allows program segment sizes to be G N D(2) determined by the application rather than BUS forcing the designer to adopt an arbitrary CLK segment size without regard to his in- DATA> DO.D7 dividual requirements. < BUS Exception processing allows the AS SCN68008 to handle interrupts, address RIW errors, unimplemented instructions, and 4 DS ASYNCHRONOUS other commonly encountered exceptions BUS CONTROL FC1 while maintaining absolute system integri- PROCESSOR STATUS ty. The exception processing state is 2 DTACK associated with interrupts, trap instructions, tracing, and other exceptional conditions. An exception may be generated BR BUS ARBITRATION internally by an instruction or by an PERIPHERAL BG ICONTROL unusual condition occurring during pro- CONTROL A gram execution. Exception processing provides an efficient context switch to

enable the processor to handle unusual B IPLO/2 conditions without degrading system RESET INTERRUPT integrity. SYSTEM CONTROL CONTROL IPL1 I

Signetics 4.51 MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120ISCN68121

Preliminary

DESCRIPTION FUNCTIONAL DESCRIPTION PIN CONFIGURATIONi The SCN68120/SCN68121 Intelligent Peri- The SCN68120/SCN68121 are 8-bit Intelli- pheral Controllers (IPCs) are general pur- gent Peripheral Controllers which can be pose, mask programmable peripheral con- configured to function in a wide variety of Vs5 ERESET trollers. The IPC provides the interface applications. This flexibility is provided by 47 P24 between an S68000 or M6800 family micro- its ability to be hardware programmed into HALT/ BA/NMI 46 P23 processor (or microprocessors with equiv- eight different operating modes. These 45 P22 alent synchronous interfaces) and the operating modes allow the IPC to operate El final peripheral device through a system on its local bus and communicate with an SR/W EP21 bus and control lines. System bus data is external system bus through the internal DTACK EP20 transferred to and from the IPC via a dual- dual-port RAM. The operating mode con- Ts-E E SC2 port RAM while the software utilizes trols the configuration of 18 of the 48 pins semaphore registers to control RAM task- on the IPC, the available on-chip SA7 41 SC1 ing or any shared resource. Multiple resources, the memory map, the location SA6 EP30 (internal or external) of interrupt vectors, operating modes range from a single chip SA5 E EP31 mode with 21 I/O lines and two control and the type of local bus. The configura- lines to an expanded mode supporting an tion of the remaining 30 pins is not con- SA4E EP32 address space of 64K bytes. The trolled by the operating mode. Vcc E EP33 SCN68121 utilizes only the expanded ad- SA3 13 E P34 dress modes, due to the absence of an on- The dual-port RAM provides a vehicle for SA2 P35' chip ROM. devices on two separate buses to ex- E E change data without directly affecting the SA1 E EP36 A serial communications interface, 16-bit devices on the other bus. The dual-port SAO 16 EP37 RAM is accessible from the IPC's CPU and timer, dual-ported RAM and semaphore SDOE EP40 registers are available for use by the IPC in accessible synchronously or asyn- all operating modes. chronously to the system bus through 5D1 18 EP41 port 1. Semaphore registers are provided SD2 EP42 as a software tool to arbitrate shared SD3E EP43 resources such as the dual-port RAM. The FEATURES semaphore registers are accessible from SD4 21 EP44 • System bus compatible with the asyn• both buses in the same way each bus ac- SD5E EP45 chronous S68000 family cesses the dual-port RAM. SD6H 26 P46 • System bus compatible with the syn- P47 chronous M6800 family processors/ The remaining ports (2, 3, and 4) are I/O sirE E peripherals (or microprocessors with ports. Each port is controlled by its data TOP VIEW equivalent synchronous interfaces) direction register. The CPU has direct ac- • Compatible with Motorola 6801 source cess to the port pins of each port through The SCN68121 has all of the features o and object code its data register. Port pins are labelled as the SCN68120 except for the on-CHIP • Upward compatible with Motorola 6800 Pii, where i identifies one of three ports ROM. Thus, the SCN68121 operates only source and object code and j indicates the particular bit. Port 2 is a in the modes utilizing external ROM • 2048 bytes of ROM (SCN68120 only) 5-bit port which can be configured for I/O (modes 2 and 3). • 128 bytes of dual-ported RAM or for use by the on-chip timer and serial • Multiple operation modes ranging from communications interface (SCI). Ports 3 DUAL PORT RAM AND single chip to expanded, with 64K byte and 4 may be used as 16-bits of I/O or may SEMAPHORE REGISTERS address space form a local address and data bus with The dual-port RAM can be accessed from • Six shared semaphore registers control lines allowing comunications with both the SCN68120/SCN68121 CPU and • 21 parallel I/O lines and two handshake external memory and peripherals. the external system bus. The six sema- lines (five I/O lines on the SCN68121) phore registers are tools provided for the • Serial communications interface (SCI) The IPC contains a synchronous MPU programmer's use in arbitrating simultan- • 16-bit three-function timer which is upward source and object code eous accesses of the same resource. • 8-bit CPU and internal bus compatible with the Motorola MC6800 and • Haltlbus available capability control directly compatible with the MC6801. The For the internal CPU, the dual-port RAM is • 8 x 8 multiply instruction programming model is shown in Figure 1, located from $0080 through $00FF in all • TTL compatible inputs and outputs where accumulator D is a concatenation modes except 3 and 4. In mode 3, the dual- • External and internal interrupts of accumulators A and B. port RAM has been relocated in high

ORDERING CODE

Vcc = 5V ±5% TA = 0° to 70°C Packages With ROM Without ROM 1.0MHz 1.25MHz 1.0MHz 1.25MHz lln this data sheet, barring signal names (overscore) to indicate low is done only for the pin configuration Ceramic DIP SCN68120C1148 SCN68120C2148 SCN68121C1148 SCN68121C2148 diagram, signal descdptIon headings, tables and Plastic DIP SCN68120C1N48 SCN68120C2N48 SCN68121C1N48 SCN68121C2N48 figures.

4.52 Signetics

MICROPROCESSOR DIVISION JANUARY 1983

INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

111 ?,

1i2',211:11 1. /' ' DATA BUFFER ADDRESS BUFFER

S DATA ONLY)

S ADDRESS SC68120 (

2 O LOCAL BUS

...I—. P40 A8 AO 110 .1-11. P41 A9 Al 110 DATA P42 A10 A2 I/0 P43 All A3 110 P44 Al2 A4 110 O — P45 A13 AS I/0 ADDRESS) r—r. P46 A14 A6 110 P47 A15 A7 I/O

wo--s. SC1 AS IOS 1S3 SC2 R1W RIW 0S3 -.—•• P30 AO/DO DO I/O P31 A1/D1 D1 110 - P32 A2/D2 D2 I/O 110 TDATA P24 C*1 Ia At—o. P33 A3/D3 D3 110 I/0 RDATA P23 ▪ P34 A4/D4 D4 110 110 SCLK P22 O a. ▪ P35 A5105 D5 110 I TOUT P21 P36 A6/D6 D6 110 I/0 TIN P20 P37 A71D7 D7 1/0 a a

H tc; Pz" 0 2 0 a a 0

'81

Signetics 4.53 MICROPROCESSOR DIVISION JANUARY 1983

INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

7 7 8-BIT ACCUMULATORS A AND B OR A B 16-BIT DOUBLE ACCUMULATOR D D 15 0

15 INDEX REGISTER (X)

15 SP STACK POINTER (SP)

15 PC PROGRAM COUNTER (PC)

1 H 1 N CONDITION CODE REGISTER (CCR)

CARRY/BORROW FROM MSB

OVERFLOW

ZERO

NEGATIVE

INTERRUPT

HALF CARRY (FROM BIT 3)

Figure 1. Programming Model

memory from $C080 through $COFF thus from the system bus. The direction of data should be avoided. The responsibility for allowing use of direct addressing mode on transfer is selected by the system read/- mutual exclusion resides in software. The external memory/peripherals. Note that no write (SR/W) line. The data transfer semaphore registers are a convenient direct addressing of internal control acknowledge (DTACK) signal is the asyn- means for the software to control the registers is possible in mode 3. In mode 4, chronous handshake required by the simultaneous accesses involving a write the internal RAM is not fully decoded and SCN68000 DTACK can be used to control to the dual-port RAM. Each of the six appears in locations $XX80 through a memory ready signal on a processor semaphore registers consist of a sema- $XXFF. From the external system bus, the where memory ready capability is pro- phore bit (SEM, bit7) and an ownership bit dual-port RAM is found in locations vided (see Figure 4). The latter would allow (OWN, bit6). The remaining six bits (b0-b5) c/.. 10000000-11111111, as shown in the M6800 family processor (or micropro- will be all zeros. Table 1. cessors with an equivalent interface) to run asynchronously with the SCN68120/ Semaphore Register The reserved memory areas %0-0001 SCN68121. It should be noted that if the 0110 and %0001 1101-0111 1111 cannot memory ready signal (on M6800 pro- 7 6 5 4 3 2 1 be written to from the system bus. If read cessors) is to be used with the DTACK LSEM OWN 10 I 0 I 0 I 0 1 0 1 0 from the system bus, these memory loca- signal, the system clock must be faster tions return a value of $FF. than or equal to the clock driving the IPC. The semaphore bits are test and set bits Example clock circuits are shown in with hardware arbitration during simul- The dual-port RAM is accessed from the Figures 5 and 6. taneous accesses. Basically, the external system bus via eight address semaphore bit is cleared when written and lines (SAO-SA7) and eight data lines (SDO- The semaphore registers allow arbitration set when read, during a single processor SD7). Three control lines provide for syn- between shared resources, which may be access. This is shown in Table 2. chronous or asynchronous access to the part or all of the dual-port RAM, or a dual-port RAM through port 1. Figure 2 peripheral. The semaphore registers can The data written is disregarded and the in- shows an example of a synchronous inter- also be used to indicate that non-reentrant formation obtained from the read can be face (using the MC6809) and Figure 3 code is in use or that a task is in process interpreted as: 0—resource available or shows an example of an asynchronous in- or is complete. To prevent the writing or 1—resource not available. Thus, any write terface (using the SCN68000). The dual- reading of erroneous data from the dual- to a semaphore clears the semaphore bit port RAM is selected in each case by ad- port RAM, all simultaneous accesses in- and makes the associated resource dress lines SAO-SA7 and chip select (CS) volving a write to the dual-port RAM 'available'.

4.54 Signetics MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

Table 1 LOCATION OF SEMAPHORE REGISTERS AND DUAL-PORTED RAM

System Bus Address Feature IPC Address" ISA7-SAO) %0000 0000 — 0001 0110 Reserved — Internal Registers 500-16 0001 0111 — 0001 1100 Semaphore Registers 17-1C 0001 1101 — 0111 1111 Reserved 10-1F External Mem./Unusable• 20-7F 1000 0000 — 1111 1111 Dual-Ported RAM 80-FF %= Binary; S= Hexadecimal -Mode Dependent

CLOCK E, E. CIRCUIT 0*

AS* . SCN68120 MC6809 UPPER OR ADDRESS MICROPROCESSOR LINES WITH EQUIVALENT CS CHIP SELECT SYNCHRONOUS CIRCUIT INTERFACE

ssicy

DTACK

SDO-SDI

DATA LINES

< SAO-SA7

LOWER ADDRESS LINES

•E and O are inputs for MC6809E "Only needed in expanded multiplexed modes.

Figure 2. Synchronous System Bus Access Interface

Table 2. SINGLE PROCESSOR SEMAPHORE BIT TRUTH TABLE

Original Data Resulting RAW SEM Bit Read SEM Bit 0 R 0' 1 1 R 1* 1 0 W — 0 1 W 0

*0 — Resource Available 1 — Resource Not Available Signetics 4.55 MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

E CLOCK CIRCUIT

AS. SCN68120 SCN68000 UPPER ADDRESS LINES CS as CHIP SELECT CIRCUIT

DATA STROBE sntiri .46 DTACK Ycc 1110 Al-AS <SDO-SD7

LOWER DATA LINES

(SAO-SA7

LOWER ADDRESS LINES

*Only needed in expanded multiplexed modes.

Figure 3. Asynchronous System Bus Interface

CLOCK CIRCUIT AS" MC6809 OR SCN68120 UPPER MICROPROCESSOR ADDRESS WITH EQUIVALENT LINES SYNCHRONOUS CS CHIP SELECT INTERFACE CIRCUIT

MRDY

SDO-SD7

DATA LINES

SAO-SA7

ADDRESS LINES

"Only needed in expanded m Itiplexed modes.

Figure 4. Memory Ready — DTACK Configuration

4-56 Signetics MICROPROCESSOR DIVISION JANUARY 1983

INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

Ycc SCHEMATIC

► 0 C _L_ AS = D CLR 0 CLR 0 D CLR CLR D Ula U1b U1c U1d

----'>CLK CLK >CLK VCC 8MHz U1 SN74LS175 U2 SN74LS08 taic= 10as

TIMING

8MHz I

C/A

As L

Figure 5. Clock Circuit Example 1 — Schematic and Timing

Signetics 4.57 MICROPROCESSOR DIVISION JANUARY 1983

INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

SCHEMATIC vCC

0 PRE CLR CLK 0 al> • ► E Ula U1b

CLK TI D CLR PRE O no. 1110, AS

410 O CLR PRE CLK 0 U2a 1.121)

CLK 73--EDU3d U1, U2 — SN74LS74 PRE CLR U3 — SN74LSO2 O U

TIMING

410

04 ----I

AS -

Figure 6. Clock Circuit Example 2 — Schematic and Timing

4.58 Signetics MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

Table 3. DUAL PROCESSOR SEMAPHORE BIT TRUTH TABLE IPC System Original _ Data Data Resulting SEM Bit R/W Read R/W Read SEM Bit 0 R 0' R 1 1 1 R 1' W 0 PROPER 1 W — R 1 0 1 R 1 R 1 1 0 W — W 0 0 R 0' W — IMPROPER W VV 0 0 W — R 0' 1 •0 — Resource Available 1 — Resource Not Available

An access where both the IPC and system the system processor set it when the IPC FUNCTIONAL PIN processors attempt to read or write the RESET is held low. DESCRIPTIONS same semaphore register simultaneously is a contested access. During a contested PROGRAM STORAGE MEMORY Ifcc and Vss access, the hardware decides which pro- — ROM N./cc and Vss provide power and ground to cessor reads a clear semaphore bit and The standard SCN68120 comes prepro- the IPC. which reads a set semaphore bit. Table 3 gammed with a monitor in the ROM. describes contested operation of a sema- Custom programs are placed in ROM by phore bit. special order (see appendix A). RESET Provides the IPC with an orderly and de- The IPC always reads the actual The SCN68120 contains 2048 bytes of on- fined start-up procedure from a power- semaphore bit; the system processor chip, mask programmable read-only down condition, returns to start-up condi- reads the semaphore bit in all cases ex- memory (ROM) in memory locations $F800 tions without an intervening power-down cept the simultaneous read of a clear through $FFFF. The contents of this ROM condition and provides a control signal to semaphore bit. This arbitration during a allows the IPC to perform a custom func- latch the operating mode. simultaneous read ensures that only one tion for the user. The interrupt vectors processor reads a clear bit and therefore $FFF0-$FFFF are decoded to provide vec- During reset (low logic level on RESET controls the resource; that processor is ar- tors at the top of resident ROM. Address pin), execution of the current instruction bitrarily the IPC. lines Al2 and A13 of the decoder for the is suspended and the CPU enters a 'reset ROM can be mask programmed as a 0 or 1 state'. The register contents are not In Table 3, the first four states are con- to change the ROM starting address from pushed onto the stack and their contents sidered proper and they occur in correctly $F800 to $C800, $D800 or $E800. Al2 and become undefined during reset. The 'reset written software. The last four states are A13 can also be 'don't cares' in this state' initializesthe I PC as shown in Table 5. improper and only exist in improperly writ- decoder. Address $FFEF is reserved for ten software. the checksum value for the ROM. This On the positive edge of RESET, the IPC value is the complement of the exclusive latches the operating mode from P22, P21 The ownership bit is a read-only bit that in- OR of the 2047 bytes of mask programmed and P20, and then configures port 3, port dicates which processsor sets the sema- ROM. An IPC without ROM is also avail- 4, SC1 and SC2. The restart vector is then phore bit. If the semaphore bit is set, the able as the SCN68121. The SCN68121 fetched and transferred to the program ownership bit indicates which processor should only be used in modes 2 and 3 to counter, and then instruction execution set it. If the semaphore bit is not set, the access external ROM after reset. begins. ownership bit indicates which processor last set the semaphore bit: OWN = 0, the other processor set SEM; OWN = 1, this Table 4. RESET STATE OF SEMAPHORE REGISTER processor set SEM. SEM IPC System Reg The reset state of the semaphore and No. Sem Own Sem Own ownership bits is defined in Table 4. All of the semaphore bits are set after an IPC 1 1 1 1 0 reset. The IPC owns all of them except the 2 1 0 1 1 second semaphore which is owned by the 3 1 1 1 0 system processor. This configuration 4 1 1 1 0 should prevent the system processor from 5 1 1 1 0 reading a clear semaphore and implying 6 1 1 1 0

Signetics 4.59 MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN681 2,1

Preliminary

Reset timing is illustrated in Figure 7. The negative half-cycle of E and the selected Halt/Bus Available/Nonmaskable RESET line must be held low for a device must be enabled to the data bus Interrupt (HALT/BA/NMI) minimum of three E-cycles for the IPC to during the next positive half-cycle. The complete its entire reset sequence. An ex- data bus is active only while E is high. It This pin functions as either NMI or ternal RC network may be used to obtain should be noted that this input should HALT/BA and the function selected is the required timing. have some provision to obtain the determined by the halt control (HC, bit 2) specified logical high level which is bit of the functional control register (loca- Enable (E) greater than standard TTL levels. tion $14). If the HC bit is set (to a'1'), then The E clock input is required for timing to the NMI function is activated. Alternately, synchronize data bus transfers. A 'CPU if HC is cleared (to a '0' as it is during E-cycle' (or bus cycle) consists of a Enable is the primary IPC system timing reset), the HALT/BA function is activated. negative half-cycle of E followed by a signal and all timing data specified as An external pullup resistor to Vcc is re- positive half-cycle. For any given bus cy- cycles is assumed to be referenced to the quired on pin 3 for either function. Typical cle, the address is valid during the clock unless otherwise noted. pullup resistor values range from 3K to

Table 5. STATE OF IPC DURING RESET Bits or Registers Effective State CPU I-Bit set (IRO1 and IRQ2 disabled) NMI Interrupt Latch cleared (NMI disabled) Halt Control Bit cleared (HALT/BA selected) All Data Direction Registers cleared SCI Rate and Mode Control Register cleared Receive Data Register cleared Timer Control and Status Register cleared Free Running Counter cleared Buffer for LSB of Counter cleared Port 3 Control and Status Register cleared Port 2, 3, 4 Data Registers undefined after Power-up Reset and not changed after Reset SCI Transmit/Receive Control and Status Register Preset to $20 Output Compare Register Preset to SFFFF Semaphore Bits Preset to l's Ownership Bit of Semaphore Register 2 Preset to System Ownership All other Ownership Bits Preset to IPC Ownership All Ports 2 and 3 Lines High Impedance (inputs) All Port 4 Lines High Impedance (inputs) with pullup resistors SC1' High Impedance with pullup resistors SC2 Active High "If in mode 5, SC1 will go active high; otherwise it will remain in the high impedance state.

MAX N MIN VCC 1.0 EXTERNAL E STARTUP TIME 101- tPCS -, PCS RESET VIH Pay

INTERNAL ADDRESS BUS xtv IMP alM 4WIMM FFFE FFFE FFFE FFFE' FFFF NEW PC FFFE FFFE INTERNAL R/Vi

INTERNAL DATA BUS SUS 410M PCB-1S MNPCO -7 FIRST INSTRUCTION NOT VALID

*Mode 0 — $BFFE, BFFF Note: Timing measurements are referenced to and from a low voltage of 0.8 volts and a high voltage of 2.0 volts, unless otherwise noted.

Figure 7. Reset Timing

4.60 Signetics MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

10K depending on the drive capability of the external device.

When the NMI function is implemented, pin 3 is configured as an input. A negative edge on pin 3 then requests an IPC non- VCC maskable interrupt sequence, but the cur- 3-10k7 rent instruction will be completed before SN74L574 responding to this request. To assure an PRE interrupt under all conditions, NMI must be held low for at least one E-Cycle. NMI O can be used to cause the IPC to exit the wait instruction. For interrupt timing BA 0 CLK specifications, see Interrupts. CLR • When configured to utilize the HALT/BA function of this pin, such as after reset, SCNB13120/ the circuit of Figure 8 is recommended to SCN68121 detect and supply continuous HALT and SN74LS74 • BA signals. Figure 9 shows the appropriate timing diagram for HALT/BA HALT with the recommended circuit. T. ,e pullup resistor shown in the circuit maintains a 3 PR high logic level when HALT is not active. imILK 0 t HALTIITNINWII During a positive half-cycle of E, pin 3 is CLR SN74L Si 26 an input sampled to determine if the halt state is requested (active low). During the negative half cycle of E, the BA signal is output through pin 3. After the request for halt state signal is detected and the processor completes its current instruction, the CPU is halted and the active low BA signal is output through pin 3 during the negative half cycle of E. The local bus is then available for other devices to utilize Figure 8. HALT/BA Demultiplexing Circuit until the halt state signal has returned to a

VEIH E VIL HALT \\\\\\ —114.1 41- tPCH / / CH

HALT/137 IN 411-6. .44/IN 411-111. .411-144. 411-111. 08-1114. IN/OUT IN IN IN IN IN IN IN IN IN IN IN BA

R/W 411111/11111/ 'WNW ADD/DATA 11011100011004111)11011KNICI>00•01100 DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA

ADD 11111111111111MIIIIIMMIIM*111•11MIIM Ine. FETCH 41101411-EXEC 6+1 HALT FETCH EXEC HALT 114.1441TETCHIP

Figure 9. HALT/BA Timing

Signetics 4.61

MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120ISCN68121

Preliminary

high level, thus allowing the IPC back on from $FFF8 and $FFF9, transferred to the register. The strobe is generated by a read the local bus. During the halt state, R/W is program counter, and instruction execu- (OSS= 0) or write (OSS = 1) to the port 3 high, and the address bus displays the ad- tion is continued at the new location (see data register. 0S3 timing diagram and the dress of the next instruction. Interrupts). IRQ1 typically requires an ex- corresponding electrical specifications ternal resistor (3K to 10K depending on ex- are contained towards the end of this data When single instruction operation is ternal device's drive capability) to Vcc for sheet. desired, in program debug for instance, it wire-OR applications. IRQ1 has no internal is advantageous to single step through in- pullup resistor. Expanded Non•multiplexed Mode—In this structions. After BA goes low, HALT must mode, both SC1 and SC2 are configured be brought high for one E-cycle and Strobe Control (SC1 and SC2) as outputs. SC1 functions as input/output returned low again to single step through The functions of SC1 and SC2 depend on select (I0S) and is asserted (active-low) instructions. Figure 9 illustrates the tim- the operating mode. SC1 is configured as only when addresses $0100 through ing involved while stepping through a an output in all modes except the ex- $01FF are accessed. SC2 is configured as single byte, two bus cycle instruction, panded non-multiplexed mode, whereas R/W and is used to control the direction of such as CLRA. SC2 is always an output. SC1 and SC2 can local data bus transfers. An MPU read is drive one Schottky load and 90pF. enabled when R/W and E are high. BA is not output in response to the wait instruction. If interrupts are to be utilized in Single Chip Modes—In these modes, SC1 Expanded Multiplexed Modes—In these removing the processor from a wait state and SC2 are configured as an input and modes, SC1 is configured as an input and while in the HALT/BA mode, then IRQ1 output, respectively, and both function as SC2 is configured as an output. In the ex- and IRQ2 are the only interrupts which port 3 control lines. SC1 functions as an panded multiplexed modes, the IPC has may do so; therefore, their masks must be input strobe (IS3) and can be used to in- the ability to access a 64K byte address cleared before entering the wait state. dicate that port 3 input data is ready or space. SC1 functions as an input, address output data has been accepted. Three op- strobe, which controls demultiplexing and Maskable Interrupt Request 1 tions associated with IS3 are controlled by enabling of the eight least significant ad- (IRQ1) the control and status register for port 3 dresses and the data buses. This level-sensitive input can be used to (see Port 3 description). request an interrupt sequence. The IPC By using a transparent latch such as a will complete the current instruction SC2 is configured as an output strobe 74LS373, address strobe (AS) can also be before it responds to the request. If the in- (0S3) and can be used to strobe output used to demultiplex the two buses exter- terrupt mask bit (I-bit) in the condition data or acknowledge input data for port 3. nal to the IPC (see Figure 10). SC2 pro- code register is clear, the IPC will begin an It is controlled by output strobe select vides the local data bus control signal call- interrupt sequence: a vector is fetched (OSS) in the port 3 control and status ed read/write (R/W) and is used to control

GND ►

AS ►

EN/G OC DI 01

5N74LS373 PORT 3 IMP (TYPICAL) ADDRESS: AO-A7 ADDRESS/DATA

08 08

DATA: DO-D7

Figure 10. Typical Latch Arrangement

4.62 Signetics MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary the direction of local data bus transfers. data acknowledge signal for asyn- Single Chip Modes—In these modes, port An MPU read is enabled when R/W and E chronous data transfers. As an input, it is 3 is an 8-bit I/O port where each line is con- are high. sampled on the falling edge of CS by the figured by the port 3 data direction IPC to determine if the system bus is be- register. Associated with port 3 are two System Bus Interface ing accessed synchronously or asyn- lines, IS3 and 0S3, which can be used to Port 1 is a mode-independent 8-bit data chronously with respect to the E clock. If control port 3 data transfers. port which permits the external system DTACK is low when sampled, the system bus to access the dual-port RAM and bus is synchronous and data will be Three port 3 options, controlled by the semaphore registers either asynchronous- transferred during E high. If DTACK is port 3 control and status register and ly or synchronously with respect to the E high when sampled, the system bus is available only in the single chip modes clock. In addition to the eight data lines asynchronous. In this mode, DTACK are: port 3 input data can be latched using (SDO-SD7), eight address (SAO-SA7) and becomes an output that is asserted low IS3 as a control signal; 0S3 can be three control lines (SR/W, CS, DTACK) are when data is on the bus during a system generated by either an IPC read or write to used to access the dual-port RAM and read or when a data transfer is completed the port 3 data register; and an IRQ1 inter- semaphore registers. during a system write. rupt can be enabled by an IS3 negative edge. Port 3 timing diagram and cor- Port 1 Data Lines (SDO-SD7)—These data DTACK requires an external pullup responding electrical specifications are 4 lines are bidirectional data lines which resistor when the system bus is run asyn- contained towards the end of this data allow data transfer between the dual-port chronously since it is then a bidirectional sheet. RAM or the semaphore registers, and the handshake line for information transfer on Port 3 Control and Status Register system bus. The data bus output drivers the system data bus. 7 6 5 4. 3 2 1 0 OSS LATCH SOF are three-state devices which remain in 103 153 the high-impedance state except during a DTACK timing diagrams and corre- FLAG 1601 ENABLE ENABLE read of the IPC dual-port RAM or sema- sponding electrical specifications are phore registers by the system processor. contained towards the end of this data Bits 0-2 Not used sheet. Bit 3 Latch enable—This bit controls System Address Lines (SAO-SA7)—The ad- the input latch for port 3. If set, dress lines together with the chip select Port 2 (P20-P24) input data is latched by an IS3 signal allow any of the 128 bytes of RAM Port 2 is a mode independent 5-bit I/O port negative edge. The latch is or six semaphore registers to be uniquely where each line is configured by its data transparent after a read of the selected from the system bus. The ad- direction register. During reset, all lines port 3 data register. Latch dress lines must be valid before the CS are configured as inputs. The TTL com- enable is cleared by reset. signal goes low for the asynchronous in- patible three-state output buffers can Bit 4 OSS (output strobe select)— terface and valid before the E signal goes drive one Schottky TTL load and 30pF, or This bit determines whether 0S3 high for the synchronous interface. The CMOS devices using external pullup will be generated by a read or system interface must be deselected be- resistors. P20, P21 and P22 must always write of t -le port 3 data register. tween reads or between writes for the be connected to provide the operating When clear, the strobe is asynchronous operation. mode. generated by a read; when set, it Port 2 Data Register is generated by a write. OSS is System Read/Write (SR/W)—This signal is cleared by reset. generated by the system bus to control 7 6 5 4 3 2 1 Bit 5 Not used PC2 PC1 PC0 P24Egi P22 D P20 the direction of data transfer on the data sm Bit 6 IS3-IRQ1 enable—When set, an bus. With the IPC selected, a low on the IRQ1 interrupt will be enabled SR/W line enables the input buffers, and Inputs on P20, P21 and P22 determine the whenever IS3 flag is set; when data is transferred from the system pro- operating mode which is latched into the clear, the interrupt is inhibited. cessor to the IPC. When SR/W is high and program counter register on the positive This bit is cleared by reset. the chip is selected, the data output buf- edge of RESET. The mode can be read Bit 7 IS3 flag—This read-only status fers are turned on and data is transferred from the port 2 data register (PC2 is bit is set by an IS3 negative from the IPC to the system bus. latched from pin 45). edge. It is cleared by a read of the port 3 control and status Chip Select (CS)—This signal is a TTL Port 2 also provides an interface for the register (with IS3 flag set) fol- compatible input signal used to activate serial communications interface and lowed by a read or write to port 3 the system bus interface and allows timer. Bit 1, if configured as an output, is data register or by reset. transfer of data between the IPC and the dedicated to the timer output compare system processor during synchronous or function and cannot be used to provide Expanded Non-Multiplexed Mode—In this asynchronous accesses. CS provides the output from the port 2 data register. mode, port 3 is configured as a bi- synchronizing signal for the semaphore directional data bus (D0-D7). The direction registers during access by the system Port 3 (P30-P37) of data transfers is controlled by R/W bus. Port 3 can be configured as an I/O port, a (SC2). Data transfers are clocked by E bidirectional 8-bit data bus, or a multi- (enable). Data Transfer Acknowledge (DTACK)— plexed address/data bus depending on the This bidirectional control line is used to operating mode. The TTL compatible Expanded Multiplexed Modes—In these determine synchronous or asynchronous three-state output buffers can drive one modes, port 3 is configured as a time- system bus accesses and to provide the Schottky TTL load and 90pF. multiplexed address (A0-A7) and data bus Signetics 4.63 MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

(DO-D7). Address strobe (AS) must be input Table 6. SIGNAL SUMMARY on SC1, and can be used externally to demultiplex the two buses. Port 3 is held Signal Name Mnemonic Input/Output Active State Three State in a high-impedance state between valid System Address Bus SAO-SA7 input/output high no address and data to prevent potential bus System Data Bus SDO-SD7 input/output high yes conflicts. System Read/Write SR/W input read-high — write-low Port 4 (P40•P47) Chip Select CS input low — Port 4 is configured as an 8-bit I/O port, as Data Transfer DTACK input/output low yes address outputs, or as data inputs Acknowledge depending on the operating mode. Port 4 Strobe Control #1 SC1 output high yes can drive one Schottky TTL load and 90pF Strobe Control #2 SC2 input high — and is the only port with internal pullup Enable E input high — resistors. Reset RESET input low — Interrupt Request 1 IRQ1 input low — Single Chip Modes—In these modes, port Halt, Bus Available, 4 functions as an 8-bit I/O port where each Non-maskable Interrupt HALT/BA/NMI input/output low yes line is configured by the port 4 data direc- I/O Port 2 P20-P24 input/output high yes tion register. Internal pullup resistors I/O Port 3 P30-P37 input/output high yes allow the port to directly interface with I/O Port 4 P40-P47 input/output high yes CMOS at 5 volt levels. External pullup Ground Vss input — — resistors to more than 5 volts, however, Power Input input — — cannot be used. Vcc

Expanded Non-Multiplexed Mode—In this mode, port 4 is configured from reset as and expanded multiplexed. Single chip in- cant on-chip resources. Port 3 functions an 8-bit input port, where the data direc- cludes modes 4 and 7, expanded non- as an 8-bit bi-directional data bus and port tion register can be written to provide any multiplexed is mode 5 and the remaining 4 is configured as an input data port. Any or all of address lines AO-A7. Internal five are expanded multiplexed modes. A combination of AO to A7 can be provided pullup resistors are intended to pull the system utilizing three SC68120's, one in while retaining the remainder as input lines high until the data direction register each of the fundamental operating modes, data lines. Any combination of the eight is configured. is shown in Figure 11. Table 7 summarizes least-significant address lines can be ob- the characteristics of the operating tained by writing to the port 4 data direc- Expanded Multiplexed Mode—In all of modes. tion register. Internal pullup resistors are these modes, except mode 6, port 4 func- provided to pull port 4 lines high until it is tions as half of the address bus and pro- configured. Single Chip Modes (4, 7)— In single chip vides A8 to A15. In mode 6, the port is con- mode, three of the four IPC ports are configured from reset as an 8-bit parallel input Figure 13 illustrates the external re- figured as parallel input/output data ports, port; the port 4 data direction register sources available in the expanded non- as shown in Figure 12. The IPC functions must be written to provide any or all of ad- multiplexed mode. The IPC interfaces as a complete microcomputer in these two dress lines A8 to A15. Internal pullup directly with the Motorola M6800 family modes without external address or data resistors are intended to pull the lines parts (or parts with equivalent interfaces) buses. A maximum of 21 I/O lines and two high until the data direction register is and can access 256 bytes of external ad- port 3 control lines are provided. configured (bit 0 controls A8, etc.) dress space at $100 through $1FF. IOS provides an address decode of external In single chip test mode (4), the RAM Signal Summary memory ($100-$1FF) and can be used as responds to addresses $XX80 (X= don't Table 6 is a summary of all the signals an address or chip select line. care) through $XXFF and the ROM is discussed in the previous paragraphs. removed from the internal address map. A Expanded Multiplexed Modes (0, 1, 2, 3, test program must first be loaded into 6)—In the expanded multiplexed modes, RAM using modes 0, 1, 2, or 6. If the IPC is OPERATING MODES the IPC has the ability to access a reset and then programmed into mode 4, The IPC provides eight different operating 64K-byte memory space. Port 3 functions execution will begin at $XXFE:XXFF. modes which are selectable by hardware as a time-multiplexed address/data bus Mode 5 can be irreversibly entered from programming and referred to as modes 0 with the address valid on the negative mode 4 without going through reset by through 7. The operating mode controls edge of address strobe (AS) and the data setting bit 5 of the port 2 data register. the memory map, configuration of port 3, bus valid while E is high. In modes 0 to 3, This mode is used primarily to test port 3 port 4, SC1 and SC2, and the address loca- port 4 provides address lines A8-A15. and 4 in the single chip and non- tion of the interrupt vectors. However, in mode 6, port 4 can provide any multiplexed modes. subset of A8 to A15 while retaining the re- Fundamental Modes mainder as input lines. Writing l's to the The eight modes of the IPC can be Expanded Non-Multiplexed Mode (5)—A desired bits in the data direction register grouped into three fundamental modes modest amount of external memory space (DDR) will output the corresponding ad- which refer to the type of bus it supports; is provided in the expanded non- dress lines while the remaining bits will re- single chip, expanded non-multiplexed, multiplexed mode while retaining signifi- main inputs (as configured from reset or

4-64 Signetics MICROPROCESSOR DIVISION JANUARY 1983

INTELLIGENT PERIPHERAL CONTROLLER SCN68120ISCN68121

Preliminary

SCN68000, M68000, OR MICROPROCESSOR WITH EQUIVALENT SYNCHRONOUS INTERFACE

21 00

RAM SCN68120 SINGLE CHIP MODE

10110

SCN68120 ROM

ADDRESS EXPANDED PERIPHERALS NON-MULTIPLEXED MODE DATA SYSTEM BUS

5 I/0 EXPANDED SCN68120/SCN68121 MULTIPLEXED MODE

ROM

LOCAL BUS 0 RAM

PERIPHERALS

Figure 11. IPC Fundamental Operating Modes

Signetics 4.65 MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary Table 7. SUMMARY OF IPC OPERATING MODES

Common to all Modes: Expanded Multiplexed Modes System Bus Interface Four Memory Space Options 164K Address Space): Reserved Register Area 111 MOOS Compatible 6 Semaphore Registers (21 No ROM I/O Port 2 (31 External Vector Space Programmable Timer 14) ROM with Partial Address Bus* Serial Communications Interface External Memory Space Accessed Through: 128 bytes of Dual Ported RAM Port 3 as a Multiplexed Address/Data Bus Single Chip Mode* Port 4 as an Address Bus (High) 2048 Bytes of ROM (Internal) SC1 is Address Strobe Bus IASL Input Port 3 is a Parallel I/O Port with Two Control Lines SC2 is Read/Write (R/WI Port 4 is a Parallel I/O Port SC1 is Input Strobe 3 (IS3/ Test Modes SC2 is Output Strobe 3 1OS3I Expanded Multiplexed Test Mode May be Used to Test RAM and ROM' Expanded Non-Multiplexed Mode* Single Chip and Non-Multiplexed Test Mode* 2048 Bytes of ROM (Internal) May be Used to Test Ports 3 and 4 as I/O Ports 256 Bytes of External Memory Space Port 3 is an 8-Bit Data Bus Port 4 is an Address Bus SC1 is Input/Output Select (10S) SC2 is Read/Write IR/W1 •SCN68120 only

Ypc

RESET SCN68120 ► HALTUMMI IR01

PORT 3 8 SYSTEM 8 I/O LINES ADDRESS LINES

PORT 1 8 SYSTEM SYSTEM DATA LINES BUS

••• SRIW

PORT 4 DTACK 8110 LINES PORT 2 5 I/O LINES SERIAL I/O, 16-BIT TIMER

Figure 12. Single Chip Mode

4.66 Signetics MICROPROCESSOR DIVISION JANUARY 1983

INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

Vic

E RESET SCN68120

.01 IR 1

PORT 3 i> 8 SYSTEM 8 DATA LINES I ADDRESS LINES

> PORT 1 RIW 8 SYSTEM SYSTEM DATA LINES BUS

IOS 411 SRIW

PORT 4 fo. T.W07. 8 ADDRESS LINES <1_1> PORT 2 5 I/0 LINES SERIAL 110, 16-BIT TIMER

Figure 13. Expanded Non-Multiplexed Mode

from O's written to the DDR). Internal ing the positive edge of RESET. These are INTERRUPTS pullup resistors are provided to pull port 4 latched into PC2, PC1, and PCO of the pro- lines high until software configures the gram control register. The operating mode The IPC supports two types of interrupt report. Initialization of port 4 in mode 6 must can be read from the port 2 data register quests: maskable and non-maskable. A be done to obtain any upper address lines and programming levels and timing must non-maskable interrupt (NMI) is always externally. be met as shown in Figure 15 and Table 8. recognized and acted upon at the comple- A brief outline of the operating modes in tion of the current instruction. Maskable Figure 14 depicts the external resources shown in Table 9. interrupts are controlled by the condition available in the expanded multiplexed code register I-bit and by individual enable modes. Address strobe can be used to Circuitry to provide the programming bits. The I-bit controls all maskable inter- control a transparent D-type latch to cap- levels is primarily dependent on the nor- rupts. Of the maskable interrupts, there ture addresses A0-A7, as shown in figure mal system use of the three pins. If con- are two types: IRQ1 and IRQ2. The pro- 10. This allows port 3 to function as a data figured as outputs, the circuit shown in grammable timer and serial communica- bus when E is high. Figure 16 can be used; otherwise, three- tions interface use an internal IRQ2 inter- state buffers can be used to provide isola- rupt line, as shown in the block diagram of In mode 0, the reset vector is external at tion while programming the mode. the IPC. External devices (and IS3) use $BFFE and $BFFF after the positive edge IRQ1. An IRQ1 interrupt is serviced before of RESET. In addition, the internal and ex- an IRQ2 interrupt if both are pending. ternal data buses are connected together MEMORY MAPS so there must be no memory map overlap The IPC provides up to 64K bytes of ad- (to avoid potential bus conflicts). Mode 0 dress space depending on the operating is used primarily to verify the ROM pattern mode. A memory map for each operating All IRQ2 interrupts use hardware priori- and monitor the internal data bus with mode is shown in Figure 17. In modes 1R tized vectors. The single SCI interrupt and automated test equipment. and 6R, the R means the ROM has been three timer interrupts are serviced in a relocated by a mask option. The first 32 prioritized order where each is vectored to MODE PROGRAMMING locations of each map are reserved for the a separate location. All IPC vector loca- The operating mode is programmed by the IPC internal register area, as shown in tions are shown in Table 11, from highest levels asserted on P22, P21, and P20 dur- Table 10, with exceptions as indicated. (top) to lowest (bottom) priority. Signetics 4.67 MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

Vcc

RESET HALTraRTA SCN68120/ SCN68121 11101

PORT 3 8 LINES MULTIPLEXED 8 SYSTEM ADDRESS/DATA ADDRESS LINES

PORT 1 8 SYSTEM SYSTEM DATA LINES BUS

AS SRIW

CS PORT 4 <=> 8 ADDRESS LINES

PORT 2 5110 LINES SERIAL 110, 16.131T TIMER

Figure 14. Expanded Multiplexed Mode

VIH RESET VIL PWRSTL 1MPH IMPS MODE INPUTS VMPH MIN DATA VALID (P20, P21, P22) VM PL VMPL MAX

SEE FIGURE 16 FOR DIODE ARRANGEMENT VMPDD

VMPL (P20, P21, P22) MODE LATCH LEVEL

RESET —

Figure 15. Mode Programming Timing

4.68 Signetics MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

Table 8. MODE PROGRAMMING SPECIFICATIONS (See Figure 15)

Characteristic Symbol Min Typ Max Unit

Mode Programming Input Voltage Low VMPL — 1.8 V Mode Programming Input Voltage High VmpH 4.0 — V

Mode Programming Diode Differential if Diodes are Usedl VMPDD 0.6 — V RESET Low Pulse Width PWRSTL 3.0 — — [-Cycles Mode Programming Setup Time tMpS 2.0 — E-Cycles Mode Programming Hold Time RESET Rise Time. 1 As tMPH 0 — — ns RESET Rise Time< 1 iLs 100 —

Table 9. MODE SELECT SUMMARY

Pin 45 Pin 44 Pin 43 Interrupt Bus Operating Mode P22 P21 P20 ROM RAM Vectors Mode Mode PC2 PC1 PCO 7 H H H I I I I Single Chip 6 H H L I I I MUX15, 6> Multiplexed/Partial Decode(5) 5 H L H I I I NMUX15, 61 Non-Multiplexed/Partial Decode(5) 4 H L L 1 121 l (1) I I Single Chip Test 3 L H H E 1 17) E MUX(4) Multiplexed/RAM(4) 2 L H L E I E MUX(4) Multiplexed/RAM(4) 1 L L H I I E MUX(4) Multiplexed/RAM and ROM (4) 0 L L L I I E131 MUX141 Multiplexed Test(4)

Legend: Notes: I — Interna 111 Internal RAM is addressed at 8XX80 E — External 121 Internal ROM is disabled MUX — Multiplexed 131 Interrupt vectors externally located at $13FFO-SBEFF NMUX — Non-Multiplexed 141 Addresses associated with Ports 3 and 4 are considered external in Modes 0, 1, 2, and 3 L — Logic "0" 151 Addresses associated with Port 3 are considered external in Modes 5 and 6 H — Logic "1" 161 Port 4 default is user data input; address output is optional by writing to Port 4 Data Direction Register 171 Internal RAM and registers located at SCOXX (for use with MOOS)

Table 10. INTERNAL REGISTER AREA

Address**** Address**** Register Register (Hexadecimal) (Hexadecimal) Reserved 00 SCI Rate and Mode Control Register 10 Port 2 Data Direction Register*" 01 Transmit/Receive Control and Status Register 11 Reserved 02 SCI Receive Data Register 12 Port 2 Data Register 03 SCI Transmit Data Register 13 Port 3 Data Direction Register*** 04* Port 4 Data Direction Register•" 05•• Function Control Register 14 Port 3 Data Register 06* Counter Alternate Address (High Byte) 15 Port 4 Data Register 07" Counter Alternate Address (Low Byte) 16 Timer Control and Status Register 08 Semaphore 1 17 Counter (High Byte) 09 Semaphore 2 18 Counter ILow Byte) OA Semaphore 3 19 Output Compare Register (High Byte) 08 Semaphore 4 1A Output Compare Register (Low Byte) OC Semaphore 5 1B Input Capture Register (High Bytel OD Semaphore 6 1C Input Capture Register ILow Byte) OE Reserved 1D-1F Port 3 Control and Status Register OF* *These external addresses in Modes 0, 1, 2, 3, 5, 6 cannot be ac- •••1 = Output, 0= Input cessed in Mode 5 Ino 10S1. ****These addresses relocated at $C000-SCO1F in Mode 3. **These are external addresses in Modes 0, 1, 2, 3. Signetics 4.69

MICROPROCESSOR DIVISION JANUARY 1983

INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

SCN681201 2 SCN68121

48 RESET ast RESET 43 P20 411: I P20 (PC0) 44 P21 111 P21 (PC1) 45 P22 41111 P22 (PC2) L_-J OPTIONAL I THREE-STATE BUFFERS MODE CONTROL SWITCHES

Notes: 1. Mode 7 as shown Dj 2. R2•C = Reset time constant 3. R1 = 10k (typical) 4. D= 1N914, 1N4001 (typical) • C I

Figure 16. Typical Mode Programming Circuit

The interrupt flowchart is shown in Figure Timer Control and a match has been found between the free- 18. The program counter, index register, Status Register ($08) running counter and the output compare accumulator A, accumulator B, and condi- The timer control and status register register, or that the free-running counter tion code register are pushed to the stack. (TCSR) is an 8-bit register of which all bits has overflowed. The I-bit is set to inhibit maskable inter- are readable, while bits 0-4 can be written. rupts and a vector is fetched corrrespond- The three most significant bits provide the Each of the three events can generate an ing to the current highest priority inter- timer status and indicate that a proper IRQ2 interrupt and is controlled by an in- rupt. The vector is transferred to the pro- level transition has been detected, or that dividual enable bit in the TCSR. gram counter and instruction execution is resumed. The general interrupt timing se- Table 11. MCU VECTOR LOCATIONS* quence is shown in Figure 19. The interrupt HALT/BA timing is illustrated in MSB LSB Interrupt Figures 8 and 9. SFFFE FFFF RESET" FFFC FFFD NMI FFFA FFFB Software Interrupt ISWII PROGRAMMABLE TIMER FFF8 FFF9 IR01 (or IS3) The programmable timer can be used to FFF6 FFF7 ICF (Input Capture) perform input waveform measurements FFF4 FFF5 OCF (Output Compare) while independently generating an output waveform. Pulse widths can vary from FFF2 FFF3 TOF (Timer Overflow) several microseconds to many seconds. A FFFO FFF1 SCI (RDRF+ORFE+TDREI block diagram of the timer is shown in *These locations are relocated at $BFFO-$BFFF in Mode 0. Figure 20. **Highest prio ity.

4.70 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

SCN88120 MODE MULTIPLEXED TEST MODE 0

$0000 INTERNAL REGISTERS 0001F EXTERNAL MEMORY SPACE

$0080 NOTES 1. Excludes the following addresses which may be used exter- INTERNAL RAM nally: $04, $05, $06, $07 and $OF. 2. The interrupt vectors are externally located at $BFF0- $00FF $BFFF. 3. There must be no overlapping of internal and external memory spaces to avoid driving the data bus with more than one EXTERNAL MEMORY SPACE device. 4. This mode is the only mode which may be used to examine the interrupt vectors in internal ROM using an external $8 FF0 RESET vector. EXTERNAL INTERRUPT VECTORS(2) 5. SCN68120 only. $BFFF EXTERNAL MEMORY SPACE $F800

INTERNAL ROM(8)

$FFFF(2)

SCN88120 SCN88120 MODE MODE

MULTIPLEXED/RAM AND ROM MULTIPLEXED/RAM AND ROM

$0000 $0000 INTERNAL REGISTERS(1) //, INTERNAL REGISTERS(1) $001F $001F EXTERNAL MEMORY SPACE EXTERNAL MEMORY SPACE $0080 $0080 vA INTERNAL RAM INTERNAL RAM $00FF $00FF

EXTERNAL MEMORY SPACE EXTERNAL MEMORY SPACE $X800 r INTERNAL ROO) $F800 /A $XFFF INTERNAL ROM EXTERNAL MEMORY SPACE EFFEF $FFFO EFFF0 EXTERNAL INTERRUPT VECTORS(2) EXTERNAL INTERRUPT VECTORS EFFFF $FFFF

NOTES NOTES 1. Excludes the following addresses which may be used exter- 1. Excludes the following addresses which may be used externally: $04, $05, $06, $07 and $0F. nally: $04, $05, $06, $07 and $0F. 2. Internal ROM addresses $FFFO to $FFFF are not usable. 2. Starting addresses for the internal ROM may be $C800, $D600 or $E800 as a mask option.

Figure 17. IPC Memory Maps

Signetics 4.71

M ICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

MULTIPLEXEDIRAM, MDOS COMPATIBLE(1) SCN68120/ SCN68120/ SCN68121 $0000 SCN68121 MULTIPLEXEDIRAM MODE MODE

$0000 INTERNAL REGISTERS(1) $001F EXTERNAL MEMORY SPACE EXTERNAL MEMORY SPACE

$0080 INTERNAL RAM vA $C000 $00FF INTERNAL REGISTERS(2) SCO1F

EXTERNAL MEMORY SPACE

$C060 > EXTERNAL MEMORY SPACE 7 A INTERNAL RAM SCOFF

EXTERNAL MEMORY SPACE

$FFFO EXTERNAL INTERRUPT VECTORS $FFFO $FFFF EXTERNAL INTERRUPT VECTORS $FFFF NOTES 1. Relocating the internal registers and the internal RAM to high memory allows NOTES processor to run MDOS. 1. Excludes the following addresses which may be used externally: $04, $05, $06, 2. Excludes the following addresses which may be used externally: $C004, $0005, $07 and $0F. $C006, $0007 and $000F.

SCN68120 SCN68120 MODE MODE SINGLE CHIP TEST(2) 4 NON-MULTIPLEXEDIPARTIAL DECODE(2X3) 5 50000(1) 0 }INTERNAL REGISTERS ) INTERNAL REGISTERS(5) $001F 0001F v UNUSABLE $0080

INTERNAL RAM 500FF $0100 EXTERNAL MEMORY SPACE $01 FF UNUSABLE(1")

UNUSABLE

$F800

INTERNAL ROM $XX80(3) /A INTERNAL RAO ) INTERNAL INTERRUPT VECTORS INTERNAL INTERRUPT VECTORS $XXFF $FFFF NOTES NOTES 1. The internal ROM is disabled. 1. Excludes th following addr sses which may not be used externally: $04, $06 2. Mode 4 may be changed to Mode 5 without having to assert RESET by writing a and $OF (no OS). "1" into bit 5 (PCO) of Port 2 Data Register. 2. This mode may be entered w•thout going through Reset by using Mode 4 and 3. Addresses A8 to A15 are treated as "don't cares" to decode internal RAM. subsequent) writing a "1" into bit 5 (PCO) of Port 2 Data Register. 4. Internal RAM will appear at $XX80 to $XXFF. 3. Address line AO to A7 will not contain addresses until the Data Direction Regis- 5. MPU read of Port 3 Data Direction Register will access Port 3 Data Register ter for Port has been written with "1"s In the appropriate bits. These address instead. lines will as ert "1"s until made outputs by writing the Data Direction Register.

Figure 17. IPC Memory Maps (Continued)

4.72 Signetics MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

R SCN68120 SCN68120 6 MODE MODE

MULTIPLEXED/PART AL DECODE MULTIPLEXED/PARTIAL DECODE $0000 tr/ $0000 y / INTERNAL REGISTERS(1N2) Z INTERNAL REGISTERS 1N2) $001F /46 $001F EXTERNAL MEMORY SPACE EXTERNAL MEMORY SPACE $0080 x $0080

( // INTERNAL RAM 7///2/ INTERNAL ROM(3) $00FF 6 SOOFF

EXTERNAL MEMORY SPACE

8X800(3) V

/^ INTERNAL ROM(3)

SF808pize $XFFF

EXTERNAL MEMORY SPACE INTERNAL ROM SFFF0

EXTERNAL INTERRUPT VECTORS // 1 /4 INTERNAL INTERRUPT VECTORS SFFFF • SFFFF NOTES NOTES 1. Excludes the following addresses which may be used externally: $04, $06, $0F. 1. Excludes the following addresses which may be used externally: $04, $06, $OF. 2. Address lines A8-A15 will not contain addresses until the Data Direction Regis- 2. Address lines A8-A15 will not contain addresses until the Data Direction Regis- ter for Port 4 has been written with "1"s in the appropriate bits. These address ter for Port 4 has been written with "1"s in the appropriate bits. These address lines will assert "1"s until made outputs by writing the Data Direction Register. lines will assert "1"s until made outputs by writing the Data Direction Register. 3. Starting addresses for the internal ROM may be $C800, $D800 or $E800.

SCN68120 7 MODE

SINGLE CHIP y $0000 (1) /,)INTERNAL REGISTERS $001F UNUSABLE $0080 :://, A} INTERNAL RAM $00FF NOTES 1. MPU reads of Port 3's Data Direction Register will access Port 3's Data Register instead.

UNUSABLE

$F :/:/// } 1

INTERNAL ROM

NTERNAL INTERRUPT VECTORS SFFFF /

Figure 17. IPC Memory Maps (Continued)

Signetics 4.73

erru nt I . 18 gure Fi rt rt a owch Fl pt • • MODES 1-7 MODE 0 0 0 BA V 1 HALT CONTROL;1---.I ( RESET VECTOR -.PC BA; 1 RESET RESET BFFE-BFFF TIMP; FFFE-FFFF ITMP OPCODE FETCH I 4fr ITMP EXECUTE OPCODE FETCH O I IMEICIUMIGIUB CONDITION CODEREGISTER STACK MACHINESTATE PC, X,A,B,CC ITMP a 1 NMI TOF IRQ1 SWI OCF ICF SCI CONTROL HALT BFF6-BFF7 BFF8-BFF9 BFFA-BFFB BFF4-BFF5 BFF2-BFF3 BFFC-BFFD BFFO-BFF1 MODE 0 1 1 FFFO-FFF1 FFF2-FFF3 FFFC-FFFD FFFA-FFFB MODES1-7 FFF4-FFF5 FFF8-FFF9 FFF6-FFF7 ITMP I VECTOR -.PC WAI MASKABLE INTERRUPTREQUEST1 SOFTWARE INTERRUPT SCI INTERRUPT(TDRE+ RDRF+ORFE) TIMER OVERFLOWINTERRUPT INPUT CAPTUREINTERRUPT OUTPUT COMPAREINTERRUPT NON-MASKABLE INTERRUPT SCI= TIE_TDRI+RIE_(RDRFORFE) V a 5 3 cp

1Z689NOS/OZ1,99NOS d3110211N00 1V213Hd1213d 1N3011131NI

£86 /WINN(' NOISIAIGelOSS300e1c10dOIN MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

4.1 CYCLE LAST INSTRUCTION #4 #6 47 #9 I 112 #2 #3 #8 #10 _ F 1-BIT SET INTERNAL ADDRESS BUS 1/ ------MIMI MD - - OP CODE OP CODE SPInl SP10 SPIn 21 SPIn SPIn SPlo SPOI SI SPIn 71 VECTOR VECTOR NEW PC ADDR ADDR r- 1 MSB ADDR LSB ADDR ADDRESS IRO1

t PSC

NW or IRO2 --WI tPCS FIRST INST OF INTERRUPT ROUTINE INTERNAL DATA BUS 4111111M11 1=111111111111114111111 MEI 5 ACCA ACCB CCR IRRELEVANT VECTOR VECTOR OP CODE OP CODE PC0.7 PC8 15 X 0 7 X 8 LSB +1 DATA MSB INTERNAL RAT

Figure 19. Interrupt Sequence

SCN68120/SCN68121 INTERNAL BUS

$013:0C 69:0A ($15.16) SOD.OF

OUTPUT COMPARE FREE RUNNING INPUT CAPTURE REGISTER 16.BIT COUNTER REGISTER

OVERFLOW OUTPUT COMPARE EDGE DETECT DETECT

0 OUTPUTLEELV ICF OCFI TOF

TIMER REGISTER CONTROL AND STATUS REGISTER BIT 1 SOB PORT 2 DDR

OUTPUT COMPARE PULSE I OUTPUT INPUT LEVEL EDGE BIT 1 BIT 0 PORT 2 PORT 2

Figure 20. Programmable Timer— Block Diagram

Signetics 4.75 MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

Timer Control and Status Register (TSCR) Counter ($09:0A) mark/space (NRZ) and bi-phase. Both for- The key timer element is- a 16-bit free- mats provide one start bit, eight data bits, 7 6 5 4 3 2 1 running counter which is incremented by and one stop bit. Baud and bit rate are ICF I OCF I TOF I EICI I EOCI I ET01 I IEDGI MVI $08 E (enable). It is cleared during reset and is used synonymously in the following a read-only with one exception: a write to description. OLVL Output level—OLVL is clocked to the counter ($09) will preset it to $FFF8. the output level register by a suc- This feature, intended for testing, can Wake-Up Feature cessful output compare and will disturb serial operations because the In a typical serial loop multiprocessor con- appear at P21 if bit 1 of the port 2 counter provides the SCI internal bit rate figuration, the software protocol will data direction register is set. It is clock. TOF is set whenever the counter usually identify the addressee(s) at the cleared by reset. contains all l's. The counter can also be beginning of the message. In order to read at locations $15 and $16 to avoid the IEDG Input edge—IEDG is cleared by allow uninterested MPUs to ignore the re- clearing of the TOF. reset and controls which level mainder of the message, a wake-up fea- transition will trigger a counter ture is included whereby all further SCI transfer to the input capture Output Compare Register receiver flag (and interrupt) processing register: ($OB:OC) can be inhibited until the data line goes IEDG= 0 transfer on a negative The output compare register is a 16-bit idle. An SCI receiver is reenabled by an edge read/write register to control an output idle string of ten consecutive l's or by IEDG = 1 transfer on a positive waveform or provide an arbitrary timeout reset. Software must provide the required edge flag. It is compared with the free-running idle string between consecutive mes- counter on each E-cycle. When a match is sages and prevent it within messages. ETOI Enable timer overflow interrupt— found, OCF is set and OLVL is clocked to When set, an IRQ2 interrupt is an output level register. If port 2, bit 1 is enabled for a timer overflow; when configured as an output, OLVL will appear Programmable Options clear, the interrupt is inhibited. It at P21. The output compare register and The following features of the SCI are pro- is cleared by reset. OLVL can then be changed for the next grammble: compare. The compare function is in- — Format: standard mark/space (NRZ) or EOCI Enable output compare inter- hibited for one cycle after a write to the bi-phase rupt—When set, an IRQ2 interrupt high byte of the counter (SOB) to ensure a — Clock: External or internal clock source is enabled for an output compare; valid compare. The output compare — Baud rate: One of four per E-clock fre- when clear, the interrupt is in- register is set to $FFFF by reset. quency or one-eighth of the external hibited. It is cleared by reset. clock input to P22 — Wake-up features: enabled or disabled EICI Enable input capture interrupt— Input Capture Register ($OD:OE) — Interrupt requests: enabled individually When set, an IRQ2 interrupt is The input capture register is a 16-bit read- for transmitter and receiver enabled for an input capture; only register used to store the free- — Clock output: internal bit rate clock when clear, the interrupt is in- running counter when a 'proper' input enabled or disabled to P22 hibited. It is cleared by reset. transition occurs as defined by IEDG. Port 2, bit 0 should always be configured as an TOF Timer overflow flag —TOF is set input, but the edge detect circuit always Serial Communications Registers when the counter contains all l's. senses P20, even when configured as an The SCI includes four addressable regis- It is cleared by reading the TCSR output. An input capture can occur in- ters as depicted in Figure 21. It is con- (with TOF set) followed by reading dependently of ICF: the input capture trolled by the rate and mode control the highest byte of the counter register always contains the most current register and the transmit/receive control ($09), or by reset. Reading the value regardless of whether ICF was and status register. Data is transmitted counter at $15 will not clear TOF. previously set or not. Counter transfer is and received utilizing a write-only transmit inhibited, however, between accesses of a OCF Output compare flag—OCF is set register and read-only receive register. double byte IPC read. The input pulse when the output compare register The shift registers are not accessible by width must be at least two E-cycles to en- matches the free-running counter. software. sure an input capture under all conditions. It is cleared by reading the TCSR Rate and Mode Control Register ($10)— (with OCF set) and then writing to SERIAL COMMUNICATIONS the output compare register ($0B The rate and mode control register or $0C), or by reset. INTERFACE (RMCR) controls the SCI baud rate, for- A full-duplex asynchronous serial com- mat, clock source, and under certain con- ICF Input capture flag—ICF is set to munications interface (SCI) is provided ditions, the configuration of P22. The indicate a proper level transition. with two data formats and a choice of register consists of four write-only bits It is cleared by reading the TCSR baud rates. The SCI transmitter and which are cleared by reset. The two least (with ICF set) and then reading the receiver are functionally independent, but signficant bits control the baud rate of the input capture register high byte use the same data format and bit rate. internal clock and the remaining two bits ($0D), or by reset. Serial data formats include standard control the format and clock source.

4.76 Signetics MICROPROCESSOR DIVISION JANUARY 1983

INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

BIT 7 RATE AND MODE CONTROL REGISTER BIT 0

CC1 CC0 SS1 SSO 510

TRANSMIT/RECEIVE CONTROL AND STATUS REGISTER

RDRF ORFE TDRE RIE RE TIE TE WU $11

RECEIVE DATA REGISTER

512

PORT 2 (NOT ADDRESSABLE) RX 46 BIT 416 RECEIVE SHIFT REGISTER 3

CLOCK 45 BIT RATE BIT GENERATOR E 2

(NOT ADDRESSABLE)

TRANSMIT SHIFT REGISTER

TX 47 BIT 4

413

TRANSMIT DATA REGISTER

Figure 21. SCI Registers

Table 12. SCI BIT TIMES AND RATES SS1:SSO E 614.4 kHz 1.0 MHz 1.2288 MHz 0 0 .- 16 26 As/38,400 Baud 16 As/62,500 Baud 13.0 As/76,800 Baud 0 1 .- 128 208 As/4,800 Baud 128 As/7812.5 Baud 104.2 As/9,600 Baud 1 0 .- 1024 1.67 ms/600 Baud 1.024 ms/976.6 Baud 833.3 As/1,200 Baud 1 1 --4096 6.67ms/150 Baud 4.096 ms/244.1 Baud 3.33 ms/300 Baud

Table 13. SCI FORMAT AND CLOCK SOURCE CONTROL Clock Port 2 CC1:CCO Format Source Bit 2 0 0 Bi-Phase Internal Not Used 0 1 NRZ Internal Not Used 1 0 NRZ Internal Output 1 1 NRZ External Input

Signetics 4.77 MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

Rate and Mode Control Register (RMCR) TE Transmit enable—When set, the Serial Operations P24 DDR bit is set, cannot be The SCI is initialized by writing the control 7 6 5 4 3 2 1 0 changed, and will remain set if TE bytes first to the rate and mode control X X X X CC1 CCO SS1 SSC 51c is subsequently cleared. When TE register and then to the transmit/receive is changed from clear to set, the control and status register. When TE is transmitter is connected to P24 set, the output of the transmit shift SS1:SSO Speed Select—These two bits and a preamble of nine con- register is connected to P24 and serial select the baud rate when us- secutive l's is transmitted. TE is output is initiated by the transmission of a ing the internal clock. Four cleared by reset. 9-bit preamble of l's. At this point, if the rates may be selected which TIE Transmit interrupt enable—When transmit data register (TDRE) is empty are a function of the IPC input set, an IRQ2 interrupt is enabled (TDRE= 1), a continuous string of l's will frequency (E). Table 12 lists bit when TDRE is set; when clear, the be sent indicating an idle line, or if a byte times and rates for three interrupt is inhibited. TIE is has been written to the TDRE (TDRE= 0), selected IPC frequencies. cleared by reset. the byte will be transferred to the transmit CC1:CC0 Clock control and format RE Receive enable—When set, the shift register (synchronized with the bit select—These two bits control P23 DDR bit is cleared, cannot be rate clock), TDRE will be set and transmis- the format and select the serial changed, and will remain clear if sion will begin. clock source. If CC1 is set, the RE is subsequently cleared. While data direction register (DDR) RE is set, the SCI receiver is The start bit (0), eight data bits (beginning value for P22 is forced to the enabled. RE is cleared by reset. with bit 0) and a stop bit (1), will be complement of CCO and cannot RIE Receiver interrupt enable—When transmitted. If TDRE is still set when the be altered until CC1 is cleared. set, an IRQ2 interrupt is enabled next byte transfer should occur, l's will be If CC1 is cleared after having when RDRF and/or ORFE is set; sent until more data is provided. Receive been set, its DDR value is un- when clear, the interrupt is in- operation is controlled by RE which con- changed. Table 13 defines the hibited. RIE is cleared by reset. figures P23 as an input and enables the format, clock source, and the TDRE Transmit data register empty— receiver. In bi-phase format, the output use of P22. TDRE is set when the contents of toggles at the start of each bit and at half the transmit data register is time when a '1' is sent. SCI data formats If both CC1 and CCO are set, an external transferred to the output serial are illustrated in Figure 22. In receiving bi- TTL compatible clock must be connected shift register or by reset. It is phase, a'1' is input when two transitions to P22 at eight times (8X) the desired baud cleared by reading the TRCSR occur in less than 3/4 bit-time, and a '0' is rate, but not greater than E, with a duty cy- (with TDRE set) and then writing input when more than 3/4 bit-time passes cle of 50% (± 10%). If CC1:CCO= 10, the to the transmit data register. Ad- after a transition on P23. internal baud rate clock is provided at P22 ditional data will be transmitted regardless of the values for TE or RE. only if TDRE has been cleared. ORFE Overrun framing error—If set, NOTE: ORFE indicates either an overrun The source of the SCI internal baud rate INSTRUCTION SET or framing error. An overrun oc- clock is the free-running counter of the The SCN68120/SCN68121 is upward source curs when a new byte is ready to and object code compatible with the timer. An IPC write to the counter can transfer to the receiver data Motorola MC6800 processor and directly disturb serial operations. register with RDRF still set. A compatible with the M6801 family pro- receiver framing error has oc- cessors. Transmit/Receive Control and Status curred when the byte boundaries Register ($11)—The transmit/receive con- of the bit stream are not synchro- Programming Model trol and status register (TRCSR) controls nized to the bit counter. An over- A programming model for the SCN68120/ the transmitter, receiver, wake-up run can be distinguished from a SCN68121 is shown in Figure 1. Ac- features, and two individual interrupts and framing error by the value of cumulator A can be concatenated with ac- monitors the status of serial operations. RDRF: if RDRF is set, then an cumulator B and jointly referred to as ac- All eight bits are readable while only bits 0 overrun has occurred; otherwise, cumulator D, where A is the most signifi- to 4 are writable. The register is initialized a framing error has been cant byte. Any operation which modifies to $20 by reset. detected. Data is not transferred the double accumulator will also modify to the receive data register in an accumulator A and/or B. Other registers Transmit/Receive Control and Status overrun condition. ORFE is are defined as follows: Register (TRCSR) cleared by reading the TRCSR (with ORFE set) then reading the Program Counter—The program counter

7 6 5 4 3 2 receive data register, or by reset. is a 16-bit register which always points to [RDR*RFEITDRE1 RIE RE I TIE I TE I WU 511 RDRF Receive data register full—RDRF the next instruction. is set when the contents of the input serial shift register is transfer- Stack Pointer—The stack pointer is a WU 'Wake-up' on the idle line—When red to the receive data register. It 16-bit register which contains the address set, WU enables the wake-up is cleared by reading the TRCSR of the next available location in a function; it is cleared by ten con- (with RDRF set), and then reading pushdownlpullup (LIFO) queue. The stack secutive l's or by reset. WU will the receive data register, or by resides in random access memory at a not set if the line is idle. reset. location specified by the software.

4.78 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120ISCN68121

Preliminary

Index Register—The index register is a condition bits: negative (N), zero (Z), in Tables 14, 15, 16 and 17 where execu- 16-bit register which can be used to store overflow (V), carry/borrow from MSB (C), tion times are provided in E-cycles. In- data or provide an address for the indexed and half carry from bit 3 (H). These bits are struction execution times are summarized mode of addressing. testable by the conditional branch instruc- in Table 18. With an input frequency (E) of tions. Bit 4 is the interrupt mask (I-bit) and 1MHz, E-cycles are equivalent to micro- Accumulators—The IPC contains two inhibits all maskable interrupts when set. seconds. A cycle-by-cycle description of 8-bit accumulators, A and B, which are The two unused bits, b6 and b7, are read bus activity for each instruction is provided used to store operands and results from as ones. in Table 19 and a description of selected in- the arithmetic logic unit (ALU). They can structions is shown in Figure 23. also be concatenated and referred to as the D (double) accumulator. Addressing Modes Immediate Addressing—The operand is The SCN68120/SCN68121 provides six ad- contained in the following byte(s) of the Condition Code Register—The condition dressing modes which can be used to instruction where the number of bytes code register indicates the results of an reference memory. A summary of address- matches the size of the register. These are instruction and includes the following five ing modes for all instructions is presented two or three byte instructions. Direct Addressing—The least significant 4 byte of the operand address is contained OUTPUT — in the second byte of the instruction and CLOCK the most significant byte is assumed to be $00. Direct addressing allows the user to access $00 through $FF using two byte instructions and execution time is reduced by eliminating the additional memory ac- NRZ FORMAT cess (see Table 19).

In most applications, this 256-byte area is reserved for frequently referenced data.

BI-PHASE Note that no direct addressing of internal FORMAT control registers is possible in mode 3.

IDLE START Bio 6 7 STOP 1 2 3 4 5 Extended Addressing—The second and third bytes of the instruction contain the DATA: 01001101 ($4D) absolute address of the operand. These are three byte instructions. Figure 22. SCI Data Formats

Table 14. INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS Condition Codes Immed Direct Index Extnd Inherent 5 4 3 2 1 0 Pointer Operations Mnemonic OP - # OP - # OP - # OP - # OP - # Boolean/ H I NZ VC Arithmetic Operation Compare Index Reg CPX 8C 4 3 9C 5 2 AC 6 2 BC 6 3 X- M M+ 1 • • 1 I I Decrement Index Reg DEX 09 3 1 X - 1 -.--X • • • • • Decrement Stack Pntr DES 34 3 1 SP - 1 -..-SP • • • • • • Increment Index Reg INX 08 3 1 X + 1 —X • • • 4 • • Increment Stack Pntr INS 31 3 1 1 SP + 1 -..-SP • • • • • • Load Index Reg LDX CE 3 3 DE 4 2 EE 5 2 FE 5 3 M —XH, (M + 1) —XL • • R • Load Stack Pntr LDS 8E 3 3 9E 4 2 AE 5 2 BE 5 3 M —SPH, (M + 1) —SPL • • R • Store Index Reg STX DF 4 2 EF 5 2 FF 5 3 XH -.-M, XL -.--(M + 1) . • • R • Store Stack Pntr STS 9F 4 2 AF 5 2 BF 5 3 SPH —M, SPL ----)N1 + 1) • • R • Index Reg - Stack Pntr TXS 35 3 1 X - 1 —SP • • • • • • Stack Pntr - Index Reg TSX 30 3 1 SP + 1 -.--X • • • • • • Add ABX 3A 3 1 B+X--X • • • • • • Push Data PSHX 3C 4 1 XL -.-Msp, SP - 1 -+-SP • • • • • • XH -.-MSR. SP - 1 -*-SP Pull Data PULX 38 5 1 SP + 1 —SP, Msp -.--XH • • • • • • SP + 1 -.-SP, Msp — XL Signetics 4.79 MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

Indexed Addressing—The unsigned off- branch range of - 126 to 129 bytes from ecute in the same manner. Exceptions are set contained in the second byte of the in- the first byte of the intruction. These are indicated in the table. structions is added with carry to the index two byte instructions. register and used to reference memory Note that during MPU reads of internal without changing the index register. locations, the resultant value will not ap- These are two byte instructions. CYCLE-BY-CYCLE OPERATION pear on the external data bus except in SUMMARY mode 0. 'High order' byte refers to the Table 19 provides a detailed description of most significant byte of a 16-bit value. Inherent Addressing—The operand(s) are the information present on the address registers and no memory reference is re- bus, data bus, and the R/W line during The coding of the first (or only) byte cor- quired. These are single byte instructons. each cycle of each instruction. The infor- responding to an executable instruction is mation is useful in comparing actual with sufficient to identify the instruction and Relative Addressing—Relative addressing expected results during debug of both the addressing mode. The hexadecimal Is used only for branch instructions. If the software and hardware as the program is equivalents of the binary codes, which branch condition is true, the program executed. The information is categorized result from the translation of the 82 in- counter is overwritten with the sum of a in groups according to addressing mode structions in all valid modes of address- signed single byte displacement in the and number of cycles per instruction. In ing, are shown in Table 20. There are 220 second byte of the instruction and the cur- general, instructions with the same ad- valid machine codes, 34 unassigned rent program counter. This provides a dressing mode and number of cycles ex- codes and two reserved for test purposes.

Table 15. ACCUMULATOR AND MEMORY INSTRUCTIONS Accumulator and Immed Direct Index Extend Inner Boolean Condition Codes MNE Op ...., # Op y Op y # Op y # Op ,... # Memory Operations Expression H I N Z V C Add Acmltrs ABA 1B 2 1 A+13-i-A • Add B to X ABX 3A 3 1 00:8 + X -- X • • • • • • Add with Carry ADCA 89 2 2 99 3 2 A9 4 2 89 4 3 A+M+C-i-A , • ADCB C9 2 2 D9 3 2 E9 4 2 F9 4 3 B+M+C-i--B Add ADDA 8B 2 2 9B 3 2 AB 4 2 BB 4 3 A + M —A • ADDB CB 2 2 DB 3 2 EB 4 2 FB 4 3 B+ M -,--A • Add Double ADDD C3 4 3 D3 5 2 E3 6 2 F3 6 3 D + M:M + 1 —D • • And ANDA 84 2 2 94 3 2 A4 4 2 B4 4 3 A • M -•••••A • • R • ANDB C4 2 2 D4 3 2 E4 4 2 F4 4 3 B • M -.-B • • R • Shift Left, ASL 68 6 2 78 6 3 • • I i Arithmetic ASIA 48 2 1 • • ASLB 5 8 2 1 • • hiftS Left Dbl ASLD 05 3 1 • • I Shift Right, ASR 67 6 2 77 6 3 • • I Arithmetic ASRA 47 2 1 • • I ASRB 57 2 1 • • I I Bit Test • BITA 85 2 2 95 3 2 A5 4 2 B5 4 3 A • M • • R • BITB C5 2 2 D5 3 2 E5 4 2 F5 4 3 B • M • • R • Compare Acmltrs CBA 11 2 1 A- B • • I I Clear CLR 6F 6 2 7F 6 3 00 -I-- M ••RSRR CLRA 4F 2 1 00 ---A ••RSRR CLRB 5F 2 1 00 -i--B ••RSRR Compare • CMPA 81 2 2 91 3 2 Al 4 2 B1 4 3 A- M • • CMPB Cl 2 2 D1 3 2 El 4 2 Fl 4 3 B- M • • 11 l's Complement COM 63 6 2 73 6 3 M —M • • R S COMA 43 2 1 A. —A • • R S COMB 53 2 1 IN -.-13 • • R S Decimal Adj, A DAA 19 2 1 Adj binary sum to BCD • • I Decrement DEC 6A 6 2 7A 6 3 M - 1 —M • • • DECA 4A 2 1 A - 1 -- A • • • DECB 5A 2 1 B - 1 —B • • • Exclusive OR EORA 88 2 2 98 3 2 A8 4 2 138 4 3 A C) M ---A • • R • EORB C8 2 2 08 3 2 E8 4 2 F8 4 3 B C) M --i-B • • R •

4.80 Signetics MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120ISCN68121

Preliminary

Table 15. ACCUMULATOR AND MEMORY INSTRUCTIONS (Continued) Accumulator and Immed Direct Index Extend Inher Boolean Condition Codes MNE Memory Operations Op _ # Op — # Op — # Op — # Op — # Expression H INZVC Increment INC 6C 6 2 70 6 3 M + 1 —M • • • INCA 4C 2 1 A + 1 —A • • • INCB 5C 2 1 B + 1 —B • • • Load Acmltrs LDAA 86 2 2 96 3 2 A6 4 2 B6 4 3 M —A • • R • LDAB C6 2 2 D6 3 2 E6 4 2 F6 4 3 M —B • • R • Load Double LDD CC 3 3 DC 4 2 EC 5 2 FC 5 3 M.M + 1 —D • • R • Logical Shift, LSL 68 6 2 78 6 3 • • Left LSLA 48 2 1 • • t LSLB 58 2 1 • • LSLD 05 3 1 • • Shift Right, LSR 64 6 2 74 6 3 • • R , Logical LSRA 44 2 1 • • R LSRB 54 2 1 • • R LSRD 04 3 1 • • R Multiply MUL 3D 10 1 A X B—D • • • • • 2's Complement NEG 60 6 2 70 6 3 00 - M —M • • (Negate) NEGA 40 2 1 00 - A —A • • 1 1 1 NEGB 50 2 1 00 - B —8 • • I 1 No Operation NOP 01 2 1 PC + 1 —PC • • • • • • Inclusive OR ORAA 8A 2 2 9A 3 2 AA 4 2 BA 4 3 A+ M —A • • 1 1 R • ORAB CA 2 2 DA 3 2 EA 4 2 FA 4 3 B+ M —B • • 1 R • Push Data PSHA 36 3 1 A —Stack • • • • • • PSHB 37 3 1 B --Stack • • • • • • Pull Data PULA 32 4 1 Stack —A • • • • • • PULE 33 4 1 Stack -).-B • • • • • • Rotate Left ROL 69 6 2 79 6 3 • • 1 1 ROLA 49 2 1 • • I 1 ROLB 59 2 1 • • 1 Rotate Right ROR 66 6 2 76 6 3 • • 1 RORA 46 2 1 • • 1 RORB 56 2 1 • • 1 Subtract Acmltr SBA 10 2 1 A - B —A • • Subtract with SBCA 82 2 2 92 3 2 A2 4 2 B2 4 3 A- M- C —A • • Carry SBCB C2 2 2 02 3 2 E2 4 2 F2 4 3 B-M-C-.)-B • • 1 Store Acmltrs STAA 97 3 2 A7 4 2 B7 4 3 A —M • • R • STAB D7 3 2 E7 4 2 F7 4 3 B —M • • R • STD DD 4 2 ED 5 2 FD 5 3 D --.--M:M + 1 • • R • Subtract SUBA 80 2 2 90 3 2 AO 4 2 BO 4 3 A- M -.--A • • j 1 SUBB CO 2 2 DO 3 2 EC) 4 2 FO 4 3 B- M —B • • ' 1 t Subtract Double SUBD 83 4 3 93 5 2 A3 6 2 B3 6 3 D- M.M + 1 —D • • I 1 Transfer Acmltr TAB 16 2 1 A —B • • t R • TBA 17 2 1 B —A • • 1 R • Test, Zero or TST 6D 6 2 7D 6 3 M - 00 • • R R Minus TSTA 4D 2 1 A - 00 • • R R TSTB 5D 2 1 B- 00 • • : R R The Condition Code Register notes are listed after Table 17.

Signetics 4.81 MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

Table 16. JUMP AND BRANCH INSTRUCTIONS Cond. Code Reg. Direct Relative Index Extnd Inherent 5 4 3 2 1 0 Operations Mnemonic OP — # OP — # OP — # OP — # OP — # Branch Test H I N Z V C Branch Always BRA 20 3 2 None • • • • • • Branch Never BRN 21 3 2 None • • • • • • Branch If Carry Clear BCC 24 3 2 C = 0 • • • • • • Branch If Carry Set BCS 25 3 2 C = 1 • • • • • • Branch If = Zero BEO 27 3 2 Z = 1 • • • • • • Branch If i?_ Zero BGE 2C 3 2 N 0 V = 0 • • • • • • Branch If > Zero BGT 2E 3 2 Z + (N O+ V) = 0 • • • • • • Branch If Higher BHI 22 3 2 C + Z = 0 • • • • • • Branch If Higher or Same BHS 24 3 2 C =0 • • 5 • • • Branch If 5. Zero BLE 2F 3 2 Z + (N (DV) = 1 • • • • • • Branch If Carry Set BLO 25 3 2 C = 1 • • • • • • Branch If Lower Or Same BLS 23 3 2 C + Z = 1 • • • • • • Branch If < Zero BLT 2D 3 2 N C)V = 1 • • • • • • Branch If Minus BMI 2B 3 2 N = 1 • • • • • • Branch If Not Equal Zero BNE 26 3 2 Z = 0 • • • • • • Branch If Overflow Clear BVC 28 3 2 V = 0 • • • • • • Branch If Overflow Set BVS 29 3 2 V = 1 • • • • • • Branch If Plus BPL 2A 3 2 N = 0 • • • • • • BSR 8D 6 2 • • • Branch To Subroutine I See Special • • • Jump JMP 6E 3 2 7E 3 3 Operations — • • • • • • Jump To Subroutine JSR 9D 5 2 AD 6 2 BD 6 3 Figure 23 • • • • • • No Operation NOP 01 2 1 • • • • • • Return From Interrupt RTI 36 10 1

Return From Subroutine RTS 39 5 1 See Special • • • • • • Software Interrupt SWI 3F 12 1 Operations — • S • • • • Figure 23 Wait For Interrupt WAI 3E 9 1 • • • • • •

Table 17. CONDITION CODE REGISTER MANIPULATION INSTRUCTIONS Cond. Code Reg. Inherent 5 4 3 2 1 0 Operations Mnemonic OP Boolean Operation H I N Z V C Clear Carry CLC OC 2 1 0 —C • • • • • R Clear Interrupt Mask CLI OE 2 1 0 —I • R • • • • Clear Overflow CLV OA 2 1 0 —V • • • • R • Set Carry SEC OD 2 1 1 —C • • • • 0 S Set Interrupt Mask SEI OF 2 1 1 —I • S • • • • Set Overflow SEV OB 2 1 1 —V • • • • S • Accumulator A —CCR TAP 06 2 1 A —CCR Mt I 1 CCR —Accumulator A TPA 07 2 1 CCR —A • • • • • • LEGEND OPOperation Code (Hexadecimal) + Boolean Inclusive OR CONDITION CODE SYMBOLS — Number of MPU Cycles C) Boolean Exclusive OR H Half-carry from bit 3 MSP Contents of memory location ircil Complement of M Interrupt mask pointed to by Stack Pointer Transfer Into N Negative (sign bit) # Number of Program Bytes O Bit = Zero Z Zero (byte) + Arithmetic Plus 00 Byte = Zero V Overflow, 2"s complement Arithmetic Minus Carry/Borrow from MSB • Boolean AND R Reset Always X Arithmetic Multiply Set Always Affected C Not Affected

4.82 Signetics MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary Table 18. INSTRUCTION EXECUTION TIMES IN E-CYCLES

ADDRESSING MODE ADDRESSING MODE

te te

d d t t ia a) ia a) d d d de de lai > .,-. >

n ren '«

o • 0 a) ten

te 19. 1 he heren 'I' .0 dexe a) a) ;

Imme 0 Imme In In Ex In a Ex cc 0 tx 1 1 ABA • • • • 2 • INX • • • 3 • ABX • • • • 3 • JMP • • co 3 • • ADC 2 3 4 4 • • JSR • 5 co 6 • • . ADD 2 3 4 4 • • LDA 2 3 1. 4 • • ADDD 4 5 6 6 • • LDD 3 4 Ln 5 • • AND 2 3 4 4 • • LDS 3 4 Ln 5 • • ASL • • 6 6 2 • LDX 3 4 5 • • ASLD • • • • 3 • LSL • • 6 6 2 • ASR • • 6 6 2 • LSLD • • • • 3 • BCC • • • • • 3 LSR • • 6 6 2 • BCS • • • • • 3 LSRD • • • • 3 • BEQ • • • • 5 3 MUL • • • • 10 • BGE • • • • • 3 NEG • • 6 6 2 • BGT • • • • • 3 NOP • • 0 • 2 • BHI • • • • • 3 ORA 2 3 4 4 • • BHS • • • • • 3 PSH • • • • 3 • BIT 2 3 4 4 • • PSHX • • • • 4 • BLE • • • • • 3 PUL • • • • 4 • BLO • • • • • 3 PULX • • a • 5 • BLS • • • • • 3 ROL • • 6 6 2 • BLT • • • • • 3 ROR • • 6 6 2 • BMI • • • • • 3 RTI • • • • 10 • BNE • • • • • 3 RTS • • • • 5 • BPL • • • • • 3 SBA • • • • 2 • BRA • • • • • 3 SBC 2 3 4 4 • • BRN • • • • • 3 SEC 0 • • • 2 • BSR 0 • • • • 6 SEI • • • • 2 • BVC 0 • • • • 3 SEV • • • • 2 • BVS • • • • • 3 STA • 3 4 4 • • CBA 0 • • • 2 • STD • 4 5 5 • • CLC • • • • 2 • STS • 4 5 5 • • CLI • • • • 2 • STX • 4 5 5 0 • CLR • • 6 6 2 • SUB 2 3 4 4 0 • CLV • • • • 2 • SUBD 4 5 6 6 • • CMP 2 3 4 4 • • SWI • • • • 12 • COM • • 6 6 2 • TAB • • • • 2 • CPX 4 5 6 6 • • TAP • • • • 2 • DAA • • • • 2 • TBA • • • I 2 • DEC • • 6 6 2 • TPA • • • • 2 5 DES • • • • 3 0 TST • • 6 6 2 • DEX • • • • 3 • TSX • • • • 3 • EOR 2 3 4 4 • • TXS • • • • 3 • INC • • 6 6 • • WAI • • • • 9 • INS • • • • 3 •

Signetics 4.83 MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

MAIN PROGRAM PC $9D = JSR

DIRECT K NEXT MAIN INSTR. RTN K = DIRECT ADDRESS

MAIN PROGRAM SP STACK $AD=JSR --OD SP-2 JSR, JUMP TO SUBROUTINE INDXD K =OFFSET SP.1 RTNH NEXT MAIN INSTR. RTNL RTNPC SP

MAIN PROGRAM PC $BD=JSR SH =SUBR. ADDR. EXTND SL =SUBR. ADDR. NEXT MAIN INSTR. RTN

MAIN PROGRAM SP STACK PC $8D= BSR - SP.2 BSR, BRANCH TO SUBROUTINE K =OFFSET SP.1 RTNH NEXT MAIN INSTR. SP RTNL RTN

SUBROUTINE SP STACK PC $39 = RTS SP RTS, RETURN FROM SUBROUTINE SP +1 RTNH - - SP + 2 RTNL

MAIN PROGRAM SP STACK PC $3F = SWI — Dv SP-7 SWI, SOFTWARE INTERUPT RTN SPE CONDITION CODE SPE ACMITR B SP-4 ACMITR A SP-3 INDEX REGISTER (XH) MAIN PROGRAM SP-2 INDEX REGISTER (XL) PC $3E= WAI SP.1 RTNH WAI, WAIT FOR INTERRUPT SP RTNL RTN

PC INTERRUPT PROGRAM SP STACK $3B= RTI SP RTI, RETURN FROM INTERRUPT SP +1 CONDITION CODE SP +2 ACMITR B SP +3 ACMITR A SP + 4 INDEX REGISTER (XH) SP +5 INDEX REGISTER (XL) SP+6 RTNH - -411. SP + 7 RTNL

MAIN PROGRAM MAIN PROGRAM PC $6E= JMP PC $7E=Jmp K =OFFSET KH = NEXT ADDRESS JMP, JUMP INDXD EXTENDED KL = NEXT ADDRESS

'NEXT INSTRUCTION' NEXT INSTRUCTION X + K

LEGEND: RTN = Address of next instruction in Main Program to be executed upon return from subroutine = Stack pointer after execution RTNH = Most significant byte of Return Address K= 8-bit unsigned value RTNL = Least significant byte of Return Address Figure 23. Special Operations

4.84 Signetics MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

Table 19. CYCLE BY CYCLE OPERATION Address Mode & Cycle R/W Cycles Address Bus Data Bus Instructions # Line IMMEDIATE ADC EOR 2 1 Op Code Address 1 Op Code ADD LDA 2 Op Code Address + 1 1 Operand Data AND ORA BIT SBC CMP SUB LDS 3 1 Op Code Address 1 Op Code LDX 2 Op Code Address + 1 1 Operand Data (High Order Byte) LDD 3 Op Code Address + 2 1 Operand Data (Low Order Byte) CPX 4 1 Op Code Address 1 Op Code SUED 2 Op Code Address + 1 1 Operand Data (High Order Byte) ADDD 3 Op Code Address + 2 1 Operand Data (Low Order Byte) 4 Address Bus FFFF 1 Low Byte of Restart Vector DIRECT ADC EOR 3 1 Op Code Address 1 Op Code ADD LDA 2 Op Code Address + 1 1 Address of Operand AND ORA 3 Address of Operand 1 Operand Data BIT SBC CMP SUB STA 3 1 Op Code Address 1 Op Code 2 Op Code Address + 1 1 Destination Address 3 Destination Address 0 Data from Accumulator LDS 4 1 Op Code Address 1 Op Code LDX 2 Op Code Address + 1 1 Address of Operand LDD 3 Address of Operand 1 Operand Data (High Order Byte) 4 Operand Address + 1 1 Operand Data (Low Order Byte) STS 4 1 Op Code Address 1 Op Code STX 2 Op Code Address + 1 1 Address of Operand STD 3 Address of Operand 0 Register Data (High Order Byte) 4 Address of Operand + 1 0 Register Data (Low Order Byte) CPX 5 1 Op Code Address 1 Op Code SUBD 2 Op Code Address + 1 1 Address of Operand ADDD 3 Operand Address 1 Operand Data (High Order Byte) 4 Operand Address + 1 1 Operand Data (Low Order Byte) 5 Address Bus FFFF 1 Low Byte of Restart Vector JSR 5 1 Op Code Address 1 Op Code 2 Op Code Address + 1 1 Irrelevant Data 3 Subroutine Address 1 First Subroutine Op Code 4 Stack Pointer 0 Return Address (Low Order Byte) 5 Stack Pointer + 1 0 Return Address (High Order Byte)

Signetics 4.85 MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN681201SCN68121

Preliminary Table 19. CYCLE BY CYCLE OPERATION (Continued)

Address Mode & Cycle R/W Cycles Address Bus Data Bus Instructions Line

EXTENDED JMP 3 1 Op Code Address 1 Op Code 2 Op Code Address + 1 1 Jump Address (High Order Byte) 3 Op Code Address + 2 1 Jump Address (Low Order Byte) ADC EOR 4 1 Op Code Address 1 Op Code ADD LDA 2 Op Code Address + 1 1 Address of Operand AND ORA 3 Op Code Address + 2 1 Address of Operand (Low Order Byte) BIT SBC 4 Address of Operand 1 Operand Data CMP SUB STA 4 1 Op Code Address Op Code 2 Op Code Address + 1 Destination Address (High Order Byte)

3 Op Code Address + 2 - Destination Address (Low Order Byte) 4 Operand Destination Address Data from Accumulator

1 LDS 5 1 Op Code Address 1 Op Code LDX 2 Op Code Address + 1 1 Address of Operand (High Order Byte) LDD 3 Op Code Address + 2 1 Address of Operand (Low Order Byte) 4 Address of Operand 1 Operand Data (High Order Byte) 5 Address of Operand + 1 1 Operand Data (Low Order Byte) STS 5 1 Op Code Address 1 Op Code STX 2 Op Code Address + 1 1 Address of Operand (High Order Byte) STD 3 Op Code Address + 2 1 Address of Operand (Low Order Byte) 4 Address of Operand 0 Operand Data (High Order Byte) 5 Address of Operand + 1 0 Operand Data (Low Order Byte) ASL LSR 6 1 Op Code Address 1 Op Code ASR NEG 2 Op Code Address + 1 1 Address of Operand (High Order Byte) CLR ROL 3 Op Code Address + 2 1 Address of Operand (Low Order Byte) COM ROR 4 Address of Operand 1 Current Operand Data DEC TST 5 Address Bus FFFF 1 Low Byte of Restart Vector INC 6 Address of Operand 0 New Operand Data CPX 6 1 Op Code Address 1 Op Code SUBD 2 Op Code Address + 1 1 Operand Address (High Order Byte) ADDD 3 Op code Address + 2 1 Operand Address (Low Order Byte) 4 Operand Address 1 Operand Data (High Order Byte) 5 Operand Address + 1 1 Operand Data (Low Order Byte) 6 Address Bus FFFF 1 Low Byte of Restart Vector JSR 6 1 Op Code Address 1 Op Code 2 Op Code Address + 1 1 Address of Subroutine (High Order Byte) 3 Op Code Address + 2 1 Address of Subroutine (Low Order Byte) 4 Subroutine Starting Address 1 Op Code of Next Instruction 5 Stack Pointer 0 Return Address (Low Order Byte) 6 Stack Pointer - 1 0 Return Address (High Order Byte)

4.86 Signetics MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120ISCN68121

Preliminary

Table 19. CYCLE BY CYCLE OPERATION (Continued) Address Mode & Cycle R/W Cycles Address Bus Data Bus Instructions # Line INDEXED JMP 3 1 Op Code Address 1 Op Code 2 Op Code Address + 1 1 Offset 3 Address Bus FFFF 1 Low Byte of Restart Vector ADC EOR 4 1 Op Code Address 1 Op Code ADD LDA 2 Op Code Address + 1 1 Offset AND ORA 3 Address Bus FFFF 1 Low Byte of Restart Vector BIT SBC 4 Index Register Plus Offset 1 Operand Data CMP SUB STA 4 1 Op Code Address 1 Op Code 2 Op Code Address + 1 1 Offset 3 Address Bus FFFF 1 Low Byte of Restart Vector 4 Index Register Plus Offset 0 Operand Data LDS 5 1 Op Code Address 1 Op Code LDX 2 Op Code Address + 1 1 Offset LDD 3 Address Bus FFFF 1 Low Byte of Restart Vector 4 Index Register Plus Offset 1 Operand Data (High Order Byte) 5 Index Register Plus Offset + 1 1 Operand Data (Low Order Byte) STS 5 1 Op Code Address 1 Op Code STX 2 Op Code Address + 1 1 Offset STD 3 Address Bus FFFF 1 Low Byte of Restart Vector 4 Index Register Plus Offset 0 Operand Data (High Order Byte) 5 Index Register Plus Offset + 1 0 Operand Data (Low Order Byte) ASL LSR 6 1 Op Code Address 1 Op Code ASR NEG 2 Op Code Address + 1 1 Offset CLR ROL 3 Address Bus FFFF 1 Low Byte of Restart Vector COM ROR 4 Index Register Plus Offset 1 Current Operand Data DEC TST (1) 5 Address Bus FFFF 1 Low Byte of Restart Vector INC 6 Index Register Plus Offset 0 New Operand Data CPX 6 1 Op Code Address 1 Op Code SUBD 2 Op Code Address + 1 1 Offset ADDD 3 Address Bus FFFF 1 Low Byte of Restart Vector 4 Index Register + Offset 1 Operand Data (High Order Byte) 5 Index Register + Offset + 1 1 Operand Data (Low Order Byte) 6 Address Bus FFFF Low Byte of Restart Vector JSR 6 1 Op Code Address 1 Op Code 2 Op Code Address + 1 1 Offset 3 Address Bus FFFF 1 Low Byte of Restart Vector 4 Index Register + Offset 1 First Subroutine Op Code 5 Stack Pointer 0 Return Address (Low Order Byte) 6 Stack Pointer - 1 0 Return Address (High Order Byte)

Signetics 4.87 MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary Table 19. CYCLE BY CYCLE OPERATION (Continued) Address Mode & Cycle R/W Cycles Address Bus Data Bus Instructions # Line INHERENT ABA DAA SEC 2 1 Op Code Address 1 Op Code ASL DEC SEI 2 Op Code Address +1 1 Op Code of Next Instruction ASR INC SEV CBA LSR TAB CLC NEG TAP CLI NOP TBA CLR ROL TPA CLV ROR TST COM SBA ABX 3 1 Op Code Address 1 Op Code 2 Op Code Address +1 1 Irrelevant Data 3 Address Bus FFFF 1 Low Byte of Restart Vector ASLD 3 1 Op Code Address 1 Op Code LSRD 2 Op Code Address +1 1 Irrelevant Data 3 Address Bus FFFF 1 Low Byte of Restart Vector DES 3 1 Op Code Address 1 Op Code INS 2 Op Code Address +1 1 Op Code of Next Instruction 3 Previous Register Contents 1 Irrelevant Data INX 3 1 Op Code Address 1 Op Code DEX 2 Op Code Address +1 1 Op Code of Next Instruction 3 Address Bus FFFF 1 Low Byte of Restart Vector PSHA 3 1 Op Code Address 1 Op Code PSHB 2 Op Code Address +1 1 Op Code of Next Instruction 3 Stack Pointer 0 Accumulator Data TSX 3 1 Op Code Address 1 Op Code 2 Op Code Address +1 1 Op Code of Next Instruction 3 Stack Pointer 1 Irrelevant Data TXS 3 1 Op Code Address 1 Op Code 2 Op Code Address +1 1 Op Code of Next Instruction 3 Address Bus FFFF 1 Low Byte of Restart Vector PULA 4 1 Op Code Address 1 Op Code PULB 2 Op Code Address +1 1 Op Code of Next Instruction 3 Stack Pointer 1 Irrelevant Data 4 Stack Pointer +1 1 Operand Data from Stack PSHX 4 1 Op Code Address 1 Op Code 2 Op Code Address +1 1 Irrelevant Data 3 Stack Pointer 0 Index Register (Low Order Byte) 4 Stack Pointer -1 0 Index Register (High Order Byte) PULX 5 1 Op Code Address 1 Op Code 2 Op Code Address +1 1 Irrelevant Data 3 Stack Pointer 1 Irrelevant Data 4 Stack Pointer +1 1 Index Register (High Order Byte) 5 Stack Pointer +2 1 Index Register (Low Order Byte) RTS 5 1 Op Code Address 1 Op Code 2 Op Code Address +1 1 Irrelevant Data 3 Stack Pointer 1 Irrelevant Data 4 Stack Pointer +1 1 Address of Next Instruction (High Order Byte) 5 Stack Pointer +2 1 Address of Next Instruction (Low Order Byte) .-

WAI 9 1 Op Code Address Op Code •-

2 Op Code Address +1 0 Op Code of Next Instruction 3 Stack Pointer Return Address (Low Order Byte) 4 Stack Pointer -1 Return Address (High Order Byte) 5 Stack Pointer -2 Index Register (Low Order Byte) 6 Stack Pointer -3 Index Register (High Order Byte) 7 Stack Pointer -4 Contents of Accumulator A 8 Stack Pointer -5 Contents of Accumulator B 9 Stack Pointer -6 Contents of Cond. Code Register 4-88 Signetics MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

Table 19. CYCLE BY CYCLE OPERATION (Continued)

Address Mode & Cycle RAN Cycles Address Bus Data Bus L Instructions # Line INHERENT MUL 10 1 Op Code Address 1 Op Code 2 Op Code Address +1 1 Irrelevant Data 3 Address Bus FFFF 1 Low Byte of Restart Vector 4 Address Bus FFFF 1 Low Byte of Restart Vector 5 Address Bus FFFF 1 Low Byte of Restart Vector 6 Address Bus FFFF 1 Low Byte of Restart Vector 7 Address Bus FFFF 1 Low Byte of Restart Vector 8 Address Bus FFFF 1 Low Byte of Restart Vector 9 Address Bus FFFF 1 Low Byte of Restart Vector 10 Address Bus FFFF 1 Low Byte of Restart Vector RTI 10 1 Op Code Address 1 Op Code 2 Op Code Address +1 1 Irrelevant Data 3 Stack Pointer 1 Irrelevant Data 4 Stack Pointer +1 1 Contents of Cond. Code Reg. from Stack 5 Stack Pointer +2 1 Contents of Accumulator B from Stack 6 Stack Pointer +3 1 Contents of Accumulator A from Stack 7 Stack Pointer +4 1 Index Register from Stack (High Order Byte) 8 Stack Pointer +5 1 Index Register from Stack (Low Order Byte) 9 Stack Pointer +6 1 Next Instruction Address from Stack (High Order Byte) 10 Stack Pointer +7 1 Next Instruction Address from Stack (Low Order Byte)

SWI 12 1 Op Code Address 1 Op Code

2 Op Code Address +1 -- Irrelevant Data 3 Stack Pointer Return Address (Low Order Byte) 4 Stack Pointer -1 Return Address (High Order Byte) 00 5 Stack Pointer -2 Index Register (Low Order Byte) 6 Stack Pointer -3 Index Register (High Order Byte) 7 Stack Pointer -4 Contents of Accumulator A 8 Stack Pointer -5 Contents of Accumulator B 9 Stack Pointer -6 Contents of Cond. Code Register 10 Stack Pointer -7 Irrelevant Data 11 Vector Address FFFA (Hex) Address of Subroutine (High Order Byte) --.00000

12 Vector Address FFFB (Hex) - Address of Subroutine (Low Order Byte)

RELATIVE BCC BHT BNE BLO 3 1 Op Code Address 1 Op Code BCS BLE BPL BHS 2 Op Code Address +1 1 Branch Offset BEQ BLS BRA BRN 3 Address Bus FFFF 1 Low Byte of Restart Vector BGE BLT BVC BGT BMT BVS BSR 6 1 Op Code Address 1 Op Code 2 Op Code Address +1 1 Branch Offset 3 Address Bus FFFF 1 Low Byte of Restart Vector 4 Subroutine Starting Address 1 Op Code of Next Instruction 5 Stack Pointer 0 Return Address (Low Order Byte) 6 Stack Pointer -1 0 Return Address(High Order Byte)

Signetics 4.89 MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

Table 20. CPU INSTRUCTION MAP

OP MNEM MODE ,--, 0 OP MNEM MODE ,-.- a OP MNEM MODE ^. # OP MNEM MODE ,.., OP MNEM MODE -- oo • 34 DES INHFR 68 ASL INDXD 6 2 9C CPX DIR 5 DO SUER DIR 01 NOP INNER 2 1 35 TXS 69 ROL 6 2 9D JSR 5 D1 CMPB 02 • I 36 PSHA 6A DEC 6 2 9E LDS 4 D1 SBCB 03 • 37 PSHB 68 • 91 STS DIR 4 D3 ADDD 04 LSRD 3 38 PULX 6C INC 6 2 40 SUBA INDXD 4 D4 ANDS 05 ASLD 3 39 RTS 6D TST 6 2 AlCMPA 4 D5 BITB 06 TAP 2 3A ABX 6E JMP 3 2 A2 SBCA 4 06 LDAB 07 TPA 2 3B RTI I0 6F CLR INDXD 6 2 A3 SUBD 6 D7 STAB 08 INX 3 3C PSHX 4 70 NEG EXTND 6 3 A4 ANDA 4 D8 EORB 09 DE X 3 3D MUL 10 71 • A5 BITA 4 D9 ADCB OA CLV 2 3E WAI 9 72 • A6 LDAA 4 DA ORAB 013 SEV 2 3F SWI 12 73 COM 47 STAA 4 DB USDA OC CLC 2 40 NEGA 2 74 LSR 48 FORA 4 DC LOD OD SEC 2 41 • 75 • A9 ADCA 4 DS STD OE CLI 2 42 • 76 BOP AA ORAA 4 DE LOX OF SRI 2 43 COMA 77 ASR 48 ADDA 4 DF ST X DIR 10 SBA 2 44 LSRA 78 ASL AC CPX 6 50 SUBB 1NDXD 11 C8A 2 45 • 79 ROL AD JSR 6 E1 CMPB 12 • 46 RORA 7A DEC AE LDS 5 62 SOCA 13 • 47 ASRA 7B • AF STS INDXD 5 E3 ADDD 14 • 48 ASLA 7C INC BO SOBA EX No 4 E4 ANDS 15 • 49 ROLA 7D TST B1 CMPA 4 ES BITB 16 TAB 2 1 4A DECA 7E IMP B2 SBCA 4 E6 LDAB 17 TRA 2 1 48 • 7F CLR EXTND 83 SUBS 6 E7 STAB 18 • 4C INCA 80 SUBA IMMED B4 ANDA 4 E8 E ORB 19 DAA INNER 2 1 4D TSTA 81 CMPA g 135 B1TA 4 E9 ADCB 1A • 4E T 82 SBCA B6 LDAA 4 EA DRAB 18 ABA INNER 2 1 4F CLRA 83 SLJBD B7 STAA 4 EB ADDS 1C • 50 NEGB 84 ANDA 08 FORA 4 EC LOD 10 51 • 85 BITA 09 ADCA 4 ED STD 1E 52 • 86 LDAA BA ORAA 4 EF L DX 11 • 53 COMB 2 87 ' BB USDA 4 FF Six 10000 20 BRA REL 3 2 54 LSRB 2 88 FORA BC CPX 6 FO SORB ExT ND 21 BRN 3 2 55 • 89 ADCA BD JSR 6 FI CMPB 22 BHI 3 2 56 ROBB 2 BA ORAA BE LDS b 12 SBCB 23 BLS 3 2 57 ASRB 2 88 ADDA W BF STS EXTND 5 F3 ADM 24 BCC 3 2 58 ASLB 2 BC CPU IMMED CO SUBB IMMED 2 F4 ANDO 25 BCS 3 2 59 ROLB 2 9D BOB BEL Cl CMPB 2 '5 BITB 26 BNE 3 2 5A DECB 2 BE LDS IMMED C2 SBCB 2 F6 LDAB 27 BEG 3 2 58 BF • C3 ADDD 4 77 STAB 28 ROC 3 2 5c INCB 2 90 SUBA DIR C4 ANDS 2 F8 CORR 29 BOB 3 2 50 TSTB 2 91 CMPA C5 BITB 2 F9 ADCB 2A BPL 3 2 5E 1 92 SBCA C6 LDAB 2 FA ORAB 28 BMI 3 2 5F CLRB INNER 2 93 SURD C7 • FB ADDS 2C BGE 3 2 60 NEG INDXD 6 2 94 ANDA C8 FORE 2 FC LDD 2D ELT r 3 2 61 • 95 BITA C9 ADCB 2 FD STD 2E BGT 3 2 62 • 96 LDAA CA ORAB 2 FE LOX 2F BLE REL 3 2 63 COM 6 2 97 STAA CB ADDB 2 FF STX FROND 30 TSX INNER 3 1 64 LSR 6 2 9B FORA CC LOD 3 31 INS t 3 1 65 • 99 ADCA CD ' • UNDEFINED ()P CODE 32 PULA 0 1 66 ROB 6 2 9A ORAA • CE L Dx IMMED 3 PULE 4 CF • 33 INNER 1 67 ASA INDXD 6 2 9B ADDA DIR NOTES: 1. Addressing Modes INNER . Inherent INDXD Indexed IMMED Immediate REL. Relative EXTND Extended DIR Direct 2. Unassigned opcodes are indicated by "•" and should not be executed. 3. Codes marked by "T" force the PC to function as a 16-bit counter.

4.90 Signetics

MICROPROCESSOR DIVISION JANUARY 1983

INTELLIGENT PERIPHERAL CONTROLLER SCN681201SCN68121

Preliminary

APPENDIX A SCN68120 CUSTOM ORDERING INFORMATION

Address $FFEF is reserved for the Signetics Corporation notation for address and data), may be checksum value for the ROM, to be Microprocessor Marketing submitted for pattern generation. The generated at the factory. Bin 1276 2708s must be clearly marked to indicate P.O. Box 409 which PROM corresponds to which ad- Sunnyvale, California 94086 dress space ($X800-$XFFF). See figure A-2 CUSTOM SCN68120 ORDERING for recommended marking procedure. INFORMATION A copy of the cover letter should also be The custom SCN68120 specifications may mailed separately. be transmitted to Signetics in EPROM(s) After the EPROM(s) are marked, they formatted and packaged as indicated EPROMs should be placed in conductive IC carriers below, and mailed prepaid and insured 2708 and 2716 type EPROMs, programmed and securely packed. Do not use with a cover letter (see figure A-1) to: with the custom program (positive logic styrofoam. 4

CUSTOMER NAME

ADDRESS

STATE CITY ZIP

PHONE EXTENSION

CONTACT MS/MR

CUSTOMER PART #

ROM START ADDRESS OPTION PATTERN MEDIA' TEMPERATURE RANGE ❑ $C800 ❑ 2708 EPROM 0° to 70°C ❑ $0800 ❑ 2716 EPROM ❑ SE800 PACKAGE TYPE ❑ SF800 ❑ Ceramic ❑ Al2 and A13 don't care MARKING RAM START ADDRESS OPTION ❑ Standard ❑ $0080 ❑ Special

NOTE. Ill Other Media Require Prior Factory Approval

SIGNATURE

TITLE

Figure A-1. Ordering Information Form

Signetics 4.91 MICROPROCESSOR DIVISION JANUARY 1983

INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

ABSOLUTE MAXIMUM RATINGS1 Parameter Rating Unit Supply voltage - 0.3 to + 7.0 V Input voltage3 - 0.3 to + 7.0 V Operating temperature range2 0 to + 70 °C Storage temperature - 55 to + 150 °C

DC ELECTRICAL CHARACTERISTICS vcc =5.0V ± 5%, Vss= ov; crc to + 70 °C4'5 Limits Parameter Test Conditions Min. Typ. Max. Unit Local bus (see Figures 24, 25)

VEIH Input high voltage E Vcc - 0.75 Vcc V VEIL Input low voltage E - 0.3 0.6 V VIH Input high voltage RESET 4.0 Vcc V Other inputs6 2.0 Vcc V VIL Input low voltage All inputs6 -0.3 0.8 V lin Input load current Vin = 0 to 2.4V Port 4 0.5 mA SC1 0.8 mA lin Input leakage current V,„= 0 to 5.25V HALT/NMI,IRQ1,RESET 1.5 2.5 gA ITS! Three-state (off state) input current Vig = 0.5 to 2.4V SDO-SD7, P30-P37 2.0 10 µA P20-P24 10.0 100 gA VOH Output high voltage P30-P37 Iload = - 205gA, Vcc = min 2.5 V P40-P47, SC1, SC2 !load= - 145µA, Vcc = min 2.4 V Other outputs lioad = - 100gA, Vcc= min 2.4 V

VOL Output low voltage lload = 2.0mA, Vcc = min All outputs 0.5 V

PINT Internal power dissipation TA= 0°C 1200 mW C1,, Input capacitance V;„=0, Tg = 25°C, fo = 1.0MHz P30-P37, P40-P47, SC1 12.5 pF Other inputs 10.0 pF

System bus (see Figure 26)

VIH Input high voltage CS, DTACK, SAO-SA7, SDO-SD7, SR/W 2.0 Vcc V VIL Input low voltage CS, DTACK, SAO-SA7, SDO-SD7, SR/W -0.3 0.8 V

VOH Output high voltage DTACK, SDO-SD7 !load = - 4000,, Vcc = min 2.4 V VOL Output low voltage !load= 5.3mA, Vcc = min 0.5 V DTACK, SD0-SD7

NOTES: See AC Electrical Characteristics.

4.92 Signetics MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Prelimmary

AC ELECTRICAL SPECIFICATIONS Vcc = 5VDC 1.- 5%, Vss = OVDC, TA = 0°C to 70°045 Tentative Limits Number Characteristic Symbol Min Max Unit Peripheral port (see Figures 27 through 30)

— Peripheral data setup time tPDSU 200 ns

— Peripheral data hold time tPDH 200 ns — Delay time, enable positive transition 350 ns to 0S3 negative transition tosol — Delay time, enable positive transition 350 ns to 0S3 positive transition tOSD2 — Delay time, enable negative transition tp„ 350 ns to peripheral data valid (ports 2, 3, 4) — Delay time, enable negative transition 2.0 ps to peripheral CMOS data valid tcmos — Input strobe pulse width tPWIS 200 ns

— Input data hold time till 50 ns — Input data setup time tis 20 ns — Input capture pulse width (timer function) tPWIC 2 Ecyc

1.0MHz 1.25MHz Number Characteristic Symbol Unit Min Max Min Max Local bus (see Figures 7, 9)7

1 Cycle time tcyc 1.0 2.0 0.8 2.0 As 2 Pulse width, E low PWEL 430 1000 360 1000 ns 3 Pulse width, E high PWEH 450 1000 360 1000 ns 4 Clock rise and fall time tr, tr 25 25 ns

9 Non-muxed address hold time tAH 20 20 ns

11 Address delay from E low tAD 260 220 ns 17 Read data setup time tp„ 80 70 ns

18 Read data hold time tDHR 10 10 ns

19 Write data delay time tDDW 225 200 ns

21 Write data hold time t DHW 20 20 ns

23 Muxed address delay from AS tADM 90 70 ns

25 Muxed address hold time tAHL 20 110 20 110 ns

26 Delay time E to AS rise tASD 100 80 ns 27 Pulse width, AS high PWASH 220 170 ns

28 Delay time AS to E rise tASED 100 80 ns 29 Usable access timel° tAcc 570 435 ns

— Enable rise time extended t ERE 80 80 ns — Processor control setup time tpcs 200 200 ns

— Processor control hold time tPCH 20 40 20 40 ns NOTES: . Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is stress rating only and functional operation of the device at these or at any other condition above those indicated in the operation section of this specification is not implied. 2. For operating at elevated temperatures, the device must be derated based on +150°C maximum junction temperature. 3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. 4. Parameters are valid over specified temperature range. 5. All voltage measurements are referenced to ground (GND). For testing, all input signals swing between 0.4V and 2.4V with a transition time of 2Ons maximum. All time measurements are referenced at input voltages of 0.8V and 2.0V and output voltages of 0.8V and 2.0V as appropriate. 6. Except mode programming levels; see figure 16. Signetics 4.93 MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

AC ELECTRICAL SPECIFICATIONS (Continued)

1.0MHz 1.25MHz Number Characteristic Symbol Unit Min Max Min Max Synchronous system bus (see Figure 36)7 1 Cycle time tcyc 1.0 10 0.80 10 As

2 Pulse width, E low PWEL 430 9500 360 9500 ns 3 Pulse width, E high PWEH 450 9500 360 9500 ns 4 Clock rise and fall time tr, tf 25 25 ns

9 Address hold time tAH 10 10 ns

13 Address setup time before E tAH 80 70 ns 14 Chip select setup time before E tcs 80 70 ns

15 Chip select hold time tCH 10 10 ns

18 Read data hold time tDHR 30 100 30 85 ns

21 Write data hold time tDHW 10 10 ns

30 Output data delay time tDDR 290 240 ns

31 Input data setup time tDSW 165 120 ns

— Clock enable rise time extended tERE 80 80 ns

Number Characteristic Symbol Min Typ Max Unit Asynchronous system bus (see Figures 32 through 35)

Cycle time ty, 0.8 2.0 p.s — System address setup tsAs 30 ns

— System address hold tSAH 0 ns — System data delay read Semaphore tSDDR 0.3 0.3+ tcy,8 µs RAM tSDDR 315 ns

— System data valid tSDV 0 ns System data hold read tsoHR 30 90 ns — System data delay write Semaphores tSDDW ns RAM ISDDVV 60 ns

— System data hold write tSDHW• 0 ns — Data acknowledge Semaphore IDAL 0.5 0.5+ tcyc8 As

RAM II:1AL 315 ns

— Data acknowledge high tOAH 60 ns

— Data acknowledge three-state tOAT 90 ns — Data acknowledge low to CS high toes 60 ns

7. Voltage levels shown are VL , 0.5V, VH 2.4V, unless otherwise specified. 8. Actual values dependent on clock period. 9. Data need not be valid on write to semaphore registers. 10.Usable access time is computed by: t — (4 + 11+ 171.

4.94 Signetics MICROPROCESSOR DIVISION JANUARY 1983

INTELLIGENT PERIPHERAL CONTROLLER SCN681201SCN68121

Preliminary

POWER CONSIDERATIONS

The average chip-junction temperature, TJ, in °C can be obtained from' T J= TA + (PD•OJA) (11 Where: TA.Ambient Temperature, °C JA. Package Thermal Resistance, Junction-to-Ambient, °C/W PDE PINT+ PPORT PINT ICC x VCC, Watts — Chip Internal Power PpORT---- Port Power Dissipation, Watts — User Determined For most applications PPORT 4 PINT and can be neglected. PPORT may become significant if the device is configured to drive Darlington bases or sink LED loads. An approximate relationship between PD and TJ (if PpORT is neglected) is: PD= 1<*(T,j+ 273°C) 121 Solving equations 1 and 2 for K gives: K = PD*(TA + 273°C) + OjA•PD2 (31 Where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K the values of PD and Ti can be obtained by solving equations Wand (21 iteratively for any value of TA.

• V CC

RL=2.0 TEST POINT TEST POINT 0---ll MMD6150 or Equiv.

30 pF MMD7000 or Equiv.

C=90 pF for P30.P37, P40.P47, SC1, SC2 =30 pF for P20.P24, HALT/iTNNMI R=16.5 kS? for P40.P47, SC1, SC2 =12 Id2 for P30P37 =24 kS? for P20.P24, HALT/ETA/NMI

Figure 24. CMOS Load Figure 25. Timing Test Load Ports 2, 3, 4

Signetics 4.95 MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN681201SCN681 21

Preliminary

VCC E

Ri.= 750 Q

TEST POINT MMDI3150 or Equiv. P20.P24 P40.P47 INPUTS MMD7000 C=130 pF or Equiv. R=6 IQ P30.P37 INPUTS*

*Port 3 Non-Latched Operation (LATCH ENABLE= 0)

Figure 26. Timing Test Load SDO•SD7, DTACK Figure 27. Data Setup and Hold Times (MPU Read Local Bus)

MPU WHITE

E MPU ACCESS OF PORT 3*

0— tCMOS E 0— IPWD — 0.7 VCC 1111,11 ADDRESS MOM BUS ALL DATA M111111111111111 DATA VALID PORT OUTPUTS tOSD1 1OSD2

NOTES: 0S3 1. 10 k Pullup resistor required for Port 2 to reach 0.7 VCC 2. Not applicable to P21 3. Port 4 cannot be pulled above VCC

Figure 28. Data Setup and Hold Times (MPU Write Local Bus) Figure 29. Port 3 Latch Timing (Single Chip Mode)

4.96 Signetics MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

Figure 30. Expanded Non-Multiplexed Local Bus Timing

o "4--- 'ERE VEIN VEIN

SIH VEIL VEIL VEIL 0 0- 10S, RIS ADDRESS (NON-MUTED) X*00000C 0 NOTE 2

READ DATA MUXED AD DR/DATA NOTE 1 MUTED

o- -)1111-- 21 ADDRIDATA WRITE DATA MUTED NOTE 1 MUXED

0 0 ADDRESS STROBE (AS) -o 0 NOTES 1. Address valid on the occurrence of the latest of 11 or 23. 2. Usable access time is computed by 1 —(4+11+17), see note 1.

Figure 31. Local Bus Timing

Signetics 4.97 MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

SRIW

SAO-SA7 SAO-SA7

-a CS

SDO-SD7 SDO-SD7

DTACK THREE STATE DTACK THREE STATE

Figure 32. Asynchronous Read of Semaphore Register Figure 33. Asynchronous Write of Semaphore Register

SRTA7

SAO-SA7

SAO-SAT

'SAS 1SAH CS tSDDW CS 11111 tSDHW SDO-SD7 SDO-SD7 ( :DCS tDAL 'DAT tDAH DTACK THREE STATE DTACK THREE STATE

Figure 34. Asynchronous Read of RAM Figure 35. Asynchronous Write of RAM

4.98 Signetics MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT PERIPHERAL CONTROLLER SCN68120/SCN68121

Preliminary

Figure 36. Synchronous System Bus Timing

Signetics 4.99 MICROPROCESSOR DIVISION JANUARY 1983 PARALLEL INTERFACE/TIMER SCN68230

Preliminary

DESCRIPTION and a 5-bit prescaler can be used. It can PIN CONFIGURATION1 generate periodic interrupts, a square The SCN68230 Parallel Interface/Timer wave or a single interrupt after a program- (PUT) provides versatile double buffered med time period. Also it can be used for DEM E04 parallel interfaces and an operating sys- elapsed time measurement or as a device tem oriented timer to S68000 systems. The DEM E D3 watchdog. Table 1 is a summary of the in- parallel interfaces operate in unidirec- E D2 put and output signals and Figure 1 shows D71 tional or bidirectional modes, either 8 or the functional pin assignments. Figure 2 PAGE E D1 16 bits wide. In the unidirectional modes, is a PUT system block diagram. an associated data direction register PA1 E DO determines whether the port pins are in- FEATURES PA2 E RIW puts or outputs. In the bidirectional • S68000 bus compatible PA3M E DTACK modes, the data direction registers are ig- • Port modes include: PA41E, nored and the direction is determined Ea Bit I/O dynamically by the state of four hand- PA5I 40 CLK Unidirectional 8-bit and 16-bit shake pins. These programmable hand- Bidirectional 8-bit and 16-bit PA6 10 ERESET shake pins provide an interface flexible • Selectable handshaking options PA7 E E vss enough for connection to a wide variety of • 24-Bit programmable timer low, medium, or high speed peripherals or vccE EPC7/TIACK • Software programmable timer modes other computer systems. The PI/T ports • Contains interrupt vector generation H1 E E PC6IPIACK allow use of vectored or autovectored in- logic H2 14 E PCS/PIRO terrupts, and also provide a DMA request • Separate port and timer interrupt pin for connection to direct memory access H3 E E PC4IDMAREO service requests controllers. The PUT timer contains a 24-bit H4 16 E PC3ITOUT • Registers are read/write and directly counter and a 5-bit prescaler. The timer addressable PI30 17 E PC2/TIN can be clocked by the system clock (PUT • Registers are addressed for MOVEP PB1E EPCI CLK pin) or by an external clock (TIN pin), (move peripheral) and DMAC com• PB2 19 E PCO patibility PB3 20 29 RS1 PB4 E E RS2 ORDERING CODE PB5 22 ERS3 Vcc -,- 5V -1- 5%, TA = 0° to 70°C P136 23 E RS4 Packages 8 MHz 10 MHz PB7 24 ERS5

Ceramic DIP SCN68230C8I48 SCN68230CA148 TOP VIEW Plastic DIP SCN68230C8N48 SCN68230CAN48

DO D7 PAO.7 PBO.7 RS1•11S5

RIW H1 H2 Cs i H3 DTACK H4

PC7/TIAC K. PC6/PIACK. PCE/PIRO* CLK PC4/DMAR ED PC3/TOUT• vcc PC2/TIN• PC1 GND PCO *Individ ally Programmable Dual Function Pin. Figure 1. Functional Pin Assignment

11n this data sheet, barring signal names (overscore) to indicate low is done only for the pin configuration diagram, signal description headings, tables and figures.

4.100 Signetics

MICROPROCESSOR DIVISION JANUARY 1983

PARALLEL INTERFACE/TIMER SCN68230

Preliminary

38 39 40 41 42 43 44 45 46 47 48 1 2 3 Vss RESET CLK CS DTACK RIW DO D1 D2 D3 D4 D5 D6 D7

DATA BUS INTERFACE AND INTERRUPT VECTOR REGISTERS

PAO 4 PA1 5 PA2 6 PORT INTERNAL PORT PA3 7 INTERRUPT/ DATA BUS A PA4 8 DMA PA5 9 CONTROL PA6 10 LOGIC PA7 11

VCC 12

HANDSHAKE I-11 13 CONTROLLERS HANDSHAKE H2 14 AND INTERFACE LOGIC H3 15 MODE LOGIC ••11--0.- H4 16 TIMER

PB0 17 PB1 18 PB2 19 PORT PB3 20 B ••••• P B4 21 PBS 22 PB6 23 PB7 24

PORT C AND PIN FUNCTION MULTIPLEXER

# PC7/ PC6I PC5/ PC4/ PC3/ PC2/ PC1 PCO RS1 RS2 RS3 RS4 RS5 TIACK PIACK PIRA DMAREQ TOUT TIN 31 30 29 28 27 26 25 37 36 35 34 33 32

Signetics 4-101 MICROPROCESSOR DIVISION JANUARY 1983 PARALLEL INTERFACE/TIMER SCN68230

Preliminary Table 1 SIGNAL SUMMARY Signal Name Mnemonic Input/Output Active State Three State Bidirectional Data Bus DO-D7 input/output high yes Register Selects RS1-RS5 input high — Read/Write Input R/W input read-high — write-low Chip Select CS input low — Data Transfer Acknowledge DTACK output low yes Reset RESET input low — Clock Input CLK input high — Port A and Port B PAO-PA7, PBO-PB7 input/output high yes Handshake H1, H3 input programmable — Handshake H2, H4 input/output programmable yes Port C PCO-PC7 input/output high yes Ground VSS input — — Power Input VCC input — —

DO-D15 A1-A23 R/W WWI RS1-RS5 DO-D7 ADDRESS FC2.0 AND lbw CS LDS IACK PAO.7 DECODE fiPBO-7 PC6/PIACK +Qv H1 411.. PC7/TIACK H2 SCN68000 SCN68230 -atffl H3 —01--viv-- H4 PC5IPIRO IPL2 PC4I PC3/TOUT 011/TKE IPL1 LS348 + 5V PC2/TIN IPLO —01—s. PC1 PCO DTACK DTACK RESET CLK Vcc Vss

Figure 2. PINT System Block Diagram

4.102 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 PARALLEL INTERFACE/TIMER SCN68230

Preliminary

GENERAL DESCRIPTION DTACK pins (PCO-PC7) or any combination of six Data transfer acknowledge output. DTACK special function pins and two general pur- The PUT consists of two logically indepen- pose I/O pins (PCO-PC1). (Each dual func- dent sections; the ports and the timer. The is an active low output that signals the completion of the bus cycle. During read tion pin can be standard I/O or a special port section consists of port A (PA0-7), or interrupt acknowledge cycles, DTACK function independent of the other port C port B (PBO-7), four handshake pins (H1, is asserted by the SCN68230 after data pins.) When used as a port C pin, these H2, H3, and H4), two general I/O pins, and pins are active high. They can be in- six dual-function pins. The dual-function has been provided on the data bus; during write cycles it is asserted after data has dividually programmed as inputs or out- pins can individually operate as a third puts by the Port C data direction register. port (port C) or an alternate function been accepted at the data bus. Data transfer acknowledge is compatible with related to either ports A and B, or the The alternate functions (TIN, TOUT, and timer. The four programmable handshake the SCN68000 and with other bus masters such as the SCB68430 DMA controller. A TIACK) are timer I/O pins. TIN can be used pins, depending on the mode, can control as a rising-edge triggered external clock data transfer to and from the ports, or can holding resistor is required to maintain DTACK high between bus cycles. input or an external run/halt control pin be used as interrupt generating inputs, or (the timer is in the run state if run/halt is I/O pins. RESET high and in the halt state if run/halt is low). The timer consists of a 24-bit counter, Reset input. RESET is used to initialize all TOUT can provide an active low timer in- 4 optionally clocked by a 5-bit prescaler. PUT functions. All control and data direc- terrupt request output or a general- Three pins provide complete timer I/O: tion registers are cleared and most inter- purpose square-wave output, initially high. PC2/TIN, PC3/TOUT, and PC7/TIACK. In nal operations are disabled by the asser- TIACK is an active low input used for timer specific applications, only the pins tion of RESET (low). interrupt acknowledge. needed for the given configuration perform the timer function, while the others CLK Port A and B functions have an indepen- remain port C I/O. Clock input. The clock pin is a TTL- dent pair of active low interrupt request compatible input with the same specifica- (PIRQ) and interrupt acknowledge (PIACK) The system bus interface provides for tions as the SCN68000. The PUT contains pins. asynchronous transfer of data from the dynamic logic throughout, and hence this PUT to a bus master over the data bus clock must not be gated off at any time. It The DMAREQ (direct memory access re- (D0-D7). Data transfer acknowledge is not necessary that this clock maintain quest) pin provides an active low direct (DTACK), register selects (RS1-RS5), chip any particular phase relationship with the memory access controller (DMAC) request select, the read/write line (R/W), and port SCN68000 clock. It can be connected to pulse of three clock cycles. interrupt acknowledge (PIACK) or timer in- an independent frequency source (faster terrupt acknowledge (TIACK) control data or slower) as long as all bus specifications transfer between the PUT and the are met. SC68000. REGISTER MODEL PAO.PA7 and PBO.PB7 A register model that includes the cor- PIN DESCRIPTIONS Port A and port B. Ports A and B are 8-bit responding register selects is shown in ports that can be concatenated to form a DO-D7 Table 2. 16-bit port in certain modes. The ports can Bidirectional data bus. The data bus pins be controlled in conjunction with the DO-D7 form an 8-bit bidirectional data bus handshake pins H1-H4. For stabilization to/from the SCN68000 or other bus mas- during system power-up, ports A and B ter. These pins are active high. PORT FUNCTIONAL have internal pullup resistors to Vcc. All port pins are active high. DESCRIPTION RS1-11S5 Register selects. RS1-RS5 are active high, Hl-F14 Port Control Structure high-impedance inputs that determine Handshake pins (I/O depending on the The primary focus of most applications which of the 25 internal PUT registers is mode and submode). Handshake pins will be on ports A and B, the handshake being addressed. H1-H4 are multi-purpose pins that (de- pins, the port interrupt pins, and the DMA pending on the operational mode) can pro- request pin. The ports are controlled by R / VV. vide an interlocked handshake, a pulsed the port general control register which Read/write Input. R/W is the read/write handshake, an interrupt input (indepen- contains a 2-bit field that specifies a set of signal from the SCN68000 or bus master, dent of data transfers), or simple I/O pins. four operation modes. These govern the indicating whether the current bus cycle For stabilization during system power-up, overall operation of the ports and deter- is a read (high) or write (low) cycle. H2 and H4 have internal pullup resistors to mine their interrelationships. Some Vcc. Their sense (active high or low) can modes require additional information from CS be programmed in the port general control each port's control register to further Chip select input. The CS input selects the register bits 3-0. Independent of the mode, define its operation. In each port control PUT registers for the current bus cycle. the instantaneous level of the handshake register, there is a 2-bit submode field that Address strobe and the data strobe (upper pins can be read from the port status serves this purpose. Each port mode/sub- or lower) of the bus master, along with the register. mode combination specifies a set of pro- appropriate address bits, must be in- grammable characteristics that fully cluded in the chip select equation. A low Port C define the behavior of that port and two of level corresponds to an asserted chip (PCO-PC7/alternate function). This port the handshake pins. This structure is sum- select. can be used as eight general purpose I/O marized in Table 3 and Figure 3. Signetics 4.103 MICROPROCESSOR DIVISION JANUARY 1983 PARALLEL INTERFACE/TIMER SCN68230

Preliminary Table 2 REGISTER MODEL Register Select Bits 5 4 3 2 1 6 5 3 0 Port Mode H34 H12 H4 H3 H2 H1 Port General 0 0 0 0 0 Control Enable Enable Sense Sense Sense Sense Control Register Port Interrupt Port Service 0 0 0 0 1 it SVCRO Inte rupt Select FFS Priority Control Request Register Port A Data 0 0 0 1 0 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Direction Register Port B Data 0 0 0 1 Bit Bit Bit Bit Bit Bit Bit Bit Direction Register 7 6 5 4 3 2 1 0 Port C Data 0 0 1 0 0 Bit Bit Bit Bit Bit Bit Bit Bit Direction Register 7 6 5 4 3 2 1 0 Port Interrupt 0 0 1 0 1 Interrupt Vector Number Vector Register H2 H1 H1 Port A Control 0 0 1 1 0 Port A H2 Control Int SVCRO Stat Submode Enable Enable Ctrl. Register H4 H3 H3 2 0 0 1 1 1 Pot B H4 Control Int SVCRO Stat p rgtisyeicontrol Submode Enable Enable Ctrl. Bit Port A Data 0 1 0 0 0 Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Register Port B Data 0 1 0 0 1 Bit Bit Bit . Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Register Port A Alternate 0 1 0 1 0 Bit Bit Bit Bit Bit Bit Bit Bit Register 7 6 5 4 3 2 1 0 Port B Alternate 0 1 0 1 1 Bit Bit Bit Bit Bit Bit Bit Bit Register 7 6 5 4 3 2 1 0 Port C Data 0 1 1 0 0 Bit Bit Bit Bit Bit Bit Bit Bit Register 7 6 5 4 3 2 1 0 Port Status 0 1 1 0 H3 H2 H1 H4 Register Level Level Level Level H4S H3S H2S HI S 0 1 1 1 0 (null) 0 1 1 1 1 (null) 1 0 0 0 0 TOUT/TIACK Z D Clock Timer Timer Control Control CM. Control Enable Register Bit Bit Bit Bit Bit Bit Bit Bit 1 0 0 0 1 Timer Interrupt 7 6 5 4 3 2 1 0 Vector Register 1 0 0 1 0 (null) Bit Bit Bit Bit Bit Bit Bit Bit Counter Preload 1 0 0 1 1 23 22 21 20 19 18 17 16 Register (Highl Bit Bit Bit Bit Bit Bit Bit Bit 1 0 1 0 0 15 14 13 12 11 10 9 8 IMid) Bit Bit - Bit Bit Bit Bit Bit Bit 1 0 1 0 1 7 6 5 4 3 2 1 0 (Low) 1 0 1 1 0 * * * * * * * * (null) Bit Bit Bit Bit Bit Bit Bit Bit Count Register 1 0 1 1 1 23 22 21 20 19 18 17 16 (High) Bit Bit Bit Bit Bit Bit Bit Bit 1 1 0 0 0 (Mid) 15 14 13 12 11 10 9 8 Bit Bit Bit Bit Bit Bit Bit Bit 1 1 0 0 1 (Low) 7 6 5 4 3 2 1 0 Timer Status 1 1 0 1 0 * * * * * * * ZDS Register 1 1 0 1 1 (null) 1 1 1 0 0 (null) 1 1 1 0 1 (null) 1 1 1 1 0 (null) *Unused, read as zero. 1 1 1 1 1 (null)

4.104 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PARALLEL INTERFACEITIMER SCN68230

Preliminary

Table 3 PORT MODE CONTROL SUMMARY Port General Information and Conventions The following paragraphs introduce con- cepts that are generally applicable to the Mode 0 (Unidirectional 8-Bit Mode) 131/T ports independent of the chosen Port A mode and submode. For this reason, no Submode 00 — Double-Buffered Input particular port or handshake pins are men- H1 — Latches input data tioned; the notation H1 (H3) indicates that, H2 — Status/interrupt generating input, general-purpose depending on the chosen mode and sub- output, or operation with H1 in the interlocked or mode, the statement given may be true for pulsed input handshake protocols either the H1 or H3 handshake pin. Submode 01 — Double-Buffered Output H1 — Indicates data received by peripheral H2 — Status/interrupt generating input, general-purpose Unidirectional vs Bidirectional—Figure 3 output, or operation with H1 in the interlocked or shows the configuration of ports A and B pulsed output handshake protocols and each of the handshake pins in each Submode 1X — Bit I/O port mode and submode. In modes 0 and H1 — Status/interrupt generating input 1, a data direction register is associated 4 H2 — Status/interrupt generating input or general-purpose with each of the ports. These registers output contain one bit for each port pin to deter- Port B, H3 and H4 — Identical to Port A, H1 and H2 mine whether that pin is an input or an output. Modes 0 and 1 are, thus, called Mode 1 (Unidirectional 16-Bit Model unidirectional modes because each pin Port A — Double-Buffered Data (Most significant) assumes a constant direction, changeable Submode XX (not used) only by a reset condition or a program- H1 — Status/interrupt generating input ming change. These modes allow double H2 — Status/interrupt generating input or general-purpose buffered data transfers in one direction. output This direction, determined by the mode Port B — Double-Buffered Data (Least significant) and submode definition, is known as the Submode XO — Unidirectional 16-Bit Input primary direction. Data transfers in the H3 — Latches input data primary direction are controlled by the H4 — Status/interrupt generating input, general-purpose handshake pins. Data transfers not in the output, or operation with H3 in the interlocked or primary direction are generally unrelated, pulsed input handshake protocols and single or unbuffered data paths exist. Submode X1 — Unidirectional 16-Bit Output H3 — Indicates data received by peripheral In modes 2 and 3 there is no concept of H4 — Status/interrupt generating input, general-purpose primary direction as in modes 0 and 1. Ex- output, or operation with H3 in the interlocked or cept for port A in mode 2 (bit I/0), the data pulsed output handshake protocols direction registers have no effect. These modes are bidirectional, In that the direc- Mode 2 (Bidirectional 8-Bit Mode) tion of each transfer (always 8 or 16 bits, Port A — Bit I/O with no handshaking pins) double buffered) is determined dynamical- Submode XX (not used) ly by the state of the handshake pins. Port B — Bidirectional 8-Bit Data (Double-Buffered) Thus, for example, data may be transfer- Submode XX (not used) red out of the ports, followed very shortly H1 Indicates output data received by peripheral by a transfer into the same port pins. H2 — Operation with H1 in the interlocked or pulsed output Transfers to and from the ports are in- handshake protocols dependent and may occur in any se- H3 Latches input data quence. Since the instantaneous direction H4 — Operation with H3 in the interlocked or pulsed input is always determined by the external handshake protocols system, a small amount of arbitration logic may be required. Mode 3 (Bidirectional 16-Bit Mode) Port A — Double-Buffered Data (Most significant) Submode XX (not used) • Control of Double Buffered Data Paths— Port B — Double-Buffered Data (Least significant) Generally speaking, the PI/T is a double Submode XX (not used) buffered device. In the primary direction, H1 — Indicates output data received by peripheral double buffering allows orderly transfers H2 — Operation with H1 in the interlocked or pulsed output by using the handshake pins in any of handshake protocols several programmable protocols. (When H3 — Latches input data bit I/O is used, double buffering is not H4 — Operation with H3 in the interlocked or pulsed input available and the handshake pins are used handshake protocols as outputs or status/interrupt inputs.)

Signetics 4.105 MICROPROCESSOR DIVISION JANUARY 1983 PARALLEL INTERFACE/TIMER SCN68230

Preliminary

2. H2(H4) may be a general purpose output pin that is always negated. The MODE 0 SUBMODE 00 MODE 0 SUBMODE 01 MODE 0 SUBMODE 1X H2S(H4S) status bit is always 0.

A (B) A (B) A (B) 3. H2(H4) may be a general purpose out- 8 8 8 put pin that is always asserted. The LATCHED, DOUBLE. DOUBLE.BUFFERED BIT I/O H2S(H4S) status bit is always 0. BUFFERED INPUT OUTPUT H1(H3) H1(H3) H1(H3) 4. H2(H4) may be an output pin in the in- H2(H4) H2(H4) H2(H4) terlocked input handshake protocol. It is asserted when the port input latches are ready to accept new data. It is MODE 1 PORT B SUBMODE X0 MODE I PORT B SUBMODE X1 negated asynchronously following the H1 H1 asserted edge of the H1(H3) input. As H2 H2 soon as the input latches become A AND B A AND B ready, H2(H4) is again asserted. When (16) (16) the input double buffered latches are 401 full, H2(H4) remains negated until data LATCHED DOUBLE- DOUBLE.BUFFERED BUFFERED INPUT OUTPUT is removed. Thus, anytime the H2(H4) -44 H3 H3 output is asserted, new input data may H4 H4 be entered by asserting H1(H3). At other times, transitions on H1(H3) are ignored. The H2S(H4S) status bit is MODE 2 MODE 3 always 0. When H12 enable (H34 enable) is 0, H2(H4) is held negated. A (8) A AND B (16) 5. H2(H4) may be an output pin in the BIT I/O BIDIRECTIONAL 16 BIT pulsed input handshake protocol. It is asserted exactly as in the interlocked B (8) H2" T'lijTAXFERS input protocol, but never remains H3 INPUT asserted longer than 4 clock cycles. BIDIRECTIONAL 8 BIT H: TRANSFERS Typically, a four clock cycle pulse is HI generated. But in the case where a P12 CPUTTRANSFERS subsequent H1(H3) asserted edge occurs before termination of the pulse, H38TRANSFERS4 NPUT H2(H4) is negated asynchronously. Thus, anytime after the leading edge of the H2(H4) pulse, new data can be entered in the PUT double buffered in- Figure 3. Port Mode Layout put latches. The H2S(H4S) status bit is always 0. When H12 enable (H34 enable) is 0, H2(H4) is held negated.

Use of double buffering is most beneficial times are observed. The PUT contains a A sample timing diagram is shown in in situations where a peripheral device port status register whose H1S(H3S) Figure 4. The H2(H4) interlocked and and the computer system are capable of status bit is set anytime any input data is pulsed input handshake protocols are transferring data at roughly the same present in the double buffered latches shown. The DMAREQ pin is also shown speed. Double buffering allows the fetch that has not been read by the bus master. assuming it is enabled. All handshake pin operation of the data transmitter to be The action of H2(H4) is programmable; it sense bits are assumed to be 0 (refer to overlapped with the store operation of the may indicate whether there is room for Port General Control Register); thus, the data receiver. Thus, throughput measured more data in the PUT latches or it may pins are in the low state when asserted. in bytes or words per second can be great- serve other purposes. The following op- Due to the great similarity between ly enhanced. If there is a large mismatch tions are available, depending on the modes, this timing diagram is applicable in transfer capability between the com- mode. to all double buffered input transfers. puter and the peripheral, little or no benefit is obtained. In these cases there is Double Buffered Output Transfers—The no penalty in using double buffering. 1. H2(H4) may be an edge sensitive input PUT supports double buffered output that is independent of H1(H3) and the transfers in all modes. Data, written by the Double Buffered Input Transfers—In all transfer of port data. On the asserted bus master to the PUT, is stored in the modes, the PUT supports double buffered edge of H2(H4), the H2S(H4S) status bit port's output latch. The peripheral accepts input transfers. Data that meets the port is set. It is cleared by the direct method the data by asserting H1(H3), which setup and hold times is latched on the (refer to Direct Method of Resetting causes the next data to be moved to the asserted edge of H1(H3). H1(H3) is edge Status), the RESET pin being asserted, port's output latch as soon as it is sensitive, and may assume any duty cycle or when the H12 enable (H34 enable) bit available. The function of H2(H4) is pro- as long as both high and low minimum of the port general control register is O. grammable; it may indicate whether new

4.106 Signetics MICROPROCESSOR DIVISION JANUARY 1983

PARALLEL INTERFACE/TIMER SCN68230

Preliminary

READ READ 11111(VA••Ar•••AsaigA••••AAAA PORT DATA V4AV I JA VA

H1(H3)

112(14) INTERLOCKED

H2(H4) PULSE

DMAREO

Figure 4. Double Buffered input Transfers

data has been moved to the output latch 4. H2(H4) may be an output pin in the in- shown. The DMAREQ pin is also shown or it may serve other purposes. The terlocked output handshake protocol. assuming it is enabled. All handshake pin H1S(H3S) status bit may be programmed H2(H4) is asserted two clock cycles sense bits are assumed to be 0; thus, the for two interpretations. Normally the after data is transferred to the double pins are in the low state when asserted. status bit is a 1 when there is at least one buffered output latches. The data re- Due to the great similarity between latch in the double buffered data path that mains stable and H2(H4) remains as- modes, this timing diagram is applicable can accept new data. After writing one serted until the next asserted edge of to all double buffered output transfers. byte/word of data to the ports, an interrupt the H1(H3) input. At that time, H2(H4) is service routine could check this bit to asynchronously negated. As soon as Requesting Bus Master Service—The PUT determine if it could store another the next data is available, it is trans- has several means of indicating a need for byte/word; thus, filling both latches. When ferred to the output latches. When service by a bus master. First, the pro- the bus master is finished, it is often H2(H4) is negated, asserted transitions cessor may poll the port status register. It useful to be able to check whether all of on H1(H3) have no effect on the data contains a status bit for each handshake the data has been transferred to the paths. As is explained later, however, pin, plus a level bit that always reflects the peripheral. The H1S(H3S) status control in modes 2 and 3 they do control the instantaneous state of that handshake bit of the port A and B control registers three-state output buffers of the pin. A status bit is 1 when the PUT needs provide this flexibility. The programmable bidirectional port(s). The H2S(H4S) servicing, i.e., generally when the bus options of the H2(H4) pin are given below, status bit is always 0. When H12 enable master needs to read or write data to the depending on the mode. (H34 enable) is 0, H2(H4) is held ports, or when a handshake pin used as a negated. simple status input has been asserted. 1. H2(H4) may be an edge sensitive input The interpretation of these bits is depen- pin independent of H1(H3) and the 5. H2(H4) may be an output pin in the dent on the chosen mode and submode. transfer of port data. On the asserted pulsed output handshake protocol. It is edge of H2(H4), the H2S (H4S) status asserted exactly as in the interlocked Second, the PINT may be placed in the pro- bit is set. It is reset by the direct output protocol above, but never re- cessor's interrupt structure. As mention- method (refer to Direct Method of mains asserted longer than four clock ed previously, the PUT contains port A and Resetting Status), the RESET pin being cycles. Typically, a four clock pulse is B control registers that configure the asserted, or when the H12 enable (I-134 generated. But in the case where a sub- handshake pins. Other bits in these enable) bit of the port general control sequent H1(H3) asserted edge occurs registers enable an interrupt associated register is 0. before termination of the pulse, H2(H4) with each handshake pin. This interrupt is is negated asynchronously shortening made available through the PC5/PIRQ pin, 2. H2(H4) may be a general purpose out- the pulse. The H2S(H4S) status bit is if the PIRA function is selected. Three ad- put pin that is always negated. The always 0. When H12 enable (H34 ditional conditions are required for PIRA H2S(H4S) status bit is always 0. enable) is 0, H2(H4) is held negated. to be asserted: (1) the handshake pin status bit is set, (2) the corresponding in- 3. H2(H4) may be a general purpose out- A sample timing diagram is shown in terrupt (service request) enable bit is set, put pin that is always asserted. The Figure 5. The H2(H4) interlocked and and (3) DMA requests are not associated H2S(H4S) status bit is always 0. pulsed output handshake protocols are with that data transfer (Ni and H3 only). Signetics 4.107 MICROPROCESSOR DIVISION JANUARY 1983 PARALLEL INTERFACE/TIMER SCN68230

Preliminary

WRITE WRITE

PORT DATA 111•1111111111111111111•1111, H2(H4) INTERLOCKED

H2(H4) PULSE

Hl(H3)

DMAREO

Figure 5. Double Buffered Output Transfers

The conditions from each of the four hand- not asserting PIRO, the Pin- will make no except that no vectors are supplied and shake pins and corresponding status bits response to PIACK (DTACK will not be the PC6/PIACK pin can be used as a port C are ORed to determine PIRO. asserted). If the PUT is asserting PIRQ pin. when PIACK is received, the PUT will out- The third method of requesting service is put the contents of the PIVR and the Direct Method of Resetting Status—In via the PC4/DMAREQ pin. This pin can be prioritization bits. If the PIVR has not been certain modes one or more handshake associated with double buffered transfers intialized, SOF will be read from this pins can be used as edge sensitive inputs in each mode. If it is used as a DMA con- register. These conditions are summa- for the sole purpose of setting bits in the troller request, it can initiate requests to rized in Table 4. port status register. These bits consist of keep the PI/T's input/output double buffer- simple flip flops. They are set (to 1) by the ing empty/full as much as possible. It will The vector table entries for the PUT appear occurrence of the asserted edge of the not overrun the DMA controller. as a contiguous block of four vector handshake pin input. Resetting a hand- numbers whose common upper six bits shake status bit can be done by writing an are programmed in the PIVR. The follow- 8-bit mask to the port status register. This Vectored, Prioritized Port Interrupts—Use ing list pairs each interrupt source with is called the direct method of resetting. To of SCN68000 compatible vectored inter- the 2-bit value provided by the prioritiza- reset a status bit that is resettable by the rupts with the PUT requires the PIRO and tion logic, when interrupt acknowledge is direct method, the mask must contain a 1 PIACK pins. When PIACK is asserted, the asserted. in the bit position of the port status PUT places an 8-bit vector on the data pins register corresponding to the desired bit. D0-D7. Under normal conditions, this vec- Other positions must contain 0's. For tor corresponds to highest priority, H1 source-00 status bits that are not resettable by the enabled, active port interrupt source with H2 source-01 direct method in the chosen mode, the which the DMAREQ pin is not currently H3 source-10 data written to the port status register has associated. The most significant six bits H4 source-11 no effect. For status bits that are reset- are provided by the port interrupt vector table by the direct method in the chosen register (PIVR), with the lower two bits Autovectored Port Interrupts—Autovec- mode, a 0 in the mask has no effect. supplied by prioritization logic according tored interrupts use only the PIRO pin. to conditions present when PIACK is The operation of the PUT with vectored Handshake Pin Sense Control—The PUT asserted. It is important to note that the and autovectored Interrupts is identical contains exclusive OR gates to control the only effect on the PUT caused by interrupt acknowledge cycles is that the vector is Table 4 RESPONSE TO PORT INTERRUPT ACKNOWLEDGE placed on the data bus. Specifically, no registers, data, status, or other internal PIRO negated OR interrupt states of the PUT are affected by the cycle. Conditions request function not selected PIRO asserted PIVR has not been initialized No response from PI/T. PI/T provides SOF, the since RESET No DTACK. Uninitialized Vector.* Several conditions may be present when PIVR has been initialized the PIACK input is asserted. These condi- No response from PI/T. PI/T provides PIVR contents since RESET No DTACK. with prioritization bits. tions affect the PI/T's response and the termination of the bus cycle. If the PUT The uninitialized vector is the value returned from an interrupt vector register before it has has no interrupt function selected, or is been initialized.

4-108 Signetics MICROPROCESSOR DIVISION JANUARY 1983 1 PARALLEL INTERFACE/TIMER SCN68230

Preliminary

sense of each of the handshake pins, Handshake pins H1 and H2 are associated wanted read cycles. Refer to Figure 4 for a whether used as inputs or outputs. Four with port A and configured by program- sample timing diagram. bits in the port general control register ming the port A control register. (The H12 can be programmed to determine whether enable bit of the port general control MODE 0 SUBMODE 00 the pins are asserted in the low or high register enables port A transfers.) Hand- voltage state. As with other control shake pins H3 and H4 are associated with A (B) registers, these bits are reset to 0 when port B and configured by programming the the RESET pin is asserted, defaulting the port B control register. (The H34 enable bit asserted level to be low. of the port general control register LATCHED, DOUBLE. BUFFERED INPUT enables port B transfers.) The port A and B Enabling Ports A and B — Certain func- data direction registers operate in all three H7(H3) tions involved with double buffered data submodes. Along with the submode, they H2(H4) transfers, the handshake pins, and the affect the data read and written at the status bits, can be disabled by the exter- associated data register according to nal system or by the programmer during Table 5. They also enable the output buffer Port A or B Submode 01 (8.1311 Double Buf initialization. The port general control associated with each port pin. The fared Output)— I n mode 0, double buf- register contains two bits, H12 enable and DMAREQ pin may be associated with fered output transfers of up to 8 bits are H34 enable, which control these func- 4 either (not both) port A or port B, but does available by programming submode 01 in tions. These bits are cleared to the 0 state not function if the bit I/O submode is pro- the desired port's control register. The when the RESET pin is asserted, and the grammed for the chosen port. operation of H2 and H4 can be selected by functions are disabled. The functions are programming the port A and port B control the following: Port A or B Submode 00 (8-1311 Double Buf- registers, respectively. All five double buffered Input)— In mode 0, double buffered fered output handshake options, previous- 1. Independent of other actions by the input transfers of up to 8-bits are available ly mentioned in the Port General Informa- bus master or peripheral (via the hand- by programming submode 00 in the tion and Conventions section, are shake pins), the PI/T's disabled hand- desired port's control register. The opera- available. shake controller is held to the 'empty' tion of H2 and H4 can be selected by pro- state, i.e., no data is present in the dou- gramming the port A and port B control For pins used as inputs, data written to ble buffered data path. registers, respectively. All five double buf- the associated data register is double buffered input handshake options, previously fered and passed to the initial or final out- 2. When any handshake pin is used to set mentioned in the Port General Information put latch, as usual, but the output buffer is a simple status flip flop, unrelated to and Conventions section, are available. disabled. Refer to Figure 5 for a sample double buffered transfers, these flip timing diagram. flops are held reset to 0 (see Table 3). For pins used as outputs, the data path consists of a single latch driving the out- When H2(H4) is used in an interlocked MODE 0 SUBMODE 01 3. put buffer. Data written to the port's data or pulsed handshake with H1(H3), register does not affect the operation of H2(H4) is held negated, regardless of A (B) any handshake pin, status bit, or any other 8 the chosen mode, submode, and aspect of the PI/T. Output pins can be primary direction. Thus, for double buf- used independently of the input transfer. DOUBLE-BUFFERED fered input transfers, the programmer However, read bus cycles to the data OUTPUT can signal a peripheral when the PUT is register do remove data from the port. H1(H3) ready to begin transfers by setting the Therefore, care should be taken to avoid H2(H4) associated handshake enable bit to 1. processor instructions that perform un- The Port A and B Alternate Registers—In addition to the port A and B data registers, Table 5 MODE 0 PORT DATA PATHS the PUT contains port A and B alternate registers. These registers are read only, Read Port A/B Write Port A/B and simply provide the instantaneous Mode Data Register Data Register level of each port pin. They have no effect DDR = 0 DDR =1 DDR = X on the operation of the handshake pins, 0 Submode 00 FIL, D.B. FOL Note 3 FOL, S.B. Note 1 double buffered transfers, status bits, or 0 Submode 01 Pin FOL Note 3 IOL/FOL, D.B. Note 2 any other aspect of the PI/T, and they are 0 Submode 1X Pin FOL Note 3 FOL, S.B.Note 1 mode/submode independent. Abbreviations: IOL — Initial Output Latch S.B. — Single Buffered PORT MODES FOL — Final Output Latch D.B. — Double Buffered FIL — Final Input Latch DDR — Data Direction Register Mode 0—Unidirectional 8-Bit Mode Note 1: Data is latched in the output data registers (final output latch) and will be In mode 0, ports A and B operate in- single buffered at the pin if the DDR is 1. The output buffers will be turned dependently. Each can be configured in off if the DDR is 0. any of its three possible submodes: Note 2: Data is latched in the double-buffered output data registers. The data in the Submode 00— Double buffered input final output latch will appear on the port pin if the DDR is a 1. Submode 01—Double buffered output Note 3: The output drivers that connect the final output latch to the pins are turned Submode 1X—Bit I/O on. Signetics 4-109

MICROPROCESSOR DIVISION JANUARY 1983 PARALLEL INTERFACE/TIMER SCN68230

Preliminary

Port A or B Submode 1X (Bit I/0)— In mode direction registers operate in each sub- transfers needed for compatibility with 0, simple bit I/O is available by program- mode. Along with the submode, they af- the PI/T.) H4 can be programmed for all ming submode lx in the desired port's fect the data read and written at the data five of the handshake options mentioned control register. This submode is intended register according to Table 6. They also in the Port General Information and Con- for applications in which several indepen- enable the output buffer associated with ventions section. dent devices must be controlled or each port pin. The DMAREQ pin can be For pins used as outputs, the data path monitored. Data written to the associated associated only with H3. data register is single buffered. If the data consists of a single latch driving the output buffer. Data written to the port's data direction register bit for that pin is a 1 (out- Mode 1 can provide convenient, high register does not affect the operation of put), the output buffer is enabled. If it is 0 speed 16-bit transfers. The port A and B any handshake pin, status bit, or any other (input), data written is still latched, but is data registers are addressed for compati- aspect of the PI/T. Thus, output pins can not available at the pin. Data read from the bility with the SCN68000 move peripheral be used independently of the input data register is the instantaneous value of (MOVEP) instruction and with the S68000 transfer. However, read bus cycles to the the pin or what was written to the data DMA controllers. To take advantage of port B data register do remove data, so register, depending on the contents of the this, port A should contain the most care should be taken to avoid unwanted data direction register. H1(H3) is an edge significant byte of data and always be read read cycles. sensitive status input pin only and it con- or written by the bus master first. The in- trols no data related function. The terlocked and pulsed handshake pro- MODE 1 PORT B SUBMODE XO H1S(H3S) status bit is set following the tocols are keyed to accesses to the port B H1 asserted edge of the input waveform. It is data register in mode 1. If it is accessed H2 reset by the direct method, the RESET pin last, the 16-bit double buffered transfers being asserted, or when the H12 enable proceed smoothly. A AND B (H34 enable) bit is 0. (181 Port B Submode XO (16-Bit Double Buf- LATCHED, DOUBLE. H2(H4) can be programmed as a simple fered Input)— In mode 1 port B submode BUFFERED INPUT status input (identical to H1(H3)), or as an XO, double buffered input transfers of up H3 asserted or negated output. The inter- to 16-bits can be obtained. The level of all locked or pulsed handshake configura- 16 pins is asynchronously latched with the H4 tions are not available. asserted edge of H3. The processor can check the H3S status bit to determine if Port B Submode X1 (16-Bit Double Buf- new data is present. The DMAREQ pin can fered Output)— Refer to Figure 4 for a sam- MODE 0 SUBMODE 1X be used to signal a DMA controller to ple timing diagram. In mode 1 port B sub- empty the input buffers. Regardless of the mode X1, double buffered output transfers A (B) 8 bus master, port A data should be read of up to 16 bits can be obtained. Data is first. (Actually, port A data need not be written by the bus master (processor or BIT 110 read at all.) Port B data should be read last. DMA controller) in two bytes. The first The operation of the internal handshake byte (most significant) is written to the H1 (H3) controller, the H3S bit, and DMAREQ are port A data register. It is stored in a tem- H2 (H4) keyed to the reading of the port B data porary latch until the next byte is written register. (The S68000 DMA controllers can to the port B data register. Then all 16 bits be programmed to perform the exact are transferred to the final output latches Mode 1— Unidirectional 16-Bit Mode In mode 1, ports A and B are concatenated Table 6 MODE 1 PORT DATA PATHS to form a single 16-bit port. The port B submode field controls the configuration of Read Port A/B Write Port A/B both parts. The possible submodes are: Mode Register Register DDR = 0 DDR =1 DDR = 0 DDR = 1 Port B submode X0—double buffered 1, Port B FIL, D.B. FOL FOL, S.B. FOL, S.B. input Submode XO Note 3 Note 2 Note 2 Port B submode X1—double buffered 1, Port B Pin FOL 10L/ FOL, 10L/ FOL, output Submode X1 Note 3 D.B., D.B., Note 1 Note 1 Handshake pins H3 and H4, configured by Note 1: Data written to Port A goes to a temporary latch. When the Port B data programming the port B control register, register is later written, Port A data is transferred to IOL/FOL. are associated with the 16-bit double buf- Note 2 Data is latched in the output data registers (final output latch) and will be fered transfer. These 16-bit transfers are single buffered at the pin if the DDR is 1. The output buffers will be turned enabled by the H34 enable bit of the port off if the DDR is 0. general control register. Handshake pins Note 3: The output drivers that connect the final output latch to the pins are turned H1 and H2 can be used as simple status on. inputs not related to the 16-bit data Abbreviations: transfer or H2 can be an output. Enabling IOL — Initial Output Latch S.B. — Single Buffered of the H1 and H2 handshake pins is done FOL — Final Output Latch D.B. — Double Buffered by the H12 enable bit of the port general FIL — Final Input Latch DDR — Data Direction Register control register. The port A and B data

4.110 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 PARALLEL INTERFACEITIMER SCN68230

Preliminary

of ports A and B. Both options for inter- Double Buffered 110 (Port B)—The only data register, depending on the contents pretation of the H3S status bit, mentioned aspect of bidirectional double buffered of the port A data direction register. This in Port General Information and Com- transfers that differs from the unidirec- is summarized in table 8. ments section, are available and apply to tional modes lies in controlling the port B the 16-bit port as a whole. The DMAREQ output buffers. They are controlled by the Mode 3—Bidirectional 16-Bit Double Buf- pin can be used to signal a DMA controller level of H1. When H1 is negated, the port B fered I/O to transfer another word to the port output output buffers (all eight) are enabled and In mode 3, ports A and B are used for latches. (The S68000 DMA controllers can the pins drive the bidirectional bus. bidirectional 16-bit double buffered be programmed to perform the exact Generally, H1 is negated in response to an transfers. H1 and H2 control output transfers needed for compatibility with asserted H2 which indicates that new out- transfers, while H3 and H4 control input the PI/T.) H4 can be programmed for all put data is present in the double buffered transfers. (H1 and H2 are enabled by the five of the handshake options mentioned latches. Following acceptance of the data, H12 enable bit while H3 and H4 are in the Port General Information and Con- the peripheral asserts H1 disabling the enabled by the H34 enable bit of the port ventions section. port B output buffers. Other than con- general control register.) The instan- trolling the output buffer, H1 is edge sen- taneous direction of the data is deter- For pins used as inputs, data written to sitive as in other modes. Input transfers mined by the H1 handshake pin, and thus, either data register is double buffered and proceed identically to the double buffered the data direction registers are not used. 4 passed to the initial or final output latch, input protocol described in the Port Gen- The port A and port B submode fields do as usual, but the output buffer is disabled. eral Information and Conventions Section. not affect PUT operation in mode 3. Refer to Figure 5 for a sample timing In mode 2, only the interlocked and pulsed diagram. handshake pin options are available on H2 The only aspect of bidirectional double and H4. The DMAREQ pin can be associ- buffered transfers that differs from the MODE 1 PORT B SUBMODE X1 ated with either input transfers (H3) or out- unidirectional modes lies in controlling H1 put transfers (H1), but not both. Refer to the port A and B output buffers. They are H2 Table 7 for a summary of the port B data controlled by the level of H1. When H1 is register responses in mode 2. negated, the output buffers (all 16) are A AND B (16) enabled and the pins drive the bidirec- Bit I/O (Port A)—In mode 2, port A performs tional bus. Generally, H1 is negated in simple bit I/O with no associated hand- response to an asserted H2, which in- OUTPUT shake pins. This configuration is intended dicates that new output data is present in H3 for applications in which several indepen- the double buffered latches. Following ac- H4 dent devices must be controlled or ceptance of the data, the peripheral 1114D"BLE.BUFFERED monitored. Data written to the port A data asserts H1, disabling the output buffers. register is single buffered. If the port A Other than controlling the output buffers, Mode 2—Bidirectional 8-Bit Mode data direction register bit for that pin is 1 H1 is edge sensitive as in other modes. In- In mode 2, port A is used for simple bit I/O (output), the output buffer is enabled. If it put transfers proceed identically to the with no associated handshake pins. Port B is 0, data written is still latched but not double buffered input protocol described is used for bidirectional 8-bit double buf- available at the pin. Data read from the in the Port General information and Con- fered transfers. H1 and H2, enabled by the data register is either the instantaneous ventions section. Port A and B data is H12 enable bit in the port general control value of the pin or what was written to the latched with the asserted edge of H3. In register, control output transfers, while H3 and H4, enabled by the port general control register H34 enable bit, control in- Table 7 MODE 2 PORT B DATA PATHS put transfers. The instantaneous direction of the data is determined by the H1 hand- Read Port B Write Port B Mode shake pin. The port B data direction Data Register Data Register register is not used. The port A and port B 2 FIL, D.B. IOL/FOL, D.B. submode fields do not affect the PUT Abbreviations: operation in mode 2. IOL — Initial Output Latch MODE 2 FOL — Final Output Latch D.B. — Double Buffered FIL — Final Input Latch

BIT 110 Table 8 MODE 2 PORT A DATA PATHS

B (8) Read Port A Write Port A Mode Data Register Data Blister BIDIRECTIONAL 8.BIT DDR =0 DDR = 1 DDR= 0 DDR =1 2 Pin FOL FOL FOL, S.B. OUTPUT Abbreviations: H2H1)2 TRANSFERS S.B. — Single Buffered FOL — Final Output Latch H3H4 TRANSFERSINPUT DDR — Data Direction Register Signetics 4.111

MICROPROCESSOR DIVISION JANUARY 1983 PARALLEL INTERFACE/TIMER SCN68230

Preliminary mode 3, only the interlocked and pulsed Table 9 MODE 3 PORT A AND B DATA PATHS handshake pin options are available to H2 Read Port A and B Write Port A and B and H4. The DMAREQ pin can be associ- Mode ated with either input transfers (H3) or out- Data Register Data Register put transfers (H1), but not both. H2 indi- 3 FIL, D.B. 10L/FOL, D.B., Note 1 cates when new data is available in the Note 1: Data written to Port A goes to a temporary latch. When the Port B data port B (and implicitly port A) output register is later written, Port A data is transferred to 10L/FOL. latches, but unless the buffer is enabled Abbreviations: by H1, the data is not driving the pins. IOL — Initial Output Latch S.B. — Single Buffered FOL — Final Output Latch D.B. — Double Buffered Mode 3 can provide convenient high speed FIL — Final Input Latch 16-bit transfers. The port A and B data registers are addressed for compatibility with the SCN68000's move peripheral (MOVEP) instruction and with the S68000 DMA controllers. To take advantage of this, port A should contain the most significant data and always be read or written DATA IN OUTPUT LATCHES by the bus master first. The interlocked and pulsed handshake protocols are .*""•\ keyed to accesses to the port B data register in mode 3. If it is accessed last, the BUS WRITE NO DMA REQUEST 16-bit double buffered transfer proceeds smoothly. Refer to Table 9 for a summary DMA REQUEST PERIPHERAL ACCEPTS DATA of the port A and B data paths in mode 3.

MODE 3

A AND B BUS WRITE DMA REQUEST (161

BIDIRECTIONAL 16-BIT NO DMA REQUEST PERIPHERAL ACCEPTS DATA

H1\ OUTPUT H2/ TRANSFERS .nr H3 INPUT TRANSFERS

Figure 6. DMAREQ Associated with Output Transfers DMA REQUEST OPERATION The direct memory access request (DMAREQ) pulse (when enabled) is associated with output or input transfers to keep the initial and final output latches full or empty, respectively. Figures 6 and 7 DATA IN INPUT LATCHES show all the possible paths in generating DMA requests.

DMAREQ is generated on the bus side of PERIPHERAL PROVIDES DATA NO DMA REQUEST the SCN68230 by the synchronized' chip select. If the conditions of Figures 6 and 7 BUS READ are met, an access of the bus (assertion of DMA REQUEST CS) will cause DMAREQ to be asserted three PUT clocks (plus the delay time from the clock edge) after CS is synchronized. DMAREQ remains asserted for three clock PERIPHERAL PROVIDES DATA DMA REQUEST cycles (plus the delay time from the clock edge) and is then negated. NO DMA REQUEST BUS READ

'Synchronized means that the input signal has been seen by the PUT on the appropriate edge of the clock (rising edge for Ht(H3) and falling edge for CS). (Refer to the Bus Interface section for the exception concerning CS.) If a bus access (assertion of CS) and a port access (assertion of Ht(H3)) occur at the same time, CS will be Figure 7. DMAREQ Associated with Input Transfers recognized without delay. H1(H3) will be recognized one clock cycle later.

4.112 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PARALLEL INTERFACE/TIMER SCN68230

Preliminary

The DMAREQ pulse associated with a 3. The ZDS status bit is forced to 0, counter preload register (CPR) is peripheral or port side of the PUT is regardless of the possible zero con- transferred to the counter the first time caused by the synchronized H1(H3) input. tents of the 24-bit counter. that the prescaler passes from $00 to If the conditions of figures 6 and 7 are $1 F (rolls over) after entering the run met, a port access (assertion of the H1(H3) The run state is characterized by: state. Thereafter, the counter input) will cause DMAREQ to be asserted decrements or is loaded from the 2.5 PUT clock cycles (plus the delay time 1. The counter is clocked by the source counter preload register when the from clock edge) after H1(H3) is syn- programmed in the timer control prescaler rolls over. chronized. DMAREQ remains asserted for register. 8. For configurations in which the three clock cycles (plus the delay time 2. The counter is not reliably readable. prescaler is not used, the contents of from the clock edge) and is then negated. 3. The prescaler is allowed to decrement the counter preload registers are if programmed for use. transferred to the counter on the first TIMER 4. The ZDS status bit is set when the asserted edge of the TIN input after The SCN68230 timer can provide several 24-bit counter transitions from $000001 entering the run state. On subsequent facilities needed by S68000 operating to $000000. asserted edges the counter systems. It can generate periodic inter- decrements or is loaded from the rupts, a square wave, or a single interrupt Timer Rules counter preload registers. 4 after a programmed time period. Also, it This following set of rules allow easy ap- 9. The lowest value allowed in the counter can be used for elapsed time measure- plication of the timer. preload register for use with the ment or as a device watchdog. counter is $000001. 1. Refer to the run/halt definition above. The PI/T timer contains a 24-bit syn- 2. When the RESET pin is asserted, all Timer Interrupt Acknowledge Cycles chronous down counter that is loaded bits of the timer control register go to Several conditions can be present when from three 8-bit counter preload registers. 0, configuring the dual function pins as the timer interrupt acknowledge pin The 24-bit counter can be clocked by the port C inputs. (TIACK) is asserted. These conditions af- output of a 5-bit (divide by 32) prescaler or 3. The contents of the counter preload fect the PI/T's response and the termina- by an external timer input TIN. If the registers and counter are not affected tion of the bus cycle (see Table 10). prescaler is used, it can be clocked by the by the RESET pin. system clock (CLK pin) or by the TIN exter- 4. The count registers provide a direct nal input. The counter signals the occur- read data path from each portion of the PROGRAMMER'S MODEL rence of an event primarily through zero 24-bit counter, but data written to their The internal accessible register organiza- detection. (A zero is when the value of the addresses is ignored. (This results in a tion is represented in Table 11. Address 24-bit timer is equal to zero.) This sets the normal bus cycle.) These registers are space within the address map is reserved zero detect status (ZDS) bit in the timer readable at any time, but their contents for future expansion. Throughout the PUT status register. It can be checked by the are never latched. Unreliable data may data sheet, the following conventions are processor or can be used to generate a be read when the timer is in the run maintained. timer interrupt. The ZDS bit is reset by state. writing a 1 to the timer status register in 5. The counter preload registers are 1. A read from a reserved location in the that bit position. readable and writable at any time and map results in a read from the 'null this occurs independently of any timer register'. The null register returns all The general operation of the timer is flexi- operation. No protection mechanisms zeros for data and results in a normal ble and easily programmable. The timer is are provided against ill-timed writes. bus cycle. A write to one of these loca- fully configured and controlled by pro- 6. The input frequency to the 24-bit tions results in a normal bus cycle but gramming the 8-bit timer control register. counter from the TIN pin or prescaler no write occurs. It controls the choice between the port C output must be between 0 and the in- 2. Unused bits of a defined register are operation and the timer operation of three put frequency at the CLK pin divided by denoted by and are read as zeros. timer pins, whether the counter is loaded 32 regardless of the configuration 3. Bits that are unused in the chosen from the counter preload register or rolls chosen. mode/submode but are used in others, over when zero detect is reached, the 7. For configurations in which the are denoted by 'X', and are readable clock input, whether the prescaler is used, prescaler is used (with the CLK pin or and writable. Their content, however, is and whether the timer is enabled. TIN pin as an input), the contents of the ignored in the chosen mode/submode.

Run/Halt Definition The overall operation of the timer is Table 10 RESPONSE TO TIMER INTERRUPT ACKNOWLEDGE described in terms of the run or halt PC3/TOUT Function Response to Asserted TIACK states. The control of the current state is determined by programming the timer PC3 - Port C On No response. control register. When in the halt state, all No DTACK. of the following occur: TOUT - Square Wave No response. No DTACK. 1. The prior contents of the counter is not TOUT - Negated Timer No response. altered and is reliably readable via the Interrupt Request No DTACK. count registers. 2. The prescaler is forced to $1F whether TOUT - Asserted Timer Timer Interrupt Vector Contents. or not it is used. Interrupt Request DTACK Asserted. Signetics 4.113 MICROPROCESSOR DIVISION JANUARY 1983 PARALLEL INTERFACE/TIMER SCN68230

Preliminary

Table 11 PUT REGISTER ADDRESSING ASSIGNMENTS

Register Affected Affected Register Select Bits Accessible by by Read 5 4 3 2 1 Reset Cycle Port General Control Register IPGCR) 0 0 0 0 0 R W Yes No Port Service Request Register IPSRRI 0 0 0 0 1 R W Yes No Port A Data Direction Register d'ADDH) 0 0 0 1 0 R W Yes No Port B Data Direction Register IPBDDRI 0 0 0 1 1 R \N Yes No Port C Data Direction Register IPCDDRI 0 0 1 0 0 R W Yes No Port Interrupt Vector Register IPIVRI 0 0 1 0 1 R W Yes No Port A Control Register IPACR) 0 0 1 1 0 R \N Yes No Port B Control Register (PBCR) 0 0 1 1 1 R \A/ Yes No Port A Data Register IPADRI 0 1 0 0 0 R W No * * Port B Data Register (PBDRI 0 1 0 0 1 R \N No * * Port A Alternate Register (PAAR) 0 1 0 1 0 R No No Port B Alternate Register (PBAR) 0 1 0 1 1 R No No Port C Data Register (PCDRI 0 1 1 0 0 R 1A/ No No Port Status Register IPSR) 0 1 1 0 1 R W* Yes No Timer Control Register (TCR) 1 0 0 0 0 R W Yes No Timer Interrupt Vector Register (TIVRI 1 0 0 0 1 R W Yes No Counter Preload Register High (CPRHI 1 0 0 1 1 R W No No Counter Preload Register Middle ICPR MI 1 0 1 0 0 R W No No Counter Preload Register Low ICPRLI 1 0 1 0 1 R W No No Count Register High ICNTRHI 1 0 1 1 1 R No No Count Register Middle ICNTRM) 1 1 0 0 0 R No No Count Register Low (CNTR LI 1 1 0 0 1 R No No Timer Status Register ITSRI 1 1 0 1 0 R W* Yes No

*A write to this register may perform a special status resetting operation. R= Read * *Mode dependent. W = Write

4. All registers are addressable as 8-bit All bits are reset to 0 when the RESET pin 5 H34 Enable quantities. To facilitate operation with is asserted. O Disabled the MOVEP instruction and the DMAC, 1 Enabled addresses are ordered such that cer- The port mode control field should be 4 H12 Enable tain sets of registers can also be ac- altered only when the H12 enable and H34 O Disabled cessed as words (2 bytes) or long enable bits are 0. Except when mode 0 is 1 Enabled words (4 bytes). desired, the port general control register must be written once to establish the 3-0 Handshake Pin Sense mode, and again to enable the respective O The associated pin is at the high operation(s). voltage level when negated and at PORT GENERAL CONTROL REGISTER the low voltage level when asserted. (PGCR) 1 The associated pin is at the low Port General Control Register (PGCR) The port general register controls many of voltage level when negated and at the functions that are common to the the high voltage level when asserted. 7 6 5 4 3 2 0 overall operation of the ports. The PGCR is composed of three major fields: bits 7 Port Mode I-134 H12 H4 H3 H2 Ht PORT SERVICE REQUEST REGISTER and 6 define the operational mode of ports Control EnableEnable Sense Sense Sense Sense (PSRR) A and B and affect operation of the hand- The port service request register controls shake pins and status bits; bits 5 and 4 other functions that are common to the allow a software controlled disabling of 7 6 Port Mode Control overall operation to the ports. It is com- particular hardware associated with the 0 0 Mode 0 (unidirectional 8-Bit mode) posed of four major fields: bit 7 is unused handshake pins of each port; and bits 3-0 0 1 Mode 1 (unidirectional 16-bit mode) and is always read as 0; bits 6 and 5 define define the sense of the handshake pins. 1 0 Mode 2 (bidirectional 8-bit mode) whether interrupt or DMA requests are The PGCR is always readable and writable. 1 1 Mode 3 (bidirectional 16-bit mode) generated from activity on the Hi and H3

4.114 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 PARALLEL INTERFACEITIMER SCN68230

Preliminary

handshake pins; bits 4 and 3 determine Port Interrupt Priority Control Port Interrupt Vector Register (PIVR) whether two dual function pins operate as 2 1 0 Highest Lowest port C or port interrupt request/ 0 0 0 HIS H2S H3S H4S acknowledge pins; and bits 2, 1, and 0 con- 6 5 4 3 2 0 0 1 H2S HIS H3S H4S trol the priority among all port interrupt 0 1 0 H1S H2S H4S H3S Interrupt Vector NUM ber sources. Since bits 2, 1, and 0 affect inter- 0 1 1 H2S H1S H4S H3S rupt operation, it is recommended that 0 H3S H4S H1S H2S 0 From a normal read cycle (CS), there is they be changed only when the affected 1 H1S 0 H3S H4S H2S never a consequence to reading this interrupt(s) is disabled or known to remain 0 H4S H3S H1S H2S 1 register. Following negation of the RESET inactive. The PSRR is always readable and 1 1 H4S H3S H2S H1S writable. pin, but prior to writing to the PIVR, a $OF will be read. After writing to the register, All bits are reset to 0 when the RESET pin PORT A DATA DIRECTION REGISTER the upper 6 bits may be read and the lower is asserted. (PADDR) 2 bits are forced to 0. No prioritization The port A data direction register deter- computation is performed. Port Service Request Register (PSRR) mines the direction and buffering PORT A CONTROL REGISTER (PACR) 6 5 4 3 2 1 0 characteristics of each of the port A pins. One bit in the PADDR is assigned to each The port A control register, in conjunction SVCRO Interrupt Port Interrupt pin. A 0 indicates that the pin is used as an with the programmed mode and the port B Select RFS Priority Control input, while a 1 indicates it is used as submode, control the operation of port A an output. The PADDR is always readable and the handshake pins H1 and H2. The 6 5 SVCRQ Select and writable. This register is ignored in port A control register contains five fields: 0 X The PC4/DMAREQ pin carries the mode 3. bits 7 and 6 specify the port A submode; PC4 function; DMA is not used. bits 5, 4, and 3 control the operation of the 1 0 The PC4/DMAREQ pin carries the All bits are reset to the 0 (input) state when H2 handshake pin and H2S status bit; bit 2 DMAREQ function and is associated the RESET pin is asserted. determines whether an interrupt will be with double buffered transfers con- generated when the H2S status bit goes to trolled by H1. H1 is removed from PORT B DATA DIRECTION REGISTER 1; bit 1 determines whether a service re- the PI/T's interrupt structure, and (PBDDR) quest (interrupt request or DMA request) thus, does not cause interrupt re- The PBDDR is identical to the PADDR for will occur; bit 0 controls the operation of quests to be generated. To obtain the port B pins and the port B data the H1S status bit. The PACR is always DMAREQ pulses, port A control register, except that this register is ig- readable and writable. register bit 1 (H1 SVCRQ enable) nored in modes 2 and 3. must be a 1. All bits are cleared to 0 when the RESET 1 1 The PC4/DMAREQ pin carries the PORT C DATA DIRECTION REGISTER pin is asserted. When the port A submode DMAREQ function and is associated (PCDDR) field is relevant in a mode/submode defini- with double buffered transfers con- The port C data direction register tion, it must not be altered unless the H12 trolled by H3. H3 is removed from specifies whether each dual function pin enable bit in the port general control the PI/T's interrupt structure, and that is chosen for the port C operation is register is 0 (see Table 3). thus, does not cause interrupt re- an input (0) or an output (1) pin. The quests to be generated. To obtain PCDDR, along with bits that determine the The operation of H1 and H2 and their DMAREQ pulses, Port B Control respective pin's function, also specify the related status bits is given below for each Register bit 1 (H3 SVCRQ Enable) exact hardware to be accessed at the port of the modes specified by the port general must be 1. C data register address. (See the Port C control register bits 7 and 6. 4 3 Interrupt Pin Function Select Data Register description for more 0 0 The PC5/PIRQ pin carries the PC5 details.) The PCDDR is an 8-bit register Bits 2 and 1 carry the same meaning in function. that is readable and writable at all times. each mode/submode, and thus are The PC6/PIACK pin carries the PC6 Its operation is independent of the chosen specified only once. function. PUT mode. Port A Control Register (PACR) 0 1 The PC5/PIRQ pin carries the PIRQ These bits are cleared to 0 when the function. RESET pin is asserted. 7 6 5 4 1 3 2 1 0 The PC6/PIACK pin carries the PC6 H2 Fll H1 function. Port A PORT INTERRUPT VECTOR REGISTER H2 Control lot.SVCRO Stat 1 0 The PC5IPIRQ pin carries the PC5 Subrnode (PIVR) Enrible Enable Ctrl function. The port interrupt vector register contains The PC6/PIACK pin carries the the upper order six bits of the four port in- 2 H2 Interrupt Enable PIACK function. terrupt vectors. The contents of this 0 The H2 interrupt is disabled. 1 1 The PC5/PIRQ pin carries the PIRO register can be read two ways: by an or- 1 The H2 interrupt is enabled. function. dinary read cycle, or by a port interrupt The PC6/PIACK pin carries the acknowledge bus cycle. The exact data 1 H1 SVCRQ Enable PIACK function. read depends on how the cycle was in- 0 The H1 interrupt and DMA request are Bits 2, 1, and 0 determine port interrupt itiated and other factors. Behavior during disabled. priority. The priority is shown in descend- a port interrupt acknowledge cycle is sum- 1 The H1 interrupt and DMA request are ing order left to right. marized in Table 4. enabled. Signetics 4.115

MICROPROCESSOR DIVISION JANUARY 1983 PARALLEL INTERFACEITIMER SCN68230

Preliminary

Mode 0, Port A Submode 00 0 H1 Status Control The operation of H3 and H4 and their X Not used. related status bits is given below for each 5 4 3 H2 Control of the modes specified by the port general 0 X X Input pin—status only. Mode 2 control register bits 7 and 6. 1 0 0 Output pin—always negated. 1 0 1 Output pin—always asserted. 5 4 3 H2 Control Bits 2 and 1 carry the same meaning in 1 1 0 Output pin—interlocked input X X 0 Output pin—interlocked output each mode/submode, and thus are handshake protocol. handshake protocol. specified only once. 1 1 1 Output pin—pulsed input hand- X X 1 Output pin—pulsed output hand- Port B Control Register (PBCR) shake protocol. shake protocol.

4 3 2 0 O H1 Status Control O H1 Status Control 6 5 X Not used O The HIS status bit is 1 when either the H4 H3 H3 Port B port B initial or final output latch can H4 Control Int. SVCRQ Slat Submode Enable Enable Ctrl Mode 0, Port A Submode 01 accept new data. It is 0 when both latches are full and cannot accept new 2 H4 Interrupt Enable data. 5 4 3 H2 Control 0 The H4 interrupt is disabled. 1 The H1S status bit is 1 when both of 0 X X Input pin—status only. 1 The H4 interrupt is enabled. 1 0 0 Output pin—always negated. the port B output latches are empty. It 1 0 1 Output pin—always asserted. is 0 when at least one latch is full. 1 1 0 Output pin—interlocked output 1 H3 SVCRO Enable handshake protocol. Mode 3 0 The H3 interrupt and DMA request are 1 1 1 Output pin—pulsed output disabled. handshake protocol. 5 4 3 H2 Control The H3 interrupt and DMA request are X X 0 Output pin—interlocked output enabled. O H1 Status Control handshake protocol. 0 The H1S status bit is 1 when either the X X 1 Output pin—pulsed output hand- port A initial or final output latch can shake protocol. Mode 0, Port B Submode 00 accept new data. It is 0 when both lat- 0 H1 Status Control ches are full and cannot accept new 5 4 3 H4 Control 0 The H1S status bit is 1 when either the data. 0 X X Input pin — status only. initial or final output latch of port A 1 The HIS status bit is 1 when both of 1 0 0 Output pin — always negated. and B can accept new data. It is 0 when the port A output latches are empty. It 1 0 1 Output pin — always asserted. both latches are full and cannot accept is 0 when at least one latch is full. 1 1 0 Output pin — interlocked input new data. handshake protocol. 1 The H1S status bit is 1 when both the 1 1 1 Output pin — pulsed input hand- Mode 0, Port A Submode lx initial and final output latches of ports shake protocol. A and B are empty. It is 0 when either 5 4 3 H2 Control the initial or final latch of ports A and B O X X Input pin—status only. is full. 1 X 0 Output pin—always negated. O H3 Status Control 1 X 1 Output pin—always asserted. O Not used. PORT B CONTROL REGISTER (PBCR) The port B control register specifies the O H1 Status Control X Not used. operation of port B and the handshake Mode 0, Port B Submode 01 pins H3 and H4. The port B control register contains five fields: bits 7 and 6 specify Mode 1, Port A Submode XX, 5 4 3 H4 Control the port B submode; bits 5, 4, and 3 con- 0 X X Input pin—status only. Port B Submode XO trol the operation of the H4 handshake pin 1 0 0 Output pin—always negated. and H4S status bit; bit 2 determines 1 0 1 Output pin—always asserted. 5 4 3 H2 Control whether an interrupt will be generated 1 1 0 Output pin—interlocked output 0 X X Input pin—status only. when the H4S status bit goes to 1; bit 1 handshake protocol. 1 X 0 Output pin—always asserted. determines whether a service request (in- 1 1 1 Output pin—pulsed output hand- 1 X 1 Output pin—always asserted. terrupt request or DMA request) will oc- shake protocol. cur; bit 0 controls the operation of the H3S O H1 Status Control status bit. The PACR is always readable X Not used. and writable. There is never a conse- 0 H3 Status Control quence to reading the register. 0 The H3S status bit is 1 when either the Mode 1 Port A Submode XX port B initial or final output latch can Port B Submode X1 All bits are cleared to 0 when the RESET accept new data. It is 0 when both pin is asserted. When the port B submode latches are full and cannot accept new 5 4 3 H2 Control field is relevant in a mode/submode defini- data. 0 X X Input pin—status only. tion, it must not be altered unless the H34 1 The H3S status bit is 1 when both of 1 X 0 Output pin—always negated. enable bit in the port general control the port B output latches are empty. It 1 X 1 Output pin—always asserted. register is 0 (see Table 3). is 0 when at least one latch is full.

4.116 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PARALLEL INTERFACE/TIMER SCN68230

Preliminary

Mode 0, Port B Submode lx 0 H3 Status Control PORT C DATA REGISTER (PCDR) X Not used. The port C data register is an address for 5 4 3 H4 Control moving data to and from each of the eight 0 X X Input pin—status only. port Clalternate function pins. The exact 1 X 0 Output pin—always negated. PORT A DATA REGISTER (PADR) hardware accessed is determined by the 1 X 1 Output pin—always asserted. The port A data register is an address for type of bus cycle (read or write) and in- moving data to and from the port A pins. dividual conditions affecting each pin. O H3 Status Control The port A data direction register deter- These conditions are: whether the pin is X Not used. mines whether each pin is an input (0) or used for the port C or alternate function, and whether the port C data direction Mode 1, Port B Submode XO an output (1), and is used in configuring the actual data paths. PADR is mode register indicates the input or output direction. The port C data register is single 5 4 3 H4 Control dependent. buffered for output pins and not buffered 0 X X Input pin—status only. for input pins. These conditions are sum- 1 0 0 Output pin—always negated. This register is readable and writable at all marized in table 12. 1 0 1 Output pin—always asserted. times. Depending on the chosen model 1 1 0 Output pin—interlocked input submode, reading or writing may affect handshake protocol. the double buffered handshake The Port C data register is not affected by 1 1 1 Output pin—pulsed input hand- mechanism. The port A data register is not the assertion of the RESET pin. shake protocol. affected by the assertion of the RESET pin. 0 H3 Status Control The operation of the PCDR is independent X Not used. of the chosen PUT mode.

Mode 1, Port B Submode X1 PORT B DATA REGISTER (PBDR) Note that two additional useful benefits The port B data register is an address for result from this structure. First, it is possi- 5 4 3 H4 Control moving data to and from the port B pins. ble to directly read the state of a dual func- O X X Input pin—status only. The port B data direction register deter- tion pin while used for the non port C func- 1 0 0 Output pin—always negated. mines whether each pin is an input (0) or tion. Second, it is possible to generate 1 0 1 Output pin—always asserted. an output (1), and is used in configuring program controlled transitions on alter- 1 1 0 Output pin—interlocked output the actual data paths. PBDR is mode nate function pins by switching back to handshake protocol. dependent. the port C function, and writing to the 1 1 1 Output pin—pulsed output hand- PC DR. shake protocol. This register is readable and writable at all times. Depending on the chosen model This register is readable and writable at all O H3 Status Control submode, reading or writing may affect times. 0 The H3S status bit is 1 when either the initial or final output latch of port A the double buffered handshake mechanism. The port B data register is not af- and B can accept new data. It is 0 when PORT STATUS REGISTER (PSR) both latches are full and cannot accept fected by the assertion of the RESET pin. The port status register contains informa- new data. tion about handshake pin activity. Bits 7-4 1 The H3S status bit is 1 when both the show the instantaneous level of the initial and final output latches of ports PORT A ALTERNATE REGISTER (PAAR) respective handshake pin, and is indepen- A and B are empty. It is 0 when neither The port A alternate register is an alter- dent of the handshake pin sense bits in the initial or final latch of ports A and B nate address for reading the port A pins. It the port general control register. Bit 3-0 is full. is a read only address and no other PUT condition is affected. In all modes, the Mode 2 instantaneous pin level is read and no in- Table 12 PCDR HARDWARE put latching is performed except at the 5 4 3 H4 Control data bus interface (see Bus Interface Con- ACCESSES X X 0 Output pin—interlocked input nection). Writes to this address are Read Port C Data Register handshake protocol. answered with DTACK, but the data is ig- X X 1 Output pin—pulsed input hand- Port C Port C Alternate Alternate nored. function function function function shake protocol. PCDDR= 0 PCDDR =1 PCDDR= 0 PCDDR =1 Port C Port C O H3 Status Control PORT B ALTERNATE REGISTER (PBAR) pin output pin output X Not used. The port B alternate register is an alter- register register nate address for reading the port B pins. It Write Port C Data Register Mode 3 is a read only address and no other PUT Port C Port C Alternate Alternate function function condition is affected. In all modes, the in- function function 5 4 3 H4 Control PCDDR -= 0 PCDDR =1 PCDDR= 0 PCDDR =1 stantaneous pin level is read and no input X X 0 Output pin—interlocked input Port C Port C Port C Port C latching is performed except at the data handshake protocol. output output output output bus interface (see Bus Interface Connec- register, register, register register X X 1 Output pin—pulsed input hand- tion). Writes to this address are answered buffer buffer shake protocol. with DTACK, but the data is ignored. disabled enabled

Signetics 4.117 MICROPROCESSOR DIVISION JANUARY 1983 PARALLEL INTERFACE/TIMER SCN68230

Preliminary are the respective status bits referred to request is negated, the PUT pro- are used. The prescaler is throughout this data sheet. Their inter- duces no response, i.e., no data or decremented on the falling transi- pretation depends on the programmed DTACK to an asserted TIACK. tion of the CLK pin; the 24-bit mode/submode of the PUT. For bits 3-0, a 1 Refer to the Timer Interrupt Cycle counter is decremented or loaded is the active or asserted state. section for details. This combina- from the counter preload registers tion and the 101 state below sup- when the prescaler rolls over from port vectored timer interrupts. $00 to $1 F. The timer is in the run Port Status Register (PSR) 1 0 1 The dual function pin PC3/TOUT state when the timer enable bit is 1 carries the TOUT function and is and the TIN pin is high; otherwise 7 6 5 4 3 2 1 0 used as a timer interrupt request the timer is in the halt state. H4 H3 H2 H1 output. The timer interrupt is 1 0 The PC2/TIN pin serves as a timer in- H4S H3S H2S HIS Level Level Level Level enabled; thus, the pin is low when put and the prescaler is used. The the timer ZDS status bit is 1. The prescaler is decremented following dual function pin PC7/TIACK car- the rising transition of the TIN pin ries the TIACK function and is after syncing with the internal clock. TIMER CONTROL REGISTER (TCR) used as a timer interrupt The 24-bit counter is decremented or The timer control register determines all acknowledge input. Refer to the loaded from the counter preload operations of the timer. Bits 7-5 configure Timer Interrupt Acknowledge Cy- registers when the prescaler rolls the PC3/TOUT and PC7/TIACK pins for cle section for details. This com- over from $00 to $1F. The timer port C, square wave, vectored interrupt, or bination and the 100 state above enable bit determines whether the autovectored interrupt operation; bit 4 support vectored timer interrupts. timer is in the run or halt state. specifies whether the counter receives 1 1 0 The dual function pin PC3/TOUT 1 1 The PC2/TIN pin serves as a timer data from the counter preload register or carries the TOUT function. In the input and the prescaler is unused. continues counting when zero detect is run or halt state it is used as a The 24-bit counter is decremented or reached; bit 3 is unused and is read as 0; timer interrupt request output. loaded from the counter preload bits 2 and 1 configure the path from the The timer interrupt is disabled; registers following the rising edge CLK and TIN pins to the counter con- thus, the pin is always three- of the TIN pin after syncing with the troller; bit 0 enables the timer. This stated. The dual function pin internal clock. The timer enable bit register is readable and writable at all PC7/TIACK carries the PC7 func- determines whether the timer is in times. tion. the run or halt state. 1 1 1 The dual function pin PC3/TOUT All bits are cleared to 0 when the RESET carries the TOUT function and is 0 Timer Enable pin is asserted. used as a timer interrupt request 0 Disabled. output. The timer interrupt is 1 Enabled. enabled; thus, the pin is low when Timer Control Register (TCR) the timer ZDS status bit is 1. The TIMER INTERRUPT VECTOR REGISTER dual function pin PC7/TIACK car- (TIVR) 7 6 5 4 3 2 1 0 ries the PC7 function and autovec- The timer interrupt vector register con- tored interrupts are supported. tains the 8-bit vector supplied when the TOUT/TIACK Z D v Clock Inter Control Ctrl. Control Enable timer interrupt acknowledge pin TIACK is 4 Zero Detect Control asserted. The register is readable and 0 The counter is loaded from the counter writable at all times, and the same value is preload register on the first clock to always obtained from a normal read cycle 7 6 5 TOUT/TIACK Control the 24-bit counter after zero detect, and a timer interrupt acknowledge bus cy- 0 0 X The dual function pins PC3/TOUT and resumes counting. cle (TIACK). When the RESET pin is and PC7/TIACK carry the port C 1 The counter rolls over on zero detect, asserted, the value of $OF is automatically function. then continues counting. loaded into the register. Refer to the Timer 0 1 X The dual function pin PC3/TOUT Interrupt Acknowledge Cycle section for carries the TOUT function. In the Bit 3 is unused and is always read as 0. more details. run state it is used as a square wave output and is toggled on 2 1 Clock Control COUNTER PRELOAD REGISTER zero detect. The TOUT pin is high 0 0 The PC2/TIN input pin carries the H, M, L (CPRH-L) while in the halt state. The dual port C function and the CLK pin and The counter preload registers are a group function pin PC7/TIACK carries prescaler are used. The prescaler is of three 8-bit registers used for storing the PC7 function. decremented on the falling transi- data to be transferred to the counter. Each 1 0 0 The dual function pin PC3/TOUT tion of the CLK pin; the 24-bit of the registers is individually ad- carries the TOUT function. In the counter is decremented or loaded dressable, or the group may be accessed run or halt state it is used as a from the counter preload registers with the MOVEP.L or the MOVEP.W in- timer interrupt request output. when the prescaler rolls over from structions. The address one less than the The timer interrupt is disabled; $00 to $1 F. The timer enable bit address of CPRH is the null register, and thus, the pin is always three- determines whether the timer is in is reserved so that zeros are read in the up- stated. The dual function pin the run or halt state. per 8 bits of the destination data register PC7/TIACK carries the TIACK 0 1 The PC2/TIN pin serves as a timer in- when a MOVEP.L is used. Data written to function; however, since interrupt put and the CLK pin and prescaler this address is ignored.

4.118 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 PARALLEL INTERFACE/TIMER SCN68230

Preliminary

The registers are readable and writable at edge sensitive flip flop that is set to 1 then enables the timer. When the 24-bit all times. A read cycle proceeds in- when the 24-bit counter decrements from counter passes from $000001 to $000000, dependently of any transfer to the $000001 to $000000. The ZDS status bit is the ZDS status bit is set and the TOUT (in- counter, which may be occurring cleared to 0 following the direct clear terrupt request) pin is asserted. At the simultaneously. operation (similar to that of the ports), or next clock to the 24-bit counter, it is again when the timer is halted. Note also that loaded with the contents of the CPRs and To insure proper operation of the PUT when the RESET pin is asserted, the timer thereafter decrements. In normal opera- timer, a value of $000000 cannot be stored is disabled and thus enters the halt state. tion, the processor must direct clear the in the counter preload registers for use status bit to negate the interrupt request with the counter. This register is always readable without (see Figure 8). consequence. A write access performs a The RESET pin does not affect the con- direct clear operation if bit 0 in the written Periodic Interrupt Generator tents of these registers. data is 1. Following that, the ZDS bit is O. / 1 6 4 3 2 TOUT TIACK This register is constructed with a reset Z D Clock Timer Counter Preload Register H, M, L (CPRH•L) Control Ctri Control Enable dominant S-R flip flop so that all clearing OD or 1X charged 7 6 , 5 1 4 3 2 1 0 conditions prevail over the possible zero 67 Bit Bit Bit Bit Bit Bit 130 CPRH detect condition. 23 22 21 20 19 18 17 16 Square Wave Generator In this configuration the timer produces a Bit Bit Bit Bit Bit Bit Bit Bit Bits 7-1 are unused and are read as 0. CPRM 15 14 13 12 11 10 9 8 square wave at the TOUT pin. The TOUT Timer Status Register (TSR) pin is connected to the user's circuitry Bit Bo Bit Bir Bit Bit Bit EI0 CPRL and the TIACK pin is not used. The TIN pin 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 may be used as a clock input.

* * * ZDS The processor loads the counter preload COUNT REGISTER H, M, L (CNTRH-L) registers and timer control register, and The count registers are a group of three then enables the timer. When the 24-bit 8-bit addresses at which the counter can TIMER APPLICATIONS SUMMARY counter passes from $000001 to $000000, be read. The contents of the counter are the ZDS status bit is set and the TOUT not latched during a read bus cycle; thus, Periodic Interrupt Generator (square wave output) pin is toggled. At the the data read at these addresses is not In this configuration the timer generates a next clock to the 24-bit counter, it is again guaranteed if the timer is in the run state. periodic interrupt. The TOUT pin is con- loaded with the contents of the CPRs and (Bits 2, 1 and 0 of the timer control register nected to the system's interrupt request thereafter decrements. In this application specify the state.) Write operations to circuitry and the TIACK pin can be used as there is no need for the processor to direct these addresses result in a normal bus cy- an interrupt acknowledge input to the clear the ZDS status bit; however, it is cle but the data is ignored. timer. The TIN pin can be used as a clock possible for the processor to sync itself input. with the square wave by clearing the ZDS Each of the registers is individually ad- status bit, then polling it. The processor dressable, or the group can be accessed The processor loads the counter preload can also read the TOUT level at the port C with the MOVEP.L or the MOVEP.W in- registers and timer control register, and address. structions. The address one less than the address of CNTRH is the null register, and is reserved so that zeros are read in the up- RUN per 8 bits of the destination data register TIMER when a MOVEP.L is used. Data written to ENABLE this address is ignored. $FFFFFF Count Register H, M, L (CNTRH•L) 24-BIT COUNTER• 7 6 5 4 3 2 1 0

Bit Bit Bit Bit Bit Bit Bit Bit $000000 — CNTRH 23 22 21 20 19 18 17 16

Bit Bit 134 Bit Bit Bit Bit Bit ZDS CNTRM 15 14 13 12 11 10 9 8

Bit Bit Bo Bit Bit Bit Bit Bit CNTRL TOUT 7 6 5 4 3 2 1 0

TIACK TIMER STATUS REGISTER (TSR) • ANALOG REPRESENTATION OF COUNTER VALUE The timer status register contains one bit from which the zero detect status can be Figure 8. Periodic Interrupt Generator determined. The ZDS status bit (bit 0) is an Signetics 4.119 MICROPROCESSOR DIVISION JANUARY 1983 PARALLEL INTERFACE/TIMER SCN68230

Preliminary

Note that the PC3/TOUT pin functions as PC3 following the negation of RESET. If used in the square wave configuration, a pullup resistor may be required to keep a known level prior to programming. Prior to enabling the timer, TOUT is high (see

Figure 9). RUN Square Wave Generator TIMER ENABLE

7 I 6 I 5 3 2 I 1 0 TOUT TIACK Z D Clock Timer SFFFFFF — Control Cie Control Enable 0 0 0 00 or 10 -hanged 24-BIT — COUNTER

Interrupt After Timeout In this configuration the timer generates $000000 an interrupt after a programmed time period has expired. The TOUT pin is con- TOUT nected to the system's interrupt request / circuitry and the TIACK pin can be an in- F[ SQUARE WAVE terrupt acknowledge input to the timer. •ANALOG REPRESENTATION OF COUNTER VALUE. The TIN pin may be used as a clock input.

This configuration is similar to the periodic interrupt generator except that the zero detect control bit is set. This forces the counter to roll over after zero detect is reached, rather than reloading Figure 9. Square Wave Generator from the CPRs. When the processor takes the interrupt, it can halt the timer and read the counter. This allows the processor to measure the delay time from zero detect (interrupt request) to entering the service routine. Accurate knowledge of the interrupt latency may be useful in some applications (see Figure 10).

Interrupt After Timeout I-, RUN TIMER 7 1 6 1 5 4 3 2 1 ENABLE TOUT/TIACK Z D Clock Timer Control Ctrl Congo, En SFFFFFF 0 0 00 or 10 changed

24-BIT Elapsed Time Measurement COUNTER• Elapsed time measurement takes several forms; two are described below. The first $000000 = configuration allows time interval measurement by software. No timer pins ZDS are used.

TOUT The processor loads the counter preload registers (generally with all 1s) and timer control register, and then enables the AcKTI timer. The counter decrements until the ending event takes place. When it is •ANALOG REPRESENTATION OF COUNTER VALUE. desired to read the time interval, the processor must halt the timer, then read the counter. For applications in which the interval could have exceeded that program. mable in this timer, interrupts can be counted to provide the equivalent of additional timer bits. At the end, the timer can Figure 10. Single Interrupt After Timeout be halted and read (see Figure 11).

4.120 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 PARALLEL INTERFACE/TIMER SCN68230

Preliminary

System Clock

7 1 6 1 5 4 2 TOUT/TIACK Z D Clock Timer Enable Control Col ConOol 0 0 0 0 changed

The second configuration allows measure- E4 RUN 1,1 ment (counting) of the number of input TIMER pulses occurring in an interval in which ENABLE the counter is enabled. The TIN input pin provides the input pulses. Generally the $FFFFFF TOUT and TIACK pins are not used. ELAPSED 24.BIT TIME This configuration is identical to the COUNTER* elapsed time measurement/system clock configuration except that the TIN pin is $000000-=-• - used to provide the input frequency. It can 'ANALOG REPRESENTATION OF COUNTER VALUE. be connected to a simple oscillator, and the same methods could be used. Alter- nately, it could be gated off and on externally and the number of cycles occurring while in the run state can be counted. However, minimum pulse width high and low specifications must be met.

External Clock

Figure 11. Elapsed Time Measurement 7 1 6 1 5 4 3 2 1 TOUT/ TIACK Z D Clock Timer Control Ctrl Control Enable o 0 X 0 X changed

Device Watchdog This configuration provides the watchdog function needed in many systems. The TIN pin is the timer input whose period at the high (1) level is to be checked. Once allowed by the processor, the TIN input TIMER pin controls the run/halt mode. The TOUT ENABLE pin is connected to external circuitry requiring notification when the TIN pin has IE RUN-*- 1.1(-RUN-,11.1 been asserted longer than the programmed time. The TIACK pin (interrupt TIN acknowledge) is only needed if the TOUT pin is connected to interrupt circuitry. $FFFFFF 24-BIT The processor loads the counter preload COUNTER register and timer control register, and then enables the timer. When the TIN input is asserted (1, high) the timer transfers $000000 the contents of the counter preload ZDS register to the counter and begins counting. If the TIN input is negated before zero detect is reached, the TOUT output and TOUT the ZDS status bit remain negated. If zero *ANALOG REPRESENTATION OF COUNTER VALUE. detect is reached while the TIN input is still asserted, the ZDS status bit is set and the TOUT output is asserted. (The counter rolls over and keeps on counting).

In either case, when the TIN input is negated, the ZDS status bit is 0, the TOUT Figure 12. Device Watchdog output is negated, the counting stops, and prescaler is forced to all Is (see Figure 12).

Signetics 4.121 MICROPROCESSOR DIVISION JANUARY 1983 PARALLEL INTERFACEITIMER SCN68230

Preliminary

Device Watchdog tions. In this situation the PUT does not master, generally there is no way to recognize the reassertion of CS until guarantee that the CS setup time with 7 1 6 ] 5 4 3 2 1 1 0 respect to the PUT CLK is met. Thus, the TOUT/TIACK 2 ID Clock Timer these operations are complete. Only at Control Ctrl Control Enable that time does it begin the internal se- only way to determine that the PUT 1 X 1 1 0 0 1 changed quencing necessary to react to the recognized the assertion of CS is to wait asserted CS. Since CS also controls the for the assertion of DTACK. In this situa- BUS INTERFACE CONNECTION DTACK response, this 'bus cycle recovery tion, all latched bus inputs to the PUT The PUT has an asynchronous bus inter- time' can be related to the CLK edge on must be held stable until DTACK is face, primarily designed for use with the which DTACK is asserted for that cycle. asserted. These include register select, SCN68000 microprocessor. With care, The PUT will recognize the subsequent R/W, and write data inputs (see below). however, it can be connected to syn- assertion of CS three CLK periods after chronous microprocessor buses. This sec- the CLK edge on which DTACK was System specifications impose a maximum tion completely describes the PI/T's bus previously asserted. delay from the trailing (negated) edge of interface, and is intended for the asyn- chip select to the negated edge of DTACK. chronous bus designer unless otherwise The register select and R/W inputs pass As system speeds increase, this becomes specified. through an internal latch that is more difficult to meet with a simple pullup transparent when the PUT can recognize a resistor tied to the DTACK line. Therefore, In an asynchronous system, the PUT CLK new CS pulse (see above paragraph). the PUT provides an internal active pullup can operate at a significantly different fre- Since the internal data bus of the PUT is device to reduce the rise time, and a level quency, either higher or lower than the continuously enabled for read transfers, sensitive circuit that later turns this bus master and other system com- the read access time (to the data bus buf- device off. DTACK is negated asyn- ponents, as long as all bus specifications fers) begins when the register selects are chronously as fast as possible following are met. The SCN68230 CLK pin has the stabilized internally. Also, when the PUT is the rising edge of chip select, then three- same specifications as the SCN68000 ready to begin a new bus cycle, the asser- stated to avoid interference with the next CLK, and must not be gated off at any time. tion of CS enables the data bus buffers bus cycle. within a short propagation delay. This The following signals generate normal does not contribute to the overall read ac- The system designer must take care that read and write cycles to the PUT: CS (chip cess time, unless CS is asserted DTACK is negated and three-stated quick- select), R/W (read/write), RS1-RS5 (five significantly after the register select and ly enough after each bus cycle to avoid in- register select bits), DO-D7 (the 8-bit R/W inputs are stabilized (as may occur terference with the next one. With the bidirectional data bus), and DTACK (data with synchronous bus microprocessors). SCN68000 this necessitates a relatively transfer acknowledge). To generate inter- fast external path from the data strobe to rupt acknowledge cycles, PC6/PIACK or In addition to chip select's previously CS going negated. PC7ITIACK is used instead of CS and the mentioned duties, it controls the asser- register select pins are ignored. No com- tion of DTACK and latching of read data at Write Cycles bination of the following pins can be the data bus interface. Except for controll- In many ways write cycles are similar to asserted simultaneously: CS, PIACK, or ing input latches and enabling the data normal read cycles (see above). On write TIACK. bus buffers, all of these functions occur cycles, data at the DO-D7 pins must meet only after CS has been recognized inter- the same setup specifications as the Read Cycles via Chip Select nally and synchronized with the internal register select and R/W lines. Like these This category includes all register reads, clock. Chip select is recognized on the signals, write data is latched on the except port or timer interrupt falling edge of the CLK if the setup time is asserted edge of CS, and must meet small acknowledge cycles. When CS is met, and DTACK is asserted (low) on the setup and hold time requirements with asserted, the register select and R/W in- next falling edge of the CLK. Read data is respect to that edge. The same bus cycle puts are latched internally. They must latched at the PI/T's data bus interface at recovery conditions exist as for normal meet small setup and hold time re- the same time DTACK is asserted. It is read cycles. No other differences exist. quirements with respect to the asserted stable as long as chip select remains edge of CS (see the AC Electrical asserted independent of other external Read Cycles via Interrupt Acknowledge Characteristics table). The PUT is not pro- conditions. Special internal operations take place on tected against aborted (shortened) bus PUT interrupt acknowledge cycles. The cycles generated by an address error or From the above discussion, it is clear that port interrupt vector register or the timer bus error exception in which it is ad- if the CS setup time prior to the falling interrupt vector register are implicitly addressed. edge of the CLK is met the PUT can con- dressed by the assertion of PC6/PIACK or sistently respond to a new read or write PC7/TIACK, respectively. The signals are Certain operations triggered by normal bus cycle every four CLK cycles. This fact first synchronized with the falling edge of read (or write) bus cycles are not complete is especially useful in designing the PI/T's the CLK. One clock period after they are within the time allotted to the bus cycle. clock in synchronous bus systems not us- recognized, the data bus buffers are enabl- One example is transfers to/from the dou- ing DTACK. (An extra CLK period is re- ed and the vector is driven onto the bus. ble buffered latches that occur as a result quired in interrupt acknowledge cycles, DTACK is asserted after another clock of the bus cycle. If the bus master's CLK is see Read Cycles via Interrupt period to allow the vector some setup significantly faster than the PI/T's, the Acknowledge). prior to DTACK. DTACK is negated, then possibility exists that, following the bus three-stated as with the normal read or cycle, CS can be negated then reasserted In asynchronous bus systems in which the write cycle when PIACK or TIACK is before completion of these internal opera- PI/T's CLK differs from that of the bus negated.

4.122 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PARALLEL INTERFACE/TIMER SCN68230

Preliminary ABSOLUTE MAXIMUM RATINGS1 Parameter Rating Unit

Supply voltage —0.3 to + 7.0 V Input voltage3 —0.3 to + 7.0 V Operating temperature range2 0 to + 70 °C Storage temperature — 55 to + 150 °C

DC ELECTRICAL CHARACTERISTICS (Vcc = 5.0V ± 5%, TA = 0 °C to + 70°C4'5 Limits Parameter Test Conditions Unit Min Max

VIH Input high voltage 2.0 Vcc V

VIL Input low voltage —0.3 0.8 V l,n Input leakage current V,n = 0 to 5.25V H1,H3,R/W,RESET,CLK, RS1-RS5, CS 10.0 µA

ITS! Three-state (off state) input current Vin = 0.4 to 2.4 DTACK,PCO-PC7, D0-D7 ± 20 µA H2,H4, PAO-PA7,PBO-PB7 — 0.1 — 1.0 mA

VOH Output high voltage DTACK, D0-D7 'LOAD= — 400µA, V00 = min 2.4 V

H2,H4, PBO-PB7, PAO-PA7 1LOAD = — 150mA, V00 = min 2.4 V PCO-PC7 'LOAD — — 100mA, V00 = min 2.4 V VOL Output low voltage PC3/TOUT,PC5/PIRQ I LOAD = 8.8n1A, Vcc= min 0.5 V D0-D7, DTACK ILoAD= 53mA, Vcc = min 0.5 V PAO-PA7, PBO-PB7,H2,H4, PCO-PC2,PC4,PC6,PC7 1LOAD = 2.4mA, Vcc = min 0.5 V

PINT Power dissipation TA = 0°C 500 mW Cin Input capacitance Vin = OV, TA = 25°C, f = 1MHz 15 pF

NOTES 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is stress rating only and functional operation of the device at these or at any other condition above those indicated in the operation section of this specification is not implied. 2. For operating at elevated temperatures, the device must be derated based on +150*C maximum junction temperature. 3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima. 4. Parameters are valid over specified temperature range. 5. All voltage measurements are referenced to ground (GND). For testing, all input signals swing between 0.4V and 2.4V with a transition time of 2Ons maximum. All time measurements are referenced at input voltages of 0.8V and 2.OV and output voltages of 0.8V and 2.OV as appropriate.

Signetics 4.123 MICROPROCESSOR DIVISION JANUARY 1983 PARALLEL INTERFACE/TIMER SCN68230

Preliminary

AC ELECTRICAL SPECIFICATIONS Vcc. 5VDC ± 5%, Vss = OVDC, TA = CI°V to 70°C (see figures 14-18)45

Tentative Limits Number Characteristic 8MHz 10MHz Unit Min Max MM Max 1 R/W, RS1-RS5 valid to CS low (setup time) 0 0 ns 215 CS low to R/W and RS1-RS5 invalid (hold time) 100 65 ns 36 CS low to CLK low (setup time) 30 20 ns 47 CS low to data out valid (delay) 75 60 ns 5 RS1-RS5, R/W valid to data out valid (delay) 140 100 ns 6 CLK low to DTACK low (read/write cycle) (delay) 0 70 0 60 ns 78 DTACK low to CS high (hold time) 0 0 ns 8 CS or PIACK or TIACK high to data out invalid (hold time) 0 0 ns 9 CS or PIACK or TIACK high to D0-D7 high impedance (delay) 50 45 ns 10 CS or PIACK or TIACK high to DTACK high (delay) 50 30 ns 11 CS or PIACK or TIACK high to DTACK high impedance (delay) 100 55 ns 12 Data in valid to CS low (setup time) 0 0 ns 13 CS low to data in invalid (hold time) 100 65 ns 14 Input data valid to H1(H3) asserted (setup time) 100 60 ns 15 H1(H3) asserted to input data invalid (hold time) 20 20 ns 16 Handshake input H1(H3) pulse width asserted 40 40 ns 17 Handshake input H1(H3) pulse width negated 40 40 ns 18 H1(H3) asserted to H2(H4) negated (delay) 150 120 ns 19 CLK low to H2(H4) asserted (delay) 100 100 ns 209 H2(H4) asserted to H1(H3) asserted 0 0 ns 2110 CLK low to H2(H4) pulse negated (delay) 125 125 ns 2214,16 Synchronized H1(H3) to CLK low on which DMAREQ is asserted (see figures 6 and 7) 2.5 3.5 2.5 3.5 clk per 23 CLK low DMAREQ is asserted to CLK low on which DMAREQ is negated 3 3 3 3 clk per 24 CLK low to output data valid (delay) (modes 0, 1) 150 120 ns 2514,16 Synchronized H1(H3) to output data invalid (modes 0, 1) 1.5 2.5 1.5 2.5 clk per

6. This specification only applies if the PVT had completed all operations Initiated by the previous bus cycle when CS was asserted. Following a normal read or write bus cycle, all operations are complete within three CLKs after the falling edge of the CLK pin on which DTACK was asserted. If CS is asserted prior to completion of these operations, the new bus cycle, and hence DTACK is postponed. If all operations of the previous bus cycle were complete when CS was asserted, this specification is made only to insure that DTACK is asserted with respect to the falling edge of the CLK pin as shown in the timing diagram, not to guarantee operation of the part. If the CS setup time is violated, DTACK may be asserted as shown, or may be asserted one clock cycle later. 7. Assuming the RS1.RS5 to data valid time has also expired. 8. This specification imposes a lower bound on CS low time, guaranteeing that CS will be low for at least 1 CLK period. 9. This specification assures recognition of the asserted edge of H1(H3). 10. This specification applies only when a pulsed handshake option is chosen and the pulse is not shortened due to an early asserted edge of H1(H3). 11. CLK refers to the actual frequency of the CLK pin, not the maximum allowable CLK frequency. 12. If the setup time on the rising edge of the clock is violated, H1(H3) may not be recognized until the next rising edge of the clock. 13. This limit applies to the frequency of the signal at TIN compared to the frequency of the CLK signal during each clock cycle. If any period of the waveform at TIN is smaller than the period of the CLK signal at that instant, then it is likely that the timer circuit will completely ignore one cycle of the TIN signal. If these two signals are derived from different sources, they will have different instantaneous frequency variations. In this case the frequency applied to the TIN pin must be distinctly less than the frequency at the CLK pin to avoid lost cycles of the TIN signal. With signals derived from different crystal oscillators applied to the TIN and CLK pins with fast rise and fall times, the TIN frequency can approach 80 to 90% of the frequency of the CLK signal without a loss of a cycle of the TIN signal. If these two signals are derived from the same frequency source, then the frequency of the signal applied to TIN can be 100% of the frequency at the CLK pin. They may be generated by different buffers from the same signal or one may be an inverted version of the other. The TIN signal may be generated by an AND function of the clock and a control signal. 14. The maximum value is caused by a peripheral access (H1(H3) asserted)) and bus access (CS asserted) occurring at the same time. 15. See Bus Interface Connection for exception. 16. Synchronized means that the input signal has been seen by the PINT on the appropriate edge of the clock (rising edge for H1(H3)) and falling edge for CS. Refer to Bus Interface Connection for exception concerning CS. 4.124 Signetics MICROPROCESSOR DIVISION JANUARY 1983 PARALLEL INTERFACE/TIMER SCN68230

Preliminary

AC Electrical Specifications (Continued) Voc =. 5VDC ± 5%, Vss = OVDC, TA = 13ni to 70°C (see figures 14-18)45 Tentative Limits Number Characteristic 8MHz 10MHz Unit Min Max Min Max

26 H1 negated to output data valid (modes 2, 3) 70 50 ns 27 H1 asserted to output data high impedance (modes 2, 3) 0 70 0 70 ns 28 Read data valid to DTACK low (setup time) 0 0 ns 29 CLK low to data output valid (interrupt acknowledge cycle) 120 100 ns 3012 H1(H3) asserted to CLK high (setup time) 50 40 ns 31 PIACK or TIACK low to CLK low (setup time) 50 40 ns 3216 Synchronized CS to CLK low on which DMAREQ is asserted (see figures 6 and 7) 3 3 3 3 clk per 3314,16 Synchronized H1(H3) to CLK low on which H2(H4) is asserted 3.5 4.5 3.5 4.5 clk per 34 CLK low to DTACK low (interrupt acknowledge cycle) (delay) 75 60 ns 35 CLK low to DMAREQ low (delay) 0 120 0 100 ns 36 CLK low to DMAREQ high (delay) 0 120 0 100 ns A CLK low to PIRO low or high impedance 250 225 ns B13 TIN frequency (external clock)—prescaler used 0 1 0 1 Fclk(Hz)11 C TIN frequency (external clock)—prescaler not used 0 1/32 0 1/32 Fclk(Hz)11 D TIN pulse width high or low (external clock) 55 45 ns E TIN pulse width low (run/halt control) 1 1 clk F CLK low to TOUT high, low, or high impedance 0 250 0 225 ns G CS, PIACK, or TIACK high to CS, PIACK, or TIACK low 50 30 ns

CLOCK TIMING (see Figure 13) 8MHz 10MHz Parameter Unit Min Max MM Max f Frequency of operation 2.0 8.0 2.0 10.0 MHz tcyc Cycle time 125 500 100 500 ns tCL Clock pulse width 55 250 45 250 ns tcH Clock pulse width 55 250 45 250 ns to. Clock rise time 10 10 ns tcf Clock fall time 10 10 ns

Signetics 4.125 MICROPROCESSOR DIVISION JANUARY 1983

PARALLEL INTERFACEITIMER SCN68230

Preliminary

POWER CONSIDERATIONS

The average chip-junction temperature, Tj, in °C can be obtained from: T j= TA+ IPD•OJA) 111 Where: TA =Ambient Temperature, °C OjA.- Package Thermal Resistance, Junction-to-Ambient, °C/W PD'- PINT + PPORT PINT= ICC x VCC, Watts — Chip Internal Power PpoRTE Port Power Dissipation, Watts — User Determined For most applications PPORT PINT and can be neglected. PPORT may become significant if the device is configured to drive Darlington bases or sink LED loads. An approximate relationship betweer PD and TJ (if PPORT is neglected) is: PD= K= (Tj + 273°C) 121 Solving equations 1 and 2 for K gives: K= PD•1TA+ 2730D +OjA•PD2 (3) Where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K the values of PD and T j can be obtained by solving equations (11 and 12) iteratively for any value of TA.

tO yO

tCL -10)0 tCH 2.0 V 0.8 V tCr a- Ict

Figure 13. Input Clock Waveform

CLK -0- WV% O

RS1.RS5 \\\ \\\\\\ -0-\\\\\\\\ \\\\\\\ 0 CS

O DO D7 O 0 DTACK 32 DMARECI

Figure 14. Bus Read Cycle Timing

4.126 Signetics MICROPROCESSOR DIVISION JANUARY 1983

PARALLEL INTERFACE/TIMER SCN68230

Preliminary

CLK

0 RIW \\ \ \\\\\\\ \ \\\\ \\\\\\\\ \\\\ \\

S-1.12S5 .....\X \\\\\\\\\\\\\\\\\\\\\\\-\\\\\ ..f— 0 —a. CS 0.---.' 23 1 DO 07

10 ). DTACK

D Mkt;] J *

15. Bus Write Cycle Timing

CLK

PIACK OR TIACK 0 0 DO 07 0

DTACK

Figure 16. Interrupt Acknowledge Functional Timing

Signetics 4.127 NOTE TIMINGDIAGRAMSHOWSHi,H2,I-13,ANDH4ASSERTEDLOW (PULSED) PA(PB)0.7 DMAREO H2(H4) H2(H4) Hl(H3) (INTL) CLK F 14 Figure 17.Peripheral InterfaceInputTiming >

4 CLOCKSMAX)0MIN 20 a CD 3 0 5

2130111/30VA2131N11311VaVd

£961, AdVIINVI NOISIAIG dOSS30021d0d011Al PA(PB)0-7 PA(PB)0.7 (PULSED) DMAREO (MD 2,3) (MD 01) H1(H3) H2(H4) H2(H4) (INTL) NOTE: TIMINGDIAGRAMSHOWSH1,H2,H3ANDH4ASSERTEDLOW. CLK ix

24 26 0 Figure 18.Peripheral InterfaceOutputTiming 8

0 < 30 0

27 0 0- a 3 a> -13 C) ND Cl) OD d30111139Vid31N11311VaVd

£966 AdVill\ df NOISIAla dOSS300dd0d011A1 MICROPROCESSOR DIVISION JANUARY 1983 DIRECT MEMORY ACCESS INTERFACE (DMAI) SCB68430

Preliminary

DESCRIPTION FEATURES PIN CONFIGURATION The SCB68430 Direct Memory Access • Bus compatible with SCN68000 Interface (DMAI) is a single channel inter- microprocessor face circuit which is intended to comple- • Software compatible with other 68K ment the performance and architectural family DMA controllers DBENN E Al capabilities of the SCN68000 microproc- • Single address transfers OWNN E A2 essor. The DMAI functions by transferring Cycle steal and burst mode operation • DTACKN E A3 a series of operands (data) between mem- • Bus arbitration daisy chain A4 ory and a device: operand sizes may be • Automatic rerun on bus error CSN E byte, word, or long word. A block is a • Supports 32-bit transfers for VME bus ASN E A5 sequence of operands: the number of • Supports SCN68000 vectored LDSN 43 A6 operands in the block is determined by a interrupts IRON E A7 transfer count stored within the DMAI. • 24-bit address counter The SCN68430 can be programmed to uti- • 16-bit transfer counter UDSN 41 DO/A8 lize single cycle (cycle stealing) or burst • Maximum transfer rate of 4Mbytes RIWN E Dl/A9 data transfers. per second IACKN 10 E D2/A10 • Signetics ISL bipolar technology The DMAI provides two interfaces. The BGN 11 E3 D31All microprocessor interface is fully compat- vcc E D4/Al2 ible with the SCN68000 microprocessor. The device interface includes lines for re- VBB E E vs, questing, acknowledging, controlling, and BGOUTN El E D51A13 timing the data transfers. The DMAI is a BGACKN 15 34 D6/A14 single-channel subset of the other 68000 family DMA controllers (68440 and 68450). BRN 16 E D7/A15 It is software compatible with these de- CLK 17 E D8/A16 vices and provides similar interfacing DONEN 18 E D9/A17 signals to both the system bus and the RDYN 19 30 D10/A18 device. ACKN 20 29 D11/A19 The SCB68430 is constructed using Signetics ISL bipolar technology and is DTCN 21 28 D12/A20 contained in a 48-pin dual-in-line package. REON 22 E D13/A21 RERUNN 23 26 D14/A22 RESETN E E D15/A23

TOP VIEW

ORDERING CODE

Vcc= 5V ± 5%, TA = 0°C to 70°C Packages 8MHz 10MHz Ceramic DIP SCB68430C8148 SCB68430CA 148 Plastic DIP SCB68430C8N48 SCB68430CA N 48

4.130 Signetics MICROPROCESSOR DIVISION JANUARY 1983

DIRECT MEMORY ACCESS INTERFACE (DMAI) SCB68430

Preliminary BLOCK DIAGRAM

BGN RERUNN RERUN DATA AND BUS GRANT LOGIC ADDRESS BUS DAISY BGOUTN

BRN CONTROL & STATUS BGACKN COUNTER ASN ► 68000 LDSN I BUS UDSN INTERFACE * R/WN ► 16-BIT DTACKN TRANSFER DO-D15 COUNTER < A8-A23 OWNN MUX CONTROL DBENN

CONTROL N 24-BIT LOGIC ADDRESS N ADDRESS COUNTER DECODE REON A1 A7 ACKN RDYN DEVICE DTCN HANDSHAKE DONEN IRON INTERRUPT LOGIC & REGISTER IACKN

PIN DESIGNATIONS MNEMONIC PIN NO. TYPE DESCRIPTION A1-A7 48-42 I/O Address Lines: Active high, three-statable. In the MPU mode, these low order address lines specify which internal register of the DMAI is being accessed. In DMA mode, A1-A7 are outputs which provide the low order address bits of the location being accessed. Three-stated in IDLE mode. A8-A23/ 41-37 I/O Address/Data Lines: Active high, three-statable. These lines are time multiplexed for data and ad- DO-D15 35-25 dress leads. The lines OWNN, RWN, CSN, and DBENN are used to control the demultiplexing of the address and data using external circuitry. In MPU mode, the bidirectional data lines (DO-D15) are used to transfer data between the MPU and the DMAI. In DMA mode, A8-A23 provide the high order address bits of the location being accessed. Three-stated in IDLE mode. ASN 5 I/O Address Strobe: Active low, three-statable. In MPU and IDLE modes, ASN is an input which indicates that the current bus master has placed a valid address on the bus. It is monitored by the DMAI during bus arbitration to ascertain that the previous bus master has completed the current bus cycle. In DMA mode, it is an output indicating that the DMAI has placed a valid address on the bus. UDSN 8 I/O Upper Data Strobe: Active low, three-statable. In MPU and IDLE modes, UDSN is an input which indicates that the upper data byte of the addressed word is being addressed. In DMA mode, it is an output with the same meaning. LDSN 6 I/O Lower Data Stobe: Active low, three-statable. In MPU and IDLE modes, LDSN is an input which indicates that the lower data byte of the addressed word is being addressed. In DMA mode, it is an output with the same meaning. R/WN 9 I/O Read/Write: Active high for read, low for write, three-statable. In MPU mode, R/WN is an input which controls the direction of data flow through the DMAI's input/output data bus interface and, if required, through an external data bus buffer. R/WN high causes the DMAI to place the data from the addressed register on the data bus, while R/WN low causes the DMAI to accept data from the data bus. In DMA mode, R/WN is an output to memory and I/O controllers indicating the type of bus cycle. It is held three-stated during IDLE mode. Signetics 4.131 MICROPROCESSOR DIVISION JANUARY 1983 DIRECT MEMORY ACCESS INTERFACE (DMAI) SCB68430

Preliminary

PIN DESIGNATIONS (Continued) MNEMONIC PIN NO. TYPE DESCRIPTION CSN 4 I Chip Select: Active low. When low, places the DMAI into the MPU mode. This input signal is used to select the DMAI for programmed data transfers. These transfers take place over DO-D15 as controlled by the RIWN and A1-A7 inputs. The DMAI is deselected when CSN is high. CSN is ignored during DMA mode. DTACKN 3 I/O Data Transfer Acknowledge: Active low, three-statable. In MPU mode, DTACKN is asserted on a write cycle to indicate that the data on the bus has been latched, and on a read cycle or interrupt acknowledge cycle to indicate that valid data is present on the bus. The signal is negated (driven high) when completion of the cycle is indicated by negation of the CSN or IACKN input, and returns to the inactive third state a short time after it is negated. In DMA mode, DTACKN is an input monitored by the DMAI to determine when the addressed device (memory) has latched the data (write cycle) or put valid data on the bus (read cycle). RESETN 24 I Master Reset: Active low. Assertion of this pin clears internal control registers (see table 1), initializes the interrupt vector register to H 'OF', and sets the status register to the default value B'0000 000X', where X is the state of RDYN. All bidirectional I/O lines are three-stated and the DMAI is placed in the IDLE mode. CLK 17 I Clock: Active high. Usually the system clock, but may be any clock meeting the electrical specifications. Used by the DMAI to synchronize device functions and external control lines, and may not be gated off at any time. IRON 7 0 Interrupt Request: Active low, open collector. This output is asserted, if interrupts are enabled, upon end of transfer, on occurrence of a bus error, and on receipt of an abort from the MPU. The CPU can read the status register to determine the interrupting condition(s), or can respond with an interrupt acknowledge cycle to cause the DMAI to output an interrupt vector on the data bus. IACKN 10 I Interrupt Acknowledge: Active low. When asserted, indicates that the current cycle is an interrupt acknowledge cycle. The DMAI normally responds by placing the contents of the interrupt vector register on the data bus and asserting DTACKN. IACKN is not serviced if the DMAI has not generated an interrupt request. BRN 16 0 Bus Request: Active low, open collector. BRN is asserted by the DMAI to request ownership of the bus after a DMA request is sensed on the REQN input from the I/O device. It is negated when the bus has been granted (BGN low) and BGACKN has been asserted, or, in burst DMA request mode, if the I/O device negates its request at least one clock cycle before BGACKN is asserted. BGN 11 I Bus Grant: Active low. BGN indicates to the DMAI that it is to be the next bus master. This signal is originated by the MPU and propagated via a daisy chain or other prioritization mechanism. After BGN is asserted, the DMAI waits until DTACKN, ASN, and BGACKN have become inactive before assuming ownership of the bus by asserting BGACKN. BGOUTN 14 0 Bus Grant Output: Active low. Daisy chain output which is asserted by the DMAI when BGN is asserted and the DMAI does not have a bus request pending. BGACKN 15 I/O Bus Grant Acknowledge: Active low, three-statable. As an input, BGACKN is monitored by the DMAI during the bus arbitration cycle to determine when it can assume ownership of the bus (BGACKN negated). In DMA mode, it is asserted by the DMAI to indicate that it is the bus master. Three-stated in MPU and IDLE modes. RERUNN 23 I Rerun: Active low. This input is asserted by external error detect logic to indicate a bus error. In DMA mode, the DMAI stops operation and three-states the data, address, and control lines, except BGACKN. It remains halted until RERUNN becomes inactive, and then re-tries the last bus cycle. If RERUNN is asserted again, the DMAI sets the ERR bit in the status register, stops DMA operation, releases the bus, and interrupts the CPU, if interrupts are enabled, responding with a special interrupt vector when IACKN is asserted. Not monitored in MPU and IDLE modes. REQN 22 I DMA Request: Active low. This input from the I/O device requests service from the DMAI and causes the DMAI to request control of the bus. In burst mode, the input is level sensitive, and the DMAI releases the bus after REQN is negated and the current DMA cycle is completed. In cycle steal mode, the REQN input is negative edge triggered. A negative going edge must occur at least one clock cycle before DTCN is asserted to accomplish continuous transfer cycles. ACKN 20 0 DMA Request Acknowledge: Active low. ACKN is asserted by the DMAI to indicate that it has gained the bus and the requested bus cycle is now beginning. It is asserted at the beginning of every bus cycle after ASN has been asserted, and is negated at the end of every bus cycle.

4.132 Signetics MICROPROCESSOR DIVISION JANUARY 1983 DIRECT MEMORY ACCESS INTERFACE (DMAI) SCB68430

Preliminary

PIN DESIGNATIONS (Continued) MNEMONIC PIN NO. TYPE DESCRIPTION RDYN 19 I Device Ready: Active low. RDYN is asserted by the requesting device to indicate to the DMAI that valid data has either been stored or put on the bus. If negated, it indicates that the data has not been stored or presented, causing the DMAI to enter wait states. RDYN can be held low continuously if the device is fast enough so that wait states are not required. DTCN 21 0 Device Transfer Complete: Active low. In DMA mode, DTCN is asserted by the DMAI to indicate to the device that the requested data transfer is complete. On a write to memory operation, it indicates that the data provided by the device has been successfully stored. On a read from memory operation, it indicates to the device that the data from memory is present on the data bus and should be latched. DONEN 18 I/O Done: Active low, open collector. As an output, DON EN is asserted by the DMAI concurrent with the ACKN output to indicate to the device that the transfer count is exhausted and that the DMAI s operation is completed as a result of that transfer. As an input, if asserted by the device before the transfer count became zero, it causes the DMAI to abort service and generate an interrupt request, if interrupts are enabled. OWNN 2 0 Own: Active low, open collector. This output is asserted by DMAI during the DMA mode to indicate bus mastership. It can be used to enable external address/data and control buffers. Inactive in MPU and IDLE modes. DBENN 1 0 Data Bus Enable: Active low, open collector. Asserted by the DMAI when CSN is asserted or when IACKN is asserted and the DMAI has an interrupt request pending. Can be used to enable bidirectional data buffers for DO-D15. Inactive in IDLE mode. Vcc 12 I Power Supply: + 5 volt power input. VBB 13 I Power Supply: + 1.5 volt power input. Vss 36 I Ground: Signal and power ground input.

PIN DESCRIPTION read as indicated in the register Device Control Register (DCR) The Pin Designation table describes the descriptions. 115) External Request Mode. This bit function of each of the pins of the DMAI. 3. All registers are addressable as 8-bit selects whether the DMAI operates in Signal names ending in 'N' are active low. quantities. To facilitate operation with burst or cycle steal mode. All other signals are active high. In the the 68K MOVEP instruction, addresses 0 Burst mode. This mode allows a descriptions, 'MPU mode' refers to the are ordered such that certain sets of device to request the transfer of state when the DMAI is chip selected. The registers may also be accessed as multiple operands using consecu- term 'DMA mode' refers to the state when words or long words. tive bus cycles. In this mode the the DMAI assumes ownership of the bus. request (REQN) line is an active low The DMAI is in the 'IDLE mode' at all other The operation of the DMAI is programmed input which is asserted by the times. by writing control words into the appropriate registers. Operational feedback is pro- device to request an operand trans- In this data sheet signals are discussed vided via status registers which can be fer. The DMAI services the request using the terms 'active' and 'inactive' or read by the CPU. The contents of certain by arbitrating for the bus, obtaining 'asserted' and 'negated' independent of control and status registers are initialized the bus, and notifying the periph- whether the signal is active in the high on RESET. eral by asserting the acknowledge (logic one) state or the low (logic zero) (ACKN) output. If the request line is To provide compatibility with the other state. Refer to the individual pin descrip- active when the DMAI asserts 68K family DMA controllers, control and tions for the definition of the active level ACKN, and remains active at least status bits are mapped in bit positions of each signal. until the DMAI asserts device equivalent to where they are located in the transfer complete (DTCN), the register map of the other devices. Bits REGISTERS AND COUNTERS DMAI recognizes a valid request for which are used in the other devices but another operand, which will be Register Map not in the DMAI are assigned default val- The internal accessible register organiza- transferred during the next bus cy- ues. If upward compatibility to the other tion of the DMAI is shown in table 1. The cle. If the request line is negated controllers is required, the programmer following rules apply to all registers: before the DMAI asserts DTCN, the should use these default values when DMAI relinquishes the bus and 1. A read from a reserved location in the writing the control words to the registers, waits for the next request. map results in a read from the the 'null although they have no effect in the DMAI. register'. The null register returns all When a register is read, the default value 1 Cycle steal mode. In this mode, the ones for data and results in a normal is returned regardless of the value used device requests an operand trans- bus cycle. A write to one of these loca- when the register is programmed. The de- fer by generating a falling edge on tions results in a normal bus cycle but fault value is indicated by '(x)' in unused the request (REQN) line. The DMAI no write occurs. bit positions in the register formats, which services the request by arbitrating 2. Unused bits of a defined register are are illustrated in table 2. for the bus, obtaining the bus, and Signetics 4.133 MICROPROCESSOR DIVISION JANUARY 1983 DIRECT MEMORY ACCESS INTERFACE (DMAI) SCB68430

Preliminary notifying the peripheral by assert- [5:4] Operand Size. The programming of 10 Long word. The operand size is 32 ing the acknowledge (ACKN) out- these bits determine whether UDSN, bits. The operand is transferred as put. The request line must be in the LDSN, or both are generated during the two 16-bit words. The MAC is incre- inactive state for at least one clock transfer cycle and the increment by which mented by two after each 16-bit cycle before a request is made. the memory address counter (MAC) is word is transferred. The value of After a request has been asserted, changed in each transfer cycle. the LSB of the MAC is ignored and it must remain at the assertion both UDSN and LDSN are asserted 00 Byte. The operand size is 8 bits. level for at least one clock cycle. If during the transfer. The transfer The MAC is incremented by one another request is received before counter decrements by one before after each operand transfer. If the the first operand part of a former the entire long word is transferred. LSB of the MAC is a '0', UDSN is request is acknowledged, the sec- Note that this mode is not imple- asserted during the transfer. If the ond request is not recognized. Nor- mented in the 68440. LSB of a MAC is a '1', LDSN is mally, the DMAI will relinquish the 11 Double word. The operand size is asserted during the transfer. The bus after servicing a valid request. 32 bits. The operand is transferred transfer counter decrements by However, if the device generates a as a single 32-bit word. The MAC is one before each byte is trans- new request before the DMAI as- incremented by four after each op- ferred. serts DTCN for the last operand erand transfer. The value of the two part, the DMAI will retain owner- 01 Word. the operand size is 16 bits. LSBs of the MAC is ignored (the Al ship of the bus and that request The MAC is incremented by two output will always be a zero in this will be serviced before the bus is after each operand transfer. The mode) and both UDSN and LDSN relinquished. value of the LSB of the MAC is are asserted during the transfer. ignored and both UDSN and LDSN The transfer counter decrements Operation Control Register (OCR) are asserted during the transfer. by one before the double word is [7] Direction The transfer counter decrements transferred. Note that this mode is by one before each word is not implemented in the 68440 or 0 Transfer is from memory to device. transferred. 68450; it is included in the DMAI to 1 Transfer is from device to memory. support VME bus operations. Table 1. DMAI ADDRESS MAP ADDRESS BITS1,2 ACRONYM REGISTER NAME MODE AFFECTED BY RESET 7 6 5 4 3 2 1 0 d d 0 0 0 0 0 0 CSR Channel Status Register R/W3 Yes d d 0 0 0 0 0 1 CER Channel Error Register R Yes d d 0 0 0 0 1 0 Reserved d d 0 0 0 0 1 1 Reserved d d 0 0 0 1 0 0 DCR Device Control Register R/W Yes d d 0 0 0 1 0 1 OCR Operation Control Register R/W Yes d d 0 0 0 1 1 0 SCR Sequence Control Register R/W4 Yes d d 0 0 0 1 1 1 CCR Channel Control Register R/W Yes d d 0 0 1 0 0 0 Reserved d d 0 0 1 0 0 1 Reserved d d 0 0 1 0 1 0 MTCH Memory Transfer Counter High R/W No d d 0 0 1 0 1 1 MTCL Memory Transfer Counter Low R/W No d d 0 0 1 1 0 0 MACH Memory Address Counter High R/W4 No d d 0 0 1 1 0 1 MACMH Memory Address Counter Middle High R/W No d d 0 0 1 1 1 0 MACML Memory Address Counter Middle Low R/W No d d 0 0 1 1 1 1 MACL Memory Address Counter Low R/W No d d 0 1 d d d d Reserved d d 1 0 0 Odd Reserved d d 1 0 0 1 0 0 Reserved d d 1 0 0 1 0 1 IVR Interrupt Vector Register R/W Yes d d 1 0 0 1 1 0 Reserved d d 1 0 0 1 1 1 IVR Interrupt Vector Register R/W Yes d d 1 0 1 Odd Reserved d d 1 0 1 1 0 0 Reserved d d 1 0 1 1 0 1 CPR Channel Priority Register R/W4 No d d 1 0 1 1 1 0 Reserved d d 1 0 1 1 1 1 Reserved d d 1 1 d d d d Reserved Notes: 1. A0=0 for UDSN asserted, AO= I for LDSN asserted. 2. 'd' designates don't care. 3. A write to this register may perform a status resetting operation. 4. This register is a dummy register present only to provide compatibility with other 68K family DMA controllers. A rite to this register has no effect on the DMAI.

4-134 Signetics MICROPROCESSOR DIVISION JANUARY 1983

DIRECT MEMORY ACCESS INTERFACE (DMAI) SCB68430

Preliminary Table 2. REGISTER BIT FORMATS

DEVICE CONTROL REGISTER

BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 BITO9 BITO8

EXTERNAL REQUEST MODE NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED DCR (0) (0) 0 = BURST (0) (1) (.1) I.) (0) 1= CYCLE STEAL

*Should be programmed as '0' for SIZE (OCR[5:4])= 00 and as '1' otherwise. When read, the value of this bit is OCR[5].OROCRt4].

OPERATION CONTROL REGISTER (OCR)

BIT07 BITO6 BITO5 BITO4 BITO3 BITO2 BITO1 BITOO

DIRECTION OPERAND SIZE

0= MEM TO 00 = BYTE OCR DEV NOT USED 01 = WORD (16 BIT) NOT USED NOT USED NOT USED NOT USED 1= DEV TO (0) 10= LONG WORD (0) (0) (1) (0) MEM 11 = WORD (32-BIT)

*Long word and 32-bit word modes are not supported by 68440. 32-bit word mode is not supported by 68450.

SEQUENCE CONTROL REGISTER (SCR)

BIT15 81714 BIT13 BIT12 B1711 BIT10 BITO9 BITO8

NOT USED NOT USED NOT USED ' NOT USED NOT USED NOT USED NOT USED NOT USED SCR (0) (0) (0) (0) (0) (1) (0) (0)

CHANNEL CONTROL REGISTER (CCR)

BITO7 BITO6 BITO5 BITO4 BITO3 BITO2 BITO1 BITOO

START SOFTWARE INTERRUPT ABORT ENABLE

CCR O=NO NOT USED NOT USED 0 = NO 0 = NO NOT USED NOT USED NOT USED 1= YES (0) (0) 1 = YES 1= YES (0) (0) (0)

CHANNEL STATUS REGISTER (CSR)

BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 BITO9 BITO8

CHANNEL NORMAL ERROR CHANNEL READY OPERATION DEVICE ACTIVE INPUT COMPLETE NOT USED TERMINATE NOT USED NOT USED STATE CSR O=NO (0) 0 = NO O=NO O=NO (0) (0) 0 = LOW 1=YES 1= YES 1 = YES 1= YES 1= HIGH

CHANNEL ERROR REGISTER (CER)

BIT07 BITO6 BIT05 BITO4 BITO3 BITO2 BITO1 BITOO

ERROR CODE

CER NOT USED NOT USED NOT USED 00000= NO ERROR (0) (0) (0) 01001 = BUS ERROR 10001 =SOFTWARE ABORT

CHANNEL PRIORITY REGISTER (CPR)

BITO7 BITO6 BITO5 BITO4 BITO3 BITO2 BITO1 BITOO

NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED CPR (0) (0) (0) (0) (0) (0) (0) (0)

Signetics 4-135 MICROPROCESSOR DIVISION JANUARY 1983 DIRECT MEMORY ACCESS INTERFACE (DMAI) SCB68430

Preliminary

Sequence Control Register (SCR) successful or not, of any DMAI operation Only the least significant 24 bits of the This register serves no function in the and indicates that the DMA transfer has counter (MACMH, MACML, and MACL) are DMAI. It is included only to provide com- completed. This bit must be cleared to implemented in the DMAI. The most sig- patibility with the programming for the start another channel operation. nificant byte of the counter, MACH, is pro- 68440 and 68450 DMA controllers. vided only to allow compatibility with pro- 1131 Normal Device Termination. This bit is gramming of the 68440 and 68450. Writing set when the device terminates the DMAI Channel Control Register (CCR) to MACH has no effect on the DMAI opera- operation by asserting the DONEN line 171 Start Operation tion. Reading MACH always returns while the device was being acknowledged. 0 No start pending. H'00'. 1 Start operation. The start bit is set This bit must be cleared to start another to initiate operation of the DMAI. channel operation. The memory address counter and Memory Transfer Counter 1121 Error. This bit is used to report that (MTCH, MTCL) the memory transfer counter should the DMAI's operation was terminated due The 16-bit memory transfer counter pro- have been previously initialized, to the occurrence of an error. The condi- grams the number of operands to be trans- and all bits of the channel status tion which caused the error can be deter- ferred by the DMAI. The counter must be register (CSR) should have previ- mined by reading the channel error regis- initialized prior to beginning the transfer ously been reset. The DMAI initi- ter (CER). This bit must be cleared to start of a block of data and then decrements ates operation by clearing any another channel operation. When this bit once per operand transfer (regardless of pending requests, clearing the is cleared, the CER is also cleared. start bit, and setting the channel operand size) until it reaches the terminal active bit in the CSR. The DMAI is [11] Channel Active. This bit is set after the value of zero. Channel operation then ter- then ready to receive requests for channel has been started and remains set minates and the COC bit in the CSR will be an operation. The channel cannot until the channel operation terminates. asserted. be started if any of the internal It is then automatically cleared by the status bits in the CSR (CSR[15:11]) DMAI. The bit is unaffected by the write Interrupt Vector Register (IVR) have not been cleared. operations. The IVR contains the value to be placed on the data bus upon receipt of an interrupt 181 Ready Input State. This bit reflects the A pending start cannot be reset by acknowledge from the MPU. Only the state of the RDYN input at the time the a write to the register. START can seven most significant bits of the pro- CSR is read. The bit is a'0' if RDYN is low be cleared only by the DMAI when grammed value are used by the DMAI. The and a'1' if RDYN is high. This bit is unaf- it starts operation or by setting the output vector from the DMAI contains a fected by write or reset operations. software abort bit (CCR[4)). zero in the least significant bit position if a 141 Software Abort Channel Error Register (CER) normal termination occurred (error bit not 0 Do not abort. 14:01 Error Code. This field indicates the set) and contains a one in the least signifi- 1 Abort operation. Setting this bit source of error when an error is indicated cant bit position if termination was due to terminates the current operation of in CER[12]. The contents of this register an error (error bit set). the DMAI and places it in the IDLE are cleared when CER[12] is cleared. The contents of this register are initialized state. The channel operation com- 00000 No error. to H'OF' by a reset. The value returned plete and error bits in the CSR are 01001 Bus error. A bus error occurred dur- will be H'OF', regardless of the error set, the channel active bit in the ing the last bus cycle generated by state, until the register is programmed by CSR is reset, and an ABORT the DMAI. See rerun description in the MPU. ERROR condition is signaled in the OPERATION section. CER. Setting this bit causes a 10001 Software abort. The channel opera- To provide compatibility with the other pending start to be reset. tion was terminated by a software 68K family DMA controllers, the IVR has abort command. See CCR[4]. two addresses (see table 1). If program [3] Interrupt Enable compatibility is required, the value written 0 Interrupts not enabled. Channel Priority Register (CPR) at the normal IVR address should have a 1 Enable interrupts. An interrupt re- This register serves no function in the zero as its LSB, and the value written at quest is generated if the channel DMAI. It is included only to provide corn- the error IVR address should be the same operation complete bit in the CSR patiblity with the programming for the but with the LSB equal to one. is set. When the IACKN input is other 68K family DMA controllers. asserted, the DMAI returns the nor- OPERATION mal interrupt vector if the error bit Memory Address Counter A DMAI operation proceeds in three princi- in the CSR is not set, or the error (MACH, MACMH, MACML, MACL) pal phases. During the initialization phase, interrupt vector if error is set. The 32-bit memory address counter is the MPU configures the channel control Channel Status Register (CSR) used to program the memory location registers, loads the initial memory ad- where the first operand to be transferred dress and transfer count, and starts the A read of this register provides the status is located or is to be transferred to, channel. During the transfer phase, the of the DMAI. The COC, NDT, and ERR bits depending on the direction of transfer. DMAI accepts requests for transfers from can be cleared by writing a '1' to the bit The counter must be initialized prior to the device, arbitrates for and acquires positions of the register which are to be beginning the transfer of a block of data ownership of the bus, and provides for ad- cleared. Those bit positions which are and then increments automatically de- dressing and bus controls for the trans- written with a '0' remain unaffected. pending on the operand length, as de- fers. The termination phase occurs after 1151 Channel Operation Complete. This bit scribed in the Operation Control Register the operation is complete, when the DMAI is set following the termination, whether description. reports the status of the operation.

4.136 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 DIRECT MEMORY ACCESS INTERFACE (DMAI) SCB68430

Preliminary

Operation Initiation least one clock cycle. If another request is Bus Arbitration After having programmed the control reg- received before the first operand part of a Upon receiving a valid request for a trans- isters, the memory address counter, and former request is acknowledged, the sec- fer from the device, the DMAI will arbitrate the memory transfer counter, the MPU ond request is not recognized. Normally, for and obtain ownership of the system sets the start bit (CCR[7]). The DMAI ini- the DMAI will relinquish the bus after serv- bus. tiates the operation by clearing any pend- icing a valid request. However, if the The DMAI indicates that it wishes to ing requests, clearing the start bit, and device generates a new request before the become the bus master by asserting its setting the channel active bit in the CSR. DMAI asserts DTCN for the last operand bus request (BRN) output. This is a wire- The DMAI is then ready to receive valid re- part, the DMAI will retain ownership of the ORed signal that indicates to the MPU quests for an operation. bus and that request will be serviced that some external device requires control before the bus is relinquished. The channel cannot be started if any of the of the bus. The processor is effectively at internal status bits in the CSR (CSR[15:11]) Acknowledge (ACKN). The DMAI asserts a lower priority level than external devices have not been cleared. An error is not sig- the acknowledge line, which implicitly ad- and will relinquish the bus after it has naled if this condition occurs. The only dresses the device making the request, completed the last bus cycle it has indication of this state is that the start bit during transfers to and from the device. started. The processor puts the bus up for remains set in the CCR. A pending start The line may be used to control buffering external arbitration by asserting its bus 4 cannot be reset by a write to the register. circuits between the data bus and the grant (BGN) output. This signal may be START can be cleared only by the DMAI MPU bus. routed through a daisy chain (such as pro- when it starts operation or by setting the Ready (RDYN). Ready is an active low in- vided by the DMAI) or through some other software abort bit (CORM). put which is asserted by the requesting priority-encoded network. When the DMAI Device/DMAI Communication device to indicate to the DMAI that valid making the bus request receives the bus Communication between the peripheral data has either been stored or put on the grant (indicated by its BGN input being device and the DMAI is accommodated by bus. If negated, it indicates that the data asserted), it is to be the next bus master. It five signal lines: has not been stored or presented, causing waits until address strobe (ASN), data the DMAI to enter wait states until RDYN transfer acknowledge (DTACKN) and bus Request (REON). The device makes a re- grant acknowledge (BGACKN) become in- quest for service by asserting the request is asserted. RDYN can be held low continuously if the device is fast enough so that active and then assumes ownership of the line. The DMAI can operate in either the bus by asserting its own BGACKN output. burst request mode or the cycle stealing wait states are not required. The current state of the ready input is reflected in The DMAI then negates the BRN output request mode, as programmed by the and proceeds with the data transfer external request mode bit (DCR[15]). CSR[8]. phase. After this phase is completed, the The burst mode allows a device to request Done (DONEN). Done is a bidirectional ac- DMAI relinquishes bus ownership by the transfer of multiple operands using tive low signal. As an output, it is asserted negating the BGACKN output. consecutive bus cycles. In this mode the and negated by the DMAI concurrent with In burst DMA mode, detection of an active request line is an active low input. The the ACKN output of the last operand part low request input after the DMAI opera- DMAI services the request by arbitrating to indicate to the device that the memory tion has been started will begin the bus for the bus, obtaining the bus, and notify- transfer count is exhausted and that the arbitration cycle. However, if the device ing the peripheral by asserting the DMAI's operation is completed as a result negates its request at least one clock acknowledge (ACKN) output. If the re- of that transfer. cycle before the DMAI asserts BGACKN, quest line is active when the DMAI asserts the DMAI will negate its bus request and ACKN, and remains active at least until The DMAI also monitors the state of the will not assume ownership of the bus. the DMAI asserts device transfer com- line while acknowledging a device. If the plete (DTCN), the DMAI recognizes a valid device asserts DONEN, the DMAI will ter- Data Transfers request for another operand, which will be minate operation after the transfer of the The actual transfer of data between the transferred during the next bus cycle. If current operand. In this case the DMAI memory and the device occurs during the the request line is negated before the clears the channel active bit and sets the data transfer phase. All transfers occur DMAI asserts DTCN, the DMAI relin- channel operation complete and normal during a single cycle except in the case of quishes the bus and waits for the next re- device termination bits in the CSR. If both long word operands, in which case two quest. For long word transfers (2 x 16), the the DMAI and the device assert DONEN, cycles are used to transfer the operand as request must be asserted at least until the the device termination is not recognized, two 16-bit words. The transfers take place acknowledge for the second part of the but the operation does terminate. using a 'single address' protocol; the operand has been asserted. Device Transfer Complete (DTCN). DTCN DMAI addresses the memory via the bus address lines, while the device is implicit- In the cycle steal mode, the device re- is an active low output which is asserted ly addressed via the acknowledge output. quests an operand transfer by generating by the DMAI to indicate to the device that a falling edge on the request line. The the requested data transfer is complete. When a request is generated using the re- DMAI services the request by arbitrating On a write to memory operation, it indi- quest method programmed in the control for the bus, obtaining the bus, and notify- cates that the data provided by the device register, the DMAI obtains the bus and ing the peripheral by asserting the has been successfully stored. On a read asserts acknowledge to notify the device acknowledge (ACKN) output. The request from memory operation, it indicates to the that a transfer is to take place. The DMAI line must be in the inactive state for at device that the data from memory is pres- asserts all 568000 bus control signals least one clock cycle before a request is ent on the data bus and should be latched. needed for the transfer and holds them made. After a request has been asserted, DTCN is not asserted if assertion of the until the device responds with ready. The it must remain at the assertion level for at RERUNN input terminates the bus cycle. bus cycle then terminates normally. Ready Signetics 4.137 MICROPROCESSOR DIVISION JANUARY 1983 DIRECT MEMORY ACCESS INTERFACE (DMAI) SCB68430

Preliminary may be tied low (asserted) if the device is DONEN, the device termination is not rec- count minus one of the attempted trans- fast enough. ognized, but the operation does terminate. fer. The memory address counter will contain the address at which the DMA opera- When the transfer is from memory to the Software Abort. The software abort bit tion was attempted. device, data is valid when DTACKN is (CCR[4]) allows the MPU to abort the cur- asserted by the memory and remains valid rent operation of the DMAI. The COC and Reset. The reset input (RESETN) provides until the data strobe(s) are negated. The error bits in the CSR are set, the channel a means of resetting and initializing the assertion of DTCN from the DMAI can be active bit in the CSR is cleared, and an DMAI from an external source. If the DMAI used to latch the data, as the data strobes abort error condition is signaled in the is a bus master when reset is received, the are not removed until one-half clock after CER. DMAI relinquishes the bus. Reset clears the assertion of DTCN. the control and error registers, sets all bits Rerun Error. The DMAI provides a rerun in- of the status register except CSR[8] to When the transfer is from device to put (RERUNN) to indicate a bus exception zero, and initializes the interrupt vector memory, the data must be valid on the bus condition. RERUNN must arrive prior to or register to H 'OF '. before the DMAI asserts the data in coincidence with DTACKN in order to strobe(s). The device indicates valid data be recognized, and the DMAI verifies that by asserting ready. The DMAI then asserts the line has been stable for two clock Interrupts. The interrupt enable bit the strobes and holds them asserted until cycles before acting on it. The occurrence (CCR[3]) determines whether the DMAI the memory accepts the data, indicated by of a rerun during a DMAI bus cycle forces generates interrupt requests. When the bit the assertion of DTACKN. The DMAI then it to terminate the bus cycle in an orderly is set, an interrupt request is generated if asserts DTCN and negates the data manner. the channel operation complete bit in the strobes. CSR is set. When the IACKN input is When the assertion of rerun is verified, the asserted, and the DMAI has an interrupt Flow charts for these operations are DMAI stops operation and three-states the request pending, the DMAI returns an shown in figures 1 and 2. Refer to the tim- data, address, and control lines, except interrupt vector on the data bus. ing section for the equivalent timing BGACKN, so that it retains ownership of diagrams. the bus. It remains halted until rerun The interrupt vector issued is the contents becomes inactive, and then re-tries the of the IVR. Only the seven most signifi- Operation Termination last bus cycle. If rerun is asserted again, cant bits of the programmed value are Termination of the block transfer occurs the DMAI stops DMA operation, releases used by the DMAI. The vector from the under the conditions detailed below. the bus, sets the error and COC bits in the DMAI contains a zero in the LSB position CSR, clears the active bit in the CSR, and if a normal termination occurred (error bit Terminal Count. As part of each transfer of not set) and contains a one in the LSB an operand, the DMAI decrements the sets the error code in the CER to indicate a bus error. position if termination was due to an error memory transfer counter. If this counter is (error bit set). decremented to zero, the operand is the While stopped due to assertion of rerun, The contents of this register are initialized last operand of the block. The DMAI opera- the DMAI does not generate any bus to H'OF' by a reset. The value returned tion is complete and it notifies the device cycles and will not honor any requests will be H 'OF ', regardless of the error of completion by asserting the DONEN until it is removed. However, the DMAI still state, until the register is programmed by output during the last operand transfer recognizes requests. cycle. When the transfer has been com- the MPU. Error Recovery Procedure. If an error oc- pleted, the channel active bit in the CSR is To provide compatibility with the other curs during a DMA transfer such that the cleared and the COC bit is set. 68K family DMA controllers, the IVR has DMAI stops the DMA operation, informa- Device Termination. The DMAI monitors tion is available to the operating system two addresses (see table 1). If program the state of the DON EN line while acknow- for an error recovery routine. compatibility is required, the value written ledging a device transfer request. If the at the normal IVR address should have a device asserts DONEN, the DMAI will ter- The information available to the operating zero as its LSB, and the value written at minate operation after the transfer of the system consists of the memory address the error IVR address should be the same current operand. When the transfer has counter, the memory transfer counter, and but with the LSB equal to one. been completed, the DMAI clears the the control, status, and error registers. channel active bit and sets the COC and The DMAI decrements the memory trans- APPLICATIONS normal device termination bits in the CSR. fer counter before attempting a DMA oper- Figure 3 illustrates a typical interconnec- If both the DMAI and the device assert ation, so the register will contain the tion of the DMAI in a 68000 based system.

4.138 Signetics MICROPROCESSOR DIVISION JANUARY 1983 DIRECT MEMORY ACCESS INTERFACE (DMAI) SCB68430

Preliminary

DMAI MEMORY DEVICE DMAI MEMORY DEVICE

Initiate Request Initiate Request 1. Assert REQN 1. Assert REQN

Acquire Bus Acquire Bus

Address Memory Address Memory 1. Set RWN to write 1. Set RWN to read 2. Place address on A1-A23 2. Place address on A1-A23 3. Assert ASN 3. Assert ASN 4. Assert ACKN 4. Assert UDSN and/or LDSN 5. Assert ACKN

Present Data 1. Place data on Present Data data bus 1. Decode address 2. Assert RDYN 2. Place data on data bus 3. Assert DTACKN Enable Data 1. Assert UDSN and/or LDSN Acquire Data 1. Load data 2. Assert RDYN Acquire Data 1. Decode address 2. Load data Terminate Transfer 3. Assert DTACKN 1. Assert DTCN 2. Negate UDSN and/or LDSN and ASN 3. Negate ACKN and DTCN Terminate Transfer 1. Assert DTCN 2. Negate UDSN and/or LDSN and ASN Terminate Cycle 3. Negate ACKN and DTCN 1. Negate DTACKN

Terminate Cycle 1. Negate DTACKN Relinquish Bus

Or Relinquish Bus

or Start Next Cycle or

Start Next Cycle

Figure 1. Transfer from Memory to Device Flow Chart Figure 2. Transfer from Device to Memory Flow Chart

Signetics 4.139 MICROPROCESSOR DIVISION JANUARY 1983

DIRECT MEMORY ACCESS INTERFACE (DMAI) SCB68430

Preliminary

RIWN

DIR RIWN

D0-D15 < '245 AID

EN EQN DBENN ACKN

SCB68430 RDYN A8-A23 '244 DMAI DEVICE +5 DTCN EN DONEN OWNN

DIR

A1-A7 < '245 A1-A7 EN CONTROL

68000 CONTROL LINES

Figure 3. DMAI Application

ABSOLUTE MAXIMUM RATINGS1 PARAMETER RATING UNIT

Supply voltages Vcc and VBB — 0.5 to + 7.0 V Input voltage —0.5 to + 5.5 V Operating temperature range2 0 to + 70 °C Storage temperature — 65 to + 150 °C

DC ELECTRICAL CHARACTERISTICS Vcc = 5.0V ± 5%, V„ = 1.5V ± 10%, TA = 0°C to + 70 °C3'4 LIMITS PARAMETER TEST CONDITIONS UNIT Min Max VIL Input low voltage 0.8 V VIH Input high voltage 2.0 V

VOL Output low voltage lour = 4mA 0.4 V lOuy = 8mA 0.5 V VOH Output high voltage, !OUT= —400µA 2.5 V all outputs except open collector outputs5

!IL Input low current VIN = 0.4V —400 AA 116 Input high current VIN = 2.7V 20 tok loc Open collector off state currents VOUT = 2.4V 20 AA Isc Output short circuit currents Vcc = max —40 — 100 mA

ICC VCC supply current 130 mA \ice = max, VBB = max 113B VBB supply current 450 mA NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is stress rating only and functional operation of the device at these or at any other conditions other than those indicated in the Electrical Characteristics section of this data sheet is not implied. 2. For operating at elevated temperatures, the device must be derated based on + 150°C maximum junction temperature. 3. Parameters are valid over specified temperature range. 4. All voltage measurements are referenced to ground (VBB). For testing, all signals swing between 0.4V and 2.4V with a transition time of 2Ons maximum. At I time measurements are referenced at input voltages of 0.8V and 2.0V as appropriate. 5. IRON, BRN, DONEN, and OWNN are open collector outputs. 6. No more than one output should be connected to ground at one time.

4-140 Signetics MICROPROCESSOR DIVISION JANUARY 1983 DIRECT MEMORY ACCESS INTERFACE (DMAI) SCB68430

Preliminary

AC ELECTRICAL CHARACTERISTICS Vcc = 5.0V ± 5%, V„ = 1.5V ± 10%, TA = 0°C to 70°C3'4 TENTATIVE LIMITS NO. FIGURE CHARACTERISTIC 8MHz 10MHz UNIT Min Max Min Max 1 4 A1-A7, ASN, RWN setup to UDSN, LDSN low 0 ns 2 4 D0-D15 3-state to invalid data from ASN, CSN,and UDSN or LDSN low 10 ns 3 4 DTACKN 3-state to high from ASN, CSN,and UDSN or LDSN low 10 ns 4 4 CSN low after UDSN or LDSN low 25 ns 5 4, 5 DBENN low after ASN and CSN low 45 ns 6 4 D0-D15 valid data from ASN, CSN, and UDSN or LDSN low 95 ns 7 4 DTACKN low after D0-D15 valid data 0 30 ns 8 4 A1-A7, ASN, RWN or CSN hold after UDSN and LDSN high 0 ns 9 4, 5 DBENN high from either ASN or CSN high 45 ns 10 4 D0-D15 to 3-state from UDSN and LDSN high 80 ns 11 4 D0-D15 to invalid data from UDSN and LDSN high 10 ns 12 4, 5 DTACKN high from UDSN and LDSN high 55 ns 13 4, 5 DTACK 3-state from either CSN or ASN high 85 ns 14 5 A1-A7, ASN, RWN setup to UDSN, LDSN low 50 ns 15 5 CSN setup before UDSN or LDSN low 20 ns 16 5 DTACKN 3-state to high after CSN and ASN low 10 ns 17 5 DO-D15 valid after UDSN or LDSN low 35 ns 18 5 DTACKN low from UDSN or LDSN low 100 ns 19 5 UDSN and LDSN low time 95 ns 20 5 A1-A7 hold after UDSN and LDSN high 0 ns 21 5 ASN, RWN and CSN hold after UDSN and LDSN high 0 ns 22 5 D0-D15 hold after UDSN and LDSN high 0 ns 23 6 DBENN low from last low of ASN, IACKN, LDSN 65 ns 24 6 D0-D7 valid after last low of ASN, IACKN, LDSN 100 ns 25 6 DTACKN 3-state to high after last low of ASN, IACKN, LDSN 100 ns 26 6 DTACKN low after last low of ASN, IACKN, LDSN 110 ns 27 6 DBENN high after first high of ASN, IACKN, LDSN 50 ns 28 6 DO-D7 hold after first high of ASN, IACKN, LDSN 60 ns 29 6 D0-D7 3-state after first high of ASN, IACKN, LDSN 80 ns 30 6 DTACKN high after first high of ASN, IACKN, LDSN 60 ns 31 6 DTACKN 3-state after first high of ASN, IACKN, LDSN 95 ns 32 7 BRN high from CLK high 45 ns 33 7, 10, 11 BGACKN low from CLK low 75 ns 34 7, 10, 11 OWNN low from CLK high 55 ns 35 7 BGACKN high from CLK low 75 ns 36 7 OWNN high from CLK high (load dependent) 37 9 REQN setup before CLK low 30 ns 38 9 REQN hold after CLK high 20 ns 39 9 BRN low from CLK high 75 ns 41 10, 11 ASN, UDSN, LDSN, RWN 3-state to high from CLK low 75 ns 43 10, 11 A1-A23 3-state to valid from CLK high 85 ns 44 10, 11 ASN low from CLK high 50 ns 45 10, 11 LDSN, UDSN low from CLK high 60 ns 46 10, 11 ACKN low from CLK high 55 ns 47 10, 11 DTACKN setup to CLK high 30 ns 48 10, 11 RDYN setup to CLK low 30 ns 49 10, 11 DTCN low from CLK high 55 ns 50 10, 11 ASN high from CLK high 75 ns 51 10, 11 LDSN, UDSN high from CLK high 90 ns 52 10, 11 DTACKN, RDYN hold after CLK high 0 ns — 10, 11 ASN, LDSN, UDSN high from DTCN low 0 ns 53 10, 11 ACKN high from CLK high 50 ns 54 10, 11 DTCN high from CLK high 50 ns 55 10, 11 Address valid after CLK low 10 ns — 10, 11 Address valid after ASN high 0 ns 56 10, 11 DONEN (output) low from CLK low 120 ns

Signetics 4.141 MICROPROCESSOR DIVISION JANUARY 1983 DIRECT MEMORY ACCESS INTERFACE (DMAI) SCB68430

Preliminary

AC ELECTRICAL CHARACTERISTICS (Continued) TENTATIVE LIMITS NO. FIGURE CHARACTERISTIC 8MHz 10MHz UNIT Min Max Min Max 57 10, 11 DONEN (output) high from CLK high 50 ns 58 10, 11 DONEN (input) setup low before CLK low 30 ns 59 10, 11 DONEN (input) hold low after CLK high 0 ns 60 10, 11 BGACKN, ASN, UDSN, LDSN, RWN to 3-state from CLK low 75 ns 61 10, 11 OWNN high from CLK high 50 ns 62 10, 11 A1-A23 valid to 3-state from CLK high 100 ns 63 11 R/WN low from CLK high 50 ns 64 11 R/WN high from CLK high 75 ns 65 12 RERUNN setup low before CLK high 30 ns 66 12 RERUNN hold low from CLK high 20 ns 67 12 A1-A23 to idle state from CLK low 100 ns 68 12 A1-A23 to valid after CLK low 85 ns

Al A7

ASN

RWN

CSN

UDSN

LDSN

0 0

DBENN

0 10 H A DO D15 tINVALID DATA VALID DATA INVALID

O 4 DTACKN 0 k- 12

Figure 4. DMAI Read Timing

4.142 Signetics MICROPROCESSOR DIVISION JANUARY 1983

DIRECT MEMORY ACCESS INTERFACE (DMAI) SCB68430

Preliminary

Al A7

ASN

RWN

CSN I CD

UDSN

LDSN ro DBENN --I Ho DO-D15

(1)

DTACKN

Figure 5. DMAI Write Timing

Signetics 4.143

MICROPROCESSOR DIVISION JANUARY 1983 DIRECT MEMORY ACCESS INTERFACE (DMAI) SCB68430

Preliminary

Al-A7

ASN

IACKN

RWN

UDSN

LDSN

OWNN

DBENN 27

DO-D7

DTACKN c=1

Figure 6. CPU IACK Cycle to DMAI

4.144 Signetics MICROPROCESSOR DIVISION JANUARY 1983

DIRECT MEMORY ACCESS INTERFACE (DMAI) SCB68430

Preliminary

CLK

BRN 22

BGN1

BGACKN 35 — e T4 22 BUS CYCLES 22 1—C

OWNN 3 4 --1 •••••

2 CONTROL BUS 22

NON DMAI DEAD DMAI CYCLES DEAD

Figure 7. DMAI Bus Arbitration Timing

NOTES: 1. Device will become master if BGN is asserted concurrent with or later than REQN (same clock edge or later). 2. ASN, DTACKN and BGACKN must be negated in order for DMAI to become master. Timing assumes all these happen concurrent with BON—if not, it is from the latest signal which is negated.

Signetics 4.145 \I D IV IRE 2JO CT 3 21d0 0 300 ME MORY IAIG dOSS

CLK NOIS A CCES

REQN A 22 / 22 S INTERFACE

BRN

2 2 BGN I \, 2/ (DMAI BGACKN

BUS CYCLES )

ACKN

DTCN

I OTHER MASTER I DEAD I DMAI CYCLES DMAI CYCLE I IDLE NON DMAI I ARBITRATION

NOTES: 1. To maintain mastership next bus cycle, REQN must remain asserted at least until 1/2 clock cycle after DTCN is asserted. 2. To guarantee that mastership is relinquished next cycle, REQN must be negated no later than 112 clock cycle prior to DTCN.

CI) 0 IMP

0) INVC AdVI Figure 8. DMAI Burst Mode Request Timing Cr.) S266

r r dVI A 966 OIN OIN

SIA10 dOSS SIA10 I NO

INV £ 0021d02J 3 co co o. CA) DIRECTMEM ORY ACCESS INTERFACE(DMAI ) (.1) 5 cp 3

) DMAI CYCLES

\ A

\ 4 ARBITRATION OTHER MASTER DMAI CYCLES Figure 9. DMAI Cycle Steal Mode Request Timing Figure 9. DMAI Cycle Steal Mode Request Timing DEAD

NON DMAI ED H

CLK BUS BRN BGN DTCN AEON ACKN CYCLES NOTE: BGACKN 1. In order to keep the bus, REQN rnust come no later than the 112 clock poor to assertion edge of DTCN. 1. In order to keep the bus, REQN rnust come no later than the 112 MICROPROCESSOR DIVISION JANUARY 1983

DIRECT MEMORY ACCESS INTERFACE (DMAI) SCB68430

Preliminary

CLK

BGACKN

44 C) ASN 1

UDSN p

LDSN

RWN

61 OWNN r

t g h- H Ho Al -A23 t H 46 ACKN

DTACKN

C) RDYN

DTCN

49 56 57 DONEN (OUT)

58 59 DONEN (IN)

Figure 10. Read from Memory, Write to Device

NOTE: 1. 16-bit transfer illustrated. For 8-bit transfer either LDSN or UDSN, but not both, will be asserted each cycle, depending on byte address.

4.148 Signetics MICROPROCESSOR DIVISION JANUARY 1983 DIRECT MEMORY ACCESS INTERFACE (DMAI) SCB68430

Preliminary

CLK

EIGACKN 4 —10 ASN /-1 44 UDSN 1 0 LDSN t p 0

RWN

OWNN tt g _o Al -A23 j 1-0 ACKN

46 DTACKN 1 / 48 r 52 ROYN --

DTCN

iF--1° 49 - 56 57 DONEN (OUT) -I I ' t C 59 DONEN (IN)

Figure 11. Write to Memory, Read from Device

NOTE: 1. 16-bit transfer illustrated. For 8-bit transfer either LDSN or UDSN, but not both, will be asserted each cycle, depending on byte address.

Signetics 4.149

MICROPROCESSOR DIVISION JANUARY 1983 DIRECT MEMORY ACCESS INTERFACE (DMAI) SCB68430

Preliminary

CLK

BGACKN

ASN

UDSN

LDSN

RWN

OWNN

-Ho Al-A23

ACKN

DTACKN

RDYN

DTCN

RERUNN

Figure 12. Rerun Asserted During Read from Memory, Write to Device

NOTES: 1. 18-bit transfer Illustrated. For 8-bit transfer either LDSN or UDSN, but not both, will be asserted each cycle, depending on byte address. 2. DMAI will release the bus after a RERUNN if there is no valid request. The next request will then retry the cycle which was terminated by the RERUNN signal. 3. RERUNN must be asserted no later than DTACKN and RDYN. 4. If a cycle is terminated by RERUNN, the transfer count will be one less than the actual data transferred correctly. The double RERUNN signal on the same cycle will terminate the DMAI operation with a status bit set and an interrupt generated (if enabled).

4.150 Signetics MICROPROCESSOR DIVISION JANUARY 1983 MEMORY MANAGEMENT UNIT SCN68451

PRODUCT BRIEF, contact your Signetics sales offices for complete information.

DESCRIPTION FEATURES FUNCTIONAL DIAGRAM The SCN68451 Memory Management Unit • Separates address spaces of system (MMU) provides address translation and and user resources protection of the 16-megabyte addressing • Provides write protection AB-A23 space of the SCN68000. The MMU can be • Increases system reliability accessed by any potential bus master, • Provides efficient memory allocation such as instruction set processors, or Al -A5 DMA controllers. Each bus master (or pro- • Allows interprocess communication cessor) in the SCN68000 family provides a through shared resources lftg) function code and an address during each • Simplifies programming model of ad- -4 r. I MEMORY MANAGEMENT bus cycle. The function code specifies an dress space 0 UNIT CONTROL address space while the address specifies • Minimizes operating system overhead a- --S- a location within that address space. The with quick context switches AS function codes are provided by the • 32 segments with variable segment UDS— SCN68000 to distinguish between program MULTIPLEXER sizes LDS I. I CONTROL and data spaces as well as supervisor and SCN68451 user spaces. This separation of address • Multiple MMU system capability DTACK spaces provides the basis of protection in • Supports both paging and segmentation IRO -4— an operating system. By simplifying the • DMA compatible GLOBAL programming model of the address space, • Provides virtual memory support IACK —1.- -4-0- HANDSHAKE the MMU also increases the reliability of a LINES • SCN68000 bus compatible complex multiprocess system. BERR

RESET --I.- FCO CLK FC1 MAPPING LOGICAL SEGMENTS TO PHYSICAL MEMORY 0- FC2 0-FC3

A READ SHARED ONLY DATA

READ A ONLY PROGRAM A

READ/ A SHARED WRITE STACK DATA

UNDEFINED

READ B A ONLY PROGRAM

B READ SHARED ONLY B DATA

UNDEFINED READ1 WRITE STACK B

READI B PHYSICAL WRITE DATA MEMORY

LOGICAL ADDRESS SPACE

Signetics 4.151

MICROPROCESSOR DIVISION JANUARY 1983 INTELLIGENT MULTIPLE DISK CONTROLLER (IMDC) SCN68454

PRODUCT BRIEF, contact your Signetics sales office for complete information. DESCRIPTION IMDC FUNCTIONAL PIN DIAGRAM The SCN68454 Intelligent Multiple Disk Controller (IMDC) is a single chip MOS- VLSI device capable of simultaneously DO-D15 ENO controlling up to four Winchester type BRN I ENI hard disk drives or floppy disk drives in BON UAS any combination. Advanced hardware and BGACKN • LAS software features make it ideally suited to IRON • perform disk drive control functions in IACKN single processor, multi-processor and/or RIWN multiprocessing systems. DTACKN LUSH UDSN SCN68454 The IMDC structure utilizes two IMDC sophisticated processing interfaces—a ASN A1,A2 host interface and a disk drive interface. CSN REDAT The host interface is compatible with the LOCAL -4 SECTOR/INDEX S68000 bus. Included in this interface is a DDIR WRGATE complete DMA controller capable of OWNX WRCLOCKIRCLOCK handling all data transfers between the RERUN WRDAT host system memory and the drives con- RESN WRCLK nected to the IMDC. The disk drive inter- SCLK TICKLER face is designed to conform to different Vcc drive interface requirements, thus giving GND the IMDC the ability to control a variety of drive types. With a minimum of external hardware, it can control any drive that has an SA1000 or Seagate ST500 drive interface standard. The IMDC also provides • Supports computer generated error direct support for double density track for- FEATURES • Combined control for hard disk and correction code mats and standard IBM track formats for floppy disk • Control signals for external phase floppy disks. — Any combination up to 4 drives locked loop • Data rate up to 10Mbits per second Data transfers on the host data bus can be — Built-in logic for floppy disk back-up • Automatic bad sector handling programmed for either 8 or 16-bit parallel • Winchester disk interface (SA1000 and • Single phase read and write clocks operation. The disk drive interface handles ST500) • 8/16-bit data bus a serial data rate up to 10Mbits per sec- • Supports MFM, FM and NRZ data for- • DMA control and transfer ond, a speed which accommodates the mats • High level commands next generation of drives. • Soft sector and hard sector • Supports programmable hard disk and — Controls — Data transfer Programming of the IMDC is performed standard IBM formats — Programmable real time record pro- through a powerful set of high level in- • Supports linked, mapped and sequen- cessing structions. A user can create the required tial file structures — Diagnostics drive interface by simply altering the con- • Multiple sector read/write — Error correction tent of drive control memory storage • Implied seek areas. Included in the instruction set are • Error correction up to 11 bits commands to format disks to user • 32-bit and 40-bit ECC codes, program. specification, multiple sector read/write mable polynomials operations with implied seeks, diagnostics, and programmable real time record processing.

The IMDC circuitry is fully TTL compatible, operates with a single + 5 volt power supply and is contained in a 48 pin DIP package.

4.152 Signetics MICROPROCESSOR DIVISION JANUARY 1983 DISK PHASE LOCKED LOOP (DPLL) SCB68459

PRODUCT BRIEF, contact your Signetics sales office for complete information.

DESCRIPTION The VCO is a programmable oscillator pro- FEATURES The SCB68459 Disk Phase Locked Loop grammed via the use of an external • On chip multiplexer for read/write data (DPLL) is a single chip bipolar digital/ capacitor. It functions as a current to fre- and free•running clock analog circuit designed for hard disk and quency converter (or voltage to frequency • Circuit operates from a single +5V floppy disk applications. This circuit of- converter). The VCO provides a read/ supply fers high performance and reliability un- write clock to the SCN68454 IMDC. • Supports composite data rate of 20MHz matched by discrete design. It is ideally The prescaler is a divider. If FM modula- • Loop filter bandwidth of 2MHz suited for use with the SCN68454 Intelli- tion is used, the divider performs divide by • Supports MFM and FM modulation gent Multiple Disk Controller (IMDC). 2; if MFM then divide by 1. The prescaler • Phase detector with output presents the reference frequency — TTL inputs The SCB68459 DPLL operates by producing to the phase detector. — 50% duty cycle for inputs an oscillator frequency to match the fre- — Adjustable gain quency of an input signal f,. In this locked The data regenerator's main function is to — No phase reversal at inputs condition, any slight change in f, (jitter) clean up the jittery input signals before — Capture range not to exceed lock first appears as a change in phase be- delivering it to the precompensation cir- range tween f, and the oscillator frequency. This cuit. • Voltage•controlled•oscillator with phase shift then acts as an error signal to The precompensation circuit will advance — Programmable oscillator change the frequency of the local DPLL or delay the pulse train before writing onto — Fast slew rate oscillator to match f,. the disk in the form of composite data. — Minimum drift due to temperature The precompensating algorithm is pro- — Minimum phase jitter The DPLL architecture utilizes two inter- grammed onto the chip. — Buffered output faces—a controller interface and a disk When the DPLL is used with the • Electrical isolation between digital drive interface. Included in the controller SCN68454 IMDC, the clock and data logic and high frequency analog circuit interface are data (read/write), clock (read/ • TTL compatible inputs and outputs write), tickler (for internal multiplexing separation and address mark detection are actually performed by the IMDC. • External loop gain control control) and other control signals. These interface signals are connected directly to/from the SCN68454 IMDC. On the other hand, the disk interface consists of FUNCTIONAL PIN DIAGRAM primarily the data (read and write) and other control signals depending on disk type.

For each disk type (i.e. SA1000 Win- chester, or floppy disk), one DPLL circuit can be used to support up to four drives. If a Winchester disk and a floppy disk are used, two DPLL circuits are required. WRDAT -4-- XTAL1 The architecture of the DPLL is basically a WRCLK --0.- XTAL2 feedback system comprised of the follow- REDAT -4— ing: RCLOCKIWCLOCK - EARLY DATA 4— NOMINAL SIGNAL • Phase detector (comparator) TICKLER CEN LATE SIGNAL • Low pass filter and error amplifier PRECOMP EN —as- • Voltage controlled oscillator (VCO) PRESCALEN —► WRITE DATA • Prescaler (or divider) READ DATA • Data regenerator Vcc • Precompensation circuit GND --4, VCO IN ► PUMP DOWN The phase detector compares the phase —4- PUMP UP and frequency of the incoming signal with - FRED PUMP the VCO frequency and generates an error CAP1 voltage that is related to the phase and fre- - CAP2 quency difference between the two CENTER FRED signals.

The low pass filter serves a dual function: first, by attenuating the high frequency error components at the output of the phase comparator, it enhances the interference rejection characteristics; second, it provides a short-term memory for the PLL and ensures a rapid recapture of the signal.

Signetics 4.153 MICROPROCESSOR DIVISION JANUARY 1983

DUAL UNIVERSAL SERIAL COMMUNICATIONS CONTROLLER SCN68562

PRODUCT BRIEF, contact your Signetics sales office for complete information.

DESCRIPTION DUSCC FUNCTIONAL PINOUT The Signetics SCN68562 Dual Universal Serial Communications Controller (DUSCC) is a single chip MOS-LSI communications device that provides two in- RXDA dependent, multi-protocol, full duplex DO D7 ► TX DA receiver/transmitter channels in a single Al A6 ► TRXCA package. The DUSCC supports bit R/WN RTXCA oriented and character oriented (byte DTACKN 4 r CTSANILCAN count and byte control) synchronous data CSN DCDAN/SYNINA RESET RTXDROAN/GP01 AN link controls as well as asynchronous pro- SCN68562 IRON DUSCC ► TXDROAN/GPO2AN/RTSAN tocols. The logic for both channels pro- IACKN vides formats, synchronization, and vali- RXDB TXDB dation for data transferred to and from the X1 /CLK TRXCB channel interface. X2/I DCN At ► RTXC B vcc CTSBN/LCBN The SCN68652 interfaces to the SCN68000 GND 4 DC DBN/SYNINB MPU via asynchronous bus control sig- RTXDROBN/GPO1BN nals and is capable of program polled, in- TXDROBN/GPO2BNIRTSBN terrupt driven, or DMA data transfers. RTXDAKAN/GPI1AN Each channel of the DUSCC consists of a RTXDAKBNIGPII BN receiver, a transmitter, a. 16-bit multi- TX DAKAN/G PI2AN 48-PIN TXDAKBN/GPI2BN function counter/timer, a digital phase VERSION ONLY DTCN locked loop (DPLL), a parity/CRC gen- DON EN erator and checker, and associated con- SYNOUTAN/RTSAN trol circuits. The operating mode and data SYNOUTBN/RTSBN format of each channel can be programmed independently. The two channels share a common bit rate generator (BRG), operating directly from a crystal or an external clock, which provides sixteen common bit rates simultaneously. The address), transmitter parameter and tim- FEATURES receiver and transmitter of each channel ing registers, receiver parameter and tim- can independently select its operating ing registers, two counter/timer preset General Features rate from the BRG, the DPLL, the registers, two counter/timer value • Dual full-duplex synchronouslasyn- counter/timer, or from an external 1x or registers, counter/timer control register, chronous receiver and transmitter 16x clock, making the DUSCC well suited output and miscellaneous register, pin • Multi-protocol operation for dual speed channel applications. configuration register, channel command — BOP: HDLC/ADCCP, SDLC, SDLC register, TxFIFO, RxFIFO, three status loop, X.25 or X.75 link level, etc. The transmitter and receiver each contain registers, and interrupt enable and priority — COP: BISYNC, DDCMP, X.21 a four-deep FIFO with appended com- registers. — ASYNC: 5.8 bits plus parity mand and status bits and a shift register. • Four character receiver and transmitter This permits reading and writing of up to Associated with the logic for both chan- FIFOs four characters at a time, minimizing the nels is an interrupt control register and a • Programmable bit rate for each , potential of receiver overrun or transmitter general status register that can be read receiver and transmitter selectable underrun, and reducing interrupt or DMA through either channel. A modified vector from: overhead. In addition, a flow control register, read through channel B, contains — 16 fixed rates: 50 to 38.4K baud capability is provided to disable a remote the programmed interrupt vector with — One user defined rate derived from transmitter when the FIFO of the local three bits of prioritized encoded status in- programmable counter/timer receiving device is full. serted. An unmodified vector register, — External lx or 16x clock read through channel A, contains the vec- — Digital phase locked loop Two modem control inputs (DCD and CTS) tor as programmed. The vector is pro- • Parity and FCS (LRC or CRC) genera- are monitored by the control logic and grammed by writing to the vector register tion and checking three modem control outputs (RTS and through channel A or B and can be pro- • Programmable data encoding/ two general purpose) are controlled by the grammed to be output on the data bus in decoding: NRZ, NRZI, FMO, FM1, Man- CPU. All of the modem control inputs and response to receipt of an interrupt chester outputs are general purpose in nature and acknowledge cycle. • Programmable channel mode: full/half optionally can be used for functions other duplex, autoecho, or local loopback than modem control. There are two versions of the DUSCC. The • Programmable data transfer mode: standard version is packaged in a 48-pin polled, interrupt, DMA, wait The register set for each channel includes DIP. A 40-pin version provides all of the • DMA interface two mode registers, two SYN registers features, but is limited to dual-address — Compatible with S68000 DMA (also used for the BOP secondary transfers during DMA operation. controllers 4.154 Signetics MICROPROCESSOR DIVISION JANUARY 1983 DUAL UNIVERSAL SERIAL COMMUNICATIONS CONTROLLER SCN68562

— Half or full duplex operation Up to two stop bits programmable in • Parity, FCS, overrun, and underrun er- — Single or dual address data 1/16 bit increments ror detection transfers lx or 16x Rx and Tx clock factors — Automatic frame termination on Parity, overrun, and framing error Bit Oriented Protocol Features terminal count or DMA 'DONE' detection • Character length: 5 to 8 bits with 0 to 7 • Interrupt capabilities False start bit detection bits residual character — Interrupt daisy chain option Start bit search 1/2 bit time after fram- • Detection of received residual — Interrupt vector output (fixed or ing error detection character: 0.7 bits modified by status) Break generation with handshake for • Automatic switch to programmed — Programmable internal priorities counting break characters character length for I field — 68K, 8080185, and 8086/88 compati- Detection of start and end of received • Zero insertion and deletion ble modes break • Optional opening PAD transmission at • Multi-function programmable 16-bit • Character compare with optional inter- beginning of frame counter/timer rupt • Detection and generation of FLAG, — Bit rate generator ABORT, and IDLE bit patterns — Event counter Character Oriented Protocol • Detection and generation of shared — Count characters received or Features (single) FLAG between frames transmitted • Character length: 5 to 8 bits • Detection of overlapping (shared zero) — Delay generator • Odd or even parity, no parity, or force FLAGs — Automatic bit length measurement parity • ABORT, ABORT-FLAGs, or FCS-FLAGs • Modem controls • LRC or CRC generation and checking line fill on underrun — RTS, CTS, DCD, and up to four • • Optional opening PAD transmission at Idle in MARK or FLAGs general purpose I/O pins per chan- beginning of frame • Secondary address recognition in- nel • Optional auto hunt mode and closing cluding group and global address — CTS and DCD are programmable PAD check after EOT or NAK • Single or dual octet secondary address auto-enables for Tx and Rx • One or two SYN characters • Extended address and control fields — Programmable interrupt on change • External sync capability • Short frame rejection for receiver of CTS or DCD • • SYN detection and optional stripping Detection and notification of received • On-chip oscillator for crystal (all or leading SYNs only) end of message • TTL compatible • • SYN or MARK linef ill on underrun CRC generation and checking • Single + 5V power supply • Idle in MARK or SYNs • SDLC loop mode capability • 40/48-pin DIP • Handling of EBCDIC and ASCII Asynchronous Mode Features BISYNC text messages, including CRC generation, SYN and DLE stripping, • Character length: 5 to 8 bits end-of-message detection, and trans- • Odd or even parity, no parity, or force parent mode switching. Automatic in parity receive and semi-automatic in transmit

Signetics 4.155 MICROPROCESSOR DIVISION JANUARY 1983 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN68681

Preliminary

DESCRIPTION FEATURES PIN CONFIGURATION The Signetics SCN68681 Dual Univer- S68000 bus compatible sal Asynchronous Receiver/Transmitter Dual full-duplex asynchronous receiver/ (DUART) is a single chip MOS-LSI commu- transmiter nications device that provides two inde- Quadruple buffered receiver data regis- Al `/cc pendent full-duplex asynchronous ters W3 W4 receiver/transmitter channels in a single Programmable data format A2 W5 package. It is compatible with other —5 to 8 data bits plus parity S68000 family devices, and can also inter- IP1 MCKN —Odd, even, no parity or force parity face easily with other microprocessors. —1, 1.5 or 2 stop bits programmable in A3 W2 The DUART can be used in polled or inter- 1/16 bit increments A4 CSN rupt driven systems. Programmable baud rate for each re- MO RESETN The operating mode and data format of ceiver and transmiter selectable from: RIWN X2 each channel can be programmed inde- —18 fixed rates: 50 to 38.4K baud pendently. Additionally, each receiver and —One user defined rate derived from DTACKN Xl/CLK transmitter can select its operating speed programmable timer/counter RxD15 RxDA as one of eighteen fixed baud rates, a 16x —External lx or 16x clock TxDB TxDA clock derived from a programmable Parity, framing, and overrun error detec- OP1 OPO counter/timer, or an external lx or 16x tion clock. The baud rate generator and OP3 OP2 False start bit detection counter/timer can operate directly from a OP5 OP4 crystal or from external clock inputs. The Line break detection and generation OP7 OP6 ability to independently program the Programmable channel mode operating speed of the receiver and trans- —Normal (full duplex) 01 DO mitter make the DUART particularly attrac- —Automatic echo 03 D2 tive for dual-speed channel applications —Local loopback 05 D4 such as clustered terminal systems. —Remote loopback D7 D6 Each receiver is quadruply buffered to • Multi-function programmable 16-bit minimize the potential of receiver overrun counterltimer GND INTRN or to reduce interrupt overhead in inter- • Multi-function 6-bit input port TOP VIEW rupt driven systems. In addition, a flow —Can serve as clock or control inputs control capability is provided to disable a —Change of state detection on four remote DUART transmitter when the buf- inputs fer of the receiving device is full. • Multi-function 8-bit output port —Output port can be configured to pro- —Individual bit setlreset capability vide a total of up to six separate wire- Also provided on the SCN68681 are a mul- OR'able interrupt outputs tipurpose 6-bit input port and a multipur- —Outputs can be programmed to be pose 8-bit output port. These can be used status/interrupt signals • Maximum data transfer: 1X — 1MB/sec, as general purpose I/O ports or can be • Versatile interrupt system 16X — 125KB/sec assigned specific functions (such as clock —Single interrupt output with eight • Automatic wake-up mode for multidrop inputs or status/interrupt outputs) under maskable interrupting conditions applications program control. — Interrupt vector output on interrupt • Start-end break interruptIstatus acknowledge • Detects break which originates in the middle of a character • On-chip crystal oscillator • TTL compatible • Single + 5V power supply

ORDERING CODE PACKAGES Vcc=SV ± 5%, TA = 0°C tO 70°C Ceramic DIP SCN68681C1140 Plastic DIP SCN68681C1N40

4.156 Signetics MICROPROCESSOR DIVISION JANUARY 1983

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN68681

Preliminary

BLOCK DIAGRAM

DO-D7 BUS BUFFER CHANNEL A

TRANSMIT HOLDING REG Tx DA TRANSMIT SHIFT REGISTER OPERATION RIWN CONTROL RECEIVE DTACKN HOLDING REG ADDRESS 131 CSN DECODE RxDA RECEIVE Al-A4 SHIFT REG R/W CONTROL RESETN MRA1,2

CRA

SRA

INTERRUPT CONTROL TxDB INTRN CHANNEL B IMR (AS ABOVE) RxDB ISR

IACKN IVR

INPUT PORT

CHANGE OF STATE TIMING DETECTORS (4) IPO IP6 17- CONTROL BAUD RATE cc GENERATOR IPCR

ACR

CLOCK SELECTORS OUTPUT PORT

COUNTER/ FUNCTION TIMER SELECT LOGIC 8 OPO-OP7

X1/CLK XTAL OSC OPCR X2 OPR

CSRA

CSRB VCC

ACR GND CTUR

CTLR

Signetics 4.157 MICROPROCESSOR DIVISION JANUARY 1983 DUAL ASYNCHRONOUS RECEIVERITRANSMITTER (DUART) SCN68681

Preliminary

PIN DESIGNATION MNEMONIC PIN NO. TYPE NAME AND FUNCTION DO-D7 25-22, 16-19 I/O Data Bus: Bidirectional 3-state data bus used to transfer commands, data and status between the DUART and the CPU. DO is the least significant bit. CSN 35 I Chip Select: Active low input signal. When low, data transfers between the CPU and the DUART are enabled on DO-D7 as controlled by the R/WN and A1-A4 inputs. When high, places the DO-D7 lines in the 3-state condition. RIWN 8 I Read/Write: A high input indicates a read cycle and a low input indicates a write cycle, when a cycle is initiated by assertion of the CSN input. A1-A4 1, 3, 5, 6 I Address Inputs: Select the DUART internal registers and ports for read/write operations. RESETN 34 I Reset: A low clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), initializes the IVR to hex OF, puts OPO-OP7 in the high state, stops the counter/timer, and puts channel A and B in the inactive state, with the TxDA and TxDB outputs in the mark (high) state. DTACKN 9 0 Data Transfer Acknowledge: Three-state active low output asserted in write, read, or interrupt cycles to indicate proper transfer of data between the CPU and the DUART. INTRN 21 0 Interrupt Request: Active low, open drain output which signals the CPU that one or more of the eight maskable interrupting conditions are true. IACKN 37 I Interrupt Acknowledge: Active low input indicating an interrupt acknowledge cycle. In response, the DUART will place the interrupt vector on the data bus and will assert DTACKN if it has an interrupt pending. X1/CLK 32 I Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be supplied at all times. If a crystal is used, a capacitor must be connected from this pin to ground (see figure 7). X2 33 I Crystal 2: Connection for other side of the crystal. Should be connected to ground if a crystal is not used. If a crystal is used, a capacitor must be connected from this pin to ground (see figure 7). RxDA 31 I Channel A Receiver Serial Data Input: The least significant bit is received first. 'Mark' is high, 'space' is low. RxDB 10 I Channel B Receiver Serial Data Input: The least significant bit is received first. 'Mark' is high, 'space' is low. TxDA 30 0 Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the 'mark' condition when the transmitter is disabled, idle, or when operating in local loopback mode. 'Mark' is high, 'space' is low. TxDB 11 0 Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the 'mark' condition when the transmitter is disabled, idle, or when operating in local loopback mode. 'Mark' is high, 'space' is low. OPO 29 0 Output 0. General purpose output, or channel A request to send (RTSAN, active low). Can be deactivated automatically on receive or transmit. OP1 12 0 Output 1: General purpose output, or channel B request to send (RTSBN, active low). Can be deactivated automatically on receive or transmit. OP2 28 0 Output 2: General purpose output, or channel A transmitter lx or 16X clock output, or channel A receiver 1X clock output. OP3 13 0 Output 3: General purpose output, or open drain, active low counter/timer output, or channel B transmitter 1X clock output, or channel B receiver 1X clock output. OP4 27 0 Output 4: General purpose output, or channel A open drain, active low, RxRDYA/FFULLA output.

4.158 Signetics MICROPROCESSOR DIVISION JANUARY 1983 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN68681

Preliminary

PIN DESIGNATION (Continued) MNEMONIC PIN NO. TYPE NAME AND FUNCTION OP5 14 0 Output 5: General purpose output, or channel B open drain, active low, RxRDYB/FFULLB output. OP6 26 0 Output 6: General purpose output, or channel A open drain, active low, TxRDYA output. OP7 15 0 Output 7: General purpose output, or channel B open drain, active low, TxRDYB output. IPO 7 I Input 0: General purpose input, or channel A clear to send active low input (CTSAN). IP1 4 I Input 1: General purpose input, or channel B clear to send active low input (CTSBN). IP2 36 I Input 2: General purpose input, or channel B receiver external clock input (RxCB), or counter/timer external clock input. When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. IP3 2 I Input 3: General purpose input, or channel A transmitter external clock input (TxCA). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. IP4 39 I Input 4: General purpose input, or channel A receiver external clock input (RxCA). When the external clock is used by the receiver, the received data is sampled on the rising edge of the clock. IP5 38 I Input 5: General purpose input, or channel B transmitter external clock input (TxCB). When the external clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Vcc 40 I Power Supply: + 5V supply input. GND 20 I Ground

BLOCK DIAGRAM Interrupt Control ate frequency is available, it may be connected to X1/CLK. The clock serves as the A single active low interrupt output The SCN68681 DUART consists of the fol- basic timing reference for the baud rate (INTRN) is provided which is activated lowing eight major sections: data bus buf- generator (BRG), the counter/timer, and upon the occurrence of any of eight inter- fer, operation control, interrupt control, other internal circuits. A clock signal nal events. Associated with the interrupt timing, communications channels A and within the limits specified in the specifica- system are the interrupt mask register B, input port and output port. Refer to the tions section of this data sheet must (IMR), the interrupt status register (ISR), block diagram. always be supplied to the DUART. the auxiliary control register (ACR), and the interrupt vector register (IVR). The IMR The baud rate generator operates from the Data Bus Buffer may be programmed to select only certain oscillator or external clock input and is conditions to cause INTRN to be asserted. capable of generating 18 commonly used The data bus buffer provides the interface The ISR can be read by the CPU to deter- data communications baud rates ranging between the external and internal data mine all currently active interrupting con- from 50 to 38.4K baud. The clock outputs busses. It is controlled by the operation ditions. When IACKN is asserted, and the from the BRG are at 16X the actual baud control block to allow read and write DUART has an interrupt pending, the rate. The counter/timer can be used as a operations to take place between the con- DUART responds by placing the contents timer to produce a 16X clock for any other trolling CPU and the DUART. of the IVR register on the data bus and baud rate by counting down the crystal asserting DTACKN. clock or an external clock. The four clock selectors allow the independent selection, Operation Control Outputs OP3-0P7 can be programmed to for each receiver and transmitter, of any of these baud rates or an external timing sig- The operation control logic receives provide discrete interrupt outputs for the operation commands from the CPU and transmitters, receivers, and counter/timer. nal. generates appropriate signals to internal The counter/timer (C/T) can be program- sections to control device operation. It med to use one of several timing sources Timing Circuits contains address decoding and read and as its input. The output of the C/T is avail- write circuits to permit communications The timing block consists of a crystal able to the clock selectors and can also be with the microprocessor via the data bus oscillator, a baud rate generator, a pro- programmed to be output at OP3. In the buffer. The DTACKN output is asserted grammable 16-bit counter/timer, and four counter mode, the contents of the C/T can during write and read cycles to indicate to clock selectors. The crystal oscillator be read by the CPU and it can be stopped the CPU that data has been latched on a operates directly from a 3.6864MHz crys- and started under program control. In the write cycle, or that valid data is present on tal connected across the X1/CLK and X2 timer mode, the C/T acts as a program- the bus on a read cycle. inputs. If an external clock of the appropri- mable divider.

Signetics 4.159 MICROPROCESSOR DIVISION JANUARY 1983 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN68681

Preliminary

Communications Channels OPERATION Receiver A and B Transmitter The SCN68681 is conditioned to receive Each communications channel of the data when enabled through the command SCN68681 comprises a full duplex asyn- The SCN68681 is conditioned to transmit register. The receiver looks for a high to chronous receiver/transmitter (UART). The data when the transmitter is enabled low (mark to space) transition of the start operating frequency for each receiver and through the command register. The bit on the RxD input pin. If a transition is transmitter can be selected independently SCN68681 indicates to the CPU that it is detected, the state of the RxD pin is sam- from the baud rate generator, the counter ready to accept a character by setting the pled each 16X clock for 7-1/2 clocks (16X timer, or from an external input. TxRDY bit in the status register. This con- clock mode) or at the next rising edge of dition can be programmed to generate an the bit time clock (1X clock mode). If RxD The transmitter accepts parallel data from interrupt request at OP6 or OP7 and is sampled high, the start bit is invalid and the CPU, converts it to a serial bit stream, INTRN. When a character is loaded into the search for a valid start bit begins inserts the appropriate start, stop, and op- the transmit holding register (THR), the again. If RxD is still low, a valid start bit is tional parity bits and outputs a composite above conditions are negated. Data is assumed and the receiver continues to serial stream of data on the TxD output transferred from the holding register to sample the input at one bit time intervals pin. The receiver accepts serial data on the transmit shift register when it is idle or at the theoretical center of the bit, until the RxD pin, converts this serial input to has completed transmission of the previ- the proper number of data bits and the parallel format, checks for start bit, stop ous character. The TxRDY conditions are parity bit (if any) have been assembled, bit, parity bit (if any), or break condition then asserted again which means one full and one stop bit has been detected. The and sends an assembled character to the character time of buffering is provided. least sigificant bit is received first. The CPU. Characters cannot be loaded into the THR data is then transferred to the receive Input Port while the transmitter is disabled. holding register (RHR) and the RxRDY bit The inputs to this unlatched 6-bit port can The transmitter converts the parallel data in the SR is set to a 1. This condition can be read by the CPU by performing a read from the CPU to a serial bit stream on the be programmed to generate an interrupt at operation at address D16. A high input re- TxD output pin. It automatically sends a OP4 or OP5 and INTRN. If the character sults in a logic 1 while a low input results start bit followed by the programmed length is less than eight bits, the most in a logic 0. D7 will always be read as a number of data bits, an optional parity bit, significant unused bits in the RHR are set logic 1 and D6 will reflect the level of and the programmed number of stop bits. to zero. IACKN. The pins of this port can also The least significant bit is sent first. Fol- After the stop bit is detected, the receiver serve as auxiliary inputs to certain por- lowing the transmission of the stop bits, if will immediately look for the next start bit. tions of the DUART logic. a new character is not available in the However, if a non-zero character was re- Four change-of-state detectors are pro- THR, the TxD output remains high and the ceived without a stop bit (framing error) vided which are associated with inputs TxEMT bit in the status register (SR) will and RxD remains low for one half of the bit IP3, IP2, IP1, and IPO. A high-to-low or low- be set to 1. Transmission resumes and the period after the stop bit was sampled, to-high transition of these inputs lasting TxEMT bit is cleared when the CPU loads a then the receiver operates as if a new start longer than 25-50µs will set the corre- new character into the THR. If the trans- bit transition had been detected at that sponding bit in the input port change reg- mitter is disabled, it continues operating point (one-half bit time after the stop bit ister. The bits are cleared when the regis- until the character currently being trans- was sampled). ter is read by the CPU. Any change of state mitted is completely sent out. The trans- The parity error, framing error, overrun er- can also be programmed to generate an in- mitter can be forced to send a continuous ror and received break state (if any) are terrupt to the CPU. low condition by issuing a send break strobed into the SR at the received charac- command. Output Port ter boundary, before the RxRDY status bit The transmitter can be reset through a is set. If a break condition is detected The 8-bit multi-purpose output port can be software command. If it is reset, operation (RxD is low for the entire character in- used as a general purpose output port, in ceases immediately and the transmitter cluding the stop bit), a character con- which case the outputs are the comple- must be enabled through the command sisting of all zeros will be loaded into the ments of the output port register (OPR). register before resuming operation. If CTS RHR and the received break bit in the SR OPR[n] = 1 results in OP[n]= low and vice- operation is enabled, the CTSN input must is set to 1. The RxD input must return to a versa. Bits of the OPR can be individually be low in order for the character to be high condition for at least one-half bit time set and reset. A bit is set by performing a transmitted. if it goes high in the middle of before a search for the next start bit write operation at address E16 with the ac- a transmission, the character in the shift begins. companying data specifying the bits to be register is transmitted and TxDA then re- The RHR consists of a first-in-first-out set (1 = set, 0= no change). Likewise, a bit mains in the marking state until CTSN (FIFO) stack with a capacity of three char- is reset by a write at address F16 with the goes low. The transmitter can also control acters. Data is loaded from the receive accompanying data specifying the bits to the deactivation of the RTSN output. If shift register into the topmost empty posi- be reset (1 = reset, 0= no change). programmed, the RTSN output will be re- tion of the FIFO. The RxRDY bit in the Outputs can be also individually assigned set one bit time after the character in the status register is set whenever one or specific functions by appropriate pro- transmit shift register and transmit hold- more characters are available to be read, gramming of the channel A mode registers ing register (if any) are completely trans- and a FFULL status bit is set if all three (MR1A, MR2A), the channel B mode regis- mitted, if the transmitter has been dis- stack positions are filled with data. Either ters (MR1B, MR2B), and the output port abled. of these bits can be selected to cause an configuration register (OPCR). interrupt. A read of the RHR outputs the

4.160 Signetics MICROPROCESSOR DIVISION JANUARY 1983 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN68681

Preliminary

data at the top of the FIFO. After the read 'slave' station. The slave stations, with PROGRAMMING cycle, the data FIFO and its associated receivers that are normally disabled, ex- status bits (see below) are 'popped' thus amine the received data stream and 'wake- The operation of the DUART is program- emptying a FIFO position for new data. up' the CPU (by setting RxRDY) only upon med by writing control words into the ap- receipt of an address character. The CPU propriate registers. Operational feedback In addition to the data word, three status is provided via status registers which can bits (parity error, framing error, and re- compares the received address to its station address and enables the receiver if it be read by the CPU. The addressing of the ceived break) are also appended to each registers is described in table 1. data character in the FIFO (overrun is not). wishes to receive the subsequent data characters. Upon receipt of another ad- Status can be provided in two ways, as The contents of certain control registers dress character, the CPU may disable the programmed by the error mode control bit are initialized to zero on RESET. Care receiver to initiate the process again. in the mode register. In the 'character' should be exercised if the contents of a mode, status is provided on a character- A transmitted character consists of a start register are changed during operation, by-character basis: the status applies only bit, the programmed number of data bits, since certain changes may cause opera- to the character at the top of the FIFO. In an address/data (A/D) bit, and the pro- tional problems. For example, changing the 'block' mode, the status provided in grammed number of stop bits. The polarity the number of bits per character while the the SR for these three bits is the logical of the transmitted A/D bit is selected by transmitter is active may cause the trans- 4 OR of the status for all characters coming the CPU by programming bit MR1A[2]/ mission of an incorrect character. In gen- to the top of the FIFO since the last 'reset MR1 B[2]. MR1A[2]/MR1 B[2) = 0 transmits a eral, the contents of the MR, the CSR, and error' command was issued. In either zero in the A/D bit position, which iden- the OPCR should only be changed while mode reading the SR does not affect the tifies the corresponding data bits as data, the receiver(s) and transmitter(s) are not FIFO. The FIFO is 'popped' only when the while MR1A[2]/MR113[2]. 1 transmits a enabled, and certain changes to the ACR RHR is read. Therefore the status register one in the A/D bit position, which identi- should only be made while the CIT is should be read prior to reading the FIFO. fies the corresponding data bits as an ad- stopped. dress. The CPU should program the mode If the FIFO is full when a new character is Mode registers 1 and 2 of each channel are received, that character is held in the re- register prior to loading the corresponding data bits into the THR. accessed via independent auxiliary point- ceive shift register until a FIFO position is ers. The pointer is set to MR1x by RESET available. If an additional character is re- In this mode, the receiver continuously or by issuing a 'reset pointer' command ceived while this state exits, the contents looks at the received data stream, whether via the corresponding command register. of the FIFO are not affected: the character it is enabled or disabled. If disabled, it Any read or write of the mode register previously in the shift register is lost and sets the RxRDY status bit and loads the while the pointer is at MR1x switches the the overrun error status bit (SR[4]) will be character into the RHR FIFO if the re- pointer to MR2x. The pointer then remains set upon receipt of the start bit of the new ceived A/D bit is a one (address tag), but at MR2x, so that subsequent accesses are (overruning) character. discards the received character if the always to MR2x unless the pointer is reset The receiver can control the deactivation received A/D bit is a zero (data tag). If to MR1x as described above. of RTS. If programmed to operate in this enabled, all received characters are transferred to the CPU via the RHR. In either Mode, command, clock select, and status mode, the RTSN output will be negated registers are duplicated for each channel when a valid start bit was received and the case, the data bits are loaded into the data FIFO while the A/D bit is loaded into the to provide total independent operation FIFO is full. When a FIFO position be- and control. Refer to table 2 for register bit comes available, the RTSN output will be status FIFO position normally used for parity error (SRA[5] or SRB[5]). Framing descriptions. re-asserted automatically. This feature error, overrun error, and break detect oper- can be used to prevent an overrun, in the ate normally whether or not the receiver is receiver, by connecting the RTSN output enabled. to the CTSN input of the transmitting device. If the receiver is disabled, the FIFO char- Table 1 68681 REGISTER ADDRESSING acters can be read. However, no additional A4 A3 A2 Al READ (R/WN =1) WRITE (R/WN = 0)

characters can be received until the re O 0 0 0 Mode Register A (MR1A, MR2A) Mode Register A (MR1A, MR2A)

ceiver is enabled again. If the receiver is r 0 reset, the FIFO and all of the receiver 0 0 0 Status Register A (SRA) Clock Select Reg. A (CSRA)

status, and the corresponding output 0 0 1 0 *Reserved* Command Register A (CRA) ports and interrupt are reset. No addi- 0 0 1 RX Holding Register A (RHRA) TX Holding Register A (THRA) tional characters can be received until the 0 1 0 Input Port Change Reg. (IPCR) Aux. Control Register (ACR) 1 O receiver is enabled again. 0 1 0 Interrupt Status Reg. (ISR) Interrupt Mask Reg. (IMR) 0 1 1 Counter/Timer Upper (CTU) CIT Upper Register (CTUR) *-

Multidrop Mode 0 1 1 0 Counter/Timer Lower (CTL) CIT Lower Register (CTLR)

1 0 0 0 The DUART is equipped with a wake up Mode Register B (MR1B, MR2B) Mode Register B (MR1 B, MR2B) mode used for multidrop applications. 1 0 0 Status Register B (SRB) Clock Select Reg. B (CSRB)

1 0 1 This mode is selected by programming *Reserved* Command Register B (CRB) 1 0 1 RX Holding Register B (RHRB) TX Holding Register B (THRB)

bits MR1A[4:3] or MR1B[4:3] to '11' for 0

1 1 0 0 channels A and B respectively. In this Interrupt Vector Reg. (IVR) Interrupt Vector Reg. (IVR) 1 1 0 mode of operation, a 'master' station Input Port Output Port Conf. Reg. (OPCR) 1 1 1 transmits an address character followed Start Counter Command Set Output Port Bits Command 1 1 1 Stop Counter Command by data characters for the addressed Reset Output Port Bits Command Signetics 4.161 MICROPROCESSOR DIVISION JANUARY 1983

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN68681

Preliminary Table 2 REGISTER BIT FORMATS BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO RX RTS RX INT ERROR PARITY PARITY MODE BITS PER CHAR. CONTROL SELECT MODE TYPE

MR1A 0= no 0= RXRDY 0 = char 00 = with parity 0= even 00=5 MR1B 1= yes 1= FFULL 1= block 01= force parity 1= odd 01= 6 10 = no parity 10=7 11 = multi-drop mode 11 = 8

BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO Tx RTS CTS CHANNEL MODE STOP BIT LENGTH* CONTROL ENABLE Tx

MR2A 00= Normal 0= no 0= no 0 = 0.563 4=0.813 8=1.563 C=1.813 M R2B 01= Auto echo 1= yes 1= yes 1=0.625 5=0.875 9=1.625 D= 1.875 10 = Local loop 2=0.688 6 = 0.938 A = 1.688 E= 1.938 11= Remote loop 3=0.750 7=1.000 B = 1.750 F = 2.000 *Add 0.5 to values shown for 0-7 if channel is programmed for 5 bits/char. BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO RECEIVER CLOCK SELECT TRANSMITTER CLOCK SELECT CSRA CSRB See text See text

BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO MISCELLANEOUS COMMANDS DISABLE Tx ENABLE Tx DISABLE Rx ENABLE Rx CRA not used— CRB must be 0 See text 0= no 0= no 0= no 0= no 1= yes 1= yes 1= yes 1= yes

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO RECEIVED FRAMING PARITY OVERRUN TxEMT TxRDY FFULL RxRDY BREAK ERROR ERROR ERROR SRA 0= no 0= no 0= no 0= no 0= no 0= no 0= no 0= no SRB 1= yes 1= yes 1= yes 1= yes 1= yes 1= yes 1= yes 1= yes , .

'These status bits are appended to the corresponding data character in the receive FIFO. A read of the s atus register provides these bits (7:5) from the top of the FIFO together with bits 4:0. These bits are cleared by a 'reset error tatus' command. In character mode they are discarded when the corresponding data character is read from the FIFO. BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO OP7 OP6 OP5 OP4 OP3 OP2 0= OPR[7] 0= OPR[6] 0= OPR[5] 0= OPR[4] 00= OPR[3] 00= OPR[2] OPCR 1= TxRDYB 1= TxRDYA 1= RxRDY/ 1= RxRDY/ 01 = C/T OUTPUT 01 = TxCA (16X) FFULLB FFULLA 10= TxCB (1X) 10= TxCA (1X) 11 = RxCB (1X) 11 = RxCA (1X)

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO BRG SET COUNTER/TIMER DELTA DELTA DELTA DELTA SELECT MODE AND SOURCE IP3 INT IP2 INT IP1 INT IPO INT ACR 0= set1 See table 4 0= off 0= off 0= off 0= off 1= set2 1= on 1= on 1= on 1= on

BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BITO DELTA DELTA DELTA DELTA IP3 IP2 IP1 IPO IPCR IP3 IP2 IP1 IPO 0= no 0= no 0= no 0= no 0= low 0= low 0 = low 0= low 1= yes 1= yes 1= yes 1= yes 1= high 1= high 1= high 1= high

4.162 Signetics MICROPROCESSOR DIVISION JANUARY 1983 DUAL ASYNCHRONOUS RECEIVERITRANSMITTER (DUART) SCN68681

Preliminary Table 2 REGISTER BIT FORMATS (Continued) BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO INPUT DELTA RxRDYI COUNTER DELTA RXRDY/ PORT TxRDYB TxRDYA BREAK B FFULLB READY BREAK A FFULLA ISR CHANGE 0= no 0= no 0= no 0= no 0= no 0= no 0= no 0= no 1= yes 1= yes 1= yes 1= yes 1= yes 1= yes 1= yes 1= yes

BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO IN. PORT DELTA RxRDYI COUNTER DELTA RxRDYI TxRDYB TxRDYA CHANGE BREAK B FFULLB READY BREAK A FFULLA INT INT IMR INT INT INT INT INT INT 0= off 0= off 0 = off 0= off 0= off 0= off 0= off 0= off 1= on 1= on 1= on 1= on 1= on 1= on 1= on 1= on

BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO C/T[15] C/T[14] C/T[13] C/T[12] CIT[11] C/T[10] C/T[9] C/T[8] CTUR

BIT7 BIT6 BITS BIT4 BIT3 BiT2 BIT1 BITO C/T[7] C/T[6] CIT[5] C/T[4] CIT[3] CIT[2] Ca[l] C/T[0] CTLR

BIT7 BIT6 BITS BIT4 BIT3 BIT2 BIT1 BITO IVR[7] IVR[6] IVR[5] IVR[4] IVR[3] IVR[2] IVR[1] IVR[0] IVR

MR1A — Channel A Mode MR1A[6] — Channel A Receiver Interrupt MR1A[4:3] — Channel A Parity Mode Register 1 Select — This bit selects either the chan- Select — If 'with parity' or 'force parity' is nel A receiver ready status (RXRDY) or the selected, a parity bit is added to the trans- MR1A is accessed when the channel A MR channel A FIFO full status (FFULL) to be mitted character and the receiver per- pointer points to MR1. The pointer is set used for CPU interrupts. It also causes the forms a parity check on incoming data. to MR1 by RESET or by a 'set pointer' com- selected bit to be output on OP4 if it is MR1A[4:3]= 11 selects channel A to oper- mand applied via CRA. After reading or programmed as an interrupt output via the ate in the special multidrop mode de- writing MR1A, the pointer will point to OPCR. scribed in the Operation section. MR2A. MR1A[5] — Channel A Error Mode Select MR1A[2] — Channel A Parity Type Select MR1A[7] — Channel A Receiver Request• — This bit selects the operating mode of — This bit selects the parity type (odd or to-Send Control — This bit controls the the three FIFOed status bits (FE, PE, re- even) if the 'with parity' mode is program. deactivation of the RTSAN output (OPO) by ceived break) for channel A. In the 'charac- med by MR1A[4:3], and the polarity of the the receiver. This output is normally ter' mode, status is provided on a charac- forced parity bit if the 'force parity' mode asserted by setting OPR[0] and negated by ter-by-character basis: the status applies is programmed. It has no effect if the `no resetting OPR[0]. MR1A[7]= 1 causes only to the character at the top of the parity' mode is programmed. In the special RTSAN to be negated upon receipt of a FIFO. In the 'block' mode, the status pro- multidrop mode it selects the polarity of valid start bit if the channel A FIFO is full. vided in the SR for these bits is the ac- the A/D bit. However, OPR[0] is not reset and RTSAN cumulation (logical OR) of the status for will be asserted again when an empty all characters coming to the top of the FIFO position is available. This feature FIFO since the last 'reset error' command MR1A[1:0) — Channel A Bits per Character can be used for flow control to prevent for channel A was issued. Select — This field selects the number of overrun in the receiver by using the data hits per character to be transmitted RTSAN output signal to control the CTSN and received. The character length does input of the transmitting device. not include the start, parity, and stop bits.

Signetics 4163 MICROPROCESSOR DIVISION JANUARY 1983 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN68681

Preliminary MR2A - Channel A Mode 4. The received parity is not checked and TxDA output remains in the marking state Register 2 is not regenerated for transmission, and the transmission is delayed until i.e., transmitted parity bit is as re- CTSAN goes low. Changes in CTSAN MR2A is accessed when the channel A MR ceived. while a character is being transmitted do pointer points to MR2, which occurs after 5. The receiver must be enabled. not affect the transmission of that charac- any access to MR1A. Accesses to MR2A ter. do not change the pointer. 6. Character framing is not checked, and the stop bits are retransmitted as re- MR2A[3:0] - Channel A Stop Bit Length ceived. MR2A[7:6] - Channel A Mode Select - Select - This field programs the length of 7. A received break is echoed as received Each channel of the DUART can operate in the stop bit appended to the transmitted until the next valid start bit is detected. one of four modes. MR2A[7:6] = 00 is the character. Stop bit lengths of 9/16 to 1 and normal mode, with the transmitter and re- 1-9/16 to 2 bits, in increments of 1/16 bit, The user must exercise care when switch- ceiver operating independently. MR2A[7:6] can be programmed for character lengths ing into and out of the various modes. The = 01 places the channel in the automatic of 6, 7, and 8 bits. For a character length of selected mode will be activated immedi- echo mode, which automatically retrans- 5 bits, 1-1/16 to 2 stop bits can be pro- ately upon mode selection, even if this oc- mits the received data. The following con- grammed in increments of 1/16 bit. The re- curs in the middle of a received or trans- ditions are true while in automatic echo ceiver only checks for a 'mark' condition mitted character. Likewise, if a mode is de- mode: at the center of the first stop bit position selected, the device will switch out of the (one bit time after the last data bit, or after 1. Received data is reclocked and retrans- mode immediately. An exception to this is the parity bit if parity is enabled) in all mitted on the TxDA output. switching out of autoecho or remote loop- cases. 2. The receive clock is used for the trans- back modes: if the de-selection occurs mitter. just after the receiver has sampled the If an external 1X clock is used for the transmitter, MR2A[3]= 0 selects one stop 3. The receiver must be enabled, but the stop bit (indicated in autoecho by asser- bit and MR2A[3]= 1 selects two stop bits transmitter need not be enabled. tion of RxRDY), and the transmitter is enabled, the transmitter will remain in to be transmitted. 4. The channel A TxRDY and TxEMT autoecho mode until the entire stop bit status bits are inactive. has been retransmitted. MR1B - Channel B Mode 5. The received parity is checked, but is Register 1 not regenerated for transmission, i.e., MR1B is accessed when the channel BMR transmitted parity bit is as received. MR2A[5] - Channel A Transmitter Re- quest-to-Send Control - This bit controls pointer points to MR1. The pointer is set 6. Character framing is checked, but the the deactivation of the RTSAN output to MR1 by RESET or by a 'set pointer' com- stop bits are retransmitted as received. (OPO) by the transmitter. This output is mand applied via CRB. After reading or 7. A received break is echoed as received normally asserted by setting OPR[0] and writing MR1B, the pointer will point to until the next valid start bit is detected. negated by resetting OPR[0]. MR2A[5]. 1 MR2B. 8. CPU to receiver communication contin- causes OPR[0] to be reset automatically The bit definitions for this register are ues normally, but the CPU to transmit- one bit time after the characters in the identical to the bit definitions for MR1A, ter link is disabled. channel A transmit shift register and in except that all control actions apply to the Two diagnostic modes can also be config- the THR, if any, are completely transmit- channel B receiver and transmitter and the ured. MR2A[7:6]= 10 selects local loop- ted, including the programmed number of corresponding inputs and outputs. back mode. In this mode: stop bits, if the transmitter is not enabled. This feature can be used to automatically 1. The transmitter output is internally terminate the transmission of a message connected to the receiver input. as follows: MR2B - Channel B Mode 2. The transmit clock is used for the re- Register 2 Program auto-reset mode: MR2A[5]. 1. ceiver. 1. 2. Enable transmitter. MR2B is accessed when the channel B MR 3. The TxDA output is held high. pointer points to MR2, which occurs after 3. Assert RTSAN: OPR[0]= 1. 4. The RxDA input is ignored. any access to MR1B. Accesses to MR2B 4. Send message. 5. The transmitter must be enabled, but do not change the pointer. 5. Disable transmitter after the last char- the receiver need not be enabled. The bit definitions for this register are acter is loaded into the channel A THR. 6. CPU to transmitter and receiver com- identical to the bit definitions for MR2A, munications continue normally. 6. The last character will be transmitted except that all control actions apply to the and OPR[0] will be reset one bit time The second diagnostic mode is the remote channel B receiver and transmitter and the after the last stop bit, causing RTSAN loopback mode, selected by MR2A[7:6] = corresponding inputs and outputs. to be negated. 11. In this mode: 1. Received data is reclocked and retrans- MR2A[4] - Channel A Clear-to-Send Con- CSRA - Channel A Clock Select mitted on the TxDA output. trol - If this bit is 0, CTSAN has no effect 2. The receive clock is used for the trans- on the transmitter. If this bit is a 1, the Register mitter. transmitter checks the state of CTSAN CSRA[7:4] - Channel A Receiver Clock 3. Received data is not sent to the local (IPO) each time it is ready to send a charac- Select - This field selects the baud rate CPU, and the error status conditions ter. If IPO is asserted (low), the character is clock for the channel A receiver as fol- are inactive. transmitted. If it is negated (high), the lows:

4.164 Signetics MICROPROCESSOR DIVISION JANUARY 1983 DUAL ASYNCHRONOUS RECEIVERITRANSMITTER (DUART) SCN68681

Preliminary Baud Rate CRA — Channel A Command times. TXDA will remain high for Clock = 3.6864MHz Register one bit time before the next CSRA[7:4] ACR[7] = 0 ACR[7]. 1 character, if any, is transmitted. CRA is a register used to supply com- 0 0 0 0 50 75 mands to channel A. Multiple commands 0 0 0 110 110 CRA[3] — Disable Channel A Transmitter can be specified in a single write to CRA 0 0 0 134.5 134.5 — This command terminates transmitter as long as the commands are non-conflict- 0 0 200 150 operation and resets the TxRDY and ing, e.g., the 'enable transmitter' and 0 0 0 300 300 TxEMT status bits. However, if a character 'reset transmitter' commands cannot be 0 0 600 600 is being transmitted or if a character is in specified in a single command word. 0 0 1,200 1,200 the THR when the transmitter is disabled, the transmission of the character(s) is 0 1,050 2,000 CRA[6:4] — Channel A Miscellaneous completed before assuming the inactive 0 0 0 2,400 2,400 Commands — The encoded value of this state. 0 0 4,800 4,800 field may be used to specify a single com- 0 0 7,200 1,800 mand as follows: 0 9,600 9,600 CRA[2] — Enable Channel A Transmitter 0 0 38.4K 19.2K CRA[6:4] COMMAND — Enables operation of the channel A 0 transmitter. The TxRDY status bit will be Timer Timer 0 0 0 No command. 0 IP4-16X IP4-16X asserted. 0 0 1 Reset MR pointer. Causes the IP4-1X IP4-1X channel A MR pointer to point to CRAM — Disable Channel A Receiver — The receiver clock is always a 16X clock MR1. This command terminates operation of except for CSRA[7:4]= 1111. 0 1 0 Reset receiver. Resets the chan- the receiver immediately — a character nel A receiver as if a hardware being received will be lost. The command CSRA[3:0] — Channel A Transmitter Clock reset had been applied. The re- has no effect on the receiver status bits or Select — This field selects the baud rate ceiver is disabled and the FIFO any other control registers. If the special clock for the channel A transmitter. The is flushed. multidrop mode is programmed, the re- field definition is as per CSRA[7:4] except Reset transmitter. Resets the ceiver operates even if it is disabled. See as follows: 0 1 1 channel A transmitter as if a Operation section. Baud Rate hardware reset had been ap- CSRA[3:0] ACR[7]= 0 ACR[7]= 1 plied. CRA[0] — Enable Channel A Receiver — Enables operation of the channel A re- 1 1 1 0 IP3-16X IP3-16X 1 0 0 Reset error status. Clears the ceiver. If not in the special wakeup mode, 1 1 1 1 IP3-1X IP3-1X channel A Received Break, Par- this also forces the receiver into the ity Error, Framing Error, and The transmitter clock is always a 16X search for start-bit state. clock except for CSRA[3:0] = 1111. Overrun Error bits in the status register (SRA[7:4]). Used in character mode to clear OE status CRB — Channel B Command CSRB — Channel B Clock Select (although RB, PE, and FE bits Register Register will also be cleared) and in block CRB is a register used to supply com- mode to clear all error status mands to channel B. Multiple commands CSRB[7:4] — Channel B Receiver Clock after a block of data has been can be specified in a single write to CRB Select — This field selects the baud rate received. clock for the channel B receiver. The field as long as the commands are non-conflict- 1 0 1 Reset channel A break change definition is as per CSRA[7:4] except as ing, e.g., the 'enable transmitter' and interrupt. Causes the channel A follows: 'reset transmitter' commands cannot be break detect change bit in the in- specified in a single command word. Baud Rate terrupt status register (ISR[2]) to The bit definitions for this register are CSRB[7:4] ACR[7]= 0 ACR[7] = 1 be cleared to zero. identical to the bit definitions for CRA, ex- 1 1 1 0 IP2-16X IP2-16X 1 1 0 Start break. Forces the TXDA cept that all control actions apply to the 1 1 1 1 IP2-1X IP2-1X output low (spacing). If the channel B receiver and transmitter and the The receiver clock is always a 16X clock transmitter is empty the start of corresponding inputs and outputs. except for CSRB[7:4]= 1111. the break condition will be delayed up to two bit times. If the SRA — Channel A Status transmitter is active the break CSRB[3:0] — Channel B Transmitter Clock Register Select — This field selects the baud rate begins when transmission of the clock for the channel B transmitter. The character is completed. If a char- SRA[7] — Channel A Received Break — field definition is as per CSRA[7:4] except acter is in the THR, the start of This bit indicates that an all zero character as follows: the break will be delayed until of the programmed length has been re- that character, or any others Baud Rate ceived without a stop bit. Only a single loaded subsequently are trans- CSRB[3:0] ACR[7]= 0 ACR[7]= 1 FIFO position is occupied when a break is mitted. The transmitter must be received: further entries to the FIFO are in- 1 1 1 0 IP5-16X IP5-16X enabled for this command to be hibited until the RxDA line returns to the 1 1 1 1 IP5-1X IP5-1X accepted. marking state •`c3r at least one-half a bit The transmitter clock is always a 16X 1 1 1 Stop Break. The TXDA line will time (two successive edges of the internal clock except for CSRB[3:0]= 1111. go high (marking) within two bit or external 1x clock). Signetics 4-165 MICROPROCESSOR DIVISION JANUARY 1983 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN68681

Preliminary

When this bit is set, the channel A 'change SRAM — Channel A FIFO Full (FFULLA) OPCR[4] — OP4 Output Select — This bit in break' bit in the ISR (ISR[2]) is set. ISR[2] — This bit is set when a character is trans- programs the OP4 output to provide one of is also set when the end of the break con- ferred from the receive shift register to the the following: dition, as defined above, is detected. receive FIFO and the transfer causes the — The complement of OPR[4] FIFO to become full, i.e., all three FIFO The break detect circuitry can detect — The channel A receiver interrupt out- breaks that originate in the middle of a positions are occupied. It is reset when put, which is the complement of 'SR[1]. received character. However, if a break the CPU reads the RHR. If a character is When in this mode OP4 acts as an open begins in the middle of a character, it must waiting in the receive shift register be- collector output. Note that this output cause the FIFO is full, FFULL will not be persist until at least the end of the next is not masked by the contents of the character time in order for it to be de- reset when the CPU reads the RHR. IMR. tected. SRA[0] — Channel A Receiver Ready OPCR[3:2] OP3 Output Select — This (RxRDYA) — This bit indicates that a char- SRA[6] — Channel A Framing Error — This field programs the OP3 output to provide acter has been received and is waiting in bit, when set, indicates that a stop bit was one of the following: the FIFO to be read by the CPU. It is set not detected when the corresponding data when the character is transferred from the — The complement of OPR[3] character in the FIFO was received. The receive shift register to the FIFO and reset — The counter/timer output, in which stop bit check is made in the middle of the when the CPU reads the RHR, if after this case OP3 acts as an open collector out- first stop bit position. read there are no more characters still in put. In the timer mode, this output is a SRA[5] — Channel A Parity Error — This the FIFO. square wave at the programmed fre- bit is set when the 'with parity' or 'force quency. In the counter mode, the out- parity' mode is programmed and the corre- SRB — Channel B Status Register put remains high until terminal count is reached, at which time it goes low. The sponding character in the FIFO was re- The bit definitions for this register are output returns to the high state when ceived with incorrect parity. identical to the bit definitions for SRA, ex- the counter is stopped by a stop cept that all status applies to the channel In the special multidrop mode the parity counter command. Note that this out- B receiver and transmitter and the corre- error bit stores the received A/D bit. put is not masked by the contents of sponding inputs and outputs. the IMR. SRA[4] — Channel A Overrun Error — This bit, when set, indicates that one or more OPCR — Output Port Configur- — The 1X clock for the channel B transmitter, which is the clock that shifts the characters in the received data stream ation Register have been lost. It is set upon receipt of a transmitted data. If data is not being new character when the FIFO is full and a OPCR[7] — OP7 Output Select — This bit transmitted, a free running 1X clock is character is already in the receive shift programs the OP7 output to provide one of output. register waiting for an empty FIFO posi- the following: — The 1X clock for the channel B receiver, tion. When this occurs, the character in — The complement of OPR[7] which is the clock that samples the the receive shift register (and its break — The channel B transmitter interrupt received data. If data is not being re- detect, parity error and framing error output, which is the complement of ceived, a free running 1X clock is out- status, if any) is lost. TxRDYB. When in this mode OP7 acts put. as an open collector output. Note that This bit is cleared by a 'reset error status' OPCR[1:0] — OP2 Output Select — This this output is not masked by the con- command. field programs the OP2 output to provide tents of the IMR. one of the following: SRA[3] — Channel A Transmitter Empty (TxEMTA) — This bit will be set when the OPCR[6] — OP6 Output Select — This bit — The complement of OPR[2] channel A transmitter underruns, i.e., both programs the OP6 output to provide one of — The 16X clock for the channel A trans- the transmit holding register (THR) and the followng: mitter. This is the clock selected by the transmit shift register are empty. It is — The complement of OPR[6] OSRA[3:0], and will be a 1X clock if set after transmission of the last stop bit — The channel A transmitter interrupt CSRA[3:0] = 1111. of a character if no character is in the THR output, which is the complement of — The 1X clock for the channel A trans- awaiting transmission. It is reset when the TxRDYA. When in this mode OP6 acts mitter, which is the clock that shifts the THR is loaded by the CPU or when the as an open collector output. Note that transmitted data. If data is not being transmitter is disabled. this output is not masked by the con- transmitted, a free running 1X clock is output. SRA[2] — Channel A Transmitter Ready tents of the IMR. (TxRDYA) — This bit, when set, indicates — The 1X clock for the channel A receiver, OPCR[5] — OP5 Output Select — This bit that the THR is empty and ready to be which is the clock that samples the programs the OP5 output to provide one of loaded with a character. This bit is cleared received data. If data is not being re- the following: when the THR is loaded by the CPU and is ceived, a free running 1X clock is out- set when the character is transferred to — The complement of OPR[5] put. the transmit shift register. TxRDY is reset — The channel B receiver interrupt out- when the transmitter is disabled and is set put, which is the complement of ISR[5]. when the transmitter is first enabled, viz., When in this mode OP5 acts as an open characters loaded into the THR while the collector output. Note that this output transmitter is disabled will not be trans- is not masked by the contents of the mitted. IMR.

4.166 Signetics MICROPROCESSOR DIVISION JANUARY 1983 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN68681

Preliminary ACR — Auxiliary Control Register ACR[3:0] — IP3, IP2, IP1, IPO Change of IPCR also clears ISR[71, the input change State Interrupt Enable — This field selects bit in the interrupt status register. which bits of the Input Port Change regis- ACR[7] — Baud Rate Generator Set Select The setting of these bits can be program- ter (IPCR) cause the input change bit in — This bit selects one of two sets of baud med to generate an interrupt to the CPU. rates to be generated by the BRG: the interrupt status register (ISR[7]) to be set. If a bit is in the 'on' state, the setting Set 1: 50, 110, 134.5, 200, 300, 600, 1.05K, IPCR[3:0] — IP3, IP2, IP1, IPO Current State of the corresponding bit in the IPCR will 1.2K, 2.4K, 4.8K, 7.2K, 9.6K, and — These bits provide the current state of also result in the setting of ISR[71, which 38.4K baud. the respective inputs. The information is results in the generation of an interrupt unlatched and reflects the state of the in- Set 2: 75, 110, 134.5, 150, 300, 600, 1.2K, output if IMR[7]= 1. If a bit is in the 'off' put pins at the time the IPCR is read. 1.8K, 2.0K, 2.4K, 4.8K, 9.6K, and state, the setting of that bit in the IPCR 19.2K baud. has no effect on ISR[7]. ISR — Interrupt Status Register The selected set of rates is available for use by the channel A and B receivers and This register provides the status of all IPCR — Input Port Change transmitters as described in CSRA and potential interrupt sources. The contents CSRB. Baud rate generator characteristics Register of this register are masked by the interrupt mask register (IMR). If a bit in the ISR is a 4 are given in table 3. IPCR[7:4] — IP3, IP2, IP1, !PO Change of '1' and the corresponding bit in the IMR is State — These bits are set when a change also a '1', the INTRN output will be as- ACR[6:41—Counter/Timer Mode and Clock of state, as defined in the Input Port sec- serted. If the corresponding bit in the IMR Source Select — tion of this data sheet, occurs at the re- This field selects the is a zero, the state of the bit in the ISR has spective input pins. They are cleared when operating mode of the counter/timer and no effect on the INTRN output. Note that its clock source as shown in table 4. the IPCR is read by the CPU. A read of the the IMR does not mask the reading of the Table 3 BAUD RATE GENERATOR CHARACTERISTICS ISR — the true status will be provided CRYSTAL OR CLOCK = 3.6864MHz regardless of the contents of the IMR. The contents of this register are initialized to NOMINAL RATE (BAUD) ACTUAL 16X CLOCK (KHz) ERROR (PERCENT) 0016 when the DUART is reset. 50 0.8 0 ISR[7] — Input Port Change Status — This 75 1.2 0 bit is a '1' when a change of state has 110 1.759 -0.069 occurred at the IPO, IP1, IP2, or IP3 inputs 134.5 2.153 0.059 and that event has been selected to cause 150 2.4 0 an interrupt by the programming of 200 3.2 0 ACR[3:0]. The bit is cleared when the CPU 300 4.8 0 reads the IPCR. 600 9.6 0 1050 16.756 -0.260 ISR[6] — Channel B Change in Break — 1200 19.2 0 This bit, when set, indicates that the chan- 1800 28.8 0 nel B receiver has detected the beginning 2000 32.056 0.175 or the end of a received break. It is reset 2400 38.4 0 when the CPU issues a channel B 'reset 4800 76.8 0 break change interrupt' command. 0 7200 115.2 ISR[5] — Channel B Receiver Ready or 0 9600 153.6 FIFO Full — The function of this bit is pro- 19.2K 307.2 0 grammed by MR1B[6]. If programmed as 614.4 0 38.4K receiver ready, it indicates that a character NOTE: has been received in channel B and is Duty cycle of 16X clock is 50% *1%. waiting in the FIFO to be read by the CPU. Table 4 ACR [6:4] FIELD DEFINITION It is set when the character is transferred from the receive shift register to the FIFO ACR[6:41 MODE CLOCK SOURCE and reset when the CPU reads the RHR. If after this read there are more characters 0 0 0 Counter External (IP2)1 still in the FIFO the bit will be set again 0 0 1 Counter TXCA — 1X clock of channel A transmitter after the FIFO is 'popped'. If programmed 0 1 0 Counter TXCB — 1X clock of channel B transmitter as FIFO full, it is set when a character is 0 1 1 Counter Crystal or external clock (X1/CLK) divided by 16 transferred from the receive holding regis- 1 0 0 Timer External (IP2)1 ter to the receive FIFO and the transfer causes the channel B FIFO to become full, 1 0 1 Timer External (IP2) divided by 161 i.e., all three FIFO positions are occupied. 1 1 0 Timer Crystal or external clock (X1/CLK) It is reset when the CPU reads the RHR. If 1 1 1 Timer Crystal or external clock (X1/CLK) divided by 16 a character is waiting in the receive shift register because the FIFO is full, the bit In these modes, the channel B receiver clock should normally be generated from the will be set again when the waiting charac- baud rate generator. ter is loaded into the FIFO.

Signetics 4.167 MICROPROCESSOR DIVISION JANUARY 1983 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN68681

Preliminary ISR[4] — Channel B Transmitter Ready — ISR[0] — Channel A Transmitter Ready — erated square wave is output on OP3 if it is This bit is a duplicate of TxRDYB (SRB[2]). This bit is a duplicate of TxRDYA (SRA[2]). programmed to be the C/T output. In the counter mode, the C/T counts down ISR[3] — Counter Ready — In the counter the number of pulses loaded into CTUR mode, this bit is set when the counter and CTLR by the CPU. Counting begins reaches terminal count and is reset when IMR — Interrupt Mask Register upon receipt of a start counter command. the counter is stopped by a stop counter Upon reaching terminal count (000010, the command. The programming of this register selects counter ready interrupt bit (ISR[3]) is set. which bits in the ISR cause an interrupt The counter continues counting past the In the timer mode, this bit is set once each output. If a bit in the ISR is a '1' and the terminal count until stopped by the CPU. If cycle of the generated square wave (every corresponding bit in the IMR is also a '1', OP3 is programmed to be the output of the other time that the counter/timer reaches the INTRN output will be asserted. If the C/T, the output remains high until terminal zero count). The bit is reset by a stop corresponding bit in the IMR is a zero, the count is reached, at which time it goes counter command. The command, how- state of the bit in the ISR has no effect on low. The output returns to the high state ever, does not stop the counter/timer. the INTRN output. Note that the IMR does and ISR[3] is cleared when the counter is not mask the programmable interrupt out- stopped by a stop counter command. The puts OP3-0P7 or the reading of the ISR. ISR[2] — Channel A Change in Break — CPU may change the values of CTUR and This bit, when set, indicates that the chan- CTLR at any time, but the new count be- nel A receiver has detected the beginning CTUR and CTLR — Counter/Timer comes effective only on the next start or the end of a received break. It is reset Registers counter command. If new values have not when the CPU issues a channel A 'reset been loaded, the previous count values The CTUR and CTLR hold the eight MSB's break change interrupt' command. are preserved and used for the next count and eight LSB's respectively of the value cycle. to be used by the counter/timer in either ISR[1] — Channel A Receiver Ready or the counter or timer modes of operation. In the counter mode, the current value of FIFO Full — The function of this bit is pro- The minimum value which may be loaded the upper and lower 8 bits of the counter grammed by MR1A[6]. If programmed as into the CTUR/CTLR registers is 000216. (CTU, CTL) may be read by the CPU. It is receiver ready, it indicates that a character Note that these registers are write-only recommended that the counter be stopped has been received in channel A and is and cannot be read by the CPU. when reading to prevent potential prob- waiting in the FIFO to be read by the CPU. lems which may occur if a carry from the It is set when the character is transferred In the timer (programmable divider) mode, lower 8-bits to the upper 8-bits occurs be- from the receive shift register to the FIFO the C/T generates a square wave with a tween the times that both halves of the and reset when the CPU reads the RHR. If period of twice the value (in clock periods) counter are read. However, note that a after this read there are more characters of the CTUR and CTLR. If the value in subsequent start counter command will still in the FIFO the bit will be set again CTUR or CTLR is changed, the current cause the counter to begin a new count after the FIFO is 'popped'. If programmed half-period will not be affected, but subse- cycle using the values in CTUR and CTLR. as FIFO full, it is set when a character is quent half periods will be. In this mode the transferred from the receive holding regis- C/T runs continuously. Receipt of a start ter to the receive FIFO and the transfer counter command (read with A3-A0. causes the channel A FIFO to become full, 1110) causes the counter to terminate the IVR — Interrupt Vector Register i.e., all three FIFO positions are occupied. current timing cycle and to begin a new It is reset when the CPU reads the RHR. If cycle using the values in CTUR and CTLR. This register contains the interrupt vector. a character is waiting in the receive shift The counter ready status bit (ISR[3]) is set The register is initialized to H 'OF ' by register because the FIFO is full, the bit once each cycle of the square wave. The RESET. The contents of the register are bit is reset by a stop counter command placed on the data bus when the DUART will be set again when the waiting charac- (read with A3-A0= 1111). The command, responds to a valid interrupt acknowledge ter is loaded into the FIFO. however, does not stop the C/T. The gen- cycle.

4.168 Signetics MICROPROCESSOR DIVISION JANUARY 1983 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN68681

Preliminary ABSOLUTE MAXIMUM RATINGS'

PARAMETER RATING UNIT

Operating ambient temperature2 0 to + 70 °C Storage temperature — 65 to + 150 °C All voltages with respect to ground' — 0.5 to + 6.0 V

NOTES. 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or at any other condition above those indicated in the operation section of this specification is not implied. 2. For operating at elevated temperatures. the device must be denoted based on *150°C maximum junction temperature, 3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.

DC ELECTRICAL CHARACTERISTICS TA = 0°C to + 70°C, Vcc = 5.0V ± 5% 4,5,6

LIMITS PARAMETER TEST CONDITIONS UNIT Min Typ Max

VIL Input low voltage 0.8 V VI 4 Input high voltage (except X1ICLK) 2.0 V V14 Input high voltage (X1/CLK) 4.0 V

VOL Output low voltage i0 1_ = 2.4mA 0.4 V VO4 Output high voltage (except o.c. outputs) loH= — 400AA 2.4 V 'IL Input leakage current VIN = 0 to V00 — 10 10 pi1 Ire Data bus 3-state leakage current Vo = 0 to V00 — 10 10 AA lac Open collector output leakage current Vo = 0 to V00 — 10 10 µA Icc Power supply current 150 mA NOTES: 4. Parameters are valid over specified temperature range. 5. All voltage measurements are referenced to ground (GND). For testing, all input signals swing between 0.4V and 2.4V h a transition time of 2Ons maximum. All time measurements are referenced at input voltages of 0.8V and 2.0V and output voltages of 0.8V and 2.0V as appropriate. 6. Typical values are at +25°C, typical supply voltages, and typical processing parameters,

Signetics 4.169 MICROPROCESSOR DIVISION JANUARY 1983 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN68681

Preliminary

AC ELECTRICAL CHARACTERISTICS TA= 0 °C to + 70°C, VDD = 5.0V± 5% 4' 5' 6' 7 TENTATIVE LIMITS PARAMETER UNIT Min Typ Max Reset Timing (figure 1) tREs RESETN pulse width 1.0 As Bus Timing (figures 2, 3, 4) tAs Al-A4 setup time to CSN low 10 ns tAH Al-A4 hold time from CSN low 0 ns tRws RWN setup time to CSN low 0 ns tRWH RWN holdup time to CSN high 0 ns tcsw8 CSN high pulse width 160 ns tcsD9 CSN or IACKN high from DTACKN low 20 ns tDD Data valid from CSN or IACKN low 175 ns tDF Data bus floating from CSN or IACKN high 100 ns tDs Data setup time to CLK high 100 ns tDH Data hold time from CSN high 0 ns tDAL DTACKN low from read data valid 0 ns tDcR DTACKN low (read cycle) from CLK high 125 ns tDcw DTACKN low (write cycle) from CLK high 125 ns tDAH DTACKN high from CSN or IACKN high 100 ns tDAT DTACKN high impedance from CSN or IACKN high 125 ns tDsDici CSN or IACKN setup time to clock high 90 ns Port Timing (figure 5) tps Port input setup time to RDN low 0 ns tpH Port input hold time from RDN high 0 ns tpD Port output valid from WRN high 400 ns Interrupt Reset Timing (figure 6) tip INTRN, or OP3-0P7 when used as interrupts, high from: Read RHR (RxRDYIFFULL interrupt) 300 ns Write THR (TxRDY interrupt) 300 ns Reset command (delta break interrupt) 300 ns Stop C/T command (counter interrupt) 300 ns Read IPCR (input port change interrupt) 300 ns Write IMR (clear of interrupt mask bit) 300 ns Clock Timing (figure 7) to_K X1/CLK high or low time 100 ns fC1_1( X1/CLK frequency 2.0 3.6864 4.0 MHz tuc CTCLK high or low time 100 ns f CTC CTCLK frequency 0 4.0 MHz tpx RXC high or low time 220 ns f RX RXC frequency (16X) 0 2.0 MHz (1X) 0 1.0 MHz trx TXC high or low time 220 ns fTx TXC frequency (16X) 0 2.0 MHz (1X) 0 1.0 MHz Transmitter Timing (figure 8) tpar) TXD output delay from TXC low 350 ns tTCs TXC output skew from TXD output data 150 ns Receiver Timing (figure 9) tpxs RXD data setup time to RXC high 240 ns tRxH RXD data hold time from RXC high 200 ns NOTES: 4. Parameters are valid over specified temperature range. 5. All voltage measurements are referenced to ground (GND). For testing, all input signals swing between 0.4V and 2.4V with a transition time of 2Ons maximum. All time measurements are referenced at input voltages of 0.8V and 20V and output voltages of 0.8V and 2.0V as appropriate. 6. Typical values are at +25°C, typical supply voltages, and typical processing parameters. 7. Test condition for outputs: CL= 150pF, except interrupt outputs. Test condition for interrupt outputs: CL= 50pF, RL= 2.7K ohm to VCC. 8. This specification will impose maximum 68000 CPU CLK to 6MHz. Higher CPU CLK can be used if repeating bus reads are not performed. 9. This specification imposes a lower bound on CSN and IACKN low, guaranteeing that it will be low for at least 1 CLK period. 10. This specification is made only to insure that DTACKN is asserted with respect to the rising edge of the X1/CLK pin as shown in the timing diagram, not to guarantee operation of the part. If the setup time is violated, DTACKN may be asserted as shown, or may be asserted one clock cycle later.

4.170 Signetics MICROPROCESSOR DIVISION JANUARY 1983 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN68681

Preliminary

RESETN

tRES

Figure 1. Reset Timing

ho--1csc

X1 /CLK tAS tAH

Al -A4 D( X

tRWS t RWH

RWN tCSw CSN

tDD tDF

DO D7

tcs D ► .0t s. DTACKN

tDAH tDCR tOAT

Figure 2. Bus Timing (Read Cycle)

Signetics 4-171 MICROPROCESSOR DIVISION JANUARY 1983 DUAL ASYNCHRONOUS RECEIVERITRANSMITTER (DUART) SCN68681

Preliminary

tcsc

Xl/CLK

• IAS tAH

Al -A4

tRWS tRWH RWN

tcsw CSN

DO-D7

IDH IDS tCSD DTACKN

tDCW tDAH

1DAT

Figure 3. Bus Timing (Write Cycle)

tcsc XlICLK

INTRN

IACKN

tDD F

DO D7

1DAL

DTACKN

tDCR tDAH

tDAT

Figure 4. Interrupt Cycle Timing

4.172 Signetics MICROPROCESSOR DIVISION JANUARY 1983

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN68681

Preliminary

CSN

1P5 -4—

IPO-1P5

CSN

OPO-OPT OLD DATA NEW DATA

ten

Figure 5. Port Timing

CSN (READ OR WRITE)

lie

INTERRUPT OUTPUT'

'INTRN or OP3-0P7 when used as interrupt outputs.

Figure 6. Interrupt Timing

+ 5V

CLOCK TO OTHER tCLK CHIPS

—► tCTC Cl: 10 - 15pF + (STRAY < 5pF) tRx C2: 0 - 5pF + (STRAY < 5pF) trx

XUCLK CTCLK RxC TxC tCLK

tCIR

tRx

tTx

CRYSTAL SERIES RESISTANCE SHOULD BE LESS THAN 180 OHMS.

Figure 7. Clock Timing

Signetics 4.173 MICROPROCESSOR DIVISION JANUARY 1983 DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN68681

Preliminary

1 BIT TIME (1 OR 16 CLOCKS) TxC (INPUT)

TxC (1X OUTPUT)

Figure 8. Transmit Timing

RxC (1X INPUT)

t6XS EIRXH

RxD

Figure 9. Receive Timing

Tx0 D1 D2 D3 BREAK D4 I I I 06

TRANSMITTER ENABLED

TxRDY F (SR2) . I.

CSN • (WRITE) D1 02 D3 START D4 STOP 05 WILL 6 BREAK BREAK NOT BE CTSN1 TRANSMITTED (IPO)

RTSN2 (OK) OPR(0)=1 OPR(0)= 1

NOTES 1. TIMING SHOWN FOR MR2(4)=1. 2. TIMING SHOWN FOR MR2(5)=1.

Figure 10. Transmitter Timing

4-174 Signetics MICROPROCESSOR DIVISION JANUARY 1983

DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART) SCN68681

Preliminary

RxD

D6, D7, DO WILL BE LOST

RECEIVER ENABLED

RxRDY (SRO)

FFULL (SRI)

xRDY/ FFULL (0P4)2

CSN (READ) STATUS DATA D5 WILL STATUS DATA STATUS DATA STATUS DATA

D1 I BE LOST D2 I 03 D4 OVERRUN (SR4) fRESET BY COMMAND

RTS' (OPT) OPR(0) =1

NOTES 1. TIMING SHOWN FOR MR1)7)= I. 2. SHOWN FOR OPCR(4) = 1 AND MR1(6). O.

Figure 11. Receiver Timing

MASTER STATION BIT 9 BIT 9 BIT 9

TxD ADD#211

TRANSMITTER ENABLED

TxRDY ISR2)

CSN (WRITE) MR1(4•3).11 ADD11 MR1(2)=0 DO MR1(2)=1 ADD142 MR1(2)=1

PERIPHERAL STATION BIT 9 BIT 9 BIT 9 BIT 9 BIT 9 RxD ADD# DO 10 IADD#21 IIIllii II

RECEIVER ENABLED

RxRDY (SRO)

CSN t Th f STATUS DATA MR1(4:3).11 ADD #1 STATUS DATA DO ADDR2

Figure 12. Wake up Mode

Signetics 4.175

Section 5 Video Games

Signetics

MICROPROCESSOR DIVISION JANUARY 1983 UNIVERSAL SYNC GENERATOR (PAL) SCN2621 (PALL SCN2622(NTSC)

PRODUCT BRIEF, contact your Signetics sales offices for complete information.

The Signetics SCN2621 Universal Sync The Signetics SCN2622 Universal Sync PIN CONFIGURATION Generator (USG) provides the timing and Generator (USG) provides the timing and control signals necessary for generating control signals necessary for generating and displaying TV video information in the and displaying TV video information in the PAL format. NTSC format. The USG accepts a single 3.55MHz input The USG accepts a single 3.5795MHz in- clock and generates various timing output clock and generates various timing puts including vertical, horizontal and outputs including vertical, horizontal, and composite blanking, composite sync and composite blanking, composite sync and color burst flag. Several auxiliary clock color burst flag. Several auxiliary clock outputs are also provided. outputs are also provided. The USG is primarily intended for use in microprocessor- The USG is primarily intended for use in controlled video games. A typical game microprocessor-controlled video games. A configuration consists of an SCN2622 typical game configuration consists of an USG, an SCN2650A microprocessor, an SCN2621 USG, an SCN2650A micropro- SCN2636 Programmable Video Interface, a cessor, an SCN2636 Programmable Video 2616 16K ROM, and digital video summer interface, a 2616 16K ROM, and digital circuitry. The SCN2622 is constructed video summer circuitry. using Signetics silicon gate N-channel The SCN2621 is constructed using depletion load technology and operates Signetics silicon gate N-channel depletion from a single +5 volt power supply. load technology and operates from a single +5 volt power supply.

BLOCK DIAGRAM

VERTICAL DECODER ► VRST

VERTICAL COUNTER (DIVIDE BY 312-PAL) CBLANK (DIVIDE BY 262-NTSC) LOGIC ARRAY VSR RESET CSYNC

HORIZONTAL COUNTER CLOCK BUFFER (DIVIDE BY 227) HS

► HRST CBF HORIZONTAL DECODER ► OE ► PCK

CK2

CK4

Signetics 5.1

MICROPROCESSOR DIVISION JANUARY 1983 PROGRAMMABLE VIDEO INTERFACE (PVI) SCN2636

PRODUCT BRIEF, contact your Signetics sales offices for complete information.

The Signetics SCN2636 Programmable FEATURES PIN CONFIGURATION Video Interface (PVI) is intended for use in • Four general-purpose, RAM-resident microprocessor-controlled game systems, object modules and provides all of the common game cir- PCK GND • Object duplication permitting cuits on a single chip. Circuits are pro- NIC generation of up to 80 object images INTREG vided for player inputs, background, mov- on the screen Ag RIW ing objects, scoring, and audio signals. • 280ns object resolution A5 VRST A typical system configuration consists of • Object size and position under A4 HRST five LSI circuits: a PVI, a 2616 16K ROM, a program control Digital Video Summer (DVS), a Universal • Programmable score A3 Cl Sync Generator (USG), and an SCN2650A • Programmable sound A2 C2

microprocessor. • Programmable background Al C3 • Eight programmable colors with Additional PVIs as well as random logic A5 OBJ/SCR multiple brightness levels can easily be interfaced to enhance game • 37-byte scratch pad memory A7 INTACK complexity. Since the system is micro- • processor based, the actual game itself Chip Enable outputs for system ROMs Ag Do and PROMs need not be "hardwired" into the system. VCG • I/O facilities for switch scanning and Game definition is completely contained A9 1:12 in the ROM. To change games, one simply Potentiometer inputs • D3 replaces one ROM with another. Each Wire-OR expansion capability to A10 multiple PVIs ROM can contain several games, depend- A11 D4 • Forty-pin dual-In-line package ing on game complexity and similarity CE1 D5 between games. APPLICATIONS OPACK Dg

The SCN2636 PVI is constructed using • Consumer programmable video games 0 PREO D7 Signetics' silicon gate N-channel deple- • Arcade games CE2 SOUND tion load technology and operates from a • Simulators POT2 POTI single -F5 volt power supply. • Special purpose graphic displays

• Home computer center TOP VIEW

PVI BLOCK DIAGRAM

BACK. GROUND OBJECT BACKGROUND SCORE CONTROL CONTROL CONTROL OBJECT TI'1 I SCRATCH ADDRESS BUS RAM

DATA BUS M C2 U X C3 OBJISCR

A5-A11 PCK VERTICAL HORIZONTAL TIMING VRST HRST D0-D7 COUNTER COUNTER AND & DECODE & DECODE CONTROL Rpne OPREO OPACK

ADDRESS BUS

DATA BUS

ANALOG TO INTERRUPT CHIP ENABLE DIGITAL DIGITAL CONTROL & DECODE SOUND CONVERTER STATUS f 1 1 1 CE1 CE2 POT1 POT2 SOUND INTREO INTACK

5.2 Signetics MICROPROCESSOR DIVISION JANUARY 1983 UNIVERSAL VIDEO INTERFACE (UVI) SCN2637

PRODUCT BRIEF, contact your Signetics sales offices for complete information.

DESCRIPTION FEATURES PIN CONFIGURATION The Signetics SCN2637 Universal Video Inter- face (UVI), using a new design approach, • Four general purpose, RAM-resident enables a microprocessor based system to objects OND D2 • 280nsec object resolution be interfaced more efficiently with a color or D3 D1 black and white television receiver or moni- • Object size and position under program D4 DO tor. For the first time, the SCN2637 UVI com- control bines an object oriented approach with • Programmable multi-level sound and 135 PAUSE character generation (alphanumerics or oth- noise generators DO AO • 16 characters per display row er displayable forms) plus RAM-mapped D7 Al color graphics. • 13 or 26 character rows per screen • 40 alphanumeric characters ADEN A2 The UVI's primary use is in microprocessor • 16 background characters POT4 A3 controlled home computers or game sys- • 8 program definable characters POT3 A4 tems, however, it may also be used in other • 64 graphics characters applications where the display of alphanu- • 8 programmable color codes POT2 A5 meric and graphics data is desired. In par- • Chip enable outputs for I/O logic POT1 A6 ticular, the UVI has been designed to require I/O facilities for switch scanning and • CO Al a minimum of support components thereby potentiometer (RC) inputs allowing a system configuration that is opti- • Operates with both U.S. and European c2 AB mized for the user's needs. standards RCE The UVI reads data and operational com- • Single +5 volt power supply C3 CE • Forty-pin package mands from a memory and produces video SOUND R/W signals that result in the generation of alpha- aw OPACK numeric or graphics color TV displays. Many APPLICATIONS VRST CS of the common display circuits have been • Video games incorporated in a single chip, including: • Home computers HRST OPREO PCK • Analog to digital converters which accept • Communications terminals VCC • Educational systems potentiometer inputs TOP VIEW • Alphanumeric and special character • Process control displays generators • Medical electronics • Moving object circuits • Audio signal generators

With the SCN2637, a typical system configur. ation consists of a UVI, a 2616/2632 ROM, an SCN2622 (NTSC) or SCN2621 (PAL) Universal Sync Generator (USG), an SCN2650 series microprocessor, four 2112 RAMs, and video summing circuitry. Additional UVIs, Program- mable Video Interfaces (PVIs), as well as random logic can be interfaced to enhance game or system complexity. A/D Block Internal Status Block The A/D Block converts the analog potenti- The internal status block accumulates sta- UVI FUNCTIONAL DESCRIPTION ometer position information into binary data tus information which can be read by the The SCN2637 UVI is a bus oriented device which can be read by the system's CPU. CPU; for example, collisions. with address and data busses controlling the Only two of the four potentiometers are ac- flow of data between the user's system and tive at any given time. Color Mux System the UVI (see block diagram). Both the address The color multiplexer generates the color and data busses are bidirectional. Address Block The address block provides chip enable out- codes for characters, objects, and screen. The basic clock frequency and the horizon- puts for external RAMs and I/O buffers. tal and vertical reset signals to the UVI drive ROM Character Generator vertical and horizontal counters. The two Sound Block The ROM character generator stores the counters provide the UVI with a Cartesian The sound block is a multi-level square wave character fonts. coordinate representation of the television generator sending out pulses at a user screen, i.e., each counter pair describes a programmable audio frequency. Random unique point on the screen. Typically these noise is also generated and can be mixed RAM clock and reset signals are provided by a with the audio frequency for simulating The 64 bytes of RAM stores eight pro- universal sync generator circuit. crowd noise, explosions, etc. grammable character/object fonts.

Signetics 5.3 MICROPROCESSOR DIVISION JANUARY 1983 UNIVERSAL VIDEO INTERFACE (UVI) SCN2637

BLOCK DIAGRAM

8.BIT BUS DO-07

VRST HORIZONTAL COUNTER, DMA ADDRESS BUS VERTICAL SOUND ❑ SO HRST COUNTER, TIMING AND PCLK DMA COUNTER

RAN D.-- PROCESSOR PAUSE D.-- HANDSHAKING STATUS LOGIC RAM ADDRESS OF ADEN ❑ ~- AND DATA BUS COLLISION OPACK ❑w- OBJECT MODULE POT4 1 POT3 A/D BLOCK 2 POT2 2 PAGES 5.BIT VIDEO BUS 32 BYTES 3 POT1 PER PAGE+ CHARACTER BUFFER ROM OPREQ CHARACTER COLOR Do-- GENERATOR .-4.11 ADDRESS MUX CE1 ❑~-- DECODER -> SYSTEM ❑ CS o-► ► CO (OBJECT VIDEO) CHARACTER VIDEO SHIFT REGISTER

INTERNAL 8.BIT BUS

ADDRESS BUS AO-A8

+5 VOLTS GND ❑ ❑

5.4 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 MICROPROCESSOR SCN2650A

PRODUCT BRIEF, contact your Signetics sales offices for complete information. DESCRIPTION FEATURES PIN CONFIGURATION The Signetics SCN2650A devices are 8-bit • Static 8 bit parallel NMOS microproc- general purpose microprocessors con- essor SENSE FLAG structed using Signetics N-channel sili- • Single power supply of +5 volts ADR 12 con gate MOS technology. The SCN2650 • TTL level single phase clock VCC series executes a fixed instruction set, • TLL compatible inputs and outputs ADR 11 CLOCK with each instruction being one to three • Variable length instructions of 1, 2 or 3 ADR 10 PAUSE bytes bytes in length. ADR 9 OPACK • 32K byte addressing range The SCN2650A contains a total of seven • Coding efficiency with multiple ad- ADR 8 RUN/WAIT general purpose registers which may be dressing modes ADR 7 INTACK used as a source or destination for arith- • Synchronous or asynchronous memory ADR 6 DBUS 0 metic operations, as index registers, and and I/O interface ADR 5 for I/O memory transfers. An 8-level sub- • Interfaces directly with industry stan- DBUS 1 routine return address stack is included dard memories ADR 4 DBUS 2 on the chip. • Single bit serial I/O path ADR 3 DBUS 3

Addressing range of these processors is • Seven 8 bit addressable general pur- ADR 2 DBUS 4 32K bytes of memory and 258 I/O devices. pose registers ADR 1 DBUS 5 A single level hardware vectored interrupt • Vectored interrupt capability is provided. • Subroutine return address stack ADR 0 DBUS 6 ADREN DBUS 7

RESET DBUSEN

INTREQ OPREO

ADR FUW

ADR 13-E/NE WRP

Mari GND

TOP VIEW

MICROPROCESSOR BLOCK DIAGRAM

STACK POINTER PROGRAM STATUS WORD REGISTER STACK RO CONDITION ALU SUBROUTINE CODE AND RETURN BRANCH LOGIC ADDRESS STACK MULTIPLEXER

mF .q DATA BUS

2 O INSTRUCTION ADDRESS REGISTER

ADDRESS BUS \,7

OPERAND HOLD NG INSTRUCTION REGISTER REGISTER ADDRESS I/O REGISTER CONTROL LINES

READ, DECODING WRITE, AND ADDRESS INTERRUPT CONTROL ADDER AND STOP LOGIC TIMING CLOCK LOGIC

Figure 1 Signetics 5.5 MICROPROCESSOR DIVISION JANUARY 1983 MICROPROCESSOR SCN2650A

PIN DESIGNATION MNEMONIC NUMBER NAME TYPE FUNCTION ADRO-ADR12 14-2 Address lines 0 Low order memory address lines for instruction or operand fetch. ADRO is the least significant bit and ADR12 is the most significant bit. ADRO through ADR7 are also used as the I/O device address for extended I/O instructions. ADR13-E/NE 19 Address 13- 0 Low order memory page address line during memory reference Extended/Non extended instructions. For I/O instructions this line discriminates between extended and non-extended I/O instructions. ADR14-D/U 18 Address 14- 0 High order memory page address line during memory reference Data /Control instructions. It also serves as the I/O device address for non-extended I/O instructions. ADREN 15 Address enable I Active low input allowing 3-state control of the address bus ADRO- ADR 12. DBUSO-DBUS7 33-26 Data bus I/O These lines provide communication between the CPU, Memory, and I/O devices for instruction and data transfers. DBUSEN 25 Data bus enable I This active low input allows tri-state control of the data bus.

OPREQ 24 Operation request 0 Indicates to external devices that all address, data and control information is valid. Z5T3TOT 36 Operation acknowledge I Active low input indicating completion of an external operation. This allows asynchronous functioning of external devices. M/1 20 Memory/input-output 0 Indicates whether the current operation references memory or I/O. VI/W 23 Read/Write 0 Indicates a read or a write operation. WRP 22 Write pulse 0 This is a timing signal from the SCN2650 that provides a positive- going pulse during each requested write operation (memory or I/O) and a high level during read operations. SENSE 1 Sense I The sense bit in the PSU reflects the logic state of the sense input to the processor at pin #1. FLAG 40 Flag 0 The flag bit in the PSU is tied to a latch that drives the flag output at pin #40. INTITT) 1 17 Interrupt request I This active low input line indicates to the processor that an external device is requesting service. The processor will recognize this signal at the end of the current instruction if the interrupt inhibit status bit is zero. INTACK 34 Interrupt acknowledge 0 This line indicates that the SCN2650 is ready to receive the interrupt vector (relative address byte) from the interrupting device. PAUSE 37 Pause I This active low input is used to suspend processor operation at the end of the current instruction. RUN/WAIT 35 Run/Wait 0 This output is a processor status indicator. During normal operation this line is high. If the processor is halted either by executing a halt instruction or by a low input on the pause line, the run/wait line will go low. RESET 16 Reset I Resets the instruction address register to zero. Clears interrupt inhibit. CLOCK 38 Clock I A positive going pulse train that determines the instruction execution time. VCC 39 +5V supply I +5V power GND 21 Ground I Ground

5.6 Signelics MICROPROCESSOR DIVISION JANUARY 1983 MICROPROCESSOR SCN2650A

FUNCTIONAL DESCRIPTION instruction. The IR contents are decoded accessed. The operand address register The SCN2650 series processors are general and used in conjunction with the timing infor- stores operand addresses and sometimes purpose, single chip, fixed instruction set, mation to control the activation and contains intermediate results during effec- parallel 8-bit binary processors. A general sequencing of all the other elements on the tive address calculations. purpose processor can perform any data chip. The holding register is used in some The return address stack (RAS) is a last in, manipulations through execution of a stored multiple-byte instructions to contain further first out (LIFO) storage which receives the sequence of machine instructions. The proc- instruction information and partial absolute return address whenever a branch-to-sub- essor has been designed to closely resem- addresses. routine instruction is executed. When a re- ble conventional binary computers, but ex- The arithmetic logic unit (ALU) is used to turn instruction is executed, the RAS pro- ecutes variable length instructions of one to perform all of the data manipulation oper- vides the last return address for the three bytes in length. ations, including load, store, add, subtract, processor's IAR. The stack contains eight The SCN2650 series contains a total of seven AND, inclusive OR, exclusive OR, compare, levels of storage so that subroutines may be general purpose registers, each eight bits rotate, increment and decrement. It contains nested up to eight levels deep. The stack long. They may be used as source or desti- and controls the carry bit, the overflow bit, pointer is a three bit wraparound counter nation for arithmetic operations, as index the interdigit carry and the condition code that indicates the next available level in the registers, and for I/O transfers. register. stack. It always points to the current address. The processor can address up to 32,768 The register stack contains six registers bytes of memory in four pages of 8,192 that are organized into two banks of three PROGRAM STATUS WORD bytes each. The processor instructions are registers each. The register select bit picks The program status word (PSW) is a major one, two, or three bytes long, depending on one of the two banks to be accessed by feature of the SCN2650 which greatly in- the instruction. Variable length instructions instructions. In order to accommodate the 5 creases its flexibility and processing power tend to conserve memory space since a register-to register instructions, register The PSW is a special purpose register within zero (RO) is outside the array. Thus, register one-or-two byte instruction may often be the processor that contains status and con- used rather than a three byte instruction. zero is always available along with one set trol bits. The first byte of each instruction always of three registers. specifies the operation to be performed and It is divided into two bytes called the pro- The address adder is used to increment the the addressing mode to be used. Most gram status upper (PSU) and program sta- instruction address and to calculate relative instructions use six of the first eight bits for tus lower (PSL). The PSW bits may be test- and indexed addresses. this purpose, with the remaining two bits ed, loaded, stored, preset, or cleared using forming the register field. Some instructions The instruction address register holds the the instructions which affect the PSW. The use the full eight bits as an operation code. address of the next instruction byte to be bits are utilized as shown in table 1.

The data bus and address signals are tri- state to provide convenience in system design. Memory and I/O interface signals are Table 1 PROGRAM STATUS WORD asynchronous so that direct memory access PSU0,1,2 SP Pointer for the return address stack. (DMA) and multiprocessor operations are PSU3,4 Not used. These bits are always zero. easy to implement. PSU5 Used to inhibit recognition of additional Interrupts. PSU6 F Flag is a latch directly driving the flag output. The block diagram for the SCN2650 series PSU7 S Sense equals the state of the sense input. (figure 1) shows the major internal compo- PSLO C Carry stores any carry from the high-order bit of ALU. nents and the data paths that interconnect them. In order for the processor to execute an PSL 1 COM Compare determines if a logical or arithmetic comparison is to be instruction, it performs the following general made. steps: PSL2 OVF Overflow is set if a two's complement overflow occurs. PSL3 WC With carry determines if the carry is used in arithmetic and rotate 1. The instruction address register provides instructions. an address for memory. PSL4 RS Register select identifies which bank of 3.GP registers is being used. 2. The first byte of an instruction is fetched PSL5 IDC Inter digit carry stores the bit-3 to bit-4 carry in arithmetic operations. from memory and stored in the instruction PSL6,7 CC Condition code is affected by compare, test and arithmetic instructions. register. 3. The instruction register (IR) is decoded to determine the type of instruction and the addressing mode. PSU PSL 4. If an operand from memory is required, 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 the operand address is resolved and loaded into the operand address regis- S F II SP2 SP1 SPO CC I CCO IDC RS WC OVF COM C ter. S Sense CC1 Condition code one 5. The operand is fetched from memory and F Flag CCO Condition code zero the operation is executed. II Interrupt inhibit IDC Interdigit carry 6. The first byte of the next instruction is SP2 Stack pointer two RS Register bank select fetched. SP1 Stack pointer one WC With /without carry The instruction register holds the first byte SPO Stack pointer zero OVF Overflow of each instruction and directs the subse- COM Logical arithmetic compare quent operations required to execute each C Carry /borrow Signetics 5.7 MICROPROCESSOR DIVISION JANUARY 1983 MICROPROCESSOR SCN2650A

INPUT/OUTPUT INTERFACE be used for I/O operations. When an instruc- the interrupt vector, on the data bus. The The SCN2650 series microprocessor has a tion is executed, the address may be de- relative and relative indirect addressing set of versatile I/O instructions and can per- coded by the I/O device rather than mem- modes combined with this 8-bit address al- form I/O operations in a variety of ways. One ory. low interrupt service routines to begin at any addressable memory location. and two byte I/O instructions are provided, as MEMORY INTERFACE well as a special single-bit I/O facility. The I/O The memory interface consists of the ad- modes provided by the SCN2650 are desig- INSTRUCTION SET nated as data, control, and extended I/0. dress bus, the 8-bit data bus and several The 2650 instruction set consists of many signals that operate in an interlocked or powerful instructions which are all easily Data or control I/O instructions, also called handshaking mode. understood and are typical of larger com- non-extended I/O instructions, are one byte The write pulse signal is designed to be puters. There are one-, two-, and three-byte long. Any general purpose register can be used as a memory strobe signal for any instructions as a result of the multiplicity of used as the source or destination. A special memory type. It has been particularly opti- addressing modes. control line indicates if either a data or con- mized to be used as the chip enable or Automatic incrementing or decrementing of trol instruction is being executed. read/write signal. an index register is available in the Extended I/O is a two-byte read or write INTERRUPT HANDLING arithmetic indexed instructions. All of the instruction. Execution of an extended I/O branch instructions except indexed branch- instruction will cause an 8-bit address, tak- CAPABILITY ing can be conditional. en from the second byte of the instruction, to The SCN2650 series has a single level hard- Register-to-register instructions are one be placed on the low order eight address ware vectored interrupt capability. When an byte; register-to-storage instructions are lines. The data, which can originate or termi- interrupt occurs, the processor finishes the two or three bytes long. The two-byte regis- nate with any general purpose register, is current instruction and sets the interrupt inter-to-memory instructions are either imme- placed on the data bus. This type of I/O can hibit bit in the PSW. The processor then exe- diate or relative addressing types. be used to simultaneously select a device cutes a branch to subroutine relative to loca- and send data to it. tion zero (ZBSR) instruction and sends out interrupt acknowledge and operation request Memory reference instructions that address signals. On receipt of the INTACK signal, the data outside of physical memory may also interrupt device inputs an 8-bit address,

5.8 Signetics Section 6 Application Notes

Signetics

MICROPROCESSOR DIVISION JANUARY 1983 INTERFACE TECHNIQUES FOR THE 2651 PCI App Note M22

INTRODUCTION The Signetics 2651 Programmable Commu- CE nications Interface (PCI) is a universal synchronous/asynchronous data communications controller chip designed for ICE microcomputer systems. The 2651 accepts N)( programmed instructions from a micro- A0-A1 processor and supports many serial data communication disciplines, synchronous tAS tAH and asynchronous, in the full or half-duplex -*X mode. aw XI Although designed primarily to interface to tcs ---- ICH a 2650 microprocessor, the 2651 can be easily integrated into systems employing other CPUs. This application note describes Do-D7 methods to interface the PCI to 8080A, (WRITE) SC/MP, Z80, 8085, and 6800-based micro- 1-"-- 'DS IDN computer systems.

NOT INTERFACE SIGNALS BUS DATA VALID BUS FLOATING (READ)p -D FLOATING VALID The PCI interface signals can be grouped into two types: the CPU-related signals, IDD IDE .-..— which interface the 2651 to the microprocessor system, and the device-related sig- Figure 1. Read Write Timing Diagram nals, which are used to interface to the communications device or system. The functions of the CPU-related signals of interest in this application note are detailed in Table 1. Timing signals for the CPU-PCI interface are illustrated in Figure 1, with relevant specifications summarized in Table 2. Table 1 CPU-RELATED INTERFACE SIGNALS

PIN NAME PIN NO. INPUT/OUTPUT FUNCTION

Ai-Ao 10,12 I Address lines used to select internal PCI registers. R/W 13 I Read command when low, write command when high. CE 11 I Chip enable command. When low, indicates that control and data lines to the PCI are valid and that the operation specified by the R/W, At and Ao inputs should be performed. When high, places the Do-D7 lines in the tri-state condition. D7-Do 8,7,6,5, 1/0 8-bit, three-state data bus used to transfer commands, data and status between PCI 2,1,28,27 and the CPU. Do is the least significant bit; D7 the most significant bit.

Table 2 AC ELECTRICAL CHARACTERISTICS FOR CPU INTERFACE SIGNALS LIMITS PARAMETER TEST CONDITIONS1 UNIT Min Max

tcE Chip enable pulse width 300 ns Setup and hold time ns tAS Address setup 20 tAH Address hold 20 tcs R/W control setup 20 tcH R/W control hold 20 too Data setup for write 225 tDH Data hold for write 0 too Data delay time for read CL = 100pF 250 ns tDF Data bus floating time for read CL = 100pF 150 ns

NOTES 1. TA = 0°C to +70°C, Vcc = 5V ±5%. 2. Parametric values listed are from 2651 data sheet. Consult latest data sheet for possible changes to specifications.

Signetics 6.1 MICROPROCESSOR DIVISION JANUARY 1983 INTERFACE TECHNIQUES FOR THE 2651 PCI App Note M22

2650 INTERFACE The 2651 is designed to interface directly to the 2650 microprocessor bus. The PCI may be addressed via the 2650 extended I/O instructions or it may be memory mapped, in which case it is addressed using the 2650 ADRO AO memory reference instructions. As shown in ADR1 Al Figure 2, the 2651 chip enable (CE) input is RIW generated by "NANDing" OPREQ with the RIW appropriate control signals (depending on DBUSO- the addressing mode used) and the higher DBUS7 DBO-DB7 order address lines required to select the 2650 i—NOTE 1 NOTE 3 2651 PCI. \'` NOTE 2 // MIR/. EINE 8080A INTERFACE CE With regard to interfacing to the 2651, the OPREQ 74LS major difference between a 2650 CPU and NAND GATE an 8080A system consisting of an 8080A I I CPU, 8224 Clock Generator, and 8228/38 HIGH ORDER ADDRESS LINES FOR CHIP SELECT, System Controller (Figure 3) is the absence AS REQUIRED of a combined read/write signal suitable for NOTES the 2651 R/W input. Instead, the 8080A sys- 1. Inverter required only if 2651 addressing is by extended I/O instructions (Write, Read/. tem provides separate IOR and IOW (or 2. This input required only if 2651 addressing is by extended I/O instructions and non- MEMR and MEMW) outputs which specify extended addressing is also used in the system. both the direction of data flow and the data 3. These inputs not required if all I/O addressing is memory mapped. transfer timing. The simplest way to accomplish the interface is to utilize an address line from the Figure 2. 2650.2651 Interface 8080A for the R/W input and to 'OR' the IOR and IOW (or MEMR and MEMW) signals for Table 3 PCI REGISTER ADDRESSING FOR 8080A INTERFACE ultimate use as the 2651 chip enable signal, as illustrated in Figure 4. The only impact on OPERATION A2 (R/W) Al A0 REGISTER system design is that the software must 0 0 0 Receive Holding Register specify a different address to read the PCI 0 0 1 Status Register mode or command registers than to write READ 0 1 0 Mode Registers 1/2 the same registers. The selection of these 0 1 1 Command Register addresses must result in a '0' at the R/W input for read operations and a '1' for write 1 0 0 Transmit Holding Register operations. The resulting register address- 1 0 1 SYN1/SYN2/DLE Registers ing and function are summarized in Table 3. WRITE 1 1 0 Mode Registers 1/2 An analysis of the timing characteristics for 1 1 1 Command Register the recommended configuration shows that adequate margins exist to satisfy both the 2651 and the 8080A specifications at the minimum 8080A clock period of 480ns. The timing waveforms and calculations for the read and write cycles are shown in Figures 5 and 6.

6.2 Signetics MICROPROCESSOR DIVISION JANUARY 1983 INTERFACE TECHNIQUES FOR THE 2654 PCI App Note M22

2 5 GND AO Ao 20 26 + 5V Al Al 11 27 - 5V A2 A2 28 + 12V A A3 A A4 A5

A6 8080A CPU - ADDRESS BUS A A8 13 5 SYSTEM DMA REQ. HOLD Ag Aa A10 A10 40 A A11 14 37 SYSTEM INT. REQ. Al2 Al2 INT 38 A13 A13 16 39 INT. ENABLE INTE A14 A14 36 A15 A15 c;18 WR 17 ❑ ii(TAL DBIN 21 HDLA 1-1-41 1-11 21 4 3 13 2 TANK 1 15 13 12 10 15 D0 DB DB0 OSC 9 17 16 4,2 DBI 8224 24 12 11 02 (Tn.) WAIT 02 DB2 CLOCK 4 23 7 10 822818238 D3 RDYIN GENERATOR READY BIDIRECTIONAL DB3 3 6 BUS DRIVER 5 -DATA BUS DRIVER 12 134 DI34 10 RESET 4 19 18 RESIN — Ds DB5 +12V 5 21 20 16 DO 098 +5V 19 8 7 SYNC 7 D137 OND 28 + 5V 03 INTA 14 24 GND 0 MEMR STATUS STROBE 26 0 SYSTEM MEMW -CONTROL BUS CONTROL 25 22 0 II0 R BU SEN 0 27 O 110 W

Figure 3. 8080A System

Ao Ao Al Al

A2 RIW

0130-0137 DB0-DB7 M BUS 2651 PCI SYSTE IOR (MEMR) IOW (MEMW) 8080A

HIGH ORDER ADDRESS LINES CE FOR CHIP SELECT I AS REQUIRED l

74 OR 74LS NAND GATES Figure 4. 8080A — 2651 Interface

Signetics 6.3 MICROPROCESSOR DIVISION JANUARY 1983

INTERFACE TECHNIQUES FOR THE 2651 PCI App Note M22

T1 12 T3 T1 (480) 1

STSG 290 MIN 25 MIN 320 MAX 140 MAX DBIN 0 MIN -.--- 20 MIN 30MAS( 60 MAX

IOR 0 MIN 0 MIN 30 MAX CE 30 MAX

A0-A15

200 MAX I..-- -.a— 250 MAX — 480 MIN

DATA FROM 2651 VALID 30 MAX -.--- 0 MIN DATA FROM 8228

6080A DATA IN SPEC V A

..-- (50 OR DELAY OF DBIN) MIN

150 MIN

NOTES 1. All times in nanoseconds. 2. Delay from 02 of T1 to Ao, At, A/W 200ns Max t tAs, tcs for 2651 Delay from 02 of T1 to CE input 310ns Min I are satisfied 3. Delay from 02 of T3 to Ao, At, R/W changing 480ns Min 1 tAH, tcH for 2651 Delay from 02 of T3 to CE changing 200ns Max are satisfied 4. Delay from 02 of T1 to 8080A data bus valid 690ns Max I tost, toss for Time from 02 of T1 to 6060A data required 810ns Max J 8080A are satisfied

Figure 5. 8080A — 2651 Read Timing

6.4 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 INTERFACE TECHNIQUES FOR THE 2651 PCI App Note M22

T1 T2 T3 I 71 (480)

4,1

5 MIN 5 MIN IOW 45 MAX 45 MAX

0 MIN 0 MIN CE 30 MAX 30 MAX 120 MIN 883 MIN A0-A15 163 MIN

DATA FROM 8080A VALID 5 MIN 5 MIN 40 MAX 40 MAX DATA FROM 8228 VALID

2851 DATA IN SPEC H- 50 MIN 00 MIN NOTES

1. All times in nanoseconds. 4. Data available to 2651 prior to CE, therefore tos for 2651 is satisfied 2. Time prior to WR Ao, Ar, R/W valid 683ns MM 1. tAs, tcs for 2551 5. Time after WR data available at 2651 = 125ns Min I toil for 2651 Time after WR CE valid 5ns Min I are satisfied Delay from WR to CE = 75ns Maxi is satisfied 3. Time after WR Ao, Ar, R/W valid 120ns Min 1 tso, tcv for 2651 Delay from WR to CE 75ns Min are satisfied

Figure 6. 8080A — 2651 Write Timing

Z80 INTERFACE The Z80 CPU provides separate RD and WR signals to indicate read and write operations A0 A0 respectively. In addition, an MREQ signal Al Al (for memory operations) or an IORQ signal (for I/O operations) are also provided. Al- R/W though the RD signal could logically be 0 0 used as the R/W input for the 2651, with D0-D7 DB0-DB7 either MREQ or IORQ used as the CE input, 0 2851 as appropriate, the Z80 timing specifications are such that the control hold time

N MREQ OR (ORO specification (tcHl for the 2651 could not be guaranteed. RFSH OR WI HIGH ORDER CE To overcome this problem, a technique ADDRESS LINES utilizing an address line for the R/W input is FOR CHIP SELECT, AS REQUIRED recommended, as previously discussed for the 8080A interface. 74 OR 74LS SERIES Interfaces for memory mapped and I/O mapped operations are shown in Figure 7. NOTE. The M1 signal inhibits 2651 operation dur- MREO, RFSH used for memory mapped I/O ing interrupt acknowledge cycles. Similarly, ibRO, ATM used for standard I/O RFSH inhibits operation of the 2651 during memory refresh cycles. A detailed timing analysis shows that all pertinent 2651 and Figure 7. Z80 — 2651 Interface Z80 timing specifications are satisfied with the techniques illustrated.

Signetics 6.5 MICROPROCESSOR DIVISION JANUARY 1983 INTERFACE TECHNIQUES FOR THE 2654 PCI App Note M22

SC/MP II INTERFACE The bus interface signals for the SC/MP II are similar to those previously described for the 8080A and Z80, except that only memory reference operations are available. Again, a technique using an address line for the AO AO 2651 R/W input is recommended, as shown Al Al in Figure 8. All timing requirements for the A2 TI/W 2651 and SC/MP II are easily satisfied. 6800 INTERFACE DBo-DS7 < D130-087 The 6800 microprocessor provides a R/W 2651 PCI

signal which, when inverted, is suitable for It SYSTEM BUS NRDS use by the 2651. The remainder of the inter- NWDS

face logic required consists of gating of the SCIMP L appropriate bus signals to generate the CE HIGH ORDER CE signal for the 2651, as shown in Figure 9. ADDRESS LINES FOR CHIP SELECT, The only timing parameter which is not AS REQUIRED easily satisfied is the write data hold time 74 OR 74LS NAND for the 2651 (tDH), which is specified at Ons GATES minimum. The 6800 specifications guarantee only a minimum of 1Ons data hold time with respect to the DBE processor input, which is normally the 6152 clock. To guaran- Figure 8. SC/MP II — 2651 Interface tee worst-case operation, the DBE signal should be skewed with respect to cb2 to guarantee the minimum data hold time at the 2651. Consult the M6800 System De- sign Data Manual for detailed information. 8085 INTERFACE The bus signals of an 8085 microcomputer system are similar to those of the 8080A sys-

tem shown in Figure 3. The major differ- A0 ences are the multiplexing of the eight least Al significant bits of address on the data bus and the use of an 10/M control line to R!W distinguish between memory and I/O references. DElo-DB7 D6o-DB7 2651 Since a single R/W control line is not avail- PCI able, the same addressing technique for the SYSTEM BUS

2651 registers as described for the 8080A 6800 02 interface is recommended. Thus, the inter- VMA face will be similar to the one shown in HIGH ORDER CE Figure 4. ADDRESS LINES FOR CHIP SELECT, If I/O addressing is used, A0-A2 in Figure 4 AS REQUIRED can be replaced by the non-multiplexed 74 OR 74LS SERIES higher order address lines A8-A10, since the 8085 provides the I/O address on both A0- A7 and A8-A15 during an INPUT and OUT- PUT instruction. In addition, the inverted Figure 9. 6800 — 2651 Interface 10/M signal must be used as an input to the final NAND gate. If memory addressing is used for the 2651, REFERENCES A0-A2 must be obtained by demultiplexing 1. Signetics 2651 PCI Specification from the address/data bus through an exter- 2. Signetics MP8080A Microprocessor nal latch clocked by the ALE timing signal. If Specification 10 addressing is also used in the system, the 3. Signetics SC/MP II (ISP-8A/6001 Micro- M/IO signal must be used in the final NAND processor Specification gate. 4. Zilog Z80 CPU Product Specification The 8085 timing specifications are such that 5. Intel Data Catalog, 1977 all 2651 requirements are easily satisfied. 6. Intel MCS 85 User's Manual Similarly, the 2651 timing satisfies the 8085 7. Motorola M6800 Microcomputer System requirements. Design Data

6.6 Signetics MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2651 PCI WITH BISYNC App Note M24-A

The 2651 PCI supports IBM's Binary Syn- Table 1 INITIALIZATION REQUIREMENTS vs CODE SET chronous Communications (BISYNC) protocol, with SYN and DLE character stripping, CODE SET FORMAT MR15 MR14 MR13 MR12 DLE generation, and a transparent mode of operation. Please refer to the 2651 data EBCDIC 8 bits, no parity X 2 0 1 1 sheet when reading this application note. ASCII 7 bits, odd parity 0 1 1 0 SBT 1 6 bits, no parity X 0 0 0 OPERATION IN THE NORMAL (NON-TRANSPARENT) MODE NOTES Initialization 1. Six-Bit Transcode 2. X = Don't care Initialize the internal PCI mode and command registers as follows: Table 2 ERROR CHECKING REQUIREMENTS FOR BSC MR17 = 0 Double SYN (even though the same Transmission No Transparency Transparency SYN character is Code Transparency Operating Not Operating used). EBCDIC CRC-16 CRC-16 CRC-16 MR16 = 0 Non-transparent ASCII VRC-LRC CRC-16 VRC-CRC-16 mode. SBT CRC-12 CRC-12 CRC-12 MR15-12 = See table 1.

MR11-10 = 00 Synchronous mode, The processor can read SR5 after RxRDY BCC with its accumulated BCC. An equal 1X clock. goes active to indicate that the first non- comparison indicates a good reception of MR25 0 or External/Internal SYN character is in the RHR. the previous block. 1 TxC. CRC (cyclic redundancy check) is a division MR24 0 External RxC (sup- performed by the transmitting and receiving plied by modem). stations using the numeric binary value of Error Checking the message as a dividend. The dividend is MR23-20 = 0000 Set for desired baud The type of error checking depends on the initially zero. The constant divisor is either thru rate if internal TxC is information code set used: VRC and LRC are x16 + x15 + x2 + x1 (CRC-16), or X12 + 1111 used. used with non-transparent mode ASCII, X11 + X3 + X2 + X + 1 (CRC-12). The CRC-12 is used with six-bit transcode, CRC- CR7-6 00 Normal or SYN and quotient is discarded and the remainder is 16 is used with EBCDIC, and VRC and CRC- or DLE stripping mode retained as the two-byte BCC. 16 are used with ASCII if a transparent mode 01 (depends on soft- is supported. This is summarized in table 2. The BCC accumulation (LRC or CRC) is ware). reset by the first STX or SOH after line The 2651 PCI is capable of performing VRC turnaround. Thereafter, all characters ex- The SYN1 and SYN2 registers should be generation, detection and stripping. The cept SYN and DLE (but not the second DLE- loaded with the appropriate SYN character BCC (LRC or CRC) must be computed using DLE in transparent mode) are included in the for the code set in use. The DLE register software or external hardware (see section accumulation. At the end of an intermediate should be loaded if operation in the trans- on BCC Generation /Checking). block (ITB-BCC), the accumulation resets parent mode is required. and starts again with the next received STX Each block of data transmitted is error- or SOH or DLE-STX in the transparent mode. checked at the receiver. The receiving sta- SYN Character Transmission tion normally replies with ACK 0 or ACK 1 and Reception (data accepted, continue sending) or with When the PCI transmitter is initially enabled NAK (data not accepted; i.e., a transmission OPERATION IN THE (CRO = 1), the TxD output remains high until error was detected, retransmit the block). TRANSPARENT MODE the first character to be transmitted (usually There is no error correction. BSC incorporates a submode called "trans- a SYN or PAD) is loaded into the THR. Sub- parent mode." This mode allows communi- The three error-checking methods used in sequent to this, the PCI will automatically fill cation of pure data (such as binary files) conjunction with BISYNC are VRC, LRC and gaps by transmitting a character pair con- instead of information code characters. Op- CRC. These are defined below. sisting of the contents of the SYN 1 register eration in the transparent mode is initiated followed by the contents of the SYN2 regis- VRC (vertical redundancy check) is an odd- by transmission (reception) of a DLE-STX ter (DLE-SYNI in transparent mode). parity check performed on each data char- sequence and terminated by a closing DLE- acter and the LRC character. It is disabled ETX, DLE-ETB, or DLE-ITB sequence. While The receiver enters the hunt mode on a 0-to- during operation in the transparent mode. in the transparent mode, the following pro- 1 transition of RxEN (CR2). If in the normal cedures apply: mode (CR7-6 = 00), receipt of a SYN char- LRC (longitudinal redundancy check) is a acter should be checked by doing a soft- horizontal parity check on all data bits within ware comparison. If SYN /DLE stripping is the message block. It is transmitted as a • Parity (VRC) is disabled and the character selected (CR7-6 = 01), then SYN detect single BCC (block check character) immedi- length is changed to 8 bits. This applies (SR5) indicates SYN character reception ately following an ETB, ETX, or ITB charac- only to ASCII code. For EBCDIC code, since the SYN characters will be stripped. ter. The receiver compares the transmitted VRC is never enabled.

Signetics 6.7 MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2651 PCI WITH BISYNC App Note M24-A

• DLE-SYN is used for line fill instead of send DLE bit may be used. The sequence of Returning to Normal Operation SYN-SYN. operations is as follows: 1) Normal operation is resumed after a DLE- ETX, DLE-ETB, or DLE-ITB sequence is • Any control character transmitted must be 1) Set CR3 in response to TxRDY and then received or transmitted. preceded by a DLE. load THR with the control or DLE character to follow. This ensures that a DLE will 2) MR16, MR14, and MR13-12 must be • If a data byte identical to a DLE is to be precede the character loaded. changed if they were altered when enter- transmitted, it must be preceded by an- ing the transparent mode. Mode register other DLE. 2) Reset CR3 on the next TxRDY, and then 1 should be addressed with TxEN — load THR with the next character to be Transparent Mode Bit MR16 = 1 results in: RxEN = 0. transmitted. Receiver: Enables DLE stripping if CR7-6 = Alternatively, the DLE character could be 01 and a DLE is received. loaded into THR without using CR3 if there is BCC GENERATION/CHECKING Enables DLE detect bit (SR3) if a DLE is no possibility of underrun. The 2653 PGC can be effectively used as a received. • DLE detect (SR3) Status Bit parallel CRC/ LRC generator/checker and Enables SYN detect bit (SR5) on receipt of The DLE Detect bit is set when parity is also serve as a programmable single and DLE-SYN1 after synchronization has been disabled (MR 14 = 0), the transparent mode DLE two character sequence detector. Fig- achieved. is selected (MR16 = 1), and a DLE charac- ure 1 demonstrates the 2651/ 2653 bus inter has been assembled in the receiver shift terface. Consult the 2653 data sheet in or- Transmitter: DLE-SYN1 is used as line fill register. A reset error command (CR4) must der to properly utilize that device. during underrun. be issued to clear the DLE detect condition. For BISYNC non-transparent messages, the If DLE stripping is not selected (CR7-6 = 2651 can be programmed to strip received Initiating the Transparent Mode 00), then DLE detection could be done by SYN characters which are not usually software comparison on a character-by- Receiver: Detects DLE-STX sequence in stored in main memory. Stripping mode character basis. software and sets MR16, if desired. should be terminated upon the PGC's detec- If ASCII code is used, then parity control • SYN/DLE Stripping Mode tion of a BTC (block terminating character) (MR14) should be disabled, and the charac- If CR7-6 = 01 in the synchronous mode, then or a DLE-STX SCC (second search character length (MR13-12) should match the SYN and odd DLE characters are stripped ter). In the first case, a block check charac- transparent data (usually 8 bits). from the receiver holding register. The sec- ter could match a SYN; in the second case ond DLE of a DLE-DLE pair is not stripped. the PGC needs to see all received transpar- If the mode register is changed (as pre- This mode is not recommended for transparent data characters in order to calculate the scribed) to 11/2 RxC times after RxRDY ent mode. CRC/LRC and detect the BTC properly. goes active, the character being assembled in the receiver shift register will be of the new length and parity setting. Otherwise, 5,/ RM—O the new mode characteristics apply to the INTERRUPTS TxRDY, RxRDY, TxEMT/DSCHG next character to be assembled. - TuD \.7 Transmitter: Sends DLE-STX sequence DB7-DBO RxD from THR, and then sets transparent mode 2651/ (MR16). If ASCII code is used, then MR14 2661 TVW, Al, AO PCI will be disabled and MR13-12 should match TxC the transparent data character length (usu- CEO ally 8 bits). The mode register may be - RxC changed within n TxC times after TxRDY goes active, where n = the character length CPU in the non-transparent mode (assuming transparent mode character length is greater). This ensures that the character loaded into THR will be transmitted with the new 2653 character length and parity setting. CEO PGC Cal Use of PCI Transparent Mode Features INT R • Send DLE (CR3) Command 0 +5V To ensure that there is no transmitter underrun between a DLE and the control Figure 1. 2651 or 2661/2653 interface character or DLE character to follow, the

6.8 Signetics MICROPROCESSOR DIVISION JANUARY 1983 APPLICATIONS TECHNIQUES FOR THE 2651 PCI App Note M26

INTRODUCTION be construed to be constraining and the de- the PAD character will be transmitted on The Signetics 2651 Programmable Commu- signer is encouraged to develop whatever TxD before the RTS pin (23) goes high. nications Interface (PCI) is a universal interface techniques best fit his application. Asynchronous—wait for TxEMT synchronous/ asynchronous data communi- 1. Load last character into THR in response cations controller chip designed for use with PROCEDURES FOR TERMINATING to TxRDY, microcomputers and minicomputers. The TRANSMISSION 2. Mask out the TxRDY interrupt condition 2651 accepts programmed instructions from FULL DUPLEX (RTS always true) by externally disabling it. This can be a CPU and supports many serial data com- 1. Load last character into THR in response done through a gate, interrupt controller munications disciplines, both synchronous to TxRDY going active low. chip, or CPU mask flip-flop. Note that and asynchronous, in full or half-duplex, in- 2. Disable TxEN (0 CRO) in response to the TxRDY and TxEMT cannot be tied togeth- cluding IBM's Binary Synchronous Communi- next TxRDY. This will cause TxRDY and Tx- er (see Figure 1). cations Protocol (BISYNC). The reader is EMT to remain in the high state after the 3. Drop RTS in response to the next TxEMT. referred to the 2651 Data Sheet for general last character (in TxSR) is serialized. TxEMT going active indicates that the specifications and to applications memo last character has been transmitted. The M22 for interface techniques with such HALF DUPLEX (RTS true when transmit- TxD state will be marked hold one bit microprocessors as 8080A, SC /MP, Z80, ting; false otherwise) time after TxEMT goes active. 8085, and 6800. Techniques for using the Synchronous—use a closing PAD 2651 PCI to support BISYNC are detailed in 1. Load an all l's PAD character into THR in DISTINGUISHING BETWEEN application memo M24. The purpose of this response to TxRDY. At this time the pre- TxEMT AND DSCHG applications memo is to assist the designer vious (last) data character is in TxSR be- CONDITIONS by demonstrating various interface and ing serialized. The DSCHG condition goes active on a state operational procedures which have been 2. Disable TxEN as above. In this case, the change of either the DCD or DSR pin(s) pro- successful with the 2651. While we have last data character has been transmitted vided either RxEN or TxEN = 1 but not in tried to cover several possibilities in each when TxRDY goes active. local loopback mode. The DCD and DSR procedure, the techniques shown should not 3. Drop RTS (0 —CR5). One or more bits o status bits (SR6, SR7) reflect the pin status at the time the status register is read i e they are not latched. A Status Read will clear the DSCHG condition. The TxEMT condition goes active during transmitter underrun. The condition is immediately reset when a character is loaded into THR. It is reset after the linefill is sent once the transmitter is disabled (TxEN = 0). Since both of these conditions share a pin (18) and a status register bit (SR2), it is necessary to determine which or both conditions are present when the pin /status bit is Figure 1. PC Interrupt Requests IRI and IR2 When TxEMT/DSCHG Must be active (Figure 2). Separated From TxRDY

( READ STATUS REGISTER SR2,1

HAS PROCESS DCD (SR13) YES OR DSR (SR7) THE STATE CHANGED CHANGED AS STATE? REQUIRED YES

SERVICE UNDERRUN AS REQUIRED

I( CONTINUE )

Figure 2. Flowchart to Distinguish Between TxEMT & DSCHG

Signetics 6.9 MICROPROCESSOR DIVISION JANUARY 1983 APPLICATIONS TECHNIQUES FOR THE 2651 PCI App Note M26

GENERATING CORRECT INITIALIZATION STATE OF TxD After a power-on or RESET all Mode register bits will be zero. Specifically, MR25 will select external TxC. The TxD pin requires at least one high to low transition on TxC for TxD to go high. Without a TxC input, a break (all zeros) may be transmitted. This presents a problem in asynchronous mode when using the internal BRG (MR25 = 1). To circumvent the problem, the user may take one of the following actions: a) Generate one high to low transition on TxC during a power on or RESET. b) Input a system clock or the BRCLK into TxC through a 1K resistor. MR 25=1 c) Inclusive OR RTS and TxD to produce ACTIVE LOW the Tx serial data to the modem. d) Use external logic (Figure 3) to insure Figure 3. Logic to Guarantee TxD =1 on Power Up or Reset TxD comes up in the "1" state. USING THE PCI BEYOND THE SPECIFIED SERIAL DATA RATE If local loopback is not required, the PCI will operate correctly if the RxC high and low times are equal to or greater than 500 ns. A 1 Mbps DC baseband link between two PCI's is therefore quite acceptable. The only requirement is a synchronizing flip flop at the transmitter to compensate for the uncertainty in tTXD, the TxD delay from the falling edge of TxC. That time can be anywhere from 150 ns to 650 ns (Fig. 4).

ANALYSIS OF PULL UP RESISTOR 1. Rx min: wish to maintain acceptable "0" VALUES FOR 2651 PCI WIRE-OR V output. OF OPEN DRAIN OUTPUTS VCC max — VOL max Rxmin This discussion is intended to assist the lOLmax lIL ttP user in determining pull up resistor values for (5.25 — .45) volts 4.8 open drain output TxRDY, RxRDY, 1,12 TxEMT/DSCHG shown in Figure 1 (Rx, Ry). (1.6 + .01)mA 1.61 only one output sinking (low) =31(1) 2. Rx max: wish to maintain acceptable "1" V output.

VCC max — VON min (4.75 — 2.4)V Rxmax = —117.5k11 3 x lOH lIL (3x.01 — .01)mA all outputs sourcing (high)

6.10 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER App Note 400

INTRODUCTION per second. The PGC is a device that The block check character (BCC), which When transferring data via a data commu- monitors parallel data transferred be- the 2653 computes from monitoring the 8- nications link using any protocol, the only tween a CPU or memory and a serial bit data bus, takes the form of a cyclic way to ensure a correct transfer is to per- receiver/transmitter (R/T, UART, USRT, redundancy check (CRC) on specified form error checking on the messages etc.) or other bus oriented device. Opera- characters. The CRC is a reliable method being exchanged. Error checking can be tion is two-way alternate (half-duplex) in of detecting errors in received serial data accomplished through vertical, longi- that the PGC is selected to receive streams and is employed in almost all syn- tudinal and cyclic redundancy checks, characters either from the R/T or from the chronous data communications protocols. special character recognition and CPU. Full duplex operation is achieved by The PGC can compute the BCC in four transparent operating modes. If the error using two PGCs. A unique feature of the modes: BISYNC normal, BISYNC checking is performed correctly, the 2653 is its 'character class array', a 128x2 transparent, automatic accumulate, and result is an accurate transfer of data from RAM which is used to classify received single accumulate. In each of these station to station. The checking technique characters into one of four types - normal, modes, one of three error polynomials can be performed by software only, but sync/not included, block terminating (CRC-16, CRC-12, and LRC-8) can be this may result in a reduction of the max- character, and secondary search selected. In either of the BISYNC modes, imum channel speed, may reduce the character. The received characters may the 'intelligence' provided by the number of channels which can be handled be block checked and/or compared to the character comparison capability within by the CPU, or may limit the supplemen- special characters preloaded into the the chip enables it to know which charac- tary tasks which can be performed by the character class array. In addition to the ters to include and which to exclude from CPU. The most efficient way to accom- block check character (BCC) generation, the BCC accumulation. Additionally, block plish error checking is to use a combina- the PGC is capable of single character terminating characters can be detected as tion of hardware and software. detection, two character sequence detec- well as the initiation and termination of tion and parity generation and checking. BISYNC transparent mode. As a result, it The Signetics 2653 Polynomial Generator All operating modes are software can handle character oriented processing and Checker (PGC) is designed to provide programmable and can be changed for for IBM BISYNC, ANSI 3.28, ISO 1745, the above error checking capability while each application. Figure 1 illustrates the DEC DDCMP, and other disciplines. 6 operating with asynchronous, syn- block diagram of the PGC, while figure 2 chronous or parallel receivers or transmit- describes the formats of the registers 1See the 2653 data sheet for full opera- ters at a speed of up to 500K characters used to program its operation.1 tional description.

DATA BUS DO-D7 CHARACTER REGISTER BUFFER DATA BUS

DLE OLE DETECT BCC AND VRC INTR OPERATION CONTROL GENERATION UNIT AO MODE REGISTER Al 16 COMMAND REGISTER CE1 STATUS REGISTER k/W O CEO BCC UPPER BCC LOWER

CHARACTER CLASS ARRAY 0

Figure 1. Block Diagram

Signetics 6.11 MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER App Note 400

MR7 MR6 MR5 MR4 MR3 MR2 MRI MRO

•••••••.„,•. • ACCUMULATION MODES BCC POLYNOMIAL 00 SINGLE 00 START UP MODE 01 AUTOMATIC 01 CRC•16 10 BISYNC NORMAL 10 CRC.12 11 BISYNC TRANSPARENT 11 LRC•8

ODD/EVEN PARITY RECEIVEJTRANSM IT 0 ODD 0 RECEIVE 1 EVEN 1 TRANSMIT

VRC ENABLE ENABLE ACCUMULATION (.1) WITH CEI (=1) MODE REGISTER

CR7 CR6 CR5 CR4 CR3 CR2 CR1 CRO

`••••• •••=, SECOND SEARCH CHARACTER I--- ONETIME COMMANDS DETECT INTERRUPT 00 NOP ENABLE= 1 01 START ACCUMULATION 10 CLEAR BCC REGISTER 11 MASTER RESET

BTCISC DETECT INTERRUPT ENABLE = 1 CHARACTER CLASS 00 NORMAL CLASS 01 SYN/NI CLASS 10 BTCISC CLASS 11 SSC CLASS VRC ERROR INTERRUPT ENABLE= I

BCC ERROR INTERRUPT ENABLE= 1

COMMAND REGISTER

SR7 SR6 505 SR4 SR3 SR2 SRI SRO

CR7 BCC ERROR ( = 1)

CR6 VRC ERROR (=

CR5 BTCISC DETECT (.1)

CR4 SSC DETECT (=1) STATUS REGISTER

Figure 2. PGC Register Bit Formats

6.12 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER App Note 400

A companion chip, the Signetics 2661 Enhanced Programmable Communica- tions Interface (EPCI), directly combines SYN SYN SOH Header STX Text with the 2653 to effect a synchronous/ ETX BCC asynchronous character oriented commu- LRC-8, CRC-12, or nications link. If a complete multi-protocol CRC-16, depending interface is desired, it can be obtained on character code (ASCII, using the PGC in conjunction with the Sig- netics 2652 Multi-Protocol Communica- transcode, EBCDIC) tions Controller (MPCC). Figure 3. Bisync Text Message Format PROTOCOLS Protocols provide the necessary ground rules to assure the orderly and accurate 3. Identify sender and receiver through means of identifying pure data characters transfer of data between digital equip- polling or selection. from the characters of the information ments. Data communications protocols 4. Handle special control functions such code set. For example, packed BCD, float- are becoming increasingly important as as requests for status, station reset, ing point numbers or memory image data the terminal population increases, dis- reset acknowledge, start, start ac- would be sent in the transparent mode tributed processing becomes widespread, knowledge, and disconnect. such that the receiver would not interpret and new communications technologies, that data as code set characters. such as packet switching and satellite Data link controls can be classified into Transparent mode is initiated by the se- links, become commonplace. character oriented protocols (COPs) and quence DLE-STX and terminated by a DLE bit oriented protocols (BOPS). COPs can followed by a block terminating character The protocols associated with the data be further subdivided into byte control (ETX, ETB, ITB, or ENO). communications have been classified into protocols (BCPs) and character count pro- 6 several major levels, or layers, that define tocols (CCPs). Byte controlled protocols utilize a stop and various functions and operations. Each wait automatic repeat request (ARQ) level is designed to be functionally inde- which limits operation to two way alternate pendent of the others, but each depends (half duplex). Each transmitted message on the correct operation of the previous BYTE CONTROL PROTOCOLS block must be acknowledged before the level to operate. The protocols embodied In BCPs, a defined set of communication next message may be sent. A negative ac- in these levels range from those that control characters effects the orderly knowledgement is achieved by sending a define the physical and electrical links, operation of the data link. IBM BISYNC, NAK, a positive acknowledgement is sent e.g. RS232C and CCITT V.35, to those ANSI 3.28 and ISO 1745 are all byte con- as an ACKO or ACK1 for even and odd which are responsible for functions such trolled. Control characters and two blocks respectively. The acknowledge- as message buffering, code conversion, character sequences configure and ment is sent after one or more Block recognizing and reporting faulty condi- manage the data link between sender and Check Characters (BCCs) have been tions in terminals or lines, communication receiver. Control messages or acknowl- received and checked (one character for with the host mainframe, and management edgements consist of one or two charac- LRC-8, two characters for CRC-12 or of the communication network. These pro- ters while data messages usually contain CRC-16). Table 1 presents error checking tocols are implemented by software less than 1,000 characters. For text requirements for byte controlled pro- packages such as IBM's Systems Network messages, shown in figure 3, an optional tocols. Architecture (SNA), CCITT's X.25, and header may precede each text (informa- DEC's DECnet. tion) block. The entire message block is For control and acknowledgement error checked based on the information messages the receiving processor must In the remainder of this application note, code set used (ASCII, EBCDIC, SBT) and detect various single and two character we shall concern ourselves with data link the operational status of a transparent text sequences. These are defined in tables 2 control protocols (DLC's), which are the mode. The transparent text mode is a and 3. sets of rules necessary for effective communications between terminals and computers over conventional communications Table 1 ERROR CHECKING REQUIREMENTS FOR channels. DLC's are concerned with han- BISYNC/ANSI 3.28 dling the communications link itself and moving information across it efficiently Information No Transparency Transparency and accurately. Code Transparency Operating Not Operating

The basic functions of a DLC are to: 1. Establish and terminate a connection EBCDIC CRC-16 CRC-16 CRC-16 between two stations. ASCII VRC-LRC CRC-16 VRC-CRC-16 2. Assure message integrity through error SBT CRC-12 CRC-12 CRC-12 detection, requests for retransmission, and positive or negative acknowledg- ments. Signetics 6.13 MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER App Note 400

Table 2 COMMUNICATION CONTROL CHARACTERS FOR BISYNC

Mnemonic Name Function

SOH Start of heading Start of message which is used as heading. STX Start of text Start of any message. Information code characters follow. ETX End of text Signals the end of a text. BCC(s) follow. ETB End of transmittal block Signals the end of a transmittal block. BCC(s) follow. EOT End of transmission If used by the master, it signals the end of a transmission. As a slave response, it indicates an abnormal termination of the transmission (abort). In multipoint systems, it is used by the control station to activate address decoding functions within the tributary stations. NAK Negative acknowledgement Signals back to the master station that the last data block was not accepted. It may also represent a negative response to an initialize sequence, i.e. not ready. ENQ Enquiry Request to send back status, or abort a block of transmitted data. Also used by the master station to end a polling sequence. !TB Intermediate block Blocks of the received message are released to the program via intermediate interrupts for faster processing. BCC(s) follow the ITB. DLE Data link escape Used as leader in control sequences (see table 3). ACK Acknowledgement Used as DLE trailers in control sequences (see table 3). SYN Synchronization character SYN-SYN establishes character synchronization. Inserted automatically into the data stream by the transmitter. Does not enter main storage of the receiver.

Table 3 BISYNC CONTROL CHARACTER SEQUENCES

Mnemonic Function

DLE-RVI Indicates to the transmitting statlbn that the receiving station wants to transmit data. Implies acknowledgement of last received block. DLE-SAK Indicates to the transmitter that the last message was received free of errors, but the receiver cannot continue. DLE-STX Enters transparent text mode. Allows all 256 characters to be used as data. DLE-EOT Disconnect sequence on a switched network. DLE-ETX End-of-text signal in transparent mode. BCCs follow. DLE-ETB End-of-transmittal-block signal in transparent mode. BCCs follow. DLE-ITB Intermediate-block-checking signal in transparent text mode. BCCs follow. DLE-0/1 Used as positive reply to even/odd blocks respectively. DLE-ENQ Aborts block of transparent data. BCCs do not follow. SYN-SYN Establishes character synchronization. Automatically inserted into the data stream during underrun in normal text mode. Used to maintain synchronization, and to recognize line interruptions. Does not enter main storage of receiver. DLE-SYN Automatically inserted into the data stream during underrun in transparent text mode. Used to maintain synchronization, and to recognize line interruptions. Does not enter main storage of receiver. DLE-WBT Signals to the transmitting station that the last block was received correctly, but the receiver cannot continue immediately because other operations have to be performed first. STX-ENQ Temporary text delay. Abort sequence used by the master station to announce an abnormal termination of the transmission.

6.14 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER App Note 400

Character Count Protocols Bit Oriented Protocols 2653 FUNCTIONS AND Digital Equipment Corporation's DDCMP APPLICATIONS and its associated versions used by Bell BOPs make use of only two or three spe- Labs are character count protocols. A cific control characters for operation of BCC Accumulation character count specifies the number of the data link. These characters are used to data characters in the information field of delimit the beginning (FLAG) and end The primary function of the PGC is the ac- a message: positional significance is used (FLAG, ABORT, GA) of a message frame. cumulation of the BCC for character to identify control information in the Upon receipt of the opening FLAG, posi- oriented protocol (BCP and CCP) header of the block which is verified by a tional signficance is used to delineate the messages. As described previously, there separate cyclic redundancy check. There bit sequence that follows into prescribed are four modes of BCC accumulation and are three control characters in DDCMP fields, as shown in figure 5. These fields each mode can select one of three (SOH, ENQ, DLE) - each identifies the start area address, control, information, and generating polynomials to compute the of a different type of message. Figure 4 frame check sequence. The address, con- BCC(s). The polynomials are x16+ depicts the DDCMP text message format. trol, and frame check field are fixed length; x18+x2+ 1 (CRC-16), x12+x3+x2+x + 1 the information field is variable and may be (CRC-12), and x8+1 (LRC-8). The four ac- A "go back N blocks" type of error control zero. Examples of BOPs are IBM's Syn- cumulation modes are BISYNC normal, is used in this protocol. Up to 255 blocks chronous Data Link Control (SDLC), BISYNC transparent, automatic accumu- may remain outstanding before an ac- ANSI's Advanced Data Communication late and single accumulate. knowledgement is required. This is Control Procedures (ADCCP), ISO's High- achieved by separate 8-bit send and Level Data Link Control (HDLG), Bur- In BISYNC normal mode, all characters receive block counts. When an acknowl- roughs' Data Link Control (BDLC), and loaded into the PGC's character register edgement is sent the received block count various other protocols developed by com- are accumulated except those in the SYN/ indicates the number of message blocks puter mainframe manufacturers. All of the Not Included class. During receive opera- correctly received. This is compared with above mentioned protocols are similar and tions, a detected block terminating the send block count. The difference, if can be treated as subsets of ADCCP. character (BTC) will cause the BCC ac- any, is the number of blocks that must be BOPs also utilize a "go back N" type of cumulation to stop after the next one retransmitted. error control. (LRC-8) or two (CRC-12 or CRC-16)

SYN SYN SOH Count Flags Response Sequence Address CRC-16 Information CRC-16 (14 bits) (2 bits) (8 bits) (8 bits) (8 bits) (16 bits) (any number (16 bits) of 8 bit characters)

Figure 4. DDCMP Message Format

Header

Flag Address Control Information FCS Flag (8 bits) (any number (16 bits, (8 bits) of bits) CRC-CCITT, inverted remainder)

4 Zero insertion/deletion, CRC accumulation 1

Figure 5. Bit Oriented Protocol (BOP) Message Format

Signetics 6.15 MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER App Note 400

characters have been accumulated. At In Single accumulate mode all characters Figure 9 depicts an arrangement where that time, if the BCC accumulation does are accumulated, but only after an ac- the DMA controller or slave CPU handles not equal zero there has been a block cumulate command is given by the CPU. If data bus transfers, the PGC interrogates check error. The BCC error bit will be set not given, the BCC accumulation is stop- the data bus, and the host CPU responds and an interrupt generated if the corre- ped. Operation in this mode is otherwise to PGC interrupts. sponding mask bit was enabled. In identical to automatic accumulate. Single transmit mode, the BCC accumulation is accumulate mode can be used to selec- c. BUS PARITY CHECKER automatically stopped once the BTC tively accumulate characters under CPU The PGC can be used to check the parity character has been accumulated. The control or to accumulate characters that of transactions on a system's data bus. CPU must read the BCC upper and BCC were unintentionally excluded in one of The processor first writes control informa- lower (for CRC-12 or CRC-16 only) the other modes. tion into the PGC via the CE1 pin. All other register(s) and transmit them to the R/T or bus operations are then checked for parity parallel peripheral. Since the accumula- with external address decoding used to tion has been stopped, the transfer of the Figures 6 and 7 illustrate the operation of generate an active low CEO. Bus parity first BCC to the R/T will not effect BCC the 2653 on various types of text and con- checking is useful in data transfers be- lower. This assures that the second BCC trol messages. tween CPU and peripherals or memory will be correct when it is read by the CPU. and CPU. Some computers check parity on both halves of a 16-bit word during all Note that BCCs are not checked against system bus transfers. the character class array nor are they Some Other Applications compared to the DLE ROM. This prevents The PGC can be employed in a variety of false character detections when transmit- applications other than a dedicated BCC ting or receiving BCCs. generator for a single channel. For exam- MULTI-PROTOCOL ple, it can be multiplexed among several SYNCHRONOUS CHIP SET Second search character (SSC) detection data channels, used as a programmable The Signetics 2652 Multi-Protocol Com- is enabled in BISYNC normal allowing a character comparator or it can be used to munications Controller (2652), originally two character communication control se- check parity on a system address or data targeted for bit oriented protocols and quence such as DLE-STX to be detected. bus. A brief description of each of these DDCMP, can send and receive EBCDIC, applications is given below. ASCII, and SBT data. However, the 2652 In BISYNC transparent mode characters doesn't support many of the functions of excluded from the BCC accumulation are a. MULTIPLEXED PGC byte controlled protocols. In particular, the the first DLE of a DLE-DLE pair, the DLE of One PGC may be time-shared among a 2652 has no way of knowing which a DLE-BTC pair, or DLE-SYN sequences few R/T's if the CPU saves and restores characters to include or exclude in the (the SYN is also excluded). the mode register and partial BCC result in BCC accumulation. This makes the on the BCC registers. These registers are ac- board CRC-16 generator/checker useless In receive and transmit modes, the ter- cessed via CEI. There must be separate for BISYNC. Furthermore, there are no mination of BCC accumulation works save area for each HIT (serial channel) provisions in the 2652 for transparent exactly as in BISYNC normal, except that and a channel pointer indicating the last mode DLE handling, special character the BTC must be immediately preceded by R/T that transferred or received a data detection or two character sequence an odd number of DLEs to be properly character (see figure 8). detection. But the PGC encompases all of identified. these missing functions! Thus, the 2652 - The loading of the BCC registers will clear 2653 combination can totally support Second search character detection is not SRO-SR3 and all previously detected spe- character controlled protocols as well as enabled in BISYNC transparent since cial characters, i.e., DLE, BTC/SC, BCC bit oriented and character count discip- DLE-SSC sequences are only valid in (BISYNC modes). The BCC accumulation lines. The PGC can be used for single BISYNC normal mode. will start again when the next character is character compares in SDLC/HDLC or loaded into the character register in all ac- DDCMP applications to reduce software In Automatic accumulate mode all charac- cumulation modes except single. That overhead. ters loaded into the character register are mode requires a start accumulation com- accumulated; BTC and SSC detection is mand. As shown in figure 10, only a single enabled and the BCC accumulation is not inverter is required to interface the 2652 automatically terminated. The CPU must b. CHARACTER COMPARATOR and 2653 such that 2652 data bus use single accumulate mode to stop the The PGC can be used as a programmable transfers are monitored. accumulation. When in receive mode, the data bus character comparator which BCC error bit is set/reset after accumulat- monitors data bus character transfers ing each character so that the CPU must (CPU to peripheral, CPU to CPU, CPU to A BISYNC/ASYNC CHIP SET examine this bit after the last character is memory, memory to peripheral via DMA). Although the 2653 complements any R/T accumulated. The user selectively loads the character in the support of character controlled pro- class array with BTC/SC and SSC charac- tocols it is optimized for use with the Sig- Examples of use of the automatic accumu- ters to be compared. Status bits will be set netics 2661 Enhanced Programmable late mode are a system where the R/T and an interrupt can be generated upon Communications Interface (EPCI). That (2651/2661) operates with DLE/SYN SC and DLE-SSC detection. A match on device is a USART with on chip baud rate stripping or in support of character count one to 128 different characters or DLE- generator that has special features for protocols such as DDCMP. SSC sequences can be programmed. BISYNC. There are two loadable SYN

6.16 Signetics MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER App Note 400

SHADED AREAS ACCUMULATED CHARACTER CLASS ARRAY: Rx = RECEIVE MODE SYNIBISYNC NOT INCLUDED: SYN, SOH NO DLE/SYN STRIPPING BTC/SC: ETX, ETB, ITB, ENO SSC: STX CRC-l6 OR CRC-12

SYN SYN SOH PAD 4 SET BISYNC BTC BCC ERROR (Rx) IF ACCUMULATION x 0. NORMAL MODE DETECT ACCUMULATION STOPPED AFTER 2nd (ALL EXAMPLES) BCC. NO PARITY CHECK ON BCCs

LRC.8

SYN SYN C 2. SYN SYN PAD

CPU RESETS BCC REGISTERS BTC BCC ERROR (Rx) IF 7 LS BITS OF BCCo x 0. AFTER SOFTWARE DETECT DETECT VRC ERROR IF MS BIT IS INCORRECT OF STX. THIS EFFECTIVELY PARITY. ACCUMULATION STOPPED EXCLUDES STX. AFTER 1 BCC.

BLOCK 1 BLOCK 2

SYN SYN SOH C BCC: SYN SYN six A DLE ETX BCC BCC PAD 4 4 BTC OPTIONAL SSC DETECT BTC POSSIBLE DETECT SET BISYNC DETECT BCC ERROR TRANSPARENT

POSSIBLE BCC ERROR. (IF SO RESET BCC REGISTERS). RESET BCC REGISTERS OR SET BISYNC NORMAL

SYN SYN SOH DLE STX ENO ETB ITB. ETX .IDLE iDqs1DLE SYN DLE lijOBCCEa1PAD 1 SSC DETECT BTC POSSIBLE SET BISYNC DETECT BCC ERROR TRANSPARENT MODE

BLOCK 1 BLOCK 2

SYN SYN DLE SYN I DLE FE1111DLEIIT BIBCCI8C++.4ETXIBCCFCC1 PAD

SSC BTC POSSIBLE BTC DETECT DETECT BCC ERROR DETECT

SET BISYNC POSSIBLE TRANSPARENT AND RESET BCC BCC ERROR RESET BCC REGISTERS REGISTERS (IF BCC ERROR) NOTES AND SET BISYNC 1. BCC error only for receive mode. In transmit mode, CPU must respond to BTC detect by NORMAL reading the BCC register(s) and sending them to the R /T. The accumulation is stopped after the BTC is accumulated. 2. ENO (DLE-ENO) in a text message should be treated as an abort. 3. Opening SYNs may be stripped by the RIT. 4. The single accumulate mode and command can be used to accumulate a character that inadvertently was excluded. (For example, the DLE of a DLE-STX if the PGC was in transparent mode and there was not a line turnaround prior to the DLE). The single accumulation should be done using CEI after the BCC(s) have been accumulated. Figure 6. Examples — Bisync Text Message BCC Accumulation Signetics 6.17 MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER App Note 400

BTCISC: EOT, NAK SCC: ACKO, ACK1, WACK, RVI SINGLE ACCUMULATION MODE STOPS BCC ACCUMULATION CONTROL STATION POLL OR 1. SYN SYN 1E011 PAD I SYN SYN a END SELECTION OF A TRIBUTARY STATION

BTCISC BTCISC DETECT DETECT cx REPRESENTS A UNIQUE POLLING OR SELECTION ADDRESS TRIBUTARY STATION PREPARED 2. SYN SYN I ACK 0 TO RECEIVE OR POSITIVE ACKNOWLEDGEMENT OF EVEN NUMBERED TEXT BLOCK SCC DETECT

TRIBUTARY STATION NOT READY 3. SYN SYN NAK I PAD TO RECEIVE OR NEGATIVE ACKNOWLEDGEMENT OF TEXT BLOCK

BTCISC DETECT

TRIBUTARY STATION TEMPORARILY 4. SYN SYN I WACK NOT READY TO RECEIVE 4 SCC DETECT REVERSE INTERRUPT FROM 5. SYN SYN I RVI RECEIVING STATION TO REQUEST TERMINATION OF THE CURRENT TRANSMISSION BECAUSE THE RECEIVER WANTS TO TRANSMIT SSC DETECT NOTES 1. BCC accumulation should be ignored for control messages. This can be effected by single accumulate mode without single accumulate commands. 2. Characters programmed as SSCs should be the binary equivalent of the second character of the DLE-SSC sequence. Figure 7. Examples — Bisync Control Messages

registers and a loadable DLE Register in A Send DLE command in the 2661's required when receiving and transmitting the EPCI. Figure 11 is a schematic show- transmitter can be used to prevent a pos- BISYNC text messages in both normal and ing the 2653 and 2661 interfaced to an 8- sible underrun between the DLE and a transparent modes of operation. It is not bit CPU. subsequent control character. Such an implied that the actual software program to underrun would cause an incorrect control handle these tasks necessarily follow the A transparent operating mode causes the sequence to be transmitted. For example, flow charts step by step. In an actual EPCI to automatically change the detected consider an underrun between a DLE- application, an interrupt driven structure synchronization sequence and underrun STX, the sequence used to enter would be more appropriate. Assumptions linef ill from SYN-SYN to DLE-SYN. This is transparent mode. The transmitted se- are half-duplex operation (normal for the necessary to prevent an unrecoverable quence becomes DLE-SYN-SYN-STX. But BISYNC protocol) and use of the EBCDIC problem at the receiver. If a USART sent or a DLE-SYN is illegal unless transparent code. received the normal mode SYN-SYN se- mode has been entered. Furthermore, the quence it would be interpreted as STX would set normal text mode not The receive flow, figure 12, starts with ini- transparent data rather than actual syn- transparent mode. tialization of the PGC and EPCI for the nor- chronization information. mal mode. Modem handshaking is then performed. Upon detection of carrier, indi- Another transparent mode function is FLOW CHARTS FOR BISYNC cated by assertion of the 2661's DCD sta- detecting and stripping received DLE's. OPERATION tus bit, the receiver is enabled, the PGC is Normally a software job, this task is com- Figures 12 through 15 illustrate functional setup for receive, and miscellaneous flags pletely and properly handled by the 2661. flow charts for the operation of the 2653 - are reset. Data is then read from the 2661 The DLE Detect status bit is even au- 2661 pair in BISYNC. The intent of these receive holding register and acted upon tomatically reset at the proper time. flow charts is to illustrate the procedures according to the BISYNC protocol. The

6.18 Signetics MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER App Note 400

ADDRESS DATA RIW TxD REC/XMT RxD CEO READ/WRITE MEMORY ► TxD > REC/XMT o- RxD CEO

ToO RECIXMT RxD ADDRESS, DATA, 111W, CEO /.\ ADDR CPU DATA RIW CEI \•7

PGC INT

ONE PGC IS TIME-SHARED BY THREE /Ts. THE CPU READS AND RESTORES THE PARTIAL BCC REMAINDER FOR EACH SERIAL CHANNEL. Figure 8. PGC Services Multiple Receivers/Transmitters

INT AO, A1, RIW

CEI PGC

PERIPHERAL DEVICE

CPU DATA BUS 8/

SLAVE CPU C

RIW MEMORY

MA, MC APPLICATIONS INCLUDE CHARACTER ARRAY COMPARISIONS, VRC ANDIOR BCC CHECKS ON THE DATA BUS. DMA• CONTROLLER ED NOTE •CPU initializes DMA controller for each block transfer of data.

Figure 9. PGC Data Bus Monitoring with DMA Transfers

Signetics 6.19 MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER App Note 400

INTERRUPTS TxBE, TxU, RxOA, RxSA

DB7-DBO 2652 TxD 41101/11/ 10. MPCC

A2 RxD Al AO TxC 61W DBEN RxC CE CPU DB7-DBO

CEO

2653 1111111.. Al PGC 14/W AO CE1

INT (OPEN DRAIN) +5V

Figure 10. 2652/2653 Interface — Typical Protocols: BISYNC, DDCMP, SDLC, HDLC

Figure 11. 2651 or 266112653 Interface

6.20 Signetics MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER App Note 400

PGC status flags are utilized to determine must remove the extraneous DLEs which After initialization of the PGC and EPCI if and when the transmission switches to may be imbedded in a transparent block of and establishment of the modem connec- transparent mode, and to determine the text. tion, the data is pulled from the buffer and receipt of a block terminating character transmitted. If a DLE is detected in the (BTC). The two characters following the The transmit flow chart, figure 13, oper- data stream, and that character is part of a BTC are the Block Check Character. After ates on a block of data placed in a buffer two character control sequence, the 'send these are received, the PGC status area by the controlling CPU. This data DLE' feature of the PCI is used to avoid register is examined to determine if a BCC must include the SYNs to be sent at the underrun between the two characters. error has occured. initiation of transmission and the DLEs Since the DLE is not transferred to the that form part of a two character control EPCI via the data bus, this requires that an The data stored in the buffer will be strip- sequence. DLEs in a transparent block of extra DLE be accumulated in the PGC. ped of all sync characters. DLEs are not text need not be doubled up - the EPCI will This is done by use of the PGC's capability stripped. Although the 2661 includes a automatically add a DLE if one is loaded to accumulate characters loaded via CE1. DLE stripping capability, this feature is not into its THR while operating in transparent When a BTC is detected by the PGC, the employed because the DLEs must be mode. A character counter assists the two BCC characters are read from the 'seen' by the PGC in order for it to ac- software to determine when a DLE is really BCC registers and transferred to the EPCI cumulate the BCC correctly. The CPU part of a BTC (in transparent mode). for transmission.

Signetics 6.21 MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER App Note 400

IS THIS THE SECOND BCC ( START ) CHARACTER?

WRITE PGC WRITE PCI RESET ENABLE RX OR CR BCC NON-STRIPPING DATA = 02 SET READ PGC DATA = 06 (NOTE 6) SEE FIG. 14 INITIALIZE B2FLAG STATUS PCI

SET FIRST INITIALIZE SET NON-SYNC BUFFER FFLAG RECEIVED INITIALIZE POINTER (NOTE 1) FLAG SEE FIG. 15 BCC PGC AND RESET FFLAG, TFLAG, ERROR, 81 FLAG, EFLAG

WRITE PCI O TEST ASSERT DTR CR FOR SYNC DATA = 02 IN TRANSPARENT MODE? READ PCI READ PGC STATUS STATUS READ PCI STATUS READ PCI STATUS TEST RSRDY SSC DETECT? (NOTE 2) SYN DETECT? 0 SET TFLAG SWITCH TEST DSR READ PCI GET PGC AND CHARACTER BTC WRITE PCI RHR PCI TO DETECT? MRI DECREMENT DATA =4C TRANSPARENT BUFFER MODE, SET POINTER WRITE PGC TRANSPARENT SET UP TO MR SET BIFLAG MODE FLAG READ PCI RECEIVE DATA = Cl (NOTE 3) STATUS CLEAR BCC FIRS* B2FLAG 43>WAITING 0 NON-SYNC 0 FOR RECEIVED? INCREMENT BCC? POINTER AND 0 TEST STORE FOR CHARACTER TEST DCD SYNC TEST IN BUFFER FOR ABORT BISYNC WRITE PGC TEST GO TO NORMAL MR CHAR ABORT RECEIVE FOR DLE DATA = 81 =10 ROUTINE CRC.16 (NOTE 5)

Figure 12. Bisync Receive Flow Chart

6.22 Signetics MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER App Note 400

BISYNC RECEIVE FLOW CHART NOTES GET LAST CHARACTER FROM BUFFER 1. FFLAG = the first non-sync character has been received

TFLAG = operating in transparent mode

TEST EFLAG = BCC or PAD error. FOR ITB B1 FLAG = Received block terminating character (BTC). Awaiting BCC. RESET TFLAG, BIFLAG B2FLAG = Received first BCC character. Awaiting WRITE PCI INITIALIZE second BCC. MRI FLAGS FOR 2. SSC detect is disabled by PGC while in transparent mode. DATA = OC NEXT BLOCK, RESET BCC, 3. Pointer is decremented to overwrite previously stored WRITE PGC SWITCH TO 'DLE' which was part of a 'DLE-SYN' line fill. CR BISYNC NORMAL DATA = 02 MODE 4. Test for closing PAD of at least four ones at end of WRITE PGC message. MR 5. If first non-sync character is a 'DLE', the message will start DATA = 81 READ PCI with 'DLE-STX' (transparent mode). FFLAG is not set in this STATUS case since both these characters are excluded from the accumulation.

6. First non-sync character of a new message, or first two if message starts in transparent mode, are excluded from the BCC accumulation.

NEGATE DTR. DISABLE RX

Figure 12. Bisync Receive Flow Chart (Continued)

Signetics 6.23 MICROPROCESSOR DIVISION JANUARY 1983

USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER App Note 400

TRANSPARENT OD

READ PCI STATUS •

TEST FOR SET FFLAG NOTE 21 TEST TXRDY

GET CHARACTER FROM BUFFER, WRITE PCI SET CR INCREMENT END CLE' WRIg PCI DATA = 25 SET 7a,747° DATA = 2B 'SEND DLE OUNTER ' WRIT E NORMALLY CHARACTER TO OR PCI THR WRITE CHARACTER FIRST TO NOSYNC V PCI THR SENT, WRITE TO PGC ACCUMULATE WRITE ?GC RESET CHARACTER CR INTO THE BCC DATA = 02 NOTE 31 T'gg DATA = 10 WRITE POO RESET CR TEST FOR DATA 02 (NOTE 3)

WRITE TEST FOR CHARACTER TO (NOTE 21 O PCI THF1

NOTE 6)

SET TFLAG

WRITE PCI SET INOTE 41 MR1 DFLAG SWITCH PGC DATA = TRANSPARENT WRITE PGC MODE, SET MR TRANSPARENT DATA = CD MODE FLAG

RESET DELA°

INITIAL!. BUFFER POINTER AND CHARACTER COUNTER, RESET WRITE FFLAC, TFLAG CHARACTER DFLAG TO PCI THR

Figure 13. Bisync Transmit Flow Chart

6.24 Signetics MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER App Note 400

LAST BTCTEST WAS IF .ITB VVRITE CHARACTER CHAR PCITO THR RESETAND DFLAG TFLAG READ PCI WRITE PCI STAT. DATAMR1 OC WRITE PGC DATAMR - 60 TEST WRITECR PGG • DETECTBTO , TXRDY DATA = 02 WRITEPGC THR TO CLOSINGTRANSAirl BUFFITX&ER DATA = FF FORAND NEXT COUNTER BLOCK READSTATUS PCI

READSTAT. PCI TXRDYTEST

READ PGC REGISTERBCC TRANSMIT WRITEPCI THR TO (NOTES) WRITE TO DATAPCI CR 00 DISABLEET rATN'D TXR T S READSTATUS PCI

TXRDYTEST BISYNC TRANSMIT FLOW CHART NOTES

1. Transmitter will not operate until Clear to Send (CTS) input is asserted. READ PGC 2. A DLE at this point in the transmit sequence can only be followed by an STX, which will place the system in REGISTERBCC TRANSMIT transparent mode. The 'Send DLE' capability of the PCI is used in order to prevent underrun between the DLE and BCC STX characters, and possible misinterpretation of the sequence by the receiving station, WRITE TO PCI LOWER 3. First non-sync character of a new message, or first two if message starts in transparent mode, are excluded from THR the BCC accumulation. 4. DFLAG is used to indicate that a DLE must precede the next transmitted character, 5. In transparent mode, the 2661 will automatically send an extra DLE when a DLE is loaded into the THR. 6. Underrun of PCI is not permitted at points shown. Otherwise, received data may be misinterpreted.

Figure 13. Bisync Transmit Flow Chart (Continued)

Signetics 6.25 MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER App Note 400

RESET MASTER RESET, READ CR REGISTER WRITE CR POINTER DATA . 03 PUT INTO STARTUP MODE

SYNC FORMAT, WRITE MR1 8 BITS, NO PARITY, WRITE CR SET UP FOR DATA = OC DOUBLE SYNC, DATA = 04 SYNINI CLASS NON•TRANSPARENT MODE

WRITE TO WRITE MR2 EXTERNAL CLOCKS SYNINI CLASS: DATA = 00 CHARACTER REG SYN DATA = 32

WRITE SYNC1 REGISTER EBCDIC 'SYN' WRITE CR SET UP FOR DATA = 32 DATA = 08 BTCISC CLASS

WRITE SYNC2 WRITE TO REGISTER EBCDIC 'SYR' BTCISC CLASS: CHARACTER REG DATA = 32 ETX DATA = 03 ITB DATA = 1F ETB DATA = 28 ENO DATA = 2D

WRITE DLE REGISTER EBCDIC 'DLE' DATA =10

WRITE CR SET UP FOR DATA = OC SSC CLASS

WRITE TO SSC CLASS: CHARACTER REG STX DATA = 02

Figure 14. 2661 Initialization Figure 15. 2653 Initialization

6.26 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2670/74172/73 CRT TERMINAL CHIP SET App Note 404

INTRODUCTION terminals has been concentrated in the CRT terminal. In this system, the CPU Microprocessors and LSI have had a 'CRT controller' area. These circuits pro- examines inputs from the data com- dramatic impact on the implementation vide the character timing, display munications line and the keyboard and and capabilities of alphanumeric CRT ter- addressing, and sync generation func- places the data to be displayed in a dis- minals. The first generation of CRT ter- tions required by all terminals. However, play buffer memory, which is typically a minals were little more than 'glass these controllers need to be supported by RAM which holds the data for a single or teletypes'. Current designs, implemented many other external circuits to implement multiple screenload (page) or for a single with microprocessors, are characterized a complete terminal. character row. High-end ('smart' and by an abundance of sophisticated The purpose of this application note is to 'intelligent') terminals start with the same features that were previously not provide information on the use of four new base, but append additional circuits to economically feasible: a universal hard- Signetics CRT terminal products which, provide more features and capabilities. ware design that can adapt to different when combined with standard CPUs, The following sections describe the func- user requirements simply by changing memories, and TTL, allow the implementations of each of the major blocks. software or firmware; programmability to tion of a wide spectrum of CRT terminal provide end users with the flexibility to capabilities in as few as 15 total Character Timing and Sync execute specialized routines; and local packages. These devices are: Generation intelligence and storage which off-loads • 2670 Display Character and The major function of this block is to the host CPU by permitting data manipula- Graphics Generator (DCGG) generate the horizontal and vertical timing tion and verification at the terminal site. • 2671 Programmable Keyboard and signals required to produce the TV raster Communications Controller (PKCC) on the CRT monitor. Other functions Just as the impact of microcomputers has • 2672 Programmable Video Timing include the generation of display memory been felt in the functional capabilities of Controller (PVTC) addresses in synchronism with the moni- terminais, advances in semiconductor • 2673 Video and Attributes Con- tor scan and in accordance with a defined technology have revolutionized the hard- troller (VAC) screen format (characters per row, scan ware implementation. Designs that pre- lines per row and rows per screen), viously consisted of 100 to 200 ICs can MAJOR ELEMENTS OF A CRT generation of a cursor signal at the 6 now be realized with a few dozen MSI and TERMINAL appropriate scan position, and generation LSI devices. The majority of the LSI Figure I shows the major elements of a of video blanking signals during retrace manufacturers' effort with respect to CRT typical low-end microcomputer-based intervals.

[ u 2673 CLOCK GRAPHICS GENERATOR LOGIC

VIDEO CHARACTER SHIFT GENERATOR 2872 REGISTER

CHARACTER VIDEO TIMING SYNC GENERATOR & GRAPHICS CONTROL CHAIN GENERATOR

ATTRIBUTES MONITOR LOGIC CURSOR MEMORY I LOGIC CONTROL I REFRESH RAM TIMING SYNC VIDEO TIMING it ATTRIBUTES

CPU

2671

PROGRAM DATA KEYBOARD DATA COMM MEMORY MEMORY INTERFACE INTERFACE

LINE DRIVERS MODEM DATA COMMUNICATIONS LINE KEYBOARD & RECEIVERS

Figure 1. CRT Terminal Block Diagram

Signetics 6.27 MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2670/71/72/73 CRT TERMINAL CHIP SET App Note 401

I/O Interface parallel data from the character and 2672 Programmable Video In its simplest form, this block provides an graphics generation circuits to the serial Timing Controller (PVTC) interface to a keyboard to identify the key video stream required by the CRT. Also The 2672 PVTC, figure 2, is a programma- depressed and a serial communications included are circuits to sum visual display ble device designed for use in CRT ter- link, normally operating in an asynchro- attributes such as blinking, high/low minals and display systems that employ nous format, between the terminal and the intensity, reverse video, and underlining raster scan techniques. The PVTC gener- host computer. Although these functions into the video stream. ates the vertical and horizontal timing sig- could be performed programmatically by nals necessary for the display of inter- the terminal CPU system, removing these SIGNETICS' CRT CHIP SET laced or non-interlaced data on a CRT functions to intelligent controllers unbur- As mentioned previously, the Signetics monitor. Also, the 2672 provides consecu- den the system CPU and allow it to CRT 'set' consists of four circuits. The tive addressing to a user specified display be used more effectively to provide addi- functions of these circuits correspond buffer memory domain and controls the tional features with a relatively small closely to the four major CRT terminal CPU-display buffer interface for various cost impact. blocks described above. The circuits have buffer configuration modes. A variety of been partitioned so as to allow each to be operating modes, display formats, and tim- used independent of the others, allow Character and Graphics ing profiles can be implemented by several alternative methods of implement- Generation programming the control registers in the ing the display memory interface so that These circuits convert the data stored in PVTC. the display memory to the line by line dot the hardware can be tailored to the system requirements, provide a full complement of patterns required to display the data on The CPU initializes the 2672 control and programmable capabilities, and minimize the CRT monitor. timing registers for the desired timing the number of support circuits required. profiles and memory configuration. The Video Timing and Visual The following sections give a brief PVTC provides the handshake control for Attributes description of each of the circuits. The CPU access to the display buffer. One of This section contains the high speed (dot reader is referred to the individual data four memory access modes may be rate) circuits necessary to convert the sheets for full operational details. programmed: independent mode, trans-

INTERFACE CONTROL CE CTRL 1 DISPLAY RD INITIALIZATION READ/ MEMORY CTRL 2 AND WR WRITE HANDSHAKE DISPLAY CTRL 3 CONTROL LOGIC REGISTERS LOGIC

COMMAND DECODE LOGIC A0-2 DISPLAY ADDRESS INTERRUPT DADDO-DADD13 DECODER LOGIC AND ADDRESS STATUS TIMING 14 REGISTER MULTIPLEXERS INTR CURSOR LIGHT PEN STROBE POINTER AND LIGHT PEN REGISTERS

DATA CURSOR CURSOR < DO-7 BUS AND DRIVERS COMPARE 8 LOGIC

VCC GND

HSYNC CCLK CLOCK TIMING CHAIN VSYNC/CSYNC BUFFER AND DECODE LOGIC BLANK

TIMING

Figure 2. 2672 Programmable Video Timing Controller

6.28 Signetics MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2670/71/72/73 CRT TERMINAL CHIP SET App Note 401

parent mode, shared mode, and row mode. transmitter (UART). The receiver accepts The 2670 DCGG includes latches to store These modes are described in the System serial input data and converts it to parallel the character address and line address Configurations section of this application data characters. Simultaneously, the data. A control input to inhibit character note. transmitter accepts parallel data from the data output for certain groups of charac- CPU data bus and outputs it in serialized ters is also provided. The 2670 also In all modes, the PVTC provides form. Received data is checked for parity includes a graphics capability, wherein addresses for the display buffer which and framing errors, and break conditions the 8-bit character code is translated outputs the character codes to the 2670 are flagged. Character lengths can be directly into 256 possible user program- Display Character and Graphics Genera- programmed as 5, 6, 7, or 8 bits not includ- mable graphic patterns. Thus, the DCGG tor (DCGG) and visual attribute codes to ing parity, start or stop bits. An internal can generate data for 384 distinct pat- the 2673 Video Attributes Controller baud rate generator (BRG) operating from terns, of which 128 are defined by the (VAC). The DCGG and PVTC supply the an external clock or directly from a crystal mask programmable ROM. dot data and sync timing to the VAC which can be used to derive one of sixteen generates the serialized video. receive and/or transmit clocks. An eight bit communications status register pro- Programmable features of the PVTC vides status information to the CPU. 2673 Video and Attributes include screen format (characters/row, Controller (VAC) rows/screen, scan lines/row), horizontal The PKCC has an interrupt mask register The 2673, figure 5, is a bipolar LSI device and vertical timing parameters, cursor to selectively enable keyboard and com- designed for CRT terminals and display type (block or underline) and blink rate, munications status bits to generate inter- systems that employ raster scan tech- character blink rate, interlaced or non- rupts. Priority encoded interrupt vectoring niques. It contains a high speed video shift interlaced operation, and single or double is available. Upon receipt of an interrupt register, field and character attributes height characters. acknowledge, a mask programmable inter- logic, attribute latch, cursor format logic rupt vector will be output on the data bus and half dot shift control, and can be The PVTC is capable of producing inter- reflecting the source of the interrupt. The programmed for a light or dark screen rupts based upon several internal condi- mask enabled interrupt sources can also background. 6 tions. By using these interrupts (or by poll- be read directly. ing the equivalent status register) display The VAC visual attribute capabilities are features such as non-consecutive buffer reverse video, character blank, blink, addressing for split screen operation, underline, highlight, and light pen strike- multiple cursors, horizontal and vertical 2670 Display Character and thru or, optionally, graphics. Each attribute scrolling, and smooth vertical scroll can be Graphics Generator (DCGG) has a separate control input which is implemented. The DCGG, figure 4, is a mask-program- latched internally when the AFLAG input is mable 11,648-bit line select character asserted. If the AMODE input is low, the generator. It contains 128 10x9 characters attributes are valid for one character time. 2671 Programmable Keyboard placed in a 10x16 matrix, and has the If AMODE is high, the attributes remain and Communications Controller capability of shifting certain characters, valid until the field is terminated by strob- (PKCC) such as j, y, g, p and q, that normally ing in a new attributes set. The attributes extend below the baseline; effectively, the are double buffered on a row by row basis The 2671, figure 3, is an MOS LSI device 9 active lines are lowered within the matrix internally so that field attributes can which provides a versatile keyboard inter- to compensate for the character's posi- extend across character row boundaries face and also functions as an asynchro- tion. thereby eliminating the necessity of start- nous communications controller. It is ing each row with an attribute set. intended for use in microprocessor based Seven bits of an 8-bit address code are systems and provides an eight bit data bus used to select 1 of the 128 available The horizontal dot frequency is the basic interface. characters. The eighth bit functions as a timing input element to the VAC; internally, chip enable signal. Each character is this clock is divided down to provide a The keyboard controller handles the scan- defined by a pattern of logic 1s and Os character clock output for system syn- ning, debounce, and encoding of mechani- stored in a 10x9 matrix. When a specific 4- chronization. Ten bits of dot data are cal or capacitive keyboards with a max- bit binary line address code is applied, a parallel loaded into the video shift register imum of 128 keys utilizing any of four word of 10 parallel bits appears to the out- on each character boundary. The video programmable rollover modes. A mask put. The lines can be sequentially data is shifted out on three outputs at the programmable ROM provides four levels of selected, providing a 9-word sequence of dot frequency. On the video output, the key encoding, corresponding to the sepa- 10 parallel bits per word for each video is presented as a three level signal rate shift and control input combinations. character selected by the address inputs. representing low, medium and high inten- An eight bit keyboard status register As the line address inputs are sequentially sities, and the three intensities are also transmits status information to the CPU. addressed, the device will automatically encoded on the two TTL compatible video Programmable features include rollover place the 10x9 character in 1 of 2 outputs. mode, scan rate and debounce time, preprogrammed positions on the 16-line coded or uncoded operation, and matrix with the positions defined by the 4- automatic repeat operation. line address inputs. One or more of the 10 parallel outputs can be used as control The communications section of the PKCC signals to selectively enable functions is a universal asynchronous receiver and such as half-dot shift, color selection, etc. Signetics 6.29 MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2670/71/72/73 CRT TERMINAL CHIP SET App Note 401

DATA REPEAT DBO•DB7 BUS BUFFER KEYBOARD ENCODER

KCLK

MODE & TIMING KDRES CONTROL HYS OPERATION CONTROL RD CMR WR KMR KCO.KC3 CE CSR KEYBOARD SCANNER & KRET KSR ENCODER/ AO•A2 > DECODER COMMAND DECODER KRO.KR2

4 x 128 x8 SHIFT READ•ONLY MEMORY CONTROL XINTR INTERRUPT CONTROL

VECTOR GENERATOR INTA

INTR KEYBOARD IMR DATA REGISTER

VCC KEY HOLDING GND REGISTER

TONE TONE TIMING GENERATOR

BAUD RATE GENERATOR TxC

RxC BAUD RATE CONTROL TRANSMITTER REGISTER

TRANSMIT HOLDING REGISTER

TRANSMIT TxD SHIFT REGISTER

XTALl/BRCLK

XTAL2

RECEIVER

INTERRUPTS RECEIVE HOLDING REGISTER TIMING RECEIVE CONTROLS SHIFT REGISTER RxD

Figure 3. 2671 Programmable Keyboard and Communications Controller

6.30 Signetics MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2670/71/72/73 CRT TERMINAL CHIP SET App Note 401

SCD VCC GM GND

CAO-CA7

CSTROBE CHARACTER LATCH OUTPUT INHIBIT CONTROL

GRAPHICS ADDRESS DECODER LOGIC LAO- LA3

LINE READ ONLY SELECT MEMORY MULTI. OUTPUT DO-D9 (128 x 91) PLEXERS DRIVERS

LINE ADDRESS LINE LAO-LA3 TRANSLATION ROM LATCH (32 x 10)

LSTROBE

Figure 4. 2670 Display Character and Graphics Generator

CCO CHARACTER CC1 CLOCK CCLK CC2 COUNTER

DCLK

10 DOT VIDEO SHIFT DATA 3.LEVEL D0-D9 REGISTER DRIVER VIDEO >I —12 BITS— VIDEO AND TTL TTLVID1 HDOT ATTRIBUTE DRIVERS TTLVID2 HIERARCHY CURSOR LOGIC ARVID ABLANK BKGND ABLINK CB LANK AHILT AUL ATTRIBUTE AND ALTPEN/AGM CURSOR CONTROL AFLG LOGIC AND .11 BLANK AMODE PIPELINE RESET ACD VCC BLINK VBB UL GND LL LPLIGMD

Figure 5. 2673 Video and Attributes Controller

Signetics 6.31 MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2670/71172/73 CRT TERMINAL CHIP SET App Note 401

SYSTEM CONFIGURATIONS vals in order to prevent visual distur- Similarly, a read operation proceeds as The PVTC supports four common system bances of the displayed data. follows: configurations of display buffer memory 1. Steps 2 and 3 as above. The CPU manages the data transfers by interface, designated the independent, 2. The CPU issues a 'read at cursor with/ supplying commands to the PVTC. The transparent, shared, and row buffer without increment' or 'read at pointer' commands used are: modes. The first three modes utilize a command. 1. Read/Write at pointer address. single or multiple page RAM and differ pri- 3. The PVTC negates 'RDFLG', outputs 2. Read/Write at cursor address (with marily in the means used to transfer dis- the specified address, and generates optional increment of address). play data between the RAM and the CPU. control signals to perform the read 3. Write from cursor address to pointer The row buffer mode makes use of a single operation. Data is copied from the address. row buffer (which can be a shift register or memory to the interface latch and the a small RAM) that is updated in real time to The operational sequence for a write to PVTC sets its 'RDFLG' status to indi- contain the appropriate display data. memory operation is: cate that the operation is completed. 1. The CPU loads data to be written into 4. The CPU checks the 'RDFLG' status to the display memory into the interface see if the read is completed. latch. 5. The CPU reads the data from the inter- Independent Mode 2. The CPU writes the destination face latch. The CPU to RAM interface configuration address into the PVTC's cursor or Loading the same data into a block of dis- for this mode is illustrated in figure 6. pointer registers. play memory is accomplished via the 'write Transfer of data between the CPU and dis- 3. The CPU checks the PVTC 'RDFLG' from cursor to pointer' command: play memory is accomplished via a status bit to assure that any previous 1. The CPU loads the data to be written bidirectional latched port and is controlled operation has been completed. into the display memory into the inter- by the PVTC signals read data buffer 4. The CPU issues a 'write at cursor with/ face latch. (RDB), write data buffer (W/Mi , and buffer without increment' ora 'write at pointer' 2. The CPU writes the beginning address chip enable (BCE). This mode provides a command to the PVTC. of the memory block into the PVTC's non-contention type of operation that does 5. The PVTC negates 'RDFLG', outputs cursor address register and the ending not require address multiplexers. The CPU the specified address, and generates address of the block into the pointer does not address the memory directly - the control signals to perform requested address register. read or write operation is performed at the operation. Data is copied from the 3. The CPU checks the 'RDFLG' status bit address contained in the cursor address interface latch into the memory. to assure that any previous operation register or the pointer address register as 6. The PVTC sets its 'RDFLG' status to has been completed. specified by the CPU. The PVTC enacts indicate that the write operation is com- 4. The CPU issues a 'write from cursor to the data transfers during blanking inter- pleted. pointer' command to the PVTC.

2672 REFRESH PVTC RAM DADD DISPLAY ADDRESS ADR BCE CTRL3 CE WDB CIRL1 ► WR DATA I/O CTRL2 RDB

TO DISPLAY DATA BUS VIDEO / LOGIC

CP g 741-S364 C1774LS364

RD WR — FROM CPU FROM Cpu

SYSTEM DATA BUS

Figure 6. Independent Buffer Mode Configuration

6.32 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2670171/72/73 CRT TERMINAL CHIP SET App Note 401

5. The PVTC negates 'RDFLG' and out- For the 'write from cursor to pointer' lowered to indicate that the CPU can puts block addresses and control sig- operation, the PVTC's BLANK output is access the buffer. nals to copy the data from the interface asserted automatically and remains latch into the specified block of memo- asserted until the vertical retrace interval In transparent mode, the PVTC delays the ry. following completion of the command. The granting of the buffer to the CPU until a 6. The PVTC sets its 'RDFLG' status to memory is filled at a rate of one location vertical or horizontal blanking interval, indicate that the block write is com- per two character times, plus a small thereby causing minimum disturbance of pleted. amount of overhead. the display. In shared mode, the PVTC will blank the display and grant immediate Similar sequences can be implemented on access to the CPU. an interrupt driven basis using the READY Shared and Transparent interrupt output from the PVTC to inform Buffer Modes Row Buffer Mode the CPU that a previously requested com- In these modes the display buffer RAM is a Figure 8 shows the hardware implementa- mand has been completed. part of the CPU memory domain and is tion for the row buffer mode. During the addressed directly by the CPU. Both first scan line (line 0) of each character Two timing sequences are possible for the modes use the same hardware configura- row, the PVTC halts the CPU and DMA's 'read/write at cursor/pointer' commands. tion with the CPU accessing the display the next row of character data from the If the command is given during the active buffer via three-state drivers (see figure system memory to the row buffer memory. display window (defined as first scan line 7). The processor bus request (PBREQ) The PVTC then releases the CPU and dis- of the first character row to the last scan control signal informs the PVTC that the plays the row buffer data for the program- line of the last character row), the opera- CPU is requesting access to the display med number of scan lines. The bus tion takes place during the next horizontal buffer. In response to this request, the request (BREQ) control signal informs the blanking interval. If the command is given PVTC raises bus acknowledge (BACK) CPU that character addresses and the during the vertical blanking interval, or until its bus external (BEXT) output has memory bus control (MBC) signal will start while the display has been commanded freed the display address and data busses at the next falling edge of BLANK. The blanked, the operation takes place for CPU access. BACK, which can be used CPU must release the address and data immediately. as a 'hold' input to the CPU, is then busses before this time to prevent bus

REFRESH 2672 RAM PVTC DISPLAY ADDRESS ADR

PBREQ CIRO CE WR CPU BACK CTRL3 DATA I/O BEXT CTRL2

DISPLAY DATA BUS 74LS244

74LS245 SELECT RD DECODE CPU WR

SYSTEM ADDRESS BUS

SYSTEM DATA BUS

Figure 7. PVTC Shared or Transparent Buffer Modes

Signetics 6.33 MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2670/71/72/73 CRT TERMINAL CHIP SET App Note 401

2 x 2111

2672 ROW PVTC LSB's REFRESH RAM DISPLAY ADDRESS BREO CTRL2 OD TO CPU MBC 74LS244 WR

CTRL3 CCLK DISPLAY DATA BUS

SYSTEM ADDRESS BUS

SYSTEM SELECT RAM DECODE

/N. R -Tr W

SYSTEM DATA BUS

Figure 8. Row Buffer Mode Configuration

contention. After the row of character data • Cursor control keys RAM required by the system program. is transferred to the CPU, BREQ returns • Numeric keypad Since the majority of the terminal's high to grant memory control back to the Serial Interface: features are tailored by firmware, the ROM CPU. • Full or half duplex size can be increased, either internally or • RS-232 compatible externally, to support additional func- A MINIMUM CHIP COUNT • 16 baud rates with internal baud tions.) TERMINAL IMPLEMENTATION rate generator Figure 9 is the schematic of a minimum • Character or block transmission BASIC TERMINAL SOFTWARE chip count CRT terminal using the four Operating Modes: CRT set devices. Only 15 IC packages are • Normal The software for a microcomputer based required for the complete implementation, • Transparent (displays graphic terminal is closely tied to the system hard- including all keyboard encoding and RS- and control characters) ware configuration and its characteristics. 232 level conversion for the serial inter- • Page or scroll with optional If an interrupt driven mode of operation is face. Despite this low chip count the ter- smooth scroll desired, the system hardware/software minal is capable of providing an Visual Attributes: design must be capable of prioritizing the impressive array of features including: • Blink interrupts so that the system will correctly service interrupts from different sources. Display Format: • Reverse video In a typical system, there are three inter- • 24 or 25 character rows • Highlight rupt sources: the keyboard, the com- • 80 characters per row • Underline munications interface, and the video tim- Character Format: • Non-display ing controller. The latter must usually be • 7x9 dot matrix character in a assigned the highest priority since failure 9x12 character block The system utilizes the independent buffer to service an interrupt from the video tim- • 96 ASCII alphanumeric charac- mode to minimize hardware requirements. ing controller on a timely basis may result ters The dual port interface to the 2Kx8 display in visual perturbations on the display. The • 32 special symbols buffer is via a Signetics 8X31 bidirectional keyboard and datacomm interrupts can, in • Block graphics latch. This may be replaced by a unidirec- most cases, absorb some time delay • Line drawing character set tional latch such as the 74LS374 if reading before they are serviced since they Cursor: of the RAM's contents by the CPU is not include one or more levels of data buffers. • Underline or block cursor required. • Optional blinking Keyboard: The operating program for the terminal is 1A pre-programmed 8049 microcomputer • 128 keys maximum contained in the internal ROM of the 8049 containing the operating firmware for this • Non-encoded microcomputer, which also provides the terminal will be available from Signetics.

6.34 Signetics MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2670171/72173 CRT TERMINAL CHIP SET App Note 404

p5 I

cIng

m il •

,>q

8 88 82 O

/////// L2s'Em I) N aaaaN FJ ,LisEin )'09'))':77Y))71-m"' A8281007288 ^

• 72:\ .7\ N /77 . Ox • 2\ • • 2m . T\ • N O \ N /-7 mom i 12 T\ s

/2///2///// -- 8 8 88 •-- 8881 18 \\\\\\\\\\\\\\\\\\

1815 2E2282 28

a. 8 ////2/// /8 0 22SEE'a

Figure 9. Minimum Chip Count Terminal

Signetics 6.35 MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2670/71/72/73 CRT TERMINAL CHIP SET App Note 401

ma 0 0 O 2 • • tt -I .1 .1 d .1.1,21 71 !2I 71'41 d 1 .1 Ni d ,H mom 9I ?4

t'IJ 1E' :-

•-1).0-f-J " —•

‘L 2 9 9 Li' 8

EE 0 0 0 8 )F") 00 00 aoo s,

\ \

,c2

////// // E 0 0 2 A 8 2 8

\ \ \ \ \ \ V HHI'

cn ° 0 ET_ 91 2 0 ?<1; O O t I z aIU- aN

Figure 9. Minimum Chip Count Terminal (Continued)

6.36 Signetics MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2670/71/72/73 CRT TERMINAL CHIP SET App Note 401

Often, a multi-level interrupt structure will be required so that a high priority interrupt requiring immediate service can be serviced even while the system is in the process of servicing a lower priority interrupt.

REAR COROC A simplified flowchart for the software for SSOR RA an interrupt driven terminal is shown in figure 10. After application of power, the ES microprocessor first performs a system I 1,11.12 initialization routine which consists of five

parts: CO UNICATIONS ROUTNE EYBOARD ROUTINE

1. Clear the microcomputer's scratch- YES S ST CO ROL 0 pad RAM. FU C 0 2. Initialize the 2672 PVTC for the desired screen format, monitor tim-

ing parameters, cursor parameters, CHAVCTER TO DISPLAY and display start address. srE MEMORY 3. Clear the CRT display by loading a s I TCHES non display-code (usually an ASCII 'space', 20 hex) into the buffer WRITE Mg= CHARAERCT NI A E memory. PNCC TI?1PM7R - 4. Initialize the 2671 PKCC for the desired keyboard and serial interface modes. 5. Read any mode switches (e.g., full BLE INTERRUPTS or half duplex, baud rate, cursor type, etc.) and set system parameters as required.

The processor can now enable its interrupts and wait in a loop until an interrupt is ES received. When this happens, the proc-

essor first determines the source of the coNTRouER interrupt and then performs the required system operation. YES CRT CONTROL. ROUT AE

An interrupt from the CRT timing controller DErH1c TERRUPT usually indicates that some information is required for proper screen refresh operation. For example, the PVTC may issue a 'split screen' interrupt to indicate that a new address must be loaded into its screen start registers in order for the next character row to be displayed from other than the next sequential address in memo- RETUR ry. The CPU must service this interrupt within a finite time in order for the display Figure 10. Basic Terminal Software Flowchart to operate correctly. either case the microprocessor must could have been included by selecting An interrupt from the keyboard interface determine the type of character and per- another of the numerous microprocessor may be either a displayable character or a form the necessary system operation. devices on the market with greater control function. Displayable characters program memory capacity. Major features are usually transmitted to the host com- A DESIGN EXAMPLE of the terminal are summarized in table 1., puter and also placed into the buffer A fully operational emulation of an IBM memory for display on the terminal. Cer- 3101 terminal was designed and con- 1A data package for the design, including tain control characters, such as cursor structed using the Signetics CRT chip set. details of operation, schematic, and control keys or keyboard error codes, may The terminal incorporates the majority of program listing, is available upon request cause only local actions, while others will the 3101's functions. Selected functions by writing to: also require transmission to the host. were not incorporated due to program Signetics Corporation memory limitations. For example, the tab- Microprocessor Applications Dept. An interrupt from the data communications bing functions were developed and tested Mail Station 12-76 interface may also be a displayable but were left out in deference to the block P.O. Box 409 character or a system control character. In transmission functions. More features Sunnyvale, CA 94086

Signetics 6.37 MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2670/71172/73 CRT TERMINAL CHIP SET App Note 401

ns C> Hh ttt

UN a m

O Its, 8.—O

Iii1810 t A t 9 IR 15 NIN Z\ Z\ T0

11! O

HUH S10811,109 1A1300IN

Figure 11. IBM 3101 Emulation Block Diagram

6.38 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2670171/72/73 CRT TERMINAL CHIP SET App Note 401

Table 1 — TERMINAL FEATURES selectable baud rates. The PKCC addresses two 74LS145s which act as a Display Screen Format — Erase functions: erase EOL, erase 4-to-16 decoder to drive a 16x8 matrix — 2000 character screen capacity (25 EOS, clear screen keyboard. Key depressions are detected rows x 80 columns) on the KRET input from a 74LS151 8-to-1 — Operator information area (25th Visual Attributes multiplexer. Each key depression is line) — Highlighted field debounced, encoded according to the — Block-shaped cursor with optional — Blinking field states of the SHIFT and CONTROL inputs, blinking — Non-displayed field and presented to the CPU. Repeat and — Underlined field 'typomatic' (auto-repeat) functions are processed automatically by the PKCC. Displayable Graphic Set Modes of Operation — 95 ASCII characters for non- — Transmission modes: character or transparent mode block (page or line) Timing Calculations — 128 characters for transparent — Normal or transparent One of the tasks required in the design mode phase of the terminal is the selection of a — 7x9 character matrix in 9x12 field Line Protocol suitable monitor and calculation of the — Asynchronous PVTC register values to provide suitable Keyboard — 7-bit ASCII with programmable drive signals for the selected monitor. — 63-key main keyboard parity — 12-key control key cluster — One or two stop bits The selection process begins with — 12-key numeric keypad — Full or half duplex calculation of the required horizontal scan — Keyboard lock/unlock under soft- — Online or local frequency. Each character will be con- ware control — Programmable line turnaround tained in a 9 dot by 12 line field. Since — Keyboard clicker character for block mode (EOT/ there are 25 display rows, the total number — Typamatic operation ETX/CR/XOFF) of active scan lines will be 12 x 25, or 300. — EIA RS232 interface To this we must add some number of scan 6 — Communication line speed: 50 to lines for the vertical retrace, which is Edit Functions 9,600 baud typically 5 to 10 percent of the active scan — Cursor controls: up, down, left, right, lines. For a screen refresh rate of 60 Hz, home Screen Refresh Rate this yields — Cursor address read and write — 60 Hz H frequency = (60)(300)(1.1) = 18,900 Hz.

Terminal Hardware PVTC informs the CPU when an operation A Motorola monitor was selected for the The block diagram of the 8035 based ter- is completed. application. The major timing specifica- minal is illustrated in figure 11. It is an The PVTC addresses the display buffer tions for the monitor are: expanded version of the logic shown in memory, which contains both character Horizontal frequency: 18.72 KHz ± figure 9, the major difference being a and attribute data. An attribute byte is 500 Hz larger display RAM, to provide up to two identified by the software by setting bit 7 Horizontal retrace: 8 us max pages of screen data, and the addition of of the byte to a logic 1. The RAM data out- Horizontal sync width: 4 us min several input ports to handle the large puts are applied to the 2670 DCGG, which Vertical frequency: 50/60 Hz number of option and set-up switches. The provides the character dot data informa- Vertical retrace: 750 us max terminal's software is contained in 4K of tion, and to the 2673 VAC. Vertical sync width: 50 us min program storage external to the 8035. The VAC is hardwired to operate in the field attributes mode for this application. Monitor timing definitions are shown in The 2672 PVTC is programmed to operate An attribute character occupies a screen figure 12. The worksheet illustrated in in the independent buffer mode with the position but is not displayed unless the table 2 can be used to compute the CPU isolated from the display RAM by two ACD input to the VAC is asserted. Bit 7 of required timing and associated PVTC 74LS364 eight-bit latches, which provide the character byte identifies a character register values. Some rough guesses are the path for data transfers between the as an attribute character if it is a 1. When required initially and several iterations CPU and RAM. The PVTC, responding to bit 7 on the RAM data bus is a 1, the through the worksheet will usually be commands from the CPU, completely con- attribute byte is latched into the VAC to required to arrive at final values. For trols the data transfer. To avoid display begin a new attributes field. Since the example, the character clock period must interference, the PVTC is instructed to attributes are double buffered in the VAC, be known to select the horizontal front complete the access during a blanking only one byte (at any character position) is porch (HFP), sync width (HSYNC), and interval. For massive display updates required to specify a field. back porch (HBP) values. An estimate of (clear screen, load form, etc.) the PVTC is the character period can be made initially The bipolar VAC circuit serializes the dot instructed to blank the display and service as follows: the data transfer immediately and con- data from the DCGG into a 17.5 MHz data Horizontal period = 1/18,900 = tinuously. Additional memory contention stream for the monitor. Two TTL-level 52.9 us circuitry is not necessary since the PVTC video outputs provide three levels of video: black, white, and gray. Horizontal active = total - blank = provides all of the timing and addressing 52.9 — 10 = 42.9 us (via cursor and pointer) necessary to com- The PKCC provides the asynchronous Character period = 42.9/80 = 0.53 us plete the transfer. An interrupt from the data communications link at one of sixteen approximately

Signetics 6.39 MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2670/71/72/73 CRT TERMINAL CHIP SET App Note 401

CHAR/ROW (IR5)

HBLANK FRONT PORCH (IRI) BACK PORCH (IR2)

HSYNC HSYNC (IR2) CHAR ROWSISCREEN (1R4) SCAN LINES PER ROW (IRO)

VBLANK H H FRONT PORCH (IR3) BACK PORCH (IR3)

VSYNC El —1 VSYNC (FIXED AT 3) EQUALIZING LINESIROW CONSTANT

IRO IIIIIII IRI IIIIIII

HSYNC HBACK VFRONT VBACK WIDTH PORCH PORCH PORCH

IR2 1111111 IR3

CHAR ROWSISCREEN CHARACTERS PER ROW

IR4 1 1 11 1 1 1 11 IR5 1 1 1 1 1 1 1 1 1

Figure 12. Horizontal and Vertical Timing

In calculating horizontal timing, an approx- When a scroll operation is required, the tialized so as to cause an interrupt to be imate ratio for the HFP, HSYNC, and HBP CPU changes the value in the PVTC's issued at the beginning of row 24. The of 1:2:2 respectively is recommended. 'screen start' register from 0080 to OODO. CPU responds to this interrupt by chang- This effectively shifts the displayed data ing the value in the screen start register to Table 2 contains the final values selected up one row. Upon reaching the specified 0000. The PVTC then uses this value as for the application. last buffer address (which is now the last the starting address of the next (25th) row, character in row 23), the PVTC au- causing the status line to be displayed in Memory Allocation tomatically changes the addressing se- that position. The CPU must re-load the The 4K bytes of available buffer memory quence to resume starting at 0080 for the screen start register before the end of the were allocated as follows (all addresses 24th row. The display data is now vertical blanking interval with the correct are in hex): organized: value for the first character to be dis- — 0000 to 004F: display data for row - OODO to 011F: row 1 data played on the screen. 25, status line - 0120 to 016F: row 2 data — 0050 to 0075: not used • Terminal Software — 0076 to 007F: CPU scratchpad • Because the 8035 microcomputer used in — 0080 to 07FF: display data for rows 07B0 to 07FF: row 23 data the terminal provides only a single inter- 1 to 24 0080 to 00CF: row 24 data rupt level, a totally interrupt driven soft- — 0800 to OFFF: not used, available for ware design could not be used. The inter- second page of display data The CPU can clear the previous data in rupt was assigned to the PVTC to service 0080 to OOCF so that a blank row appears the split screen interrupt described above The PVTC's 'display buffer first address' in the 24th position. and the operations required to implement and 'display buffer last address' registers the smooth scroll feature. The keyboard are loaded with the values 0080 and 07FF The status line (row 25) data is kept in a and datacomm functions are serviced by respectively so as to cause this portion of separate section of RAM to eliminate the polling the PKCC status register. Both the the RAM to act as a circular buffer. Initially necessity of moving the data whenever the keyboard interface and UART receiver are the display data is organized in the RAM scrolling operation described above double buffered in the PKCC, preventing as follows: occurs. Thus, the PVTC must be overrun even if they are not serviced im- — 0080 to 00CF: row 1 data instructed to change its addressing se- mediately. — OODO to 011F: row 2 data quence at the beginning of the 25th row. This is accomplished by use of the split The program generally follows the typical screen row interrupt capability. IR10, the program flow described previously. At — 0760 to 07FF: row 24 data 'split screen interrupt row' register, is ini- system reset the 8035 interrupts are dis-

6.40 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2670171172173 CRT TERMINAL CHIP SET App Note 401

Table 2 — CRT TIMING WORKSHEET which checks for the type of character (displayable or control) and the appropri- 1. HORIZONTAL CHARACTER BLOCK (no. of dots) 9 ate handling subroutine (ESC sequence, control sequence, cursor control, 2. VERTICAL CHARACTER BLOCK (no. of scan lines) 12 (IRO) character display, etc.) is called. If the 3. VERTICAL REFRESH RATE, Hz 60 FIFO's are empty, the polling routine checks the option switches for any 4. CHARACTERS PER ROW 80 (IR5) changes since reset entry and if so recon- 5. CHARACTER ROWS PER SCREEN 25 (IR4) figures the system as necessary. 6. TOTAL ACTIVE VIDEO SCAN LINES (step 2 x step 5) 300 The need from the FIFOs results from the method used to effect the clear row func- 7. VERTICAL FRONT PORCH (no. of scan lines) 4 (IR3) tion required when a scroll Is performed. Although the PVTC includes a 'clear from 8. VERTICAL BACK PORCH (no. of scan lines) 12 (IR3) cursor to pointer' command that can be 9. VERTICAL RETRACE INTERVAL (step 8 + 3) 15 used to clear a block of memory rapidly, the display is temporarily blanked during 10. TOTAL SCAN LINES PER FRAME (add steps 6, 7, and 9) 319 this operation. This would cause undesira- 11. HORIZONTAL LINE RATE, KHz (step 3 x step 10) 19.14 ble flashes on the display. Instead, the program does the function by a repetitive 12. HORIZONTAL FRONT PORCH (character time units) 5 loop using the 'write at cursor and Incre- ment' command. Since the write occurs 13. HORIZONTAL SYNC WIDTH (character time units) 8 (IR2) only once per scan line during the active 14. HORIZONTAL BACK PORCH (character time units) 9 (IR2) display window, a worst case total of approximately 80 scan line times Is required 15. HORIZONTAL RETRACE INTERVAL (step 13 + step 14) 17 to execute the routine. This would limit the 16. TOTAL CHARACTER TIME UNITS IN ONE HORIZONTAL maximum received character rate to ap- 6 proximately one per 80 scan lines or about SCAN LINE (add steps 4, 12, 13, and 14) 102 240 characters per second (2400 baud). To overcome this limitation, the PKCC is 17. EQUALIZING CONSTANT ([step 16 / — [2 x step 131) 35 (IR1) also polled each time through the clear 18. CHARACTER CLOCK RATE, MHz (step 16 x step 11) 1.95228 line subroutine loop, and any entries from the receiver or keyboard are stored in the 19. CHARACTER PERIOD, us (1 / step 18) 0.512 appropriate FIFO. Since the FIFO is eight 20, SCAN LINE PERIOD, us (step 19 x step 16) 53.27 deep, this allows eight characters to be received in the same time, increasing the 21. DOT CLOCK RATE, MHz (step 18 x step 1) 17.57052 maximum baud rate to 19,200. (Other program limitations actually reduce the maximum baud rate to 9600 baud). PARAMETER SPEC ACTUAL However, this does not increase the rate at which characters which cause a scroll function to occur, such as a line feed, can A. HORIZONTAL RATE, KHz 18.72 ± 0.5 19.14 be received. Each character of this type must be followed by 'fill' characters In B. HORIZONTAL RETRACE TIME, us 8 8.7 order for data rates higher than 2400 baud to be used. C. HORIZONTAL SYNC WIDTH 4 4.1 An interrupt from the PVTC will occur D. VERTICAL RATE, Hz 50 - 60 60 when the display scan reaches the row count programmed in its split screen E. VERTICAL RETRACE TIME, us 750 784 address register, row address 24 (for the 24th row). In response to the interrupt, the F. VERTICAL SYNC WIDTH, us 50 157 CPU loads the screen start registers with the address of the status line (0000) and enables the PVTC's line zero interrupt. abled, data memory and display memory The program then enters a loop where the This causes another Interrupt at the begin- are cleared to zeroes, and both the PVTC PKCC is checked for keyboard or UART ning of display of the status line. At this and PKCC are master reset through soft- entries. If an entry has occurred, the time the CPU reloads the screen start ware commands. The system option character is fetched and stored in a soft- register with the proper address to begin switches are then read and stored and the ware controlled FIFO (first-in-first-out) the next display frame and disables the PVTC and PKCC Internal registers are ini- memory which is eight bytes deep for both line zero interrupt. tilized for the selected operation. Finally, receiving or transmitting characters (the If scrolling is required the screen start the initial data for the status line is loaded, need for the FIFO is described below). If register value is incremented by 80 (pop- the PVTC, UART, and keyboard are either FIFO has an entry, the program pro- ping off the top row) and the effective bot- enabled, and the CPU interrupt is enabled. ceeds to a character recognition routine tom row cleared to nulls. If soft scrolling is Signetics 6.41 MICROPROCESSOR DIVISION JANUARY 1983 USING THE 2670171172/73 CRT TERMINAL CHIP SET App Note 401

selected, additional functions are per- 12 lines. If nothing else were changed, line showing, and now changes the verti- formed during the interrupt routines. To however, the bottom of the display would cal back porch to 8. The display moves up begin the operation, the line zero interrupt move down ten lines. Thus, during the row two more scan lines and at the next row 24 routine adds ten lines to the vertical back 24 interrupt the number of scan lines per interrupt four scan lines are shown. The porch. This causes the next active screen character row is changed to two (12-10), process continues in this manner, provid- display to begin ten scan lines later than causing only the first two scan lines of that ing the effect of the entire display, except normal and gives the effect of the display row to be shown. The next line zero inter- for the status line, smoothly scrolling up moving up two scan lines (12 lines per rupt (at row 25) restores the lines per row over a selected interval of six frames, or character row - 10) instead of jumping up count back to 12 to keep the whole status one tenth of a second.

6-42 Signetics MICROPROCESSOR DIVISION JANUARY 1983 2661 OPERATING MODE SWITCHING PROCEDURES App Note 402

INTRODUCTION SR2, to indicate the end of the parity bit or TXEMT is driven active upon underrun This application note describes pro- the first stop bit, depending on whether condition. cedures for switching the operating mode one or two stop bits are selected Note that the TXEMT pin is not driven of the Signetics' 2661 Enhanced Program- (MR17:MR16 = 01 or 11). The procedure active in echoplex mode. It is optionally mable Communications Interface (EPCI) causes TXEMT/DSCHG to be driven to its driven active when the above steps are from echoplex or remote loopback mode active state only at the completion of the followed, particularly the transmitter being to normal operation and vice-versa. last character, as shown in figure 1. enabled as indicated in step 2. Because ECHOPLEX (AUTOMATIC The recommended sequence of operation the transmitter relies on CR0 = 1 and CR2 ECHO) MODE TO NORMAL is as follows: = 0 to drive TXEMT active, it is necessary OPERATION 1. Wait for RXRDY (either RXRDY inter- to set CRO to zero in echoplex mode if it is rupt or status read). This is necessary desired not to drive TXEMT active. CRO, The echoplex operation is initiated by set- for the assembly of the last character transmitter enable, is ignored for data ting command register bits CR7:CR6 = to be completed and to ensure the transmission in echoplex mode. It is, 01, and CR2 (receiver enable bit) = 1. transfer of this character to the however, used to determine whether Echoplex operation is terminated by transmitter. TXEMT should be driven active. resetting CR2 to zero. To ensure the 2. Enable the transmitter by setting CR0 If frequent mode switching is anticipated proper transmission of the last received to one. and it is desired to drive TXEMT active, character, no change of operating mode 3. Disable the receiver by setting CR2 to step 2 of the above procedure could be should be made until the end of that zero. skipped, provided that the echoplex character. However, if mode switching is 4. Wait for TXEMT (either TXEMT/ operation is initiated by enabling both the necessary in certain applications, the DSCHG interrupt or status read). At receiver and the transmitter - that is, following procedure is recommended to this point, the parity bit or the first stop CR2:CRO = 11. ensure no garbling on the last transmitted bit (if two stop bits are selected) has character. Two potential problems may The TXEMT timing shown above is only been sent out. applicable when switching modes. Note arise: the calculated parity instead of the 5. Change mode from echoplex to normal. received parity may be transmitted, and that in normal operation, TXEMT is driven 6. Load new character into the transmit data rate may be shortened or lengthened. active at the beginning of the last data bit 6 holding register, THR. Further com- or parity bit upon underrun condition. The procedure provides the necessary munication between the 2661 chip and handshaking to avoid these potential the CPU will resume as normal - that is, REMOTE LOOP BACK MODE TO problems by making use of the TXEMT/ TXRDY is driven active to indicate that NORMAL OPERATION DSCHG pin or of the status register bit 2, the THR is available for new data and The procedure is similar to the procedure for echoplex to normal, with the following exceptions: 1. No handshaking with RXRDY is TXD START PARITY STOP required. LAST CHARACTER BIT 2. During step 3 of the previous procedure, CR2 goes to zero, and CR7:CR6 should be simultaneously changed from 11 to 01 (remote to echo- TXEMTIDSCHG plex). This is necessary because the DRIVEN ACTIVE HERE IF ONE STOP BIT IS SELECTED logic implemented to drive TXEMT active relies on echoplex information. However, this requirement does not DRIVEN ACTIVE HERE IF TWO need additional service from the con- STOP BITS ARE SELECTED troller because remote-to-echoplex switching is done at the same time as Figure 1. TXEMTIDSCHG Operation for ECHOPLEX Mode Switching disabling the receiver.

NORMAL OPERATION TO ECHOPLEX OR REMOTE TXD or PARITY OR I STOP BIT To avoid garbling the last transmitted LAST TRANSMITTED DATA LAST BIT I data, a mode switch from normal operation TXEMT to echoplex or remote operation should be performed as follows: 1. Wait for TXEMT (either TXEMT/ CE DSCHG interrupt or status read) to be asserted. DISABLE 2. Disable the transmitter by setting CR0 TRANSMITTER to zero. 3. Wait for TXEMT to be negated. CHANGE TO ECHOPLEX OR REMOTE 4. Change the mode from normal opera- Figure 2. Switching from Normal to ECHOPLEX or Remote Loopback tion to echoplex or remote. The timing is illustrated in figure 2. Signetics 6.43 MICROPROCESSOR DIVISION JANUARY 1983 2670171/72/73 CRT SET APPLICATION BRIEFS App Note 403

INTRODUCTION tains the high speed timing circuits re- only, or with a combination of hardware The Signetics CRT chip set consists of quired In CRT terminal systems. Included and software. four LSI devices which, when combined on the 2673 are a dot clock counter, video with standard microcomputer, memory, shift register, field and character at- and TTL products, permit the implementa- tributes logic, and cursor display circuits. Software Only Method tion of a CRT terminal In as few as 15 total The 2673 attributes capabilities are The software only method of smooth packages. The four LSI devices are: reverse video, character blank, blink, scrolling uses the 2872's capability to pro- underline, highlight, light pen, and gram the scan lines per row and the ver- 2870 Display Character and Graphics graphics. The device provides both TTL tical back porch, and the ability to pro- Generator (DCGO) and analog video outputs and operates at gram an Interrupt to occur at any row by The 2670 Is a mask programmable line dot frequencies up to 25MHz. programming the row value into the split select character generator which contains screen register, IR10. Three limitations of the dot patterns for 128 10x9 characters. It Individual data sheets are available which this method are: describe each of the devices In full detail. also provides a semi-graphics capability 1. Scrolling must be In an upward direc- A previously published application note wherein the 8-bit character code is tion. entitled "Using the 2670/71/72/73 CRT Ter- translated directly Into 256 graphic pat- 2. The screen area that is scrolled must terns useful for presenting data such as minal Chip Set" (App Note 401), describes start at the top of the display but can graphs and forms on the CRT display. Ad- the implementation of CRT terminals us- end at any row. ing the chip set. The purpose of this ap- ditional features of the DCGG include 3. The minimum scrolling increment Is plication note Is to provide information on character and line address latches and In- two scan lines. ternal descend logic. the Implementation of special end- product features. 2671 Programmable Keyboard and Com- The flow chart In Figure 1 shows the steps munications Controller (PKCC) necessary for scrolling starting at the top The 2671 provides a versatile keyboard In- SMOOTH (SOFT) SCROLLING of the screen and ending at character row terface and an asynchronous communica- Scrolling Is used In CRT terminals to pro- 231, with an additional non-scrolling row at tions interface In a single package. The vide the effect of an 'endless page' on row 24. The IR10 value Is set to 23, to keyboard section handles the scanning, which the data can be written. In normal cause an Interrupt to occur at row 23. This debounce, and encoding of mechanical or Implementations, once the screen fills up, Interrupt routine then enables the line capacitive keyboards with up to 128 keys the space for the next row of data Is pro- zero interrupt, so that another interrupt utilizing any of four programmable rollover vided by removing the top row and moving occurs at row 24. The line zero (row 24) In- modes. An internal ROM provides any of all the remaining rows up by one row, thus terrupt routine disables the line zero inter- four key codes for a depressed key. The creating a blank data row at the bottom of rupt so that another line zero Interrupt is communications section Is a universal the screen into which the new Information not asserted until the split screen (row 23) asynchronous receiver and transmitter Is placed. (The process may be reversed If Interrupt routine enables It again. (UART) with programmable character the new data Is to be written at the top of length, parity, and stop bits. A baud rate the screen). This technique creates a When a scroll Is desired, the system soft- generator providing 16 standard com- readability problem when viewing data ware changes the screen start address to munications frequencies which operates which Is being received at a relatively high the new value (normally an address 'n' directly from a crystal Is also Incorporated speed, since the rows are Jumping up (or characters higher than the previous value, In the 2671. down) at a fast rate. Smooth or soft scroll- where 'n' Is the number of characters per ing Improves readability by moving the row) and sets a scroll flag. The top row 2672 Programmable Video Timing Con- data In scan line Increments Instead of in disappears and normally the display troller (PVTC) whole row lumps, thus creating the effect would Jump up by one row. However, the The 2672 Is designed for use in CRT ter- of a sheet of paper slowly being moved line zero Interrupt routine notes that the minals and other display systems that through the viewing area. One system scroll flag Is set and adds the value 's-2' employ raster scan techniques. It restriction of providing the smooth scroll. (s scan lines/row) to the vertical back generates the vertical and horizontal timing feature is that the rate at which new porch (IR3). This causes the next active ing for the CRT monitor, and provides the rows of data can be received is limited to screen display to begin 's-2' lines later addressing for the display buffer memory. the rate at which the display Is being than normal and gives the effect of the The CPU to display buffer Interface can be moved. Thus, successive line feeds must display moving up two scan lines Instead programmed for several different modes be separated by a minimum number of real of Jumping a full row. If nothing else were of operation, including full screen buffer, or dummy 'fill' characters in order to allow changed, however, the bottom of the multiple page buffer, or row buffer, as re- the display to keep up with the received display would move down the same quired by the application. Programmable data. The number of fill characters will be number of scan lines. Thus, during the features of the PVTC include screen for- a function of the number of scan lines per spilt screen Interrupt routine the number mat (characters per row, scan lines per character row, the scroll rate, and the of scan lines per character row (IRO) is row, rows per screen), horizontal and ver- communications line speed, and may also changed to two, causing only the first two tical timing parameters, cursor type, inter- be effected by the Inclusion of software scan lines of that row (which is the new laced or non-interlaced operation, and and/or hardware features such as a data character and cursor blink timing. buffer in the system design. 1Rows are numbered consecutively start- 2873 Video and Attributes Controller When using the CRT chip set, smooth ing with row 0. Thus, row 23 Is the twenty- The 2673 is a bipolar LSI device that con- scrolling can be Implemented In software fourth row of characters.

6.44 Signetics MICROPROCESSOR DIVISION JANUARY 1983

2670171172173 CRT SET APPLICATION BRIEFS App Note 403

INTERRUPT ENTRY

FIRST ROW OF STATUS REGION NO SPLIT YES LAST ROW OF SCROLLING REGION

WRITE REQUIRED SCAN RESTORE SCAN LINES/ROW LINES/ROW INTO PVTC IRO TO NORMAL VALUE IRO FROM (XXX)

DISABLE LINE ZERO INTERRUPT WRITE SCREEN START REGS TO FIRST ADDRESS OF 25th STATUS ROW i

WRITE SCREEN START REGS TO FIRST ADDRESS OF DISPLAY FROM (YYY) ENABLE LINE ZERO INTERRUPT

RESET SCROLL FLAG

SET (XXX) TO TWO INCREMENT (XXX) SCAN LINES/ROW BY TWO SCAN LINES PER ROW

INCREMENT (YYY) BY NUMBER OF CHARACTERS IN A ROW

INCREASE VERTICAL BACK PORCH BY NORMAL NUMBER OF SCAN LINES/ROW - (XXX)

RESET INTERRUPTS AND RETURN

(XXX) l INTERNAL CPU REGISTERS (YYY)

Figure 1. Smooth Scroll Flow Chart

Signetics 6.45 MICROPROCESSOR DIVISION JANUARY 1983 2670/71/72/73 CRT SET APPLICATION BRIEFS App Note 403

row) to be displayed and maintaining the lines to scroll into the 4-bit latch during address for the non-scrolled region at proper value for the total scan lines. The the vertical retrace interval. The scan line the top of the screen is loaded and IR10 next line zero interrupt restores the lines adder detects when the sum of the offset is loaded with the row number required per row value back to its normal state to and the scan line address is greater than for interrupt 1. display the whole of the last character the programmed number of scan lines per 2. During interrupt 1, a new screen start row, and now decreases the vertical back row and causes the RAM address to be address for the scrolled region is porch increment by two. The display automatically offset to the next character loaded (if required), IR10 is loaded with moves up two more scan lines and at the row by the n-bit RAM address adder. The the value required for interrupt 2, and next split screen interrupt four scan lines CPU adjusts the value in the scan lines to the lines to scroll latch is loaded with are allowed. The process continues in this scroll latch at desired intervals, e.g., each five bits of data consisting of the four- manner until the scroll is completed. vertical retrace, to effect the smooth bit lines to scroll value plus an scroll. When the scroll is completed, the asserted 'scroll' bit. The hardware will Note that the CPU must complete the split screen start address is changed to the cause the scan line offset to be applied screen interrupt routine within two scan new value required for the top character to the adder at the beginning of the line times. row. next character row, as required. 3. During interrupt 2, a new screen start Hardware/Software Method address for the non-scrolled region at If only a partial screen scroll is required, The hardware/software method of smooth the bottom of the screen is loaded (if the hardware must be modified to cause scroll removes the restrictions of the soft- required), and the 'scroll' bit is the offset to be applied only during the ware only method. The scrolling region negated. The hardware will cause the scrolling area. The lines to scroll latch of can begin and end at any character row, scan line offset to be removed from the Figure 2 is replaced by the circuit shown scrolling can be performed in either the up adder at the beginning of the next in Figure 3. The software is written with or down direction, and the minimum scroll character row, as required. If the scroll split screen interrupts at the row before increment can be one scan line. region extends to the bottom of the the first row which is to be scrolled (inter- visible screen, this interrupt is not re- rupt 1) and at the last scrolled row (inter- A block diagram of the required hardware quired. Note that the time required to rupt 2). The required program actions are for the case of full screen scroll is il- service this interrupt will determine the as follows: lustrated in Figure 2. When scrolling is re- minimum number of scan lines per quired, the CPU writes the number of scan 1. During vertical retrace, the screen start scrolling increment.

FULL ADDER RAM (NOTE 1) 4

VAC ► VIDEO

ATTRIBUTE I LATCH DATA

BLANK CARRY PVTC DDS-13 LOGIC ADDRESSES D (NOTE 2) FULL ADDER DCGG DO-D9

DATA LATCH BUS

LOAD SCROLL

NOTES: 1. Hardwire adder inputs to number of characters per row. 2. Carry logic asserts output when output of adder exceeds normal scan lines/row.

Figure 2. Smooth Scroll Hardware Block Diagram

6.46 Signetics MICROPROCESSOR DIVISION JANUARY 1983 2670/71/72/73 CRT SET APPLICATION BRIEFS App Note 403

VSYNC

LINE ZERO BLANK CLK CLK R 74LS74 74LS74 DADD8 D IS

SCROLL

74LS174 TO SCAN 02 LINE ADDER FROM (FIGURE 2) CPU D1

DO CLK

LOAD SCROLL

Figure 3. Partial Screen Smooth Scroll Modification

HORIZONTAL SCROLL Horizontal scrolling allows the terminal to be used to read or write pages which are wider than the actual screen width. For example, if an actual page width of 132 INTERRUPT characters is to be displayed on a terminal with a capacity of BO characters per row, horizontal scrolling can be used to display any desired 80-character 'window' of the NO (VBLANK INTERRUPT) 132-character row. The window can be moved in response to operator keyboard WRITE PAGE START commands, allowing all 132 columns to be ADDRESS PLUS HORIZONTAL observed.The CRT set capabilities allow SCROLL INTO SCREEN horizontal scrolling in single or multiple ADD ACTUAL CHARACTERS START REGISTERS PER ROW TO PREVIOUS character increments to be implemented SCREEN START REGISTERS using software only. As described in the VALUE AND WRITE INTO 2672 data sheet, changing the contents of SCREEN START REGISTERS the screen start address register during a particular row, say row 'n', will cause the display of the next row, 'n+ 1', to begin from the new address. This feature, together with the capability to interrupt at every row via the line zero interrupt, can be used to update the contents of the screen start register once each row to effect the horizontal scroll. The software operations required are as follows (see Figure 4): 1. During the vertical retrace interval, the screen start register is initialized with the starting memory address of the display page plus the desired horizon- Figure 4. Horizontal Scroll tal scroll (in characters). Signetics 6.47

MICROPROCESSOR DIVISION JANUARY 1983 2670/71/72/73 CRT SET APPLICATION BRIEFS App Note 403

2. The line zero interrupt is enabled. Dur- through the latches to the delay of the crement once every two scan lines. The ing each interrupt service the value in video data from the VAC. external flip-flop toggles each scan line to the screen start address is in- provide a fifth bit of scan line count infor- cremented by the actual (not display) EXTERNAL VIDEO SYNC mation for the character generator. The page width. This may be done either by Some applications require overlaying of technique permits any even value of scan referencing a table of starting ad- characters on an existing video display. lines per character row from 2 to 32 to be dresses or by performing the required An example of this is the addition of sub- obtained. addition. titles to a picture display. Figure 6 illustrates a simple technique of externally COLOR DISPLAY INTERFACE synchronizing the 2672 PVTC to an exter- BIT MAPPED GRAPHICS Figure 5 illustrates the block diagram of a nal video source. The dot clock to the 2673 Figure 8 illustrates an implementation of a color monitor interface. Eight colors for VAC is stopped (character clock falling bit mapped display with the chip set. In foreground and background with three at- edge) at the start of the PVTC's sync inter- this configuration, the contents of the tributes are supplied. The system val and restarted upon occurrence of the memory will be displayed without char- operates in the character attribute mode external sync signal. The sync timing pro- acter generator translations. Thus, each with a 16-bit word of data for each grammed in the 2672 must be slightly bit in the memory corresponds to a single character: seven bits for character select, faster than the external sync rate. pixel on the display. Each horizontal scan six bits for color select, and three bits for line is defined by a contiguous set of other attributes. SCAN LINE COUNT GREATER bytes in the RAM. The data is written in THAN 16 groups of 8 bits by the CPU and is ac- The two 74LS374s delay the color informa- Certain applications may require more cessed by the PVTC in groups of 8 bits. tion by two CCLKs to allow for the two scan lines than the 16 scan lines per The character generator of a normal alpha- CCLK delays of dot data through the character row (non-interlaced) which the numeric configuration is replaced by an DCGG and VAC. The video output of the 2672 can provide. Figure 7 shows the hard- 8-bit latch to implement the one CCLK VAC selects foreground or background ware required to obtain up to 32 scan lines delay normally provided by the 2670. The color (active dot or not) for each character per character row. The PVTC must be pro- PVTC can be programmed for one scan cell via the 74LS157 multiplexer. A variable grammed for double height character line/row to cause the memory addressing CCLK delay may be required to syn- rows. This causes the scan line count out- to proceed without repetition of ad- chronize the delay of the color information puts from the 2672 (DADD4-DADD7) to in- dresses in each row.

TTLVIDI

MEMORY CHARACTER ADDRESSES DCGG VAC FROM RAM / PVTC CCLK

3 ATTRIBUTES

ADJUSTABLE DELAY

FOREGROUND COLOR MUX COLOR ATTRIBUTE RAM CK CK SELECT R Y1 —01.- RED Al • 1 B1 B i ; Y2 —Br. GREEN Cl MONITORT • „ 74LS374 74LS374 74LS157 A2 G Y3 BLUE B2 B C2 E

BACKGROUND COLOR

BLANK —

Figure 5. Color Display Block Diagram

6.48 Signetics MICROPROCESSOR DIVISION JANUARY 1983

2670171172173 CRT SET APPLICATION BRIEFS App Note 403

DOT FREQUENCY EXTERNAL ID HSYNC VSYNC VSYNC

HSYNC DOT STOP Do DOT 0 CLOCK CKK

7474

HSYNC CHARACTER CLOCK VSYNC CCLK DCLK

PVTC VAC 2872 2673

PVTC HSYNCIVSYNC

EXTERNAL HSYNCIVSYNC

DOT CLOCK

CHARACTER CLOCK —.I -

Figure 6. External Sync Lock

The PVTC can be programmed to a maximum of 256 characterslrow and 128 CHARACTER rows/screen. Thus, a 2048 by 128 bit map PVTC Is possible. If more than 128 dots are re- GENERATOR AND quired vertically, the PVTC can be pro- BLANK C LATCHES grammed for more than one scan line/row and the scan line outputs can be used as DADD7 L4 part of the RAM address, creating several DADD6 L3 segments of memory. For example, if 256 DADD5 L2 lines are required, the PVTC must be programmed for two lines/row. The use of DADD4 LAO as part of the memory address LO creates two segments. The CPU writes the data for odd scan lines in one segment of HSYNC CK the memory and the data for even scan lines in the other. As the PVTC accesses the RAM the scan line count will go from 0 VSYNC to 1 addressing the even and then odd por- TWO 2670'8 OR tion of the RAM for each character row. EQUIVALENT

Figure 8 shows the DCGG as optional. By >o using the 2672's split screen capability and changing 2672 parameters, the CPU can enable the DCGG to be active for a portion of the screen thereby incor- porating both bit-mapped and alpha- Figure 7. Greater Than 16 Scan Lines Per Row numeric sections on the same display. Signetics 6.49

MICROPROCESSOR DIVISION JANUARY 1983 2670/71/72/73 CRT SET APPLICATION BRIEFS App Note 403

OPTIONAL

SYSTEM DCGG DECODE HSYNC VSYNC LOGIC CHARACTER L DATA CCLK

— CE

RAM SBIT PVTC VAC x LATCH DOT DATA

DISPLAY ADDRESSES CPU ADDRESS BUS

PVTC CONTROL >I BIDIRECTIONAL LATCH

CPU

CPU DATA BUS CPU CONTROL

Figure 8. Implementation of Bit Mapped Display

6.50 Signetics Section 7 Microsystems

Signetics

JANUARY 1983 SMDEV10000 S68000 USER WORK STATION (UWS) Signetics PRODUCT BRIEF

FEATURES DESCRIPTION • Permits existing support The Signetics User Work Station (UWS) is a low cost, but powerful, tool equipment to be utilized designed to work with Signetics language translators in a cross devel- • 8MHz Hardware in-circuit opment environment. The UWS provides the capabilities required to emulation via Signetics execute and debug software for the SCN68000 microprocessor. Soft- Footprint ware is first entered via the host computer text editor and then assem- • Includes ROM resident bled or compiled utilizing Signetics cross development software tools. debugger and confidence The generated object code is downloaded to the UWS via a serial com- tests munications link. The engineer proceeds to test and debug the software • 8MHz SCN68000 using the UWS ROM resident debugger to set execution breakpoints, microprocessor examine and modify registers, and make changes to the software utiliz- • 64Kb of the total RAM ing the resident line oriented assembler/disassembler. The debugging complement mappable to the process may be accomplished entirely within the UWS or the available system under development UWS memory may be mapped into the system under development. The • 4 serial communications ports connection to the system under development is accomplished with the as well as serial and emulation cable and FootprintTM probe which makes all pins of the Centronics parallel printer SCN68000 available for connection of oscilloscope and logic analyzer interfaces probes in addition to providing full 8MHz hardware emulation of the • Designed to function with SC N68000. Signetics cross software products

TmFootprint is a trademark of Signetics Corporation. 7.1 Signetics MICROPROCESSOR DIVISION JANUARY 1983 SMDEV10000 S68000 USER WORK STATION (UWS)

PERIPHERAL SUPPORT ASSEMBLER/DISASSEMBLER address locations until a null line ora control Z is entered. Each instruction is The UWS firmware supports a variety of One of the most useful features of the verified as it is stored in memory. As each peripheral devices that are normally re- Signetics UWS is a resident line oriented line is entered, both the relative and ab- quired in the development process. The assembler and disassembler. This feature solute addresses of the generated code, primary peripheral device supported by facilitates the debugging process by per- as well as the resultant machine code, is the UWS is the console terminal. It can be mitting the engineer to translate existing displayed on the CRT. The disassemble of nearly any type but must transmit serial Hex values of the machine code into read- (DI) command allows the UWS to accept a data in the speed range of 110 to 19,200 able mnemonics, or to create and insert range of addresses where code is to be bits per second and have an interface new SCN68000 instructions into the rou- disassembled. As a result of this opera- which conforms to the RS-232 interface tine being tested. The assemble (AS) com- tion, the engineer will be able to display definition. The UWS supports a serial mand causes the UWS debugger to enter a the relative and absolute instruction printer interface and a Centronics parallel line assembler mode at a user specified address, a Hex translation of the machine printer interface. These hard copy devices address. the engineer may begin entering code, the instruction mnemonic, and the may be used to maintain a permanent SCN68000 assembler instructions from instruction operands within the specified record of trace data, breakpoint lists, the keyboard. The instructions will be range. PROM contents, and other information assembled and stored at consecutive that the UWS firmware can provide. A serial port connection is provided for a The following is an example of the assemble command: PROM programmer interface. The firm- MA 1 ware contains drivers for the DATA I/O >AS 10000 Model 19 and Kontron PROM program- *CLR.L DO mers. In addition, commands are present 010000 010000 INS= 4280 CLR.L DO to allow reading, writing, and verifying of *CLR.L D1 PROMs. The host computer interface is 010002 010002 INS= 4281 CLR. L D1 designed to be compatible with standard *CRL.L D2 modems or short distance line drivers that 010004 010004 INS= 4282 CLR.L D2 support the RS-232 interface. The UWS *MOVEA.L 10200,A0 firmware supports transparent terminal to 010006 010006 INS= 207900010200 host operation, downloading of object MOVEA.L 10200n.L,A0 *MOVEA.L 10204,A1 code from the host to the UWS and up- 01000C 01000C INS= 227900010204 loading of debugged or partially debugged MOVEA.L 10204n.L,A1 *MOVEA.L 10208,A2 object code from the UWS to the host. 010012 010012 INS= 247900010208 MOVEA.L 10208n .L,A2 *MOVE.L DO,[A01 CONFIDENCE TESTS 010018 010018 INS= 2080 MOVE.L DO,[A0] A set of ROM resident confidence tests *MOVE L D1,[A1] are included in the UWS. These tests are 01001A 01001A INS= 2281 MOVE L D1,[A1] intended to provide a set of known opera- *MOVE.L D2,[A2] tions on the serial and the parallel inter- 01001C 01001C INS= 2482 MOVE.L D2,[A2] faces that the UWS may be commanded to *ADD.L #1,[A0] execute to aid in the installation of the 01001E 01001E INS= 5290 ADDQ.L #1,[A0] unit. In addition, a test of the RAM *ADD.L #2,[A1] memory is executed each time the UWS 010020 010020 INS= 5491 ADDQ.L #2,[A1] power is turned on. If any errors are *ADDQ.L #3,[A2] encountered in RAM memory, the "Power 010022 010022 INS= 5692 ADDQ.L #3,[A2] Fail" LED on the front panel will remain lit *JMP 10000n.L and the UWS will halt. The execution of 010024 010024 INS= 4EF900010000 JMP.L l0000ni the confidence tests is controlled by switch settings in the UWS and is not dependent on a functioning console terminal or other peripheral devices.

7.2 Signetics MICROPROCESSOR DIVISION JANUARY 1983 SMDEV10000 S68000 USER WORK STATION (UWS)

COMMAND SUMMARY Abort Manual Breakpoint Assemble Map Auto Dtack Mode Clock Patch Memory Configure Patch Registers D H Delete Breakpoint Read PROM Delete Offset Record Delete Trace Set Breakpoint Disassemble Set Offset Display Memory Set Trace Display Registers Single Step Mode Download Single Step • Does not restrict the user to one Centronics Parallel Printer Cable Go Start Output specific peripheral device Emulation Cable Host Stop Output FootprintTm probe List Breakpoint Trigger • Uses an established 68000 format Coaxial Clock Cable List History Upload • The results of a debug session can be List Offset Verify PROM stored and retrieved at a later time Physical Characteristics List Trace Write PROM • Offers increased timing flexibility and Height: 5.22 inches FEATURES permits debugging to occur with or Width: 16.88 inches without a target system Depth: 22 inches • The UWS is designed to allow software Weight: 21 pounds • Gives a user greater control of the development to occur on mainframes Shipping weight: 31 pounds or minicomputers debugging environment • The UWS has incorporated the most Electrical Requirements desirable features of more expensive OPERATING ENVIRONMENT 117 Volts AC ±- 10%, 60Hz -± 15% emulation systems User Supplied Required Hardware • The UWS provides the capability for One asynchronous CRT terminal with EIA Environmental Characteristics both hardware emulation and RS-232 interface. Operating temperature range: 0° to 40°C software execution One modem or suitable substitute that Operating humidity range: 0 to 95% • Both the serial and parallel ports may provides an EIA RS-232 interface for asyn- relative humidity with no condensation. be reconfigured to match available chronous communication with the host peripherals computer. ORDERING INFORMATION • The UWS upload/download utility accepts object records in Motorola User Supplied Optional Hardware SMDEV10000 S68000 User Work Station (UWS), 110-120 volt S-record format One Data I/O Model 19 PROM programmer 60Hz • The UWS permits object code to be or Kontron PROM programmer. SMDEV10010 S68000 UWS either downloaded or uploaded One asynchronous serial printer with FootprintIm probe, spare • The UWS can use an internal or RS-232 interface. SMDEV10015 S68000 UWS 8MHz external clock One Centronics parallel interface printer. Emulation Cable, spare • Up to 10 concurrent breakpoints are supported Required Software SMDEV10020 S68000 UWS Cable Set, spare. Includes: One or more Signetics language Power Cable BENEFITS translators. CRT Cable Hardware which already exists in the • Host resident upload/download software Test/PROM work environment can continue to be (included with Signetics language Programmer Cable used and shared for software translators). Centronics Parallel development Printer Cable • Provides a low cost solution for Equipment Supplied Coaxial Clock Cable 68000 code development UWS with power cord DOCUMENTATION ORDERING • Reduces development and debugging User Manual INFORMATION time and increases user CRT Cable productivity Test/PROM Programmer Cable SMMAN3100 S68000 UWS User Manual SMMAN7100 S68000 UWS Reference Card

Signetics 7.3 JANUARY 1983 SMSFP10000 S68000 CROSS SOFTWARE MACRO ASSEMBLER Signetics PRODUCT BRIEF

FEATURES DESCRIPTION • Powerful, Motorola-compatible The Signetics 68000 Macro Assembler is a powerful assembler that assembly language combines the convenience of Motorola compatible instruction mne- • Interfaces directly to monics with an unambiguous language definition and many useful con- Signetics 68000 Pascal structs usually found only in high level languages. The Signetics 68000 • Unambiguous source Macro Assembler is a perfect complement to high level languages and language definition an excellent implementation language with capabilities such as modu- • Registers may have symbolic lar programming support, record and field data definition ability, a names source library facility that includes source only when referenced, and • Highly flexible constant assembler directives that minimize the task of parameter passing to definition subroutines. The Signetics macro facility offers normal macro features • Both symbolic and mnemonic such as parameter substitution and nesting but is not a character ori- logical operators are ented facility and does not support concatenation of symbols. The supported linkage editor for linking separately assembled modules is included in • Jump instruction format is the package. This linkage editor may also be used with the object mod- optimized automatically ules generated by the Pascal cross compiler, or to link Pascal and • Full complement of assembler assembler generated modules together. The upload and download soft- directives ware that allows host communication is also included in the package. It • "Section" directive allows is designed to interface with the Signetics User Work Station (UWS) and complete control of code and allows transfer of object code between the host computer and the UWS data placement as well as between the UWS and the host computer. • Record and Field capabilities for highly structural data definitions • Structured conditional assembly directives • Modular programming support • Source library facility • Powerful macro facility • Linkage editor and download software included

7.4 Signetics

MICROPROCESSOR DIVISION JANUARY 1983 SMSFT10000 S68000 CROSS SOFTWARE MACRO ASSEMBLER

BENEFITS • The Signetics 68000 Macro Assembler is Motorola instruction compatible, so no extensive retraining is required for software engineers. E8000 A S SE M SLY • The modular programming support SOURCE allows sharing of program modules CODE generated by the assembler or by high level languages such as Pascal. • Sections of source code identified as libraries by the "LIB" and "ENDLIB" assembler will process automatically if they are referenced. • The use of subroutines is encouraged • The conditional and duplicated by the availability of assembler direc- assembly capabilities allow maximum tives that support the definition and flexibility in source code structure. manipulation of parameter lists.

OPERATING ENVIRONMENT Operating System Computer Requirements VMS any VAX-11 computer (a.) VMS V2.4 or later (b.) 64Kb of real memory per active assembler user (c.) 10Mb of disk storage RSX-11M any PDP-11 computer; (a.) RSX-11M V3.2 or later any LSI-11/23 series computer (b.) minimum 128Kb total system memory to support one assembler user; 64Kb for each additional assembler user (c.) 10Mb of disk storage

Contact Rikki Kirzner for further product information on computers, operating systems, media, or formats not shown.

ORDERING INFORMATION

Order No. Product Operating System Media SMSFT10000 S68000 Macro Assembler* VMS Half-inch magnetic tape 800 BPI

SMSFT10300 S68000 Macro Assembler* RSX-11M Half-inch magnetic tape 800 BPI

SMSFT10390 S68000 Macro Assembler* RSX-11M 8-inch double density diskette

DOCUMENTATION ORDERING INFORMATION

Order Number Product SMMAN5205 S68000 Macro Assembler Reference Manual

SMMAN7211 S68000 Macro Assembler Installation Guide, RSX-11M Operating System

SMMAN7210 568000 Macro Assembler Installation Guide, VMS Operating System

SMMAN3231 S68000 Macro Assembler User Guide

*Requires software license agreement.

SignetiCS 7.5 JANUARY 1983 SMSFT16000 S68000 CROSS SOFTWARE PASCAL CROSS COMPILER Signetics PRODUCT BRIEF

FEATURES DESCRIPTION • High level structured The Signetics 68000 Pascal Cross Compiler is a powerful, flexible, high programming language level programming language. It complies with the IEEE 770-81 standard • Structured data types which is based on the Pascal language developed by Niklaus Wirth in — Array, string, record, 1968. The compiler provides a highly structured environment that boolean, character simplifies program development, produces more reliable code, and in- — User-defined data types creases the productivity of the software engineer. Programming errors • Modular programming are minimized by complete checking of data types within modules in- extensions cluding user defined data types. • Assembly language program The Signetics 68000 Pascal Cross Compiler is designed to be extremely interface modular with an emphasis on portability. The compiler, itself, is a result • Complies with IEEE 770.81 of utilizing truly state-of-the-art compiler design techniques to produce standard a superior language translator. • Generates 68000 native code The Pascal Cross Compiler allows the mass storage and development • PROM-able run-time code tools available on minicomputers and mainframes to be used in the • Full listing format control creation of microprocessor software. It is not necessary to purchase expensive, special purpose computers that are typically used only for • Flexible compiler option microprocessor software development. The upload/download software control provides a convenient path for object code to be sent from the host • Cross linkage editor and computer to the Signetics User Work Station (UWS) and for partially or upload/download software completely debugged object code to be saved on the disk of the host included computer. All object code is sent utilizing a protocol that includes error detection and control facilities to insure the validity of the transmitted data.

7.6 Signehcs

MICROPROCESSOR DIVISION JANUARY 1983 SMSFT16000 S68000 CROSS SOFTWARE PASCAL CROSS COMPILER

SIGNETICS PASCAL EXTENSIONS Separate Compilation — Allows modular programming and facilitates sharing of routines by multiple programs and projects. Assembly Language Interface — Permits mixing Pascal and assembly language routines for maximum performance and ease of direct hardware control. INCLUDE Facility — Facilitates sharing of source code and declarations of constants and variables by multiple programs and projects. Compile Time Switches — Provides control of compiler options such as array index checking. Assembly Code Generation — Simplifies performance tuning of critical program modules.

EXAMPLE The following Pascal program is an example of the structure of a Pascal program. This program is designed to eliminate all trailing blanks from the end of each line within a file such that the line termination character occurs after the last non-blank character in the line. It illustrates the use of subroutines, typing of variables, and loop structures. The actual implementation of input and output routines is system dependent, but the read and write statements used are those of the IEEE 770-81 standard .

program compact (source, destination); const BLANK=' LINESIZE= 140; type linerange= 1..LINESIZE; linetype= packed array[linerange] of char; var source, destination : text; line : linetype; length, cur, lastnonblank linerange: c : char; procedure getsourceline; begin length := 1; line[length] := BLANK; while not (eoln (source)) and (length < LINESIZE) do begin read (source, c); line[length] := c; length := length + 1 end; readln (source); if length > 1 then length := length — 1 end; begin reset (source); rewrite (destination); while not eof(source) do begin getsourceline; lastnonblank := 1; for cur := 1 to length do if line[cur] < > BLANK then lastnonblank := cur; for cur := 1 to lastnonblank do write (destination, line[curl]); writeln (destination) end end.

Signetics 7.7 MICROPROCESSOR DIVISION JANUARY 1983 SMSFT16000 S68000 CROSS SOFTWARE PASCAL CROSS COMPILER

BENEFITS • Signetics Pascal provides a standard- ized environment for developing software for the 68000. • It allows individuals familiar with Pascal to be immediately productive. • It is easy to learn since the IEEE 770-81 standard it adheres to is based on the Niklaus Wirth software engineering teaching vehicle. • It has few machine specific extensions to maximize portability. • It improves productivity by allowing source code interlisted as comments storage allocation for maximum use of multiple programs and projects to to minimize the task of performance target system resources. share both source and object code. tuning in real time systems. • An object module linker with library • An assembly language interface is pro- • A full range of listing controls is pro- capability is included with the Pascal, vided to allow direct manipulation of vided to enhance maintainability of the which links together Pascal and hardware and maximize the perfor- source code. assembly language modules and mance of time critical modules. • The compiler generated code is opti- allows specification of starting • The Pascal compiler can optionally mized in constant and sub-expression addresses of all modules. generate assembly language with usage, array indexing, jumps, and OPERATING ENVIRONMENT Operating Computers Requirements System VMS any VAX-11 computer (a.) 64Kb of real memory per active compiler user (b.) VMS V2.4 or later (c.) 10Mb of disk storage RSX-11M any PDP-11 computer; (a.) RSX-11M operating system V3.2 or later any LSI-11/23 series computer (b.) minimum 128Kb total system memory to support one compiler user; 64Kb for each additional compiler user (c.) 10Mb of disk storage

ORDERING INFORMATION Order Number Product Operating System Media SMSFT16000 PASCAL 68000* VMS Half-inch magnetic tape 800 BPI S68000 Macro Assembler* SMSFT16300 PASCAL 68000* RSX-11M Half-inch magnetic tape 800 BPI S68000 Macro Assembler* SMSFT16390 PASCAL 68000* RSX-11M 8-inch double density diskette S68000 Macro Assembler* Other host computers, operating systems, or alternate media contact factory. DOCUMENTATION ORDERING INFORMATION Order Number Product SMMAN5200 S68000 Pascal Language Reference Manual SMMAN5205 S68000 Macro Assembler Reference Manual SMMAN7200 S68000 Pascal Installation Guide, VMS Operating System SMMAN7210 S68000 Macro Assembler Installation Guide, VMS Operating System SMMAN7201 568000 Pascal Installation Guide, RSX-11M Operating System SMMAN7211 S68000 Macro Assembler Installation Guide, RSX-11M Operating System SMMAN3230 S68000 Pascal Compiler User Guide SMMAN3231 S68000 Macro Assembler User Guide *Requires software license agreement. 7.8 Signetics Section 8 Appendices

Signetics

MICROPROCESSOR DIVISION JANUARY 1983

PACKAGES—GENERAL INFORMATION

INTRODUCTION Plastic Only 11. Lid Material a. Nickel or tin plated nickel, weld seal. The following information applies to all 5. Lead material: Alloy 42 (Nickel/Iron Al- b. Ceramic, glass seal. packages unless otherwise specified on in- loy) Olin 194 (Copper Alloy) or equiv- c. ASTM alloy F-15 or equivalent, gold plated, dividual package outline drawings. alents, solder dipped. alloy seal. 6. Body material: Plastic (Epoxy) d. Be° Ceramic with glass seal. General 7. Round hole in top corner denotes lead 12. Signetics symbol, angle cut, or lead tab 1. Dimensions shown are metric units (mil- No. 1. denotes Lead No. 1. limeters), except those in parentheses 8. Body dimensions do not include molding 13. Recommended minimum offset before which are English units (inches). flash. lead bend. 2. Lead spacing shall be measured within 14. Maximum glass climb .010 inches. this zone. Hermetic Only 15. Maximum glass climb or lid skew is .010 a. Shoulder and lead tip dimensions are to 9. Lead material inches. centerline of leads. a ASTM alloy F-15 (KOVAR) or equivalent— 16. Typical four places. Tolerances non-cumulative 3. gold plated, tin plated, or solder dipped. 17. Dimension also applies to seating plane. 4. Thermal resistance values are deter- b. ASTM alloy F-30 (Alloy 42) or equivalent— mined by utilizing the linear temperature tin plated, gold plated or solder dipped. dependence of the forward voltage drop c. ASTM alloy F-15 (KOVAR) or equivalent— across the substrate diode in a digital gold plated. device to monitor the junction tempera- 10. Body Material ture rise during known power applica- a. Eyelet, ASTM alloy F-15 or equivalent— tion across VCC and ground. The values gold or tin plated, glaSs body. are based upon 120 mils square die for b. Ceramic with glass seal at leads. plastic packages and a 90 mils square c. 1380 ceramic with glass seal at leads. die in the smallest available cavity for d. Ceramic with ASTM alloy F-30 or equiv- hermetic packages. All units were sol- alent. der mounted to P.C. boards, with standard stand-off, for measurement.

THERMAL RESISTANCE

NO. OF LEADS eJA 0J0 Plastic DIP 14 150 65 16 160 75 24 106 49 28 116 53 40 70 50

Ceramic DIP 14 95 25 16 90 25 28 60 25 40 55 25

For other ratings not listed here, contact your nearest Signetics sales office.

Signetics 8.1

MICROPROCESSOR DIVISION JANUARY 1982

PACKAGE OUTLINES

N PACKAGE - PLASTIC (16•PIN)

EAD NO. 1

6.40 (.252) 6.22 (.245)

19.18 (.755) 3.18 C125) 18.92 1.745)

0.89 C035) 0.38 (.015) 1.32 ( 052)r_ 1.12 ( 044) 2.79r 1.110)-1 33:0:4 ((:13250 -17°::37 ((.3398:H/ 761.030) 2.29 (.090) 051 (.020) 0.53 L021 NON- 0.38 C015 CUMULATIVE

I PACKAGE - HERMETIC (16.PIN)

7.71LEAD - NO. 1 1- 7.87 (.310) 7.11 (.280) _I_ 20.70 (.815) v I 19.93 (.785) 1.85 (.065) 12.95 (.510) . 1.40 1.055) 8.13 (.320) 0.51 (.020) 12.45 (.490) 1 0.63 1.0251 3 05 h20) 2.03 C080) NOTE 2 13.1.005) MIN. 0.31 (.012) 0.20 1.008) 1.52 1.080) I 8.74 (.344) 1.14 1.045) 4.45 1.1751 7.11 1.280) 2,791.110) 3.18 (.126) 0.53 (.021 2.29 1.090) 0.38 1.015 NON- CUMULATIVE

8-2 Signetics MICROPROCESSOR DIVISION JANUARY 1982

PACKAGE OUTLINES

N PACKAGE - PLASTIC SLIM LINE (24-PIN)

LEAD NO. 1

8.94 (.352) 8.45 (.345)

0.80 (.031) 0.70 (.027) 30.48 (1.2001 10.41 1.410) 29.97 (1.180) 9.91 (.390) 0.89 (.035) 2.16 (.085) r0.38 1.016) I 1 1.88 (.074) 3.94 (.155) 3.68 (.145)

3.43 (.135) 0.38 (.015) 3.05 (.120) 0.25 (.010) 1.40 1.0551_.. ._ 12.57 (.495)_.] 1.14 1.045) I 10.16 (.400) 053 ( 021) 2.79 (.110) .038 (0.15) 2.29 (.090) NON- CUMULATIVE

Signetics 8.3 MICROPROCESSOR DIVISION JANUARY 1982

PACKAGE OUTLINES

N PACKAGE - PLASTIC (28.121N)

LEAD NO. 1 411111111116116 0 14.10 (.555) 0 1.595)

1.14 1.045) 38.86 (1.455) 0 51) 020) 35.78 (1.440) (C659100:11..16951 1660751) h1145..9499 194 (155) L 168 1.145) NOTE 2 t I 0.38 (.015) 0.25 (.010) fffif !!!!!!!!-43 • 43 1.32 (.052) 17.65 (.6951 1.12 (.044)1- .."- 3.05 h_ 15.24 (.600) ► (.135) 0.53 1.021.) 2.79 1.110) 2.16 1.085) F20)1 0.38 (.0151 2.29 (.090) 1.65 1.065) NON- CUMULATIVE

I PACKAGE - HERMETIC (28•PIN)

LEAD NO. 1

15.49 (.610) 14.73 (.580)

36.32 (1.430) .11 78) 15.74 1.6201 35.05 (1.380) 0 76 (.030) 14.98 1.590) 13.46 (.530) 13.46 1.5301.1 .13 IOW MIN 12.95 1.5101 12.95 (.510/ NOTE 2 T 0.31 (.012) 0.20 (.008) 1.65 (.065) 16.36 (.644) F- 0.76 (.0301 [70;3 (D21) 14.73 (.580) 0.38 1.0151 2.79 1.110) 3.05 C12 1 4.45 (.1 75) 1.52 1.060 2.29 (.090) 2.03 (.080) 3.18 (.125) 1.14 (.045) NON- CUMULATIVE

8.4 Signetics

MICROPROCESSOR DIVISION JANUARY 1982

PACKAGE OUTLINES

N PACKAGE - PLASTIC (40-PIN)

LEAD NO. 1

111111,11.111111111114.

13.84 (.545) 13.58 1.535)

OPTIONAL CONFIGURATION

TTYTTTTTYTTIrTT ?TT TY? 0.89 .035) 52.19 12.055) 0.38 (.015) 1.91 (.075) 51.81 12.040) 3 93 1 155) 15.49 (.6101 1.66 (.065) 3.68 1.145) 14.99 (.590)

NOTE 2 0.38 (.015) lgttlitr 1M-Littftjti ji t t/\ 0.25 1.0101 H /7_1.39 (.055) 3 42 1 1351 2.161.0 104 (.120) 17.65 1.695) 1.65 (.065) 2.79 1.1101 1.14 1.045) 2.29 1.0901 0.51.020) 15.24 1.6001 NON- 0.41.016) CUMULATIVE

I PACKAGE - HERMETIC (40-PIN)

LEAD NO. 1

51.56 (2.0301 50.29 (1.980) 3.05 (.120) _15.74 2.03 (.080) 14.98 L590) .13 1.005) MIN. 1.78 1.070) 13.461.530) 0.761.030) 12.95 .510 _L 1 r NOTE 2 t 0.31 1.012) 0.20 1.008) ._ 16.36 (.644) F 14.73 (.589) 1R5 L0651] I .1 1.52 (.060) 2.79 1.110)..I 0.76 (.030) 1.14 1.045) 2.29 (0901 4.45 1.1751 0.53 1.021) NON- 3.18 1.1251 0.38 1.0151 CUMULATIVE

Signetics 8.6 MICROPROCESSOR DIVISION JANUARY 1983 PACKAGE OUTLINES

I PACKAGE - HERMETIC (48-PIN)

LEAD NO.1

1 -----4- 15.34 (0.604) 14.63 (0.678)

4.32 (0.160) 81.57 (2.424) 4 3.06 (0.120) 60.36 (2.378) 1.524(0.060) 1.016 (0.040) IL ll 11 11 ll 11 ll 11 ll 11 ll 0.330 (0.013) 0.203 (0.008) 5.65 (0.616) 1.397 (0.056) 2.54 BSC -.1.1 If- 4.19 (0.165) 0.100 BSC 4.99 (0.590) 0.762 (0.030) 2.54 (0.100)

0.533(0.021) 0.381 (0.015)

I PACKAGE - HERMETIC (64-PIN)

/- LEAD NO. 1

22.96 (0.904) 22.25 (0.876) --I- 4.32 (0.170) 82.04 (3.230) 3.05 (0.120) 80.52 (3.170) 1.52 (0.060) 1.02 (0.040) 11 a ll Il Jl ll ll ll 0.33 (0.013) 0.20 (0.008) 2.54 BSC 1.- , 23.11 (0.910) 1.40 (0.055) 4.19 (0.165) 0.100 BSC 22.61 (0.890) 0.78 (0.030) 2.54 (0.100) 0.53 (0.021) 038 (0.015)

NOTE: 1. If solder dipped terminals used, terminal dimension tolerances may be increased by .001.

8.6 Signetics MICROPROCESSOR DIVISION JANUARY 1983

SALES OFFICES

MICHIGAN CANADA PENNSYLVANIA SIGNETICS Farmington Hills Etobicoke Pittsburg Phone: (313) 476-1610 Tech-Trek, Ltd. Covert & Newman Co. Phone: (416) 626-6676 Phone: (412) 531-2002 MINNESOTA Pointe Claire HEADQUARTERS Tech-Trek, Ltd. UTAH 811 East Argues Avenue Edina Phone: (514) 697-3385 P.O. Box 409 Phone: (612) 835-7455 Salt Lake City CONNECTICUT Electrodyne Sunnyvale, California 94086 Phone: (801) 486-3801 Phone: (408) 739-7700 NEW JERSEY Yalesville Parsippany Kanan Associates Phone: (201) 334-4405 Phone: (203) 265-2404 WASHINGTON Bellevue ARIZONA NEW YORK ILLINOIS Western Technical Sales Liverpool Schaumburg Phone: (206) 641-3900 Phoenix Phone: (315) 451-5470 Micro-Tex, Inc. Phone: (602) 265-4444 Spokane Melville Phone: (312) 885-1131 Western Technical Sales Phone: (5161 752-0130 Phone: (509) 922-7600 CALIFORNIA Wappingers Falls IOWA Canoga Park Phone: (914) 297-4074 Cedar Rapids WISCONSIN Phone: (213) 340-1431 Comstanr d Ic. NORTH CAROLINA Phone: (31 9)377-1575 Waukesha Cupertino Micro-Tex, Inc. Phone: (408) 725-8100 Raleigh Phone: (919) 851-2013 KANSAS Phone: (414) 542-5352 Inglewood Kansas City Phone: (213) 670-1101 OHIO B. C. Electronic Sales Irvine Worthington Phone: (913) 342-1211 Phone: (714) 833-8980 Phone: (614) 888-7143 (213) 588-3281 MASSACHUSETTS PENNSYLVANIA FOR SIGNETICS San Diego Reading Phone: (7141560-0242 Horsham Phone: (215) 443-5500 Kanan Associates PRODUCTS Phone: (617) 944-8484 COLORADO WORLDWIDE: TENNESSEE Aurora Greeneville MICHIGAN Phone: (303) 751-5011 Phone: (615) 639-0251 Bloomfield Hills ARGENTINA Enco Marketing Philips Argentina S.A. CONNECTICUT TEXAS Phone: (313) 642-0203 Buenos Aires Danbury Austin Phone: 541-7141 MINNESOTA Phone: (203) 748-3722 Phone: (512) 458-2591 AUSTRALIA Richardson Minneapolis Philips Industries Holdings Ltd. FLORIDA Phone: (214) 644-3500 High Technology Sales Lane-Cove, N.S.W. Clearwater Phone: (612) 888-8088 Phone: 61-2-427-0888 Phone: (813) 796-7086 CANADA AUSTRIA SIGNETICS CANADA, LTD. MISSOURI Osterrichische Philips Bauelemente Lighthouse Point Etobicoke, Ontario Wien Phone: (305) 782-8225 Bridgeton Phone: (416) 626-6676 B. C. lectronic Sales1 Phone: 43-222-93-26-2 SIGNETICS CANADA, LTD.ILTEE. GEORGIA PhoneE: (314) 291-110 BELGIUM Pointe-Claire, Quebec N. V. Philips & MBLE Atlanta Phone: (514) 697-3385 NEW JERSEY Bruxelles Phone: (404) 953-0067 Phone: 32-02-242-7400 East Hanover BRAZIL ILLINOIS Emtec Sales, Inc. Phone: (201) 428-0600 Ibrape Schaumburg Sao Paulo Phone: 55-011-211-2600 Phone: (312) 843-7805 REPRESENTATIVES NEW MEXICO CHILE INDIANA Albuquerque Power Enterprises Philips Chilena S.A. Kokomo ALABAMA Phone: (5051298-1918 Santiago Phone: 56-2-39-4001 Phone: 1317) 453-6462 Huntsville Electronic Sales, Inc. NEW YORK COLOMBIA KANSAS Phone: (205) 533-1735 Ithaca Sadape S.A. Overland Park ARIZONA Bob Dean, Inc. Bogota D.E. Phone: 600 600 Phone: (913) 341-8181 Thom Luke Sales, Inc. Phone: (607) 257-1111 Phone: (602) 941-1901 MARYLAND Melville DENMARK CALIFORNIA Emtec Sales, Inc. Miniwatt AIS Glen Burnie Phone: (516) 752-1630 Kobenhavn N.V. Los Gatos Phone: 45-01-69-1622 Phone: (301) 787-0220 Sierra Technology Phone: (408) 354-1626 OREGON MASSACHUSETTS FINLAND San Diego Hillsboro Oy Philips Ab Woburn Mesa Engineering Western Technical Sales Helsinki Phone: (617) 938-1000 Phone: (714) 278-8021 Phone: (503) 640-4621 Phone: 358-1-7271

Signetics 8.7 MICROPROCESSOR DIVISION JANUARY 1983 SALES OFFICES

FRANCE ITALY PERU TAIWAN R.I.C.La Radiotechnique-Compelec Philips S.p.A. Cadesa Philips Taiwan, Ltd. Paris Milano Lima Taipei Phone: 33-1.355-4499 Phone: 39-2-6994 Phone: 326070 Phone: 886-2-563-1717 GERMANY JAPAN PHILIPPINES THAILAND Valvo Signetics Japan, Ltd. Philips Industrial Dev., Inc. Philips Electrical Co. Hamburg Tokyo Makati-Rizal of Thailand Ltd. Phone: 49.40-3296-19 Phone: 813-230-1521 Phone: 868951 Bangkok Phone: 233-6330-9 GREECE KOREA PORTUGAL Philips S.A. Hellenique Philips Elect. Korea Ltd. Philips Portuguesa SARL TURKEY Athens Seoul Lisboa Turk Philips Phone: 9215111 Phone: 794-4202 Phone: 351-19-68-3121 Ticaret A.S. Istanbul HONG KONG MALAYSIA SINGAPORE Phone: 43 59 10 Philips Hong Kong, Ltd. Philips Malaysia Sdn. Berhad Philips Project Dev. Pte., Ltd. Kwai Chung Kuala Lumpur Singapore UNITED KINGDOM Phone: 852-0-245121 Phone: 77 44 11 Phone: 65-253-8811 MuIlard, Ltd. INDIA MEXICO London SOUTH AFRICA Phone: 44-01-580-6633 Peico Electronics & Elect. Ltd. Electronica S.A. de C.V. E.D.A.C. (PM, Ltd. Bombay Mexico D.F. Johannesburg Phone: 91-22-221-012 Phone: 905-533-1180 UNITED STATES Phone: 27-11-614-2362 Signetics International Corp. INDONESIA NETHERLANDS Sunnyvale, California SPAIN Phone: (408) 739-7700 P.T. Philips-Ralin Electronics Philips Nederland B.V. Miniwatt S.A. Jakarta Eindhoven Barcelona Phone: 716 131 Phone: 31-40-79-3333 URUGUAY Phone: 301 63 12 Luzilectron S.A. IRELAND NEW ZEALAND Montevideo Philips Electrical Ltd. Philips Electrical Ind. Ltd. SWEDEN Phone: 91 43 21 Dublin Auckland A.B. Elcoma Phone: 353-1-69-3355 Phone: 64-9-894-160 Stockholm VENEZUELA Phone: 46-08-67-9780 Industrias Venezolanas ISRAEL NORWAY Philips S.A. Rapac Electronics, Ltd. Norsk AIS Philips SWITZERLAND Caracas Tel Aviv Oslo Philips A.G. Phone: 58-2-36-0511 Phone: 972-3-47715 Phone: (02) 680200 Zurich Phone: 41-01-988-2211

8-8 Signetics signuties a subsidiar y of U.S.Philips Corporation Signetics Corporation 811 East Argues Avenue PO. Box 409 Sunnyvale, California 94086 Telephone 408/739-7700