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Stratix V Device Handbook Volume 1: Device Interfaces and Integration

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Stratix V Device Handbook Volume 1: Device Interfaces and Integration Stratix V Device Handbook Volume 1: Device Interfaces and Integration Subscribe SV-5V1 101 Innovation Drive 2020.09.10 San Jose, CA 95134 Send Feedback www.altera.com TOC-2 Stratix V Device Handbook Volume 1: Device Interfaces and Integration Contents Logic Array Blocks and Adaptive Logic Modules in Stratix V Devices............. 1-1 LAB ............................................................................................................................................................... 1-1 MLAB ............................................................................................................................................... 1-2 Local and Direct Link Interconnects ............................................................................................1-3 Shared Arithmetic Chain and Carry Chain Interconnects ........................................................1-4 LAB Control Signals........................................................................................................................ 1-5 ALM Resources ............................................................................................................................... 1-6 ALM Output .................................................................................................................................... 1-7 ALM Operating Modes .............................................................................................................................. 1-8 Normal Mode ...................................................................................................................................1-8 Extended LUT Mode .................................................................................................................... 1-10 Arithmetic Mode ...........................................................................................................................1-11 Shared Arithmetic Mode ..............................................................................................................1-12 LAB Power Management Techniques .................................................................................................... 1-14 Logic Array Blocks and Adaptive Logic Modules in Stratix V Devices Revision History...............1-14 Embedded Memory Blocks in Stratix V Devices................................................2-1 Types of Embedded Memory..................................................................................................................... 2-1 Embedded Memory Capacity in Stratix V Devices.....................................................................2-2 Embedded Memory Design Guidelines for Stratix V Devices...............................................................2-2 Guideline: Consider the Memory Block Selection...................................................................... 2-2 Guideline: Implement External Conflict Resolution...................................................................2-3 Guideline: Customize Read-During-Write Behavior..................................................................2-3 Guideline: Consider Power-Up State and Memory Initialization............................................. 2-7 Guideline: Control Clocking to Reduce Power Consumption...................................................2-7 Embedded Memory Features..................................................................................................................... 2-7 Embedded Memory Configurations..............................................................................................2-9 Mixed-Width Port Configurations................................................................................................ 2-9 Embedded Memory Modes...................................................................................................................... 2-11 Embedded Memory Clocking Modes..................................................................................................... 2-12 Clocking Modes for Each Memory Mode.................................................................................. 2-12 Asynchronous Clears in Clocking Modes.................................................................................. 2-13 Output Read Data in Simultaneous Read/Write........................................................................2-13 Independent Clock Enables in Clocking Modes........................................................................2-14 Parity Bit in Memory Blocks.....................................................................................................................2-14 Byte Enable in Embedded Memory Blocks............................................................................................ 2-14 Byte Enable Controls in Memory Blocks....................................................................................2-15 Data Byte Output........................................................................................................................... 2-15 RAM Blocks Operations............................................................................................................... 2-16 Memory Blocks Packed Mode Support...................................................................................................2-16 Memory Blocks Address Clock Enable Support....................................................................................2-16 Memory Blocks Asynchronous Clear......................................................................................................2-18 Altera Corporation Stratix V Device Handbook Volume 1: Device Interfaces and Integration TOC-3 Memory Blocks Error Correction Code Support.................................................................................. 2-19 Error Correction Code Truth Table.............................................................................................2-19 Embedded Memory Blocks in Stratix V Devices Revision History.................................................... 2-20 Variable Precision DSP Blocks in Stratix V Devices.......................................... 3-1 Features..........................................................................................................................................................3-1 Supported Operational Modes in Stratix V Devices............................................................................... 3-2 Resources.......................................................................................................................................................3-3 Design Considerations................................................................................................................................ 3-4 Operational Modes.......................................................................................................................... 3-5 Internal Coefficient and Pre-Adder............................................................................................... 3-5 Accumulator..................................................................................................................................... 3-5 Chainout Adder................................................................................................................................3-6 Block Architecture....................................................................................................................................... 3-6 Input Register Bank......................................................................................................................... 3-7 Pre-Adder..........................................................................................................................................3-9 Internal Coefficient.......................................................................................................................... 3-9 Multipliers.......................................................................................................................................3-10 Accumulator and Chainout Adder.............................................................................................. 3-10 Systolic Registers............................................................................................................................ 3-11 Output Register Bank.................................................................................................................... 3-11 Operational Mode Descriptions.............................................................................................................. 3-11 Independent Multiplier Mode......................................................................................................3-11 Independent Complex Multiplier Mode.....................................................................................3-16 Multiplier Adder Sum Mode........................................................................................................ 3-20 Sum of Square Mode......................................................................................................................3-23 18 x 18 Multiplication Summed with 36-Bit Input Mode.........................................................3-24 Systolic FIR Mode.......................................................................................................................... 3-25 Variable Precision DSP Block Control Signals...........................................................................3-27
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