4/1/2019 Indian Institute of Technology Jodhpur, Year 2018‐2019 Digital Logic and Design (Course Code: EE222) Lecture 27: Verilog HDL contd… Course Instructor: Shree Prakash Tiwari Email: [email protected] Webpage: http: //home.iitj.ac.in/ ~sptiwari/ Course related documents will be uploaded on http://home.iitj.ac.in/~sptiwari/DLD/ Note: The information provided in the slides are taken form text books Digital Electronics (including Mano & Ciletti), and various other resources from internet, for teaching/academic use only 1 Overview ° History of Verilog® HDL ° Overview of Digital Design with Verilog® HDL ° Hello World! ° Hierarchical Modeling Concepts Verilog HDL 2 1 4/1/2019 What is Verilog HDL? ° Verilog Hardware Description Language(HDL)? • A high-level computer language can model, represent and simulate digital design - Hardware concurrency - Parallel Activity Flow - Semantics for Signal Value and Time • Design examples using Verilog HDL - Intel Pentium, AMD K5, K6, Atheon, ARM7, etc - Thousands of ASIC designs using Verilog HDL 3 What is VHDL? ° VHDL represents another high level language for digital system design. ° In this course we study Verilog HDL • reason: - used more often in electronic and computer industry - programming style is very similar to C programming language 4 2 4/1/2019 History of Verilog® HDL ° Beginning: 1983 • “Gateway Design Automation” company • Simulation environment - CiiillfbttiComprising various levels of abstraction – Switch (transistors), gate, register-transfer, and higher levels Verilog HDL 5 History of Verilog® HDL (cont’d) ° Three factors to success of Verilog • Programming Language Interface (PLI) - Extend and customize simulation environment • Close a tten tion to the nee ds o f ASIC f ound ri es - “Gateway Design Automation” partnership with Motorola, National, and UTMC in 1987-89 • Verilog-based synthesis technology - “Gateway Design Automation” licensed Verilog to Synopsys - Synopsys introduced synthesis from Verilog in 1987 Verilog HDL 6 3 4/1/2019 History of Verilog® HDL (cont’d) ° VHDL • VHSIC (Very High Speed Integrated Circuit) Hardware Description Language • Developed under contract from DARPA • IEEE standard • Public domain • Other EDA vendors adapted VHDL • “Gateway” put Verilog in public domain Verilog HDL 7 History of Verilog® HDL (cont’d) ° Today • Market divided between Verilog & VHDL - VHDL mostly in Europe - Verilog dominant in US • VHDL - More general language - Not all constructs are synthesizable • Verilog: - Not as general as VHDL - Most constructs are synthesizable Verilog HDL 8 4 4/1/2019 Verilog ° A brief history: • Originated at Automated Integrated Design Systems (renamed Gateway) in 1985. Acquired by Cadence in 1989. • Invented as simulation language. Synthesis was an afterthought. Many of the basic techniques for synthesis were developed at Berkeley in the 80’s and applied commercially in the 90’s . • Around the same time as the origin of Verilog, the US Department of Defense developed VHDL. Because it was in the public domain it began to grow in popularity. • Afraid of losing market share, Cadence opened Verilog to the public in 1990. • An IEEE working group was established in 1993, and ratified IEEE Standard 1394 in 1995. • Verilog is the language of choice of Silicon Valley companies, initially because of high-quality tool support and its similarity to C-language syntax. • VHDL is still popular within the government, in Europe and Japan, and some Universities. • Most major CAD frameworks now support both. • Latest HDL. C++ based. OSCI (Open System C Initiative). Basic Example //2-input multiplexor in gates ° Notes: module mux2 (in0, in1, select, out); • comments • “module” input in0,in1,select; • port list output out; • declarations wire s0,w0,w1; • wire type • primitive gates not (s0, select); and (0(w0, s 0, i0)in0), (w1, select, in1); or (out, w0, w1); endmodule // mux2 5 4/1/2019 Verilog® HDL Overview of Digital Design Using Verilog Overview of Digital Design Using Verilog ° Evolution of Computer-Aided Digital Design ° Emergence of HDLs ° Typical Design Flow ° Importance of HDLs ° Popularity of Verilog HDL ° Trends in HDLs Verilog HDL 12 6 4/1/2019 Evolution of Computer-Aided Digital Design ° SSI: Small scale integration • A few gates on a chip ° MSI: Medium scale integration • Hundreds of gates on a chip ° LSI: Large scale integration • Thousands of gates on a chip • CAD: Computer -Aided Design - CAD vs. CAE • Logic and circuit simulators • Prototyping on bread board • Layout by handVerilog (on HDL paper or a computer 13 terminal) Evolution of Computer-Aided Digital Design (cont’d) ° VLSI: Very Large Scale Integration • Hundred thousands of gates • Not feasible anymore: - Bread boarding - Manual layout design • Simulator programs • Automatic place-and-route • Bottom-Up design - Design small building blocks - Combine them to develop bigger ones • More and more emphasis on logic simulation Verilog HDL 14 7 4/1/2019 Emergence of HDLs ° The need to a standardized language for hardware description • Verilog® and VHDL ° Simulators emerged • Usage: functional verification • Path to implementation: manual translation into gates ° Loggyic synthesis technology • Late 1980s • Dramatic change in digital design - Design at Register-Transfer Level (RTL) using an HDL Verilog HDL 15 Typical Design Flow 1. Design specification 2. Behavioral description 3. RTL description 4. Functional verification and testing 5. Logic synthesis 6. Gate-level netlist 7. Logical verification and testing 8. Floor planning, automatic place & route 9. Physical layout 10. Layout verification 11. Implementation Verilog HDL 16 8 4/1/2019 Netlist ° A key data structure (or Alternative format: representation) in the design process is the “netlist”: n1 g1.in1 n2 g1.in2 • Network List n3 g2.in1 ° Netlist lists components and n4 g2.in2 connects them with nodes: n5 g1.out g3.in1 ex: n1 n5 n6 g2.out g3.in2 n2 n7 n7 g3.out n3 n4 n6 g1 "and" g2 "and" g3 "or" g1 "and" n1 n2 n5 g2 "and" n3 n4 n6• Netlist is what is needed for simulation g3 "or" n5 n6 n7 and implementation. • Could be at the transistor level, gate level, ... • Could be hierarchical or flat. • How do we generate a netlist? Typical Design Flow (cont’d) ° Most design activity • In 1996: - Manually optimizing the RTL design - CAD too ls ta ke care o f genera ting lower-lldtillevel details - Reducing design time to months from years • Today - Still RTL is used in many cases - But, synthesis from behavioral-level also possible - Digital design now resembles high-level computer programming Verilog HDL 18 9 4/1/2019 Typical Design Flow (cont’d) NOTE: • CAD tools help, but the designer still has the main role - GIGO (Garbage-In Garbage-Out) concept - To o bta in an op timi zed d esi gn, th e d esi gner need s t o k now about the synthesis technology – Compare to software programming and compilation Verilog HDL 19 Design Flow Design Entry High-level Analysis Technology Mapping Low-level Analysis 10 4/1/2019 Design Flow Design • Circuit is described and Entry represented: – Graphically (Schematics) – Textually (HDL) High-level • Result of circuit specification is Analysis a netlist of: – generic primitives - logic gates, flip-flops, or – technology specific primitives - Technology LUTs/CLBs, transistors, discrete Mapping gates, or – higher level library elements - adders, ALUs, register files, decoders, etc. Low-level Analysis CLB: Configurable Logic Block Design Flow Design • High-level Analysis is used to Entry verify: – correct function – rough: High-level • timing Analysis • power • cost • Common tools used are: – simulator - check functional Technology correctness, and Mapping – static timing analyzer • estimates circuit delays based on timing model and delay Low-level parameters for library elements Analysis (or primitives). 11 4/1/2019 Design Flow Design • Technology Mapping: Entry – Converts netlist to implementation technology dependent details • Expan ds library el ement s, High-level Analysis •performs: – partitioning, – placement, – routing Technology • Low-level Analysis Mapping – Simulation and Static Tools perflform low-llhkithlevel checks with: • accurate timing models, Low-level • wire delay Analysis – For FPGAs this step could use the actual device. Design Flow Design Entry High-level Analysis Netlist: used between and internally for all steps. Technology Mapping Low-level Analysis 12 4/1/2019 Design Entry ° Schematic entry/editing was the standard method in industry Schematics are intuitive. They ma tc h our use o f ga te- level or block diagrams. They imply a physical implementation. Require a special tool (editor). Unless hierarchy is carefully designed, schematics can be ° Hardware Description confusing and difficult to Languages are the new standard follow. Importance of HDLs ° Retargeting to a new fabrication technology ° Functional verification earlier in the design cycle ° Textual concise representation of the design • Similar to computer programs • Easier to understand Verilog HDL 26 13 4/1/2019 What next ° Verilog HDL contd…… 27 14.