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Performance Analysis of NAND and NOR Logic Using 14Nm Technology Node

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International Journal of Pure and Applied Mathematics Volume 118 No. 18 2018, 4053-4060 ISSN: 1311-8080 (printed version); ISSN: 1314-3395 (on-line version) url: http://www.ijpam.eu Special Issue ijpam.eu Performance analysis of NAND and NOR logic using 14nm technology node 1Priyamanga Bhardwaj, 2P. Uma Sathyakam, 3M.Marimuthu and 4S.Balamurugan 1,2,3,4SELECT, VIT University, Vellore – 14. Abstract We carried out performance analysis of NAND and NOR logic gates at 14nm technology node, to find out the propagation delay and the average power dissipation as shown by the considered gates. We have carried out the simulations for input voltages of 0.8, 0.6, 0.45, 0.3 and 0.2 volts. We simulate the given gate conditions using Silvaco SmartSPICE. The results show that in both of these logic gates when the input voltage is higher, we face more power consumption, but the propagation delay is lesser. So for optimum performance, some midway combination can be appropriately considered on a case-to-case basis. Key Words— NAND logic, NOR logic, VLSI, propagation delay, power dissipation. 1. INTRODUCTION NAND and NOR logic gates have been in existence since a few years now, to aid in different electrical and electronics applications. Applications range from simple academic and research purposes, to heavy industrial uses, to sensitive and critical defense electronic needs. Hence it becomes very important that they are designed, and thereon utilized to give the most effective, cost-friendly and efficient performances [4]. The logic gates are programmable at various technology nodes such as 10nm, 12nm, 14nm, 16nm, 20nm etc. For our research, we have considered the standard 14nm technology node. In Section II, we have presented the NAND gate design and the NOR gate design based on which the SmartSPICE code was constructed. In Section III, we have provided the circuit validation, which includes the timing diagrams derived by applying the values of the truth tables of the respective gates. In Section IV, we have carried out the performance analysis of the circuits, which includes the propagation delay and power dissipation. This section also includes the simulation plots and the tabulated readings. Section V gives the concluding remarks. 2. CIRCUIT DESIGN The Circuit Design of the two gates in CMOS technology is considered, with M1 and M2, M3 and M4 denoting the NMOS and PMOS gates respectively. The NAND Gate design [10, 11, 12] considered is as follows: 4053 International Journal of Pure and Applied Mathematics Special Issue Fig. 1 NAND Gate design considered in this work. The NOR Gate design considered [10, 12] is as follows: Fig. 2 NOR Gate design considered in this work. The NAND and NOR gates were hence constructed in the CMOS configuration, and the circuit design variables which will later be used in constructing the SmartSPICE codes. 3.CIRCUIT VALIDATION By supplying the truth table logic gate inputs in the simulation, we obtain the timing diagrams for circuit validation as follows: 4054 International Journal of Pure and Applied Mathematics Special Issue Fig. 3 Output waveform of NOR gate Fig. 4 Output waveform of NAND gate The timing diagrams of the NAND and NOR gates were hence obtained by providing the logic gate truth table values, in plots having time versus v(out) in the axes. 4.CIRCUIT ANALYSIS For the performance analysis [5, 13] of the aforementioned NAND and NOR logic gates, we mainly gauge them based on the propagation delays shown by them and also the average power consumed [6] by them. These gates are designed using transistors. For simulations on these gates, we have used SmartSPICE. We have supplied varying input voltages (Vdd) of 0.2V, 0.3V, 0.45V, 0.6V and 0.8V, which has resulted in different readings of propagation delays and average power consumed [11,14]. The SmartSPICE code for NAND gate was constructed as follows: .temp 27 .param Supply=0.2 .include '14nfet_hp.lib' .include '14pfet_hp.lib' .options post .global vdd gnd vdd vdd gnd 'supply' m1 out ina vdd vdd pfet l=3e-008 m2 out inb vdd vdd pfet l=3e-008 m3 out ina d gnd nfet l=3e-008 m4 d inb gnd gnd nfet l=3e-008 va ina gnd pulse(0 'supply' 1n 0.1n 0.1n 10n 20n) 4055 International Journal of Pure and Applied Mathematics Special Issue vb inb gnd pulse(0 'supply' 1n 0.1n 0.1n 10n 20n) .tran 0.1ns 90ns .probe v(out) .measure prop_delay + TRIG v(ina) VAL='Supply/2' RISE=1 + TARG v(out) VAL='Supply/2' FALL=1 .measure output_power AVG power FROM=1n TO=10n .end The code for the NOR gate is: .temp 27 .param Supply=0.3 .include '14nfet_hp.lib' .include '14pfet_hp.lib' .options post .global vdd gnd vdd vdd gnd 'supply' m1 d ina vdd vdd pfet l=3e-008 m2 out inb d vdd pfet l=3e-008 m3 out ina gnd gnd nfet l=3e-008 m4 out inb gnd gnd nfet l=3e-008 va ina gnd pulse(0 'supply' 1n 0.1n 0.1n 10n 20n) vb inb gnd pulse(0 'supply' 1n 0.1n 0.1n 10n 20n) .tran 0.1ns 90ns .probe v(out) .measure prop_delay + TRIG v(ina) VAL='Supply/2' RISE=1 + TARG v(out) VAL='Supply/2' FALL=1 .measure output_power AVG power FROM=1n TO=10n .end For energizing the two logic gates to result in plots, we simulate the gates for ‘ina’ vs. ‘out’; while varying the Vdd in each case and in the two different logic gates. NAND Gate with 0.3V input Vdd [8]. Fig. 5 Plot for NAND gate with 0.3V input Vdd. 4056 International Journal of Pure and Applied Mathematics Special Issue Fig. 6 Plot for NAND gate with 0.2V input Vdd. Fig. 7 Plot for NOR gate with 0.3V input Vdd. Fig. 8 Plot for NOR gate with 0.2V input Vdd. Also we obtain the various readings of the propagation delays and average power consumed [3,7] with a fixed technology node & varying Vdd after simulations; and they are tabulated as follows: 4057 International Journal of Pure and Applied Mathematics Special Issue TABLE I Performance factors of NOR Gate using 14nm technology node Vd Delay Average Remar Description d (ps) power (nW) ks 0.8 -7.188 24.59 5n,10n 0.6 - 2.248 10n,20 0.0247 n 0.4 0.694 0.344 10n,20 5 n 0.3 31.99 0.567 10n,20 Glitch at n falling edge 0.2 81.86 0.479 10n,20 More glitch. n TABLE II Performance factors of NAND Gate using 14nm technology node Vdd Delay Average Remar Description (ps) power (nW) ks 0.8 7.825 35.137 5n,10n 0.6 1.229 1.508 10n,20 n 0.4 1.783 0.306 10n,20 5 n 0.3 41.29 0.319 10n,20 Glitch at n falling edge 0.2 237.37 0.407 10n,20 More glitch. n It can be seen that as the input voltage (Vdd) was decreased from 0.8V to 0.2V, the propagation delays increased exponentially for the two gates. But the average power consumed decreased for both the gates. Our simulations were done considering ambient temperature as 27°C. We had also considered PTM High Performance (PTM_hp) [15]. 5.CONCLUSIONS In this paper we have done the performance characteristics of the given two gates under some imposed conditions. Considering these conditions, the efficiency of the assumed technology node (14nm) was calculated. When the Vdd was 0.3V for both the gates, glitches were observed at the falling edges in the plots. Also at Vdd=0.2V, we experienced more glitch. So to strike a proper balance between the average power consumed and the propagation delay experienced, some set of values midway has to be taken into consideration on a case-to-case basis[9]. Further scope lies in simulating in different temperatures, and also taking into consideration different technology nodes. And further simulations can be undertaken for PTM Low Performance (PTM_lp) and so on. REFERENCES [1] Chin, P., Su, J. and Zhong, X., Analysis and Design of High Performance and Low Power Current Mode Logic CMOS. [2] da Silva, D.N., Reis, A.I. and Ribas, R.P., 2009. CMOS logic gate performance variability related to transistor network arrangements. Microelectronics Reliability, 49(9), pp.977-981. [3] Sankar, P.G. and Udhayakumar, K., 2014. MOSFET-like CNFET based logic gate library for low-power application: a comparative study. Journal of Semiconductors, 35(7), p.075001. 4058 International Journal of Pure and Applied Mathematics Special Issue [4] Hajare, R., Lakshminarayana, C., Sumanth, S.C. and Anish, A.R., 2015, December. Design and evaluation of FinFET based digital circuits for high speed ICs. In Emerging Research in Electronics, Computer Science and Technology (ICERECT), 2015 International Conference on (pp. 162-167). IEEE. [5] Von Arnim, K., Augendre, E., Pacha, C., Schulz, T., San, K.T., Bauer, F., Nackaerts, A., Rooyackers, R., Vandeweyer, T., Degroote, B. and Collaert, N., 2007, June. A low-power multi-gate FET CMOS technology with 13.9 ps inverter delay, large-scale integrated high performance digital circuits and SRAM. In 2007 IEEE Symposium on VLSI Technology (pp. 106-107). IEEE. [6] Yang, W.B., Lin, Y.Y. and Lo, Y.L., 2014, April. Analysis and design considerations of static CMOS logics under process, voltage and temperature variation in 90nm CMOS process. In Information Science, Electronics and Electrical Engineering (ISEEE), 2014 International Conference on (Vol. 3, pp. 1653-1656).
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