Makuhari Messe Chiba/Tokyo, Japan ASP-DAC 2015 Contents

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Date: January 19-22, 2015 Place: Makuhari Messe Chiba/Tokyo, Japan ASP-DAC 2015 Contents

Highlights ...... 4 Welcome to ASP-DAC 2015 ...... 6 Message from the Technical Program Committee ...... 7 Sponsorship ...... 8 Organizing Committee ...... 9 Technical Program Committee ...... 10 University LSI Design Contest Committee ...... 12 Designers’ Forum Committee ...... 12 Steering Committee ...... 13 University LSI Design Contest ...... 14 Designers’ Forum ...... 15 ACM SIGDA Student Research Forum at ASP-DAC 2015 ...... 16 Best Paper Award ...... 17 University LSI Design Contest Award ...... 18 10-Year Retrospective Most Inﬂuential Paper Award ...... 18 20th Anniversary Awards ...... 19 Invitation to ASP-DAC 2016 ...... 21 Tutorials ...... 22 At a glance ...... 25 Room Assignment ...... 26 Keynote Addresses ...... 27 Technical Program ...... 29 Supporter’s Exhibition ...... 46 IEEE CASS/CEDA Luncheon Presentations ...... 47 Information ...... 48 Author Index ...... 49

3 Highlights

Opening and Keynote I

Tuesday, January 20, 2015, 8:30-9:50

Udo Wolz (Executive Vice President and Director for Engineering and Innovation, Bosch Corporation) “The required technologies for Automotive towards 2020”

Keynote II

Wednesday, January 21, 2015, 9:00-9:50

Atsushi Takahara (Director of NTT Network Innovation Laboratories ) “Programmable Network”

Keynote III

Thursday, January 22, 2015, 9:00-9:50

Noriko Arai (Professor of Information and Society Research Division, National Institute of Informatics ) “When and how will an AI be smart enough to design?”

Special Sessions 1S: (Presentation + Poster Discussion) University Design Contest Tuesday, January 20, 2015, 10:20-13:40 2S: (Invited Talks) Internet of Things Tuesday, January 20, 2015, 13:50-15:30 3S: (Invited Talks) New Challenges and Solutions in Nanometer Physical Design Tuesday, January 20, 2015, 15:50-17:30 4S: (Invited Talks) Machine Learning in EDA: Promises and Challenges in Selected Applications Wednesday, January 21, 2015, 10:15-12:20 7S: (Invited Talks) The Future of Emerging ReRAM Technology Thursday, January 22, 2015, 10:15-12:20 9B: (Invited Talks) System-Level Designs and Tools for Multicore Systems Thursday, January 22, 2015, 15:50-17:30

Designers’ Forum 5S: (Oral Session) Car Electronics Wednesday, January 21, 2015, 13:50-15:30

6S: (Panel Discussion) Challenges in the Era of Big-Data Computing Wednesday, January 21, 2015, 15:50-17:30

8S: (Oral Session) Technology Trend toward 8K Era Thursday, January 22, 2015, 13:50-15:30

9S: (Panel Discussion) IP base SoC design and IP design innovation Thursday, January 22, 2015, 15:50-17:30

4 Tutorials

ASP-DAC 2015 oﬀers attendees a set of two-hour intense introductions to speciﬁc topics. Each tutorial will be presented twice a day to allow attendees to cover multiple topics. If you register for tutorials, you have the option to select three out of the six topics.

Tutorial-1: Ultra-low power ultra-low voltage design techniques in Fully Depleted SOI technologies Monday, January 19, 2015, 9:30-11:30, 13:00-15:00 Organizer: Andreia Cathelin (STMicroelectronics) Speakers: Giorgio Cesana (STMicroelectronics), Edith Beigne´ (CEA-Leti), Nobuyuki Sugii (LEAP)

Tutorial-2: Leading-Edge Lithography and TCAD Monday, January 19, 2015, 9:30-11:30, 13:00-15:00 Organizer: Shigeki Nojima (Toshiba) Speakers: Seiji Nagahara (Tokyo Electron), Tomoyuki Matsuyama (Nikon), Shigyo Naoyuki (Toshiba)

Tutorial-3: Normally-Oﬀ Computing: Synergy of New Non-Volatile Memories and Aggressive Power Management Monday, January 19, 2015, 9:30-11:30, 15:30-17:30 Organizers: Hiroshi Nakamura (The University of Tokyo), Takashi Nakada (The University of Tokyo) Speakers: Takashi Nakada (The University of Tokyo), Shinobu Fujita (Toshiba Corporate R&D Center)

Tutorial-4: Hardware Trust in VLSI Design and Implementations Monday, January 19, 2015, 9:30-11:30, 15:30-17:30 Organizers: Kazuo Sakiyama (The University of Electro-Communications), Makoto Nagata (Kobe University) Speakers: Patrick Schaumont (Virginia Tech, US), Swarup Bhunia (Case Western Reserve University, US), Kazuo Sakiyama (The University of Electro-Communications, JP), Makoto Nagata (Kobe University, JP)

Tutorial-5: High-Level Synthesis for FPGAs: From Software to Programmable Hardware Monday, January 19, 2015, 13:00-15:00, 15:30-17:30 Organizer: Jason Anderson (University of Toronto) Speakers: Jason Anderson (University of Toronto), Ben Carrion Schafer (Hong Kong Polytechnic University)

Tutorial-6: Electronic Design Automation for Nanotechnologies Monday, January 19, 2015, 13:00-15:00, 15:30-17:30 Organizers: Pierre-Emmanuel Gaillardon (EPFL), Giovanni De Micheli (EPFL) Speakers: Pierre-Emmanuel Gaillardon (EPFL), Luca Amaru (EPFL), Anupam Chattopadhay (Nanyang Technical University), Subhasish Mitra (Stanford University)

5 Welcome to ASP-DAC 2015

On behalf of the Organizing Committee, I would like to invite all of the engineers on the LSI design and design automation areas to the 20-th Asia and South Pacific Design Automation Conference (ASP-DAC 2015). ASP-DAC 2015 will be held from January 19th (Mon.) to January 22nd (Thur.), 2015 at Makuhari Messe, Chiba, Japan. ASP-DAC 2015 is a high-quality and premium conference on Electronic Design Au- tomation (EDA) area like other sister conferences such as Design Automation Confer- ence (DAC), Design, Automation & Test in Europe (DATE), and International Con- ference on Computer Aided Design (ICCAD). ASP-DAC has been started at 1995 and continuously offers the opportunity to know the recent advanced technologies on LSI design and design automation areas, and to communicate each other for researchers and designers around Asia and South Pacific regions. The conference site is Makuhari Messe, which is one of the biggest international convention complexes in Japan and a memorable place where the first ASP-DAC was held in 1995. Hundreds of companies are accumulated around the complex, and big events on various industrial fields including semiconductor and electronics are held every year. As Makuhari Messe is close to Tokyo, about 30 minutes by train, you can easily access the venue from Narita or Haneda international airport. Joining the conference and participating in technological discussions, you can also enjoy many attractions in Tokyo area, such as Tokyo Disneyland, the world-highest tower called Tokyo Sky Tree, Akihabara, etc. ASP-DAC 2015 received 318 submissions from 27 countries all over the world. Based on rigorous and thorough reviews and a full-day face-to-face meeting by the Technical Program Committee, 106 papers have been accepted and 26 technical sessions have been organized. 5 Special Sessions have also been organized based on invited talks by the Technical Program Committee. We have arranged 3 Keynote speakers at the beginning of each day to know the future directions of this area. The first Keynote speaker Dr. Udo Wolz, Executive Vice President of Bosch, will talk about “The required technologies for Automotive towards 2020.” The second Keynote speaker Dr. Atsushi Takahara, Director of NTT Network Innovation Laboratories, will introduce future “Programmable Network” technologies. The third keynote speech will be from Dr. Noriko Arai, Professor of National Institute of Informatics. “When and how will an AI be smart enough to design?” will be discueed in her talk. The Designers’ Forum is a unique program that will share design experience and solutions of actual product designs of the industries. This year’s program includes the invited talks on the next generation car electronics and 4K/8K TV technologies, and also includes panel disussions on data-centric computing platform and IP-based SoC design and IP design innovations. The University Design Contest is also an important annual event of ASP-DAC where more than 20 high-quality designs all including actual silicon proof were selected for presentation at Tuesday, January 20. Six tutorials have been arranged on Monday, January 19. Each tutorial has 2 hour presentation, and will be held 2 times. Registrants can take any 3 of 6 tutorials with the reduced tutorial fee depending on their interests and can obtain wider perspective on the recent hot topics on FD-SOI, Leading-Edge Lithography and TCAD, Normally-Off Computing, Hardware Trust in VLSI Design and Implementation, High-Level Synthesis for FPGAs, Electric Design Automation for Nanotechnologies. ASP-DAC 2015 offers you an ideal opportunity to touch the recent technologies and the future directions on the LSI design and design automation areas. You will be able to meet and discuss with a lot of researchers and designers on this area, so please do not miss ASP-DAC 2015. Finally, we would like to express our sincere appreciation to sponsors and supporters.

Kunio Uchiyama General Chair, ASP-DAC 2015

6 Message from the Technical Program Committee

Congratulations on the 20th Anniversary of the Asia and South Pacific Design Automation Conference (ASP-DAC)! On behalf of the Technical Program Committee of the Asia and South Pacific Design Automation Conference (ASP-DAC) 2015, we would like to welcome all of you to the conference scheduled for January 19 to 22, 2015 at Chiba/Tokyo, Japan. This year ASP- DAC is its 20th Anniversary, and the Technical Program Commit- tee proudly announce the 20th technical program. The Technical Program Committee put a special effort for the Naehyuck Chang TingTing Hwang Yasuhiro Takashima 20th technical program. First, we elaborated on the Call for Pa- pers. We performed major revision in the Subcommittees and formally defined their subtopic categories. The purpose of revision is to help authors select the right Subcommittees for their paper submissions without confusion and minimize paper migrations among Subcommittees after papers are submitted. We migrated Technical Program Committee members instead of the papers while ensuring their expertise so that the submitted papers to be reviewed in the original Subcommittees keeping the review workload balance among Subcommittees. How- ever, some papers have been migrated to avoid competition among topics rather than their technical content qualities. This year technical program is also lined up with the sister conference, Design Automation Conference. We also create a new Subcommittee for Security to accommodate the new initiatives of the future Electronics Design Automation (EDA). We organize the Technical Program Committee with 104 world-leading experts from 14 countries/regions. This year ASP- DAC received 318 submissions from 27 countries/regions with major contribution from Asia, North America and Europe. All committee members contributed to in-depth and thorough reviews. The review process ensured fairness through a rigorous double-blind review process and resolved all the conflict of interest. This year face-to-face Technical Program Committee meeting was organized as a full two-day program together with the EDA Workshop. The venue of the Technical Program Committee meeting was Daejeon Convention Center in Daejeon, Korea. Among 104 Technical Program Committee members, 94 Technical Program Committee members physically attended, and some members joined via teleconferencing due to their personal emergency. Thanks to the support from the Daejeon Convention Center, this year Technical Program Committee also provided quality supplements for the meeting. This year paper selection was a real challenge thanks to the quality and highly competitive submissions. This year technical program consists of 106 high-quality papers among 318 submissions that corresponds to a very competitive acceptance rate of 33.3%. The complete conference program consists of the regular papers, invitation of keynote speeches and special sessions, which is compiled into a three-day, four parallel-session program. The regular papers are presented in 26 sessions on tracks A, B, and C. The University LSI Design Contest session is allocated on the first day following the tradition. The technical sessions begins with a keynote address every morning. We have nine special sessions on Tracks S and B (2S through 9S and 9B), which again consist of invited talks on the state-of-the-art topics and industry provided designers’ forums. The topics of invited talks are EDA and methodologies focusing on internet of things, nanometer physical design, applying machine learning in EDA, emerging memory technology, and system-level designs and tools for multicore systems. Each Subcommittee was eligible to nominate one best paper candidate. The Best Paper Award Committee screened the nominees and finally selected seven best paper candidate papers. These best paper candidates went through a careful evaluation process by the Best Paper Award Committee composed of 18 TPC members. The Best Paper Award Committee finally selected the ASP-DAC 2015 Best Paper Award winner. The fruitful technical program of the ASP-DAC 2015 was not possible without hard working of the authors and reviewers as well as the Technical Program Committee. We pay special thanks to the authors, reviewers, the Technical Program Committee members, and Technical Program Committee Secretaries for their excellent jobs. Finally, we also would like to thank the members of the Organizing Committee for their extraordinary services. We hope you join us congratulating the 20th Anniversary of the ASP-DAC, enjoy the ASP-DAC 2015 technical program and exchange your visions for the next decade ASP-DAC and EDA research.

Naehyuck Chang TPC Chair, ASP-DAC 2015

TingTing Hwang TPC Vice Chair Yasuhiro Takashima TPC Vice Chair

7 Sponsorship

Sponsored by: ACM/SIGDA http://www.sigda.org/

IEEE Circuits and Systems Society http://www.ieee-cas.org/

IEEE Council on Electronic Design Automation http://ieee-ceda.org/

IEICE ESS (Institute of Electronics, Information and Communication Engineers – En- gineering Sciences Society) http://www.ieice.org/eng/

IPSJ SIGSLDM (Information Processing Society of Japan – SIG System and LSI De- sign Methodology) http://www.ipsj.or.jp/english/

Supported by: JEITA (Japan Electronics and Information Technology Industries Association) http://www.jeita.or.jp/english/

STARC (Semiconductor Technology Academic Research Center) http://www.starc.jp/about/profile-e/

The Telecommunications Advancement Foundation http://www.taf.or.jp/

SCAT (Support Center for Advanced Telecommunications Technology Research, Foun- dation) http://www.scat.or.jp/english/

Tateishi Science and Technology Foundation http://www.tateisi-f.org/

Chiba Prefecture http://www.pref.chiba.lg.jp/international/

Chiba City http://www.city.chiba.jp/front/foreign.html

Chiba Convention Bureau and International Center http://www.ccb.or.jp/e/

8 Organizing Committee

General Chair Kunio Uchiyama (Hitachi) Past Co-Chairs Yong Lian (National University of Singapore) Yajun Ha (National University of Singapore) GC Advisors Shigeru Oho (Nippon Institue of Technology) Ichiro Naka (Renesas Electronics) GC Secretaries Masanao Yamaoka (Hitachi) Yutaka Uematsu (Hitachi) Kotaro Shimamura (Hitachi) Yuichi Sakurai (Hitachi) Kenshu Seto (Tokyo City University) Nozomu Togawa (Waseda University) Technical Program Chair Naehyuck Chang (Seoul National University) TPC Vice Chairs TingTing Hwang (National Tsing Hua University) Yasuhiro Takashima (University of Kitakyushu) TPC Secretaries Hyung Gyu Lee (Daegu University) Chih-Tsun Huang (National Tsing Hua University) Yi-Yu Liu (Yuan Ze University) Tutorial Co-Chairs Makoto Ikeda (University of Tokyo) Tsuyoshi Isshiki (Tokyo Institute of Technology) Design Contest Co-Chairs Hiroyuki Ito (Tokyo Institute of Technology) Noriyuki Miura (Kobe University) Designer’s Forum Co-Chairs Yoshio Masubuchi (Toshiba) Koji Inoue (Kyushu University) Finance Co-Chairs Takeshi Matsumoto (Ishikawa National College of Technology) Atsushi Takahashi (Tokyo Institute of Technology) Publication Co-Chairs Shinobu Nagayama (Hiroshima City University) Masashi Imai (Hirosaki University) Publicity Co-Chairs Hiroyuki Tomiyama (Ritsumeikan University) Taeko Matsunaga (Kyushu Sangyo University) Naohito Kojima (Toshiba) Web Publicity Chair Yuko Hara-Azumi (Tokyo Institute of Technology) Tohru Ishihara (Kyoto University) Promotion Chair Yuichi Nakamura (NEC) ASP-DAC Liaison at SIGDA Student Research Forum Yukihide Kohira (The University of Aizu) STARC Liaison Takashi Aikyo (STARC) JEITA EDA-TC Rep. Masaya Sumita (Panasonic) JEITA EDA-TC Liaison Kazutoshi Wakabayashi (NEC) Secretariat Yoshinori Ishizaki (Japan Electronics Show Association) Mieko Mori (Japan Electronics Show Association) Kohei Torikai (Japan Electronics Show Association) Kayoko Oda (Japan Electronics Show Association)

9 Technical Program Committee

Technical Program Chair Naehyuck Chang (KAIST, Korea) Technical Program Vice Chairs TingTing Hwang (National Tsing Hua University, Taiwan) Yasuhiro Takashima (University of Kitakyushu, Japan) Secretaries Hyung Gyu Lee (Daegu University, Korea) Chih-Tsun Huang (National Tsing Hua University) Yi-Yu Liu (Yuan Ze University) Subcommittees and Subcommittee Chairs (* : Subcommittee Chairs) [1] System-Level Modeling and Design Methodologies * Soonhoi Ha (Seoul National University, Korea) Ing-Jer Huang (National Sun Yat-Sen University, Taiwan) Yosinori Watanebe (Cadence Design Systems, USA) Hoeseok Yang (Ajou University, Korea) Makoto Sugihara (Kyushu University, Japan) Akash Kumar (National University of Singapore, Singapore) Fan Dongrui (Chinese Academy of Sciences, China) [2] Embedded System Architectures and Design * Tulika Mitra (National University of Singapore, Singapore) Hiroyuki Tomiyama (Ritsumeikan University, Japan) Muhammad Shaﬁque (Karlsruhe Institute of Technology, Germany) Wei Zhang (Hong Kong University of Science and Technology, Hong Kong) Guangyu Sun (Peking University, China) Preeti Ranjan Panda (IIT Delhi, India) Dongkun Shin (Sungkyunkwan University, Korea) [3] On-chip Communication and Networks-on-Chips * Mehdi Tahoori (Karlsruhe Institute of technology, Germany) Jiang XU (Hong Kong University of Science and Technology, Hong Kong) Romain Lemaire (CEA-LETI, France) Koushik Chakraborty (Utah State University, USA) Yoshinori Takeuchi (Osaka University, Japan) Masoud Daneshtalab (University of Turku, Finland) [4] System-on-Chip Architectures and Design * Sri Parameswaran (University of New South Wales, Australia) Paul Bogdon (University of Southern California, USA) Angelo Ambrose (University of New South Wales, Australia) Lars Bauer (Karlsruhe Institute of Technology, Germany) [5] Device/Circuit-Level Modeling, Simulation and Veriﬁcation * Luca Daniel (Massachusetts Institute of Technology, USA) Jaijeet Roychowdhury (University of California at Berkeley, USA) Wenjian Yu (Tsinghua University., China) Ibrahim (Abe) Elfadel (Masdar University, United Arab Emirates) Dipanjan Gope (Indian Institute of Science, India) Roberto Suaya (Univ. Tecn. Nacion. Buenos Aires, Argentina) [6] Logic/Behavioral/High-Level Synthesis and Optimizations * Robert Wille (University of Bremen, Germany) Zhiru Zhang (Cornell University, USA) Anupam Chattopadhyay (RWTH Aachen University, Germany) Iris Hui-Ru Jiang (National Chiao Tung University, China) Mineo Kaneko (JAIST, Japan) Thambipillai Srikanthan (Nanyang Technological University, Singapore) [7] Analog, RF and Mixed Signals * Sheldon Tan (University of California, Riverside, USA) Guoyong Shi (Shanghai Jiatong University, China) Hai Wang (University of Electronic Science and Technology of China, China) Mark Lin (National Chung Cheng University, Taiwan) Zuochang Ye (Tsinghua University, China) [8] System-Level Power and Thermal Management * Chia-Lin Yang (National Taiwan University, Taiwan) Jae-Joon Kim (Posetech, Korea) Danella Zhao (University of Louisiana at Lafayette, USA) Takashi Nakada (University of Tokyo, Japan) Guihai Yan (ICT , China) Donghwa Shin (Yeungnam University, Korea) Yu Wang (Tsinghua University, China)

10 [9] Device/Circuit/Gate-Level Low Power Design * Masanori Hashimoto (Osaka University, Japan) Kimiyoshi Usami (Shibaura Institute of Technology, Japan) Yiyu Shi (Missouri University of Science and Technology, USA) Bing Li (Technical University of Munich, Germany) Bong Hyun Lee (Samsung, Korea) [10] Embedded Software * Jason Xue (City University of Hong Kong, China) Zili Shao (Hong Kong Polytechnic University, Hong Kong) Chengmo Yang (University of Delaware, USA) Kyoungwoo Lee (Yonsei University, Korea) Nan Guan (Northeastern University, China) Sidharta Andalam (TUM, Singapore) Qi Zhu (University of California at Riverside, USA) [11] Physical Design * David Z. Pan (University of Texas, Austin, USA) Ting-Chi Wang (National Tsing Hua University, Taiwan) Guojie Luo (Peking University, China) Shigetoshi Nakatake (Univ. of Kitakyushu, Korea) Tung-Chieh Chen (Synopsys, USA) Yongchan (James) Ban (LG Electronics, Korea) [12] Timing and Signal/Power Integrity * Hao Yu (Nanyang Technological University, Singapore) Fan Yang (Fudan University, China) Ray Cheung (City University of Hong Kong, Hong Kong) Yungseon Eo (Hanyang University, Korea) [13] Design for Manufacturability and Reliability * Evangeline Young (Chinese University at Hong Kong, China) Xuan Zeng (Fudan University, China) Shigeki Nojima (Toshiba Corporation, Japan) Martin Wong (University of Illinois at Urbana-Champaign, USA) Jae-seok Yang (Samsung, Korea) Charles Chiang (Synopsys, USA) Zhuo Feng (Michigan Technological University, USA) [14] Test and Design for Testability * Tomokazu Yoneda (NAIST, Japan) Yu Huang (Mentor Graphics, USA) Kohei Miyase (Kyushu Institute of Technology, Japan) Sungho Kang (Yonsei University, Korea) Chien-Mo Li (National Taiwan University, Taiwan) [15] Security and Fault-Tolerant Systems * Swarup Bhunia (Case Western Reserve University, USA) Jongsun Park (Korea University, Korea) Patrick Schaumont (Virginia Tech., USA) Kenneth Mai (Carnegie Mellon University, USA) Yongdae Kim (KAIST, Korea) [16] Emerging Technologies * Yiran Chen (University of Pittsburgh, USA) Jingtong Hu (Oklahoma State University, USA) Weisheng Zhao (Universite Paris-Sud, France) Duo Liu (Chongqing University, China) Danghui Wang (Northwestern Polytechnical University, China) [17] Emerging Applications I (Bio+nano+3D+quantum) * Tsung-Yi Ho (National Cheng Kung University, Taiwan) Juinn-Dar Huang (National Chiao Tung University, Taiwan) Dajiang Zhou (Waseda University, Japan) Yasushi Sugama (Fujitsu, Japan) [18] Emerging Applications II (Energy+EV+IoT+Smart grid+ Data center) * Tohru Ishihara (Kyoto University, Japan) Ittetsu Taniguchi (Ritsumeikan University, Japan) Sehwan (Paul) Kim (Dankook University, Korea) Yongpan Liu (Tsinghua University, China)

11 University LSI Design Contest Committee

Co-Chairs Hiroyuki Ito (Tokyo Institute of Technology, Japan) Noriyuki Miura (Kobe University, Japan)

Members Po-Hung Chen (National Chiao-Tung University, Taiwan) Louis Alarcon (University of the Philippines Diliman, Philippines) Byeong-Gyu Nam (Chungnam National University, Korea) Hiroaki Hoshino (Toshiba, Japan) Mitsuru Tomono (Fujitsu, Japan) Heng Chun Huat (National University of Singapore, Sigapore) Kousuke Miyaji (Shinshu University, Japan) Mang-I Vai (University of Macau, Macau) Man-Kay Law (University of Macau, Macau)

Designers’ Forum Committee

Co-Chairs Yoshio Masubuchi (Toshiba, Japan) Koji Inoue (Kyushu Univ., Japan)

Members Hiroe Iwasaki (NTT, Japan) Akihiko Okubora (Sony, Japan) Masaitsu Nakajima (Panasonic, Japan) Nobuyuki Nishiguchi (Cadence Design Systems, Japan) Shinichi Shibahara (Renesas Electronics, Japan) Masaru Kokubo (Hitachi, Japan) Koichiro Yamashita (Fujitsu Laboratories, Japan)

12 Steering Committee

Chair Hidetoshi Onodera (Kyoto University)

Vice Chair Shinji Kimura (Waseda University)

Secretaries Atsushi Takahashi (Tokyo Institute of Technology) Yutaka Tamiya (Fujitsu Laboratories) Nozomu Togawa (Waseda University)

Past Chair Hiroto Yasuura (Kyusyu University)

ASP-DAC 2015 General Chair Kunio Uchiyama (Hitachi)

ASP-DAC 2014 General Chairs Yong Lian (National University of Singapore) Yajun Ha (National University of Singapore)

ACM SIGDA Representative Naehyuck Chang (Seoul National University)

IEEE CAS Representative Takao Onoye (Osaka Univeristy)

IEEE CEDA Representative Yao-Wen Chang (National Taiwan University)

DAC Representative Soha Hassoun (Tufts University)

DATE Representative Jorg¨ Henkel (Karlsruhe Institute of Technology)

ICCAD Representative Youngsoo Shin (Korea Advanced Institute of Science and Technology)

International Members Kiyoung Choi (Seoul National University) Oliver C.S. Choy (the Chinese University of Hong Kong) Yajun Ha (National University of Singapore) Yuchun Ma (Tsinghua University) Sri Parameswaran (The University of New South Wales) Ren-Song Tsay (National Tsing Hua University) Xiaoyang Zeng (Fudan University)

Advisory Members Kunihiro Asada (University of Tokyo) Satoshi Goto (Waseda University) Fumiyasu Hirose (Cadence Design Systems, Japan) Masaharu Imai (Osaka University) Takashi Kambe (Kinki University) Tokinori Kozawa Chong-Min Kyung (Korea Advanced Institute of Science and Technology) Youn-Long Steve Lin (National Tsing Hua University) Isao Shirakawa (University of Hyogo) TingAo Tang (Fudan University) Kazutoshi Wakabayashi (NEC)

Kenji Yoshida (D2S KK)

13 University LSI Design Contest

The University LSI Design Contest has been conceived as a unique program at ASP-DAC. The purpose of the contest is to encourage research in LSI design at universities and its realization on a chip by providing opportunities to present and discuss the innovative and state-of-the-art design. The scope of the contest covers circuit techniques for (1) Analog / RF / Mixed- Signal Circuits, (2) Digital Signal Processor, (3) Microprocessors, (4) Custom Application Speciﬁc Circuits / Memories, and methodologies for (a) Full-Custom / Cell-Based LSIs, (b) Gate Arrays, (c) Field Programmable Devices. This year, the University LSI Design Contest Committee received 30 designs from ﬁve countries/areas, and selected 23 designs out of them. The selected designs will be disclosed in Session 1S at four-minute presentations, followed by interactive discussions in front of their posters with light meals. To outstanding two designs, The Best Design Award and The Special Feature Award will be presented in the opening session. We sincerely acknowledge the other contributions to the contest, too. It is our earnest belief to promote and enhance research and education in LSI design in academic organizations. Please come to the University LSI Design Contest and enjoy the stimulating discussions.

Date: Tuesday, January 20, 2015 Place: Makuhari Messe International Convention Complex, International Conference Hall, 1F Oral Presentation: Room 103 (10:20-12:00) Poster Presentation: Lobby [Food will be served] (12:20-13:40)

University LSI Design Contest Committee Co-Chairs: Hiroyuki Ito (Tokyo Institute of Technology) Noriyuki Miura (Kobe University)

14 Designers’ Forum

The Designers’ Forum is a unique program that will share design experience and solutions of actual product designs of the industries. This year’s program includes the invited talks on the next generation car electronics and 4K/8K TV technologies, and also includes panel discussions on data-centric computing platform and IP-based SoC design and IP design innovations.

Oral Sessions: (5S) Car Electronics (8S) Technology Trend toward 8K Era Panel Discussions: (6S) Challenges in the Era of Big-Data Computing (9S) IP base SoC design and IP design innovation

Session 5S (13:50-15:30, Jan. 21st) [Car Electronics] Three practical design examples of up-to-date automobile developments based on car electronics are described. For designing automobiles accurately and eﬀectively, this session covers vertical integration from systems modeling to verify top level architecture of the automobile system to power devices for fundamental energy conversion.

Session 6S (15:50-17:30, Jan. 21st) [Challenges in the Era of Big-Data Computing] The advent of big data era may require a paradigm shift for designing computing systems. The amount of data to be obtained from real world increases exponentially every year, whereas the speed of performance improvements of conventional computing systems is quite slow compared to such rapid grows of big-data applications. So, now it is the time to revisit computer system architecture and its design. The panel discusses the direction of computing platforms in order to satisfy such performance requirements on next generation big-data era.

Session 8S (13:50-15:30, Jan. 22nd) [Technology Trend toward 8K Era] From 2014, 4K/UHD CS digital test broadcasting has been already started, and 4K VOD services will be started in 2015 by adopting the latest CODEC standard, H.265/HEVC. Not only 4K, 8K terrestrial test digital broadcasting and 8K terrestrial practical digital broadcasting are planned to be started in 2016 and 2018 respectively. In this session, technology trend toward 8K era will be discussed from various perspective. Four very interesting talks from the key persons of NexTV forum, 8K panel provider, SoC provider and CODEC researcher will be presented.

Session 9S (15:50-17:30, Jan. 22nd) [IP base SoC design and IP design innovation] Recent SoC uses a lot of IP’s. This session discusses what innovation will happen in the next generation of SoC design with IP’s and IP design itself. Four major IP vendors are invited and will talk their views for future design innovation of SoC with their IP’s which include numbers and types of IP’s such as digital, analog, RF and even a MEMS, variety such as CPU, GPU, memory, bus, interface and so on, usage models in design hierarchy and its modeling and integration methods of those IP’s. And also in order to achieve the SoC design innovation they will mention IP itself design methodology including planning, specification, implementation, verification, validation and qualification.

Designers’ Forum Co-Chairs: Yoshio Masubuchi (Toshiba Corp., Japan) Koji Inoue (Kyushu University, Japan)

15 ACM SIGDA Student Research Forum at ASP-DAC 2015

The Student Research Forum at the ASP-DAC is renovated from a traditional poster session hosted by ACM SIGDA for students to present and discuss their dissertation research with experts in system design and design automation community. Starting from this year, the forum will include both Ph.D. and M.S. students, oﬀering great opportunity for the students to establish contacts for their future career. In addition, the forum helps the companies and academic institutes to get an overview of the latest research and discover the extraordinary candidates for their employment.

Date and Time: 18:00-20:00, January 20, 2015 Location: Room 201 [Food will be served.]

We would like to thank the following committee members for their support and contribution to this forum. Conﬁrmed committee members: Yuko Hara-Azumi (Tokyo Institute of Technology) Tsung-Yi Ho (National Chiao Tung University) Jingtong Hu (Oklahoma State University) Yuzi Kanazawa (Fujitsu Laboratories) Yukihide Kohira (University of Aizu) Xin Li (Carnegie Mellon University) Ting Li (Huawei Technologies Co. Ltd.) Duo Liu (Chongqing University) Koji Maeda (Hitachi) Akihiko Miyazaki (NTT) Shinobu Nagayama (Hiroshima City University) Yoshinori Okajima (Panasonic) Qinru Qiu (Syracuse University) Zili Shao (The Hong Kong Polytechnic University) Muhammad Shaﬁque (Karlsruhe Institute of Technology) Yiyu Shi (Missouri University of Science and Technology) Seiya Shibata (NEC) Chun-Yao Wang (National Tsing Hua University) Hai Wang (University of Electronic Science and Technology of China) Yu Wang (Tsinghua University) Shu Xu (Huawei Technologies Co. Ltd.) Chun (Jason) Xue (City University of Hong Kong) Haibo Zeng (Virginia Polytechnic Institute and State University) Qi Zhu (University of California, Riverside)

ASP-DAC liaison: Yukihide Kohira (University of Aizu)

The sponsors of this forum are ACM SIGDA and Huawei Co. Ltd. We would also like to thank ASP-DAC 2015 for supporting this forum.

ACM SIGDA Student Research Forum Chair: Yiran Chen (University of Pittsburgh)

ACM SIGDA Student Research Forum Co-Chair: Yasuhiro Takashima (University of Kitakyushu)

16 Best Paper Award

Award Winner 1C-1: “ Quantitative Modeling of Racetrack Memory, A Tradeoﬀ among Area, Performance, and Power” Chao Zhang, Guangyu Sun, Weiqi Zhang (CECA, Peking University, China), Fan Mi, Hai Li (University of Pittsburgh, U.S.A.), Weisheng Zhao (Spintronics Interdisciplinary Center, Beihang University, China)

Candidates 2A-1: “ShuttleNoC: Boosting On-Chip Communication Eﬃciency by Enabling Localized Power Adaptation” Hang Lu (Univ. of Chinese Academy of Sciences, China), Guihai Yan, Yinhe Han, Ying Wang, Xiaowei Li (Chinese Academy of Sciences, China)

3C-3: “Intra-Vehicle Network Routing Algorithm for Weight and Wireless Transmit Power Minimization” Ta-Yang Huang, Chia-Jui Chang (National Cheng Kung Univ., Taiwan), Chung-Wei Lin (Univ. of California, Berkeley, U.S.A.), Sudip Roy (National Cheng Kung Univ., Taiwan), Tsung-Yi Ho (National Chiao Tung Univ., Taiwan)

4A-4: “A Garbage Collection Aware Stripping Method for Solid-State Drives” Min Huang (Harbin Inst. of Tech., China), Yi Wang (Shenzhen Univ., China), Zhaoqing Liu, Liyan Qiao (Harbin Inst. of Tech., China), Zili Shao (Hong Kong Polytechnic Univ., Hong Kong)

4B-2: “New Electromigration Modeling and Analysis Considering Time-Varying Temperature and Current Den- sities” Hai-Bao Chen, Sheldon X.-D. Tan, Xin Huang (Univ. of California, Riverside, U.S.A.), Valeriy Sukharev (Mentor Graphics, U.S.A.)

5C-1: “Useful Clock Skew Scheduling Using Adjustable Delay Buﬀers in Multi-Power Mode Designs” Juyeon Kim, Taewhan Kim (Seoul National Univ., Republic of Korea)

8C-1: “On Test Syndrome Merging for Reasoning-Based Board-Level Functional Fault Diagnosis” Zelong Sun (Chinese Univ. of Hong Kong, Hong Kong), Li Jiang (Shanghai Jiao Tong Univ., China), Qiang Xu (Chinese Univ. of Hong Kong, Hong Kong), Zhaobo Zhang, Zhiyuan Wang, Xinli Gu (Huawei Technologies, U.S.A.)

17 University LSI Design Contest Award

Best Design Award

1S-1: “An HDL-Synthesized Gated-Edge-Injection PLL with A Current Output DAC” Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Mat- suzawa (Tokyo Institute of Technology, Japan)

Special Feature Award

1S-23: “Circuit and Package Design for 44GBs DRAMSoC Interface” Akira Okada, Abdul Raziz Junaidi, Yasuhiro Take, Atsutake Kosuge, Tadahiro Kuroda (Keio Univ., Japan)

10-Year Retrospective Most Inﬂuential Paper Award

Award Winner (ASP-DAC 2005)

2A-2: “Thermal-Driven Multilevel Routing for 3-D ICs”, Jason Cong, Yan Zhang (UCLA)

Candidates 1B-1: “Mapping and Physical Planning of Networks-on-Chip Architectures with Quality-of-Service Guarantees” Srinivasan Murali (Stanford University), Luca Benini (University of Bologna), Giovanni De Micheli (Stanford University)

3B-3: “Speed and Voltage Selection for GALS Systems based on Voltage/Frequency Islands” Koushik Niyogi, Diana Marculescu (Carnegie Mellon University )

7B-5s: “A Fast VLSI Architecture for Full-Search Variable Block Size Motion Estimation in MPEG-4 AVC/H.264” Minho Kim, Ingu Hwang, Soo-Ik Chae (Seoul National University)

PIII-3: “Redundant-via enhanced maze routing for yield improvement” Gang Xu (UT Austin), Li-Da Huang (Texas Instruments), David Z. Pan (UT Austin), Martin D. F. Wong (UIUC)

18 20th Anniversary Awards

Awards sponsored by ASP-DAC ASP-DAC Foundation Award • Dr. Tokinori Kozawa • Dr. Kenji Yoshida • Prof. Tatsuo Ohtsuki

ASP-DAC Leadership Award • General Chairs from 1st ASP-DAC to 20th ASP-DAC 1st (1995) : Prof. Tatsuo Ohtsuki 2nd (1997) : Prof. Isao Shirakawa 3rd (1998) : Dr. Tokinori Kozawa 4th (1999) : Prof. Richard M. M. Chen, Prof. Qian-Ling Zhang 5th (2000) : Dr. Kenji Yoshida 6th (2001) : Prof. Satoshi Goto 7th (2002) : Dr. Sunil D. Sherlekar 8th (2003) : Prof. Hiroto Yasuura 9th (2004) : Prof. Masaharu Imai 10th (2005) : Prof. Ting-Ao Tang 11th (2006) : Dr. Fumiyasu Hirose 12th (2007) : Prof. Hidetoshi Onodera 13th (2008) : Prof. Chong-Min Kyung 14th (2009) : Dr. Kazutoshi Wakabayashi 15th (2010) : Prof. Youn-Long Lin 16th (2011) : Prof. Kunihiro Asada 17th (2012) : Prof. Sri Parameswaran 18th (2013) : Prof. Shinji Kimura 19th (2014) : Prof. Yong Lian, Prof. Yajun Ha 20th (2015) : Dr. Kunio Uchiyama

19 ASP-DAC Most Frequent Author Award • Prof. Xianlong Hong ASP-DAC Frequent Author Award • Prof. Massoud Pedram • Prof. Martin D. F. Wong

ASP-DAC Most Frequently Cited Paper Award • Jingcao Hu, and Radu Marculescu, “Energy-aware mapping for tile-based NoC architectures under performance constraints,” ASP-DAC 2003, pp.233-239, 2003. ASP-DAC Frequently Cited Paper Award • Kanishka Lahiri, Sujit Dey, Debashis Panigrahi, and Anand Raghunathan, “Battery-driven system design: a new frontier in low power design,” ASP-DAC 2002, pp.261-267, 2002. • Flavius Gruian and Krzysztof Kuchcinski, “LEneS: task scheduling for low-energy systems using variable supply voltage processors,” ASP-DAC 2001, pp.449-455, 2001.

ASP-DAC Most Frequently Cited Author Award • Prof. Jason Cong ASP-DAC Frequently Cited Author Award • Prof. Andrew B. Kahng • Prof. David Z. Pan

Award presented by ACM SIGDA, IEEE CEDA, and Sister Conferences (DAC/DATE/ICCAD) Distinguished Service Award for ASP-DAC • Prof. Tatsuo Ohtsuki • Prof. Hiroto Yasuura • Prof. Hidetoshi Onodera

20 Invitation to ASP-DAC 2016

On behalf of the Organizing Committee, it is our great pleasure and honor to welcome you to the 21st ASP-DAC, to be held in Macao, China, February 1-4, 2016. Macao is one of the two special administrative regions of China which lies on the western side of the Pearl River Delta (PRD), bordering Guangdong province in the north and facing the South China Sea in the east and south. Macau has a rich heritage from both its Chinese and Portuguese past that includes many outstanding examples of western and oriental art and culture. Here you will find Chinese temples, catholic churches; ancient forts and other histori- cal relics within a modern environment that bear testimony to a cultural blend of east and west. The Historic Centre of Macao, which includes twenty-five historic monuments and public squares, was officially listed as a World Heritage Site by UNESCO in 2005. There are also many sightseeing points in Macao such as: Ruins of St. Paul’s Church, Macau Tower, A- Ma Temple, Grand Prix Museum, Mandarin’s House, etc. Macao has also a notable tourism industry that boasts a wide range of hotels, resorts, stadiums, restaurants and casinos, which probably will bring ASP-DAC 2016 participants a wonderful trip. Holding ASP-DAC 2016 in Macao will help the local academia and the worldwide academia and semiconductor industry to get closer and exchange electronic design knowledge and experience in Macao and learn from the ASP-DAC community. We warmly welcome participants from all around the world to meet and exchange our visions in the future design automation and embedded system design related technologies. Your active submissions are highly appreciated in order to contribute for an excellent technical program of ASP-DAC 2016. Last but not least, we hope to see you all in Macao ASP-DAC 2016 !

Rui P. Martins General Chair, ASP-DAC 2016

21 Tutorials

Room 102 Room 103 Room 104 Room 105 9:30 Tutorial-3: Tutorial-1: Normally-Oﬀ Computing: Tutorial-4: Ultra-low power ultra-low Tutorial-2: Synergy of New Hardware Trust in VLSI voltage design techniques Leading-Edge Lithography Non-Volatile Memories Design and in Fully Depleted SOI and TCAD and Aggressive Power Implementations technologies Management 11:30 Lunch Break [coupon] 13:00 Tutorial-1: Tutorial-5: Tutorial-6: Ultra-low power ultra-low Tutorial-2: High-Level Synthesis for Electronic Design voltage design techniques Leading-Edge Lithography FPGAs: From Software to Automation for in Fully Depleted SOI and TCAD Programmable Hardware Nanotechnologies technologies 15:00 Break 15:30 Tutorial-3: Normally-Oﬀ Computing: Tutorial-4: Tutorial-5: Tutorial-6: Synergy of New Hardware Trust in VLSI High-Level Synthesis for Electronic Design Non-Volatile Memories Design and FPGAs: From Software to Automation for and Aggressive Power Implementations Programmable Hardware Nanotechnologies Management 17:30

Tutorial-1 Monday, January 19, 9:30 - 11:30, 13:00 - 15:00@Room 102 Ultra-low power ultra-low voltage design techniques in Fully Depleted SOI technologies Organizer: Andreia Cathelin (STMicroelectronics) Speakers: Giorgio Cesana (STMicroelectronics), Edith Beigne´ (CEA-Leti), Nobuyuki Sugii (LEAP)

Tutorial Outline: Electronics is more and more pervasive in everyday life: smartphones, connected cars, wearable, Internet of Things... After decades of steady gradual evolution, the semiconductor industry is now facing its biggest and most interesting challenge: while in the last few years the number of mobile devices has significantly grown year after year, the revolution of the Internet of Things promises an exponential growth of connected devices. Semiconductor technology is the key enabler of today applications, making possible the impossible by allowing device miniaturization and co-integration. Traditional planar CMOS technology is mature and low cost, but limited in power consumption efficiency and performances from the 28nm node. These 3 talks tutorial event will bring a highlight in planar thin film fully depleted CMOS technologies that enhance innovative solutions for very energy efficient systems. The first talk will focus on the UTBB FDSOI technology from STMicroelectronics, presenting the latest technology highlights and mapped on the system design needs for energy efficient logic and also analog/RF designs. The second talk, by CEA-Leti, will get in-deep of complex digital circuit design, focusing on a 32-bit VLIW DSP exhibiting outstanding silicon results in terms of speed and energy. All the design techniques enhancing exceptional energy efficient operation will be carefully detailed. And finally, the third talk from LEAP will also present ultra-low power system design in the SOTB FDSOI technology. Design techniques will be highlighted in the frame of an energy efficient micro-controller design. • Theme 1: Planar UTBB FD-SOI technology for highly energy efficient devices Giorgio Cesana (STMicroelectronics) • Theme 2: FDSOI circuit design for a better energy efficiency: Wide operating range and ULP applications Edith Beigne´ (CEA-Leti) • Theme 3: Ultra low-power system design based on SOTB FDSOI Technology Nobuyuki Sugii (LEAP)

22 Tutorial-2 Monday, January 19, 9:30 - 11:30, 13:00 - 15:00@Room 103 Leading-Edge Lithography and TCAD Organizer: Shigeki Nojima (Toshiba) Speakers: Seiji Nagahara (Tokyo Electron), Tomoyuki Matsuyama (Nikon), Shigyo Naoyuki (Toshiba)

Tutorial Outline: As feature size becomes below the resolution limit of lithography, several complementary techniques of lithography and process have emerged, such as multiple patterning technology and block co-polymer directed self-assembly (DSA). Since these techniques start with ArF immersion lithography, the exposure system is still one of the keys for the fine patterning. For example, overlay error of an exposure system directly causes CD variation on the multiple patterning and pattern shift from the ideal position on DSA. In addition, the shrink of the feature size causes serious statistical process fluctuation, which has influence on device and circuit performance. As virtual manufacturing, TCAD is one of useful tools for robust designs of process, device and circuit. This tutorial will provide the overview of cutting-edge technologies for ArF immersion exposure system, DSA and TCAD. The topics will cover recent development status, challenges and possible future directions. Furthermore, a design considering manufacturability becomes much important when the new technologies are applied. In this tutorial, design for manufacturability, such as DSA friendly design, will also be discussed.

Tutorial-3 Monday, January 19, 9:30 - 11:30@Room 104, 15:30 - 17:30@Room 102 Normally-Oﬀ Computing: Synergy of New Non-Volatile Memories and Aggressive Power Management Organizers: Hiroshi Nakamura (The University of Tokyo), Takashi Nakada (The University of Tokyo) Speakers: Takashi Nakada (The University of Tokyo), Shinobu Fujita (Toshiba Corporate R&D Center)

Tutorial Outline: Normally-off computing is a way of computing where inactive components of computer systems are aggressively powered off with the help of new non-volatile memories (NVMs). Simple power gating cannot fully take the chances of power reduction since volatile memories lose data when power supply is off. With new NVMs, they can maintain their content without power supply. Thereore, a synergetic effect for power gating is highly expected. Hence, this tutorial presents basic design methodologies for normally-off computing, discusses major challenges and approaches in it and introduces key features related to power gating and new generation NVMs. Regarding power gating, granularity of power domain and performance/energy overheads are major concerns. For nonvolatile memory, access time and read/write energy are important problems. Essentially, it is important to understand what kind of characteristics affect the performance and energy consumption. There are trade-offs, such as break even time (BET), not only within each technology but also cross-technologies. For example, when the scheduling of a task is changed, the optimal power management may also be different. Thus, to realize normally-off computing, hardware/software co-design and co-optimization are required. This is key for not only system designers, but also hardware engineers and software developers.

Tutorial-4 Monday, January 19, 9:30 - 11:30@Room 105, 15:30 - 17:30@Room 103 Hardware Trust in VLSI Design and Implementations Organizers: Kazuo Sakiyama (The University of Electro-Communications), Makoto Nagata (Kobe University) Speakers: Patrick Schaumont (Virginia Tech, US), Swarup Bhunia (Case Western Reserve University, US), Kazuo Sakiyama (The University of Electro-Communications, JP), Makoto Nagata (Kobe University, JP)

Tutorial Outline: This tutorial provides introductory perspectives of hardware trust in the design and implementation of VLSI systems for security applications. The talks by four experts cover the front-end understandings of threats and countermeasures to the back-end knowledge including counterfeiting, active and passive attacks through side channels of IC chips. • Talk-1: Threats and Countermeasures from Protocols to Secure Hardware Implementation Patrick Schaumont (Virginia Tech, US) • Talk-2: IC Counterfeiting: Challenges and Solutions (PUFs, Aging Sensors, and Integrity Analysis) Swarup Bhunia (Case Western Reserve University, US) • Talk-3: Fault Analysis for Cryptosystems: Introduction to Diﬀerential Fault Analysis and Fault Sensitivity Analysis Kazuo Sakiyama (The University of Electro-Communications, JP) • Talk-4: Side Channel Leakage in Cryptographic Modules: Introduction to Physical Origins and Attack Models Makoto Nagata (Kobe University, JP)

23 Tutorial-5 Monday, January 19, 13:00 - 15:00, 15:30 - 17:30@Room 104 High-Level Synthesis for FPGAs: From Software to Programmable Hardware Organizer: Jason Anderson (University of Toronto) Speakers: Jason Anderson (University of Toronto), Ben Carrion Schafer (Hong Kong Polytechnic University)

Tutorial Outline: High-level synthesis (HLS) was first proposed in the 1980s, and after spending decades in the shadows of mainstream digital design, there has been tremendous ”buzz” around HLS technology in recent years. Indeed, HLS has been gaining traction as a design methodology for field-programmable gate arrays (FPGAs) to improve designer productivity and ultimately, to make FPGA technology accessible to software engineers possessing limited hardware expertise. The hope is that down the road, software developers could use HLS to realize FPGA-based accelerators customized to applications that work in tandem with standard processors to raise computational throughput and energy efficiency. Both of the main FPGA vendors have been investing heavily in HLS in recent years and in this tutorial, we provide a crash course on FPGA HLS, from both the academic research and industrial perspectives. We review the core steps taken by modern HLS tools and the underlying algorithms used inside. We then consider how the style of the high-level language code input to HLS influences the circuit produced and its performance. Special attention will be given to the differences in HLS for FPGAs, custom ASICs, and other IC media, such as coarse-grained arrays. We discuss the typical ”knobs” available to an HLS user to enable design-space exploration, for example, to control loop pipelining, resource sharing, and other optimizations. We conclude by discussing current HLS research and mention some of the remaining challenges for HLS that possibly hinder its broader update in the digital design community. The tutorial will be of interest to be EDA researchers, as well as current and future users of FPGA HLS.

Tutorial-6 Monday, January 19, 13:00 - 15:00, 15:30 - 17:30@Room 105 Electronic Design Automation for Nanotechnologies Organizers: Pierre-Emmanuel Gaillardon (EPFL), Giovanni De Micheli (EPFL) Speakers: Pierre-Emmanuel Gaillardon (EPFL), Luca Amaru (EPFL), Anupam Chattopadhay (Nanyang Technical University), Subhasish Mitra (Stanford University)

Tutorial Outline: Nanoscale emerging technologies hold the promises of drastic improvements of the key design metrics, i.e., area, delay and power consumption, of near-future computing systems. In addition to a pure improvement of the device parameters, many novel technologies exploit unconventional physical phenomena leading to larger computation capabilities at the device level. Such fundamental paradigm change precludes standard CMOS design techniques to fully leverage the performances of advanced devices. In addition to unlocking the logic capabilities of the devices from a logic synthesis perspective, the design methodologies should also consider carefully the manufacturing of the technology, i.e., the physical design, to maximize the fabrication yield. In this tutorial, we will introduce the importance for tight links between design methodologies and technology to fully exploit emerging devices. The tutorial will cover 3 principal themes: logic optimization and underlying data structures, technology mapping and physical design. To get a direct sense on the importance of design automation for nanotechnologies, each theme will be asso- ciated and discussed through a speciﬁc technology: controllable-polarity nanowire transistors, quantum gates and carbon nanotubes transistors respectively. • Theme 1: Logic Optimization - Majority and Biconditional Logic: Dr. Pierre-Emmanuel Gaillardon, Mr. Luca Amaru, EPFL, Lausanne, Switzerland • Theme 2: Technology Mapping - Reversible Logic Synthesis: Pr. Anupam Chattopadhay, Nanyang Technical University, Singapore • Theme 3: Physical Design - Robust System Design at the Nanoscale: Pr. Subhasish Mitra, Stanford University, USA

24 At a glance

Monday, January 19 18:00 20th Anniversary Reception (Room 201 [2F]) 19:30 Tuesday, January 20 S (Room 103) A (Room 102) B (Room 104) C (Room 105) 8:30 Opening & Keynote I (International Conference Room [2F]) 9:50 Coffee Break 10:20 1C: Modeling and Design 1S: University Design 1A: NoCS I (Performance 1B: Toward Power Efficient Contest and Fault Tolerance) Design Methodologies of Post-silicon Devices 12:00 Lunch Break / University Design Contest Poster Discussion (Lobby) 13:50 2S: (Special Session) 2A: NoCS II (Power and 2B: Design Automation for Tomorrow’s Circuit 2C: Emerging Applications Internet of Things Emerging Technology) Technologies 15:30 Coffee Break 15:50 3S: (Special Session) New Challenges and Solutions 3A: Circuits for 3B: Frontiers in Logic 3C: Energy Optimization Performance and for Electric Vehicles and in Nanometer Physical Reliability Synthesis Design Smart Grids 17:30 Break 18:00 ACM SIGDA Student Research Forum at ASP-DAC 2015 (Room 201 [2F]) 20:00 Wednesday, January 21 S (Room 103) A (Room 102) B (Room 104) C (Room 105) 9:00 Keynote II (International Conference Room [2F]) 9:50 Coffee Break 10:15 4S: (Special Session) ffi Machine Learning in EDA: 4A: E cient NVM 4B: Robust Timing, and 4C: New Issues in Management, from / Promises and Challenges in Register to Disk P G Modeling and Design Placement and Routing Selected Applications 12:20 Lunch Break 13:50 5B: CAD for 5S: (Designers’ Forum) Car 5A: Optimization and Analog/RF/Mixed-Signal 5C: Next-Generation Clock Electronics Exploration for Caches Design Network Synthesis 15:30 Coffee Break 15:50 6S: (Designers’ Forum) 6A: Optimization Panel Discussion: Techniques for Challenges in the Era of Non-Volatile Memory 6B: Test for Higher Quality 6C: Reliability Big-Data Computing based Systems 17:30 Break 18:00 Banquet (Convention Hall A [2F]) 20:00 Thursday, January 22 S (Room 103) A (Room 102) B (Room 104) C (Room 105) 9:00 Keynote III (International Conference Room [2F]) 9:50 Coffee Break 10:15 7S: (Special Session) The 7A: Ensuring the Future of Emerging Correctness of System 7B: Orchestrating Tasks, 7C: Design for ReRAM Technology Integration Cores, and Communication Manufacturability 12:20 Lunch Break / IEEE CASS/CEDA Luncheon Presentations 13:50 (Designers’ Forum) 8A: Exploring Better 8S: 8B: Circuit-Level 8C: Reliable and Technology Trend toward Architecture of Your Modeling and Simulation Trustworthy Electronics 8K Era Systems 15:30 Coffee Break 15:50 9S: (Designers’ Forum) 9B: (Special Session) Panel Discussion: IP Base 9A: Power/Thermal System-Level Designs and 9C: Building Secure SoC Design and IP Design Management and Modeling Tools for Multicore Systems Innovation Systems 17:30

25 Room Assignment

Room Assignment Location Event Entrance Hall (1F) Registration, Information Desk, and Cloak International Conference Room (2F) Opening and Keynote I,II,III 103 (1F) Session S, Tutorials 2,4, and University Design Contest 102 (1F) Session A and Tutorials 1,3 104 (1F) Session B and Tutorials 3,5 105 (1F) Session C and Tutorials 4,6 Lobby (1F) Poster Discussion, Supporter’s Exhibition, and Coﬀee Break Convention Hall A (2F) Banquet 201 (2F) 20th Anniversary Reception, Speaker’s Breakfast, and ACM SIGDA Student Research Forum 204 (2F) Rehearsal Room 205 (2F) File Checking Room

International Conference Hall 1F

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26 Keynote Addresses

Opening & Keynote I Tuesday, January 20, 8:30-9:50

“The required technologies for Automotive towards 2020” Dr. Udo Wolz Executive Vice President and Director for Engineering and Innovation, Bosch Corporation

This keynote speech deals with the future of the automotive industry and the requirements out of new applications and technologies. The mobility of the future will be electric, automated and connected. Until 2020 the internal combustion engine will still dominate the powertrain with approximately 90% share. This includes systems with mild electrification such as start/stop. For stronger electrified vehicles like hybrids, plug-in hybrids and full EV, battery technologies and battery management are key. Automated driving is already on the way with driver assistance functions and will end up with fully automated driving. Surround sensing of cars and connection between cars and cars to infrastructure will lead to extremely high needs of computing power. Information and Communication Technology is key here. For safety functions extremely short reaction times in milliseconds are necessary. Security mechanisms to ensure proper, unimpaired operation are a must. Seamless communication from home to car and to other parts of life is expected. This leads to smart phone connectivity with the car, car with the cloud, etc.. The car will be part of the Internet. The technologies to achieve this are currently already penetrating from consumer electronics and IT technologies to cars and vice versa. E.g. MEMS, highly reliable micromechanical sensors since long utilized for automotive applications, now entered the market for consumer electronics: Bosch sensors can be found in more than every second Smartphone worldwide. With increasing electrification, automation and connectivity, the requirements and the market demand for VLSI and embedded systems’ computing power will increase continuously.

Keynote II Wednesday, January 21, 9:00-9:50

“Programmable Network” Dr. Atsushi Takahara Director of NTT Network Innovation Laboratories

Network Virtualization such as SDN (Software Defined Network) or NFV (Network Functions Virtualization) is the important technology in the new generation network architecture. This provides flexible networking for various kinds of network usage demand. Network virtualization requires the definition of a user specific network called as ”slice” and the method for programming a slice design of programmable forwarding nodes in network. The key aspect is to introduce the programmability in network. This can provide new value for users and application providers by working together with computation and peripheral technologies such as cloud computing, Internet of Things, mobile devices and so on. Also, the delivery time of a slice can be shorter than in existing network. ”Programmable Network” has huge potential to change the games in creating network service. In this talk, the R&D activities of network virtualization and its programmability methods are introduced to explain how the flexibility is realized as hardware and software system. Then, we discuss how we utilize programmable network for creating network services. The several use cases such as 4K/8K contents distribution, resiliency of network system, and edge distributed computing are introduced to show the possibility of creating new value by Programmable Network. Finally, we discuss the possibility of applying EDA technologies for supporting the design flow of a user specific network in Programmable Network.

27 Keynote III Thursday, January 22, 9:00-9:50

“When and how will an AI be smart enough to design?” Dr. Noriko Arai Professor of Information and Society Research Division, National Institute of Informatics

The current rise of AI has mainly two origins. The ﬁrst one is, of course, the invention of machine learning. Statistics and optimization deliver their theories to the machine learning. The combination of the big data and the massively parallel computing enables the machines to ”learn” from the data existing on the web, the network and the database, though there is only small hope that machine learning technologies help the machine to solve the design problem like design automation. Another rather inconspicuous origin is the sophistication of the traditional logical approach. The virtue of the logical approach is in its ability to express complex input-output relations, such as the mapping form natural language text to its meaning and the logical relation between a premise and its consequence, in a way that a human can understand. In this talk, I introduce AI grand challenge, ”Todai Robot Project” (Can an AI get into the University of Tokyo?), initiated by National Institute of Informatics in 2011, and discuss the impact of near-term AI technologies on design automation.

28 Tuesday, January 20, 2015

1K Opening & Keynote I Time: 8:30 - 9:50, Tuesday, January 20, 2015 Location: International Conference Room Chair: Kunio Uchiyama (Hitachi) 1K-1 (Time: 8:30 - 9:50) (Keynote Address) The Required Technologies for Automotive towards 2020 ...... 1 *Udo Wolz (Bosch, Japan) 1S University Design Contest Time: 10:20 - 12:10, Tuesday, January 20, 2015 Location: Room 103 Chairs: Hiroyuki Ito (Tokyo Inst. of Tech., Japan), Noriyuki Miura (Kobe Univ., Japan) 1S-1 (Time: 10:20 - 10:24) An HDL-Synthesized Gated-Edge-Injection PLL with A Current Output DAC ...... 2 *Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan) 1S-2 (Time: 10:24 - 10:28) An Oscillator-Based True Random Number Generator with Process and Temperature Tolerance ...... 4 Takehiko Amaki, *Masanori Hashimoto, Takao Onoye (Osaka Univ., Japan) 1S-3 (Time: 10:28 - 10:32) Implementation of Double Arbiter PUF and Its Performance Evaluation on FPGA ...... 6 *Takanori Machida (Univ. of Electro-Communications, Japan), Dai Yamamoto (Fujitsu Labs., Japan), Mitsugu Iwamoto, Kazuo Sakiyama (Univ. of Electro-Communications, Japan) 1S-4 (Time: 10:32 - 10:36) A Negative-Resistance Sense Amplifier for Low-Voltage Operating STT-MRAM ...... 8 *Yohei Umeki, Koji Yanagida (Kobe Univ., Japan), Shusuke Yoshimoto (Stanford Univ., U.S.A.), Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi (Kobe Univ., Japan), Koji Tsunoda, Toshihiro Sugii (Low- Power Electronics Association and Project (LEAP), Japan) 1S-5 (Time: 10:36 - 10:40) A High Stability, Low Supply Voltage and Low Standby Power Six-Transistor CMOS SRAM ...... 10 *Nobuaki Kobayashi, Ryusuke Ito, Tadayoshi Enomoto (Chuo Univ., Japan) 1S-6 (Time: 10:40 - 10:44) An Efficient Multi-Port Memory Controller for Multimedia Applications ...... 12 *Xuan-Thuan Nguyen, Cong-Kha Pham (Univ. of Electro-Communications, Japan) 1S-7 (Time: 10:44 - 10:48) Reliability-Configurable Mixed-Grained Reconfigurable Array Compatible with High-Level Synthesis ...... 14 *Masanori Hashimoto, Dawood Alnajjar, Hiroaki Konoura (Osaka Univ./JST, CREST, Japan), Yukio Mit- suyama (Kochi Univ. of Tech./JST, CREST, Japan), Hajime Shimada (Nagoya Univ./JST, CREST, Japan), Kazutoshi Kobayashi (Kyoto Inst. of Tech./JST, CREST, Japan), Hiroyuki Kanbara (ASTEM/JST, CREST, Japan), Hiroyuki Ochi (Ritsumeikan Univ./JST, CREST, Japan), Takashi Imagawa (Kyoto Univ./JST, CREST, Japan), Kazutoshi Wakabayashi (NEC/JST, CREST, Japan), Takao Onoye (Osaka Univ./JST, CREST, Japan), Hidetoshi Onodera (Kyoto Univ./JST, CREST, Japan) 1S-8 (Time: 10:48 - 10:52) A 14µA ECG Processor with Noise Tolerant Heart Rate Extractor and FeRAM for Wearable Healthcare Systems . . . . . 16 *Yozaburo Nakai, Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi, Masahiko Yoshi- moto (Kobe Univ., Japan) 1S-9 (Time: 10:52 - 10:56) A 128-Way FPGA Platform for the Acceleration of KLMS Algorithm ...... 18 *Xiaowei Ren, Qihang Yu, Badong Chen, Nanning Zheng, Pengju Ren (Xi’an Jiaotong Univ., China) 1S-10 (Time: 10:56 - 11:00) A Real-Time Permutation Entropy Computation for EEG Signals ...... 20 *Xiaowei Ren, Qihang Yu, Badong Chen, Nanning Zheng, Pengju Ren (Xi’an Jiaotong Univ., China)

29 Tuesday, January 20, 2015

1S-11 (Time: 11:00 - 11:04) A High Eﬃcient Hardware Architecture for Multiview 3DTV ...... 22 *Jiang Yu, Geng Liu, Xin Zhang, Pengju Ren (Xi’an Jiaotong Univ., China) 1S-12 (Time: 11:04 - 11:08) Design of A Scalable Many-Core Processor for Embedded Applications ...... 24 *Hsiao-Wei Chien, Jyun-Long Lai, Chao-Chieh Wu, Chih-Tsun Huang, Ting-Shuo Hsu, Jing-Jia Liou (Na- tional Tsing Hua Univ., Taiwan) 1S-13 (Time: 11:08 - 11:12) A DPA/DEMA/LEMA-Resistant AES Cryptographic Processor with Supply-Current Equalizer and Micro EM Probe Sensor ...... 26 *Daisuke Fujimoto, Noriyuki Miura (Kobe Univ., Japan), Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki (Tohoku Univ., Japan), Makoto Nagata (Kobe Univ., Japan) 1S-14 (Time: 11:12 - 11:16) A 64×64 1200fps Dual-Mode CMOS Ion-Image Sensor for Accurate DNA Sequencing ...... 28 *Xiwei Huang, Jing Guo, Mei Yan, Hao Yu (Nanyang Technological Univ., Singapore) 1S-16 (Time: 11:16 - 11:20) A 0.21-V Minimum Input, 73.6% Maximum Eﬃciency, Fully Integrated 3-Terminal Voltage Converter with MPPT for Low-Voltage Energy Harvesters ...... 30 *Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa (Kobe Univ., Japan) 1S-17 (Time: 11:20 - 11:24) Dual-Output Wireless Power Delivery System for Small Size Large Volume Wireless Memory Card ...... 32 *Junki Hashiba, Toru Kawajiri, Yuya Hasegawa, Hiroki Ishikuro (Keio Univ., Japan) 1S-18 (Time: 11:24 - 11:28) A Tri-Level 50MS/s 10-bit Capacitive-DAC for Bluetooth Applications ...... 34 *Daisuke Kanemoto (Univ. of Yamanashi, Japan), Keigo Oshiro, Keiji Yoshida, Haruichi Kanaya (Kyushu Univ., Japan) 1S-19 (Time: 11:28 - 11:32) A Tail-Current Modulated VCO with Adaptive-Bias Scheme ...... 36 *Aravind Tharayil Narayanan, Wei Deng, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan) 1S-20 (Time: 11:32 - 11:36) A Low-Power VCO Based ADC with Asynchronous Sigma-Delta Modulator in 65nm CMOS ...... 38 *Jili Zhang, Chenluan Wang, Shengxi Diao, Fujiang Lin (Univ. of Science and Tech. of China, China) 1S-21 (Time: 11:36 - 11:40) A 0.5-V 5.8-GHz Low-Power Asymmetrical QPSK/OOK Transceiver for Wireless Sensor Network ...... 40 *Sho Ikeda, Sang yeop Lee, Shin Yonezawa, Yiming Fang, Motohiro Takayasu, Taisuke Hamada, Yosuke Ishikawa, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu (Tokyo Inst. of Tech., Japan) 1S-22 (Time: 11:40 - 11:44) A 58.3-to-65.4 GHz 34.2 mW Sub-Harmonically Injection-Locked PLL with a Sub-Sampling Phase Detection ...... 42 *Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa (Tokyo Inst. of Tech., Japan) 1S-23 (Time: 11:44 - 11:48) Circuit and Package Design for 44GB/s Inductive-Coupling DRAM/SoC Interface ...... 44 *Akira Okada, Abdul Raziz Junaidi, Yasuhiro Take, Atsutake Kosuge, Tadahiro Kuroda (Keio Univ., Japan) 1S-24 (Time: 11:48 - 11:52) Design and Analysis for ThruChip Design for Manufacturing (DFM) ...... 46 *Li-Chung Hsu, Yasuhiro Take, Atsutake Kosuge, So Hasegawa, Junichiro Kadamoto, Tadahiro Kuroda (Keio Univ., Japan)

30 Tuesday, January 20, 2015

1A NoCS I (Performance and Fault Tolerance) Time: 10:20 - 12:00, Tuesday, January 20, 2015 Location: Room 102 Chairs: Yoshinori Takeuchi (Osaka Univ., Japan), Takashi Miyamori (Toshiba) 1A-1 (Time: 10:20 - 10:45) A Novel Approach Using a Minimum Cost Maximum Flow Algorithm for Fault-Tolerant Topology Reconﬁguration in NoC Architectures ...... 48 Leibo Liu, *Yu Ren, Chenchen Deng (Tsinghua Univ., China), Jie Han (Univ. of Alberta, Canada), Shouyi Yin, Shaojun Wei (Tsinghua Univ., China) 1A-2 (Time: 10:45 - 11:10) Adaptive Remaining Hop Count Flow Control: Consider the Interaction between Packets ...... 54 *Peng Wang, Sheng Ma, Hongyi Lu, Zhiying Wang, Chen Li (National Univ. of Defense Tech., China) 1A-3 (Time: 11:10 - 11:35) A Flexible Hardware Barrier Mechanism for Many-Core Processors ...... 61 *Takeshi Soga (ISIT Kyushu, JST CREST, Japan), Hiroshi Sasaki, Tomoya Hirao (Kyushu Univ., Japan), Masaaki Kondo (Univ. of Tokyo, Japan), Koji Inoue (Kyushu Univ., Japan) 1A-4 (Time: 11:35 - 12:00) A Performance Enhanced Dual-Switch Network-on-Chip Architecture ...... 69 *Lian Zeng, Takahiro Watanabe (Waseda Univ., Japan)

1B Toward Power Eﬃcient Design Time: 10:20 - 12:00, Tuesday, January 20, 2015 Location: Room 104 Chairs: Kimiyoshi Usami (Shibaura Inst. of Tech., Japan), Masanori Hashimoto (Osaka Univ., Japan) 1B-1 (Time: 10:20 - 10:45) A Cross-Layer Framework for Designing and Optimizing Deeply-Scaled FinFET-Based SRAM Cells under Process Variations ...... 75 *Alireza Shafaei, Shuang Chen, Yanzhi Wang, Massoud Pedram (Univ. of Southern California, U.S.A.) 1B-2 (Time: 10:45 - 11:10) Controlled Placement of Standard Cell Memory Arrays for High Density and Low Power in 28nm FD-SOI ...... 81 *Adam Teman (EPFL, Switzerland), Davide Rossi (Univ. of Bologna, Italy), Pascal Meinerzhagen (EPFL, Switzerland), Luca Benini (Univ. of Bologna, Italy/ETH, Switzerland), Andreas Burg (EPFL, Switzerland) 1B-3 (Time: 11:10 - 11:35) Microarchitectural-Level Statistical Timing Models for Near-Threshold Circuit Design ...... 87 *Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ., Japan) 1B-4 (Time: 11:35 - 12:00) Stress-Aware P/G TSV Planning in 3D-ICs ...... 94 *Shengcheng Wang, Farshad Firouzi, Fabian Oboril, Mehdi B. Tahoori (Karlsruhe Inst. of Tech., Germany)

1C Modeling and Design Methodologies of Post-silicon Devices Time: 10:20 - 12:00, Tuesday, January 20, 2015 Location: Room 105 Chairs: Zili Shao (Hong Kong Polytechnic Univ., Hong Kong), Duo Liu (Chongqing Univ., China) 1C-1 (Time: 10:20 - 10:45) Quantitative Modeling of Racetrack Memory, A Tradeoﬀ among Area, Performance, and Power ...... 100 *Chao Zhang, Guangyu Sun, Weiqi Zhang (Peking Univ., China), Fan Mi, Hai Li (Univ. of Pittsburgh, U.S.A.), Weisheng Zhao (Beihang Univ., China) 1C-2 (Time: 10:45 - 11:10) Technological Exploration of RRAM Crossbar Array for Matrix-Vector Multiplication ...... 106 *Peng Gu, Boxun Li, Tianqi Tang (Tsinghua Univ., China), Shimeng Yu, Yu Cao (Arizona State Univ., U.S.A.), Yu Wang, Huazhong Yang (Tsinghua Univ., China)

31 Tuesday, January 20, 2015

1C-3 (Time: 11:10 - 11:35) Modeling Framework for Cross-Point Resistive Memory Design Emphasizing Reliability and Variability Issues ...... 112 Yang Zheng, Cong Xu (Pennsylvania State Univ., U.S.A.), *Yuan Xie (Pennsylvania State Univ./Univ. of California, Santa Barbara, U.S.A.) 1C-4 (Time: 11:35 - 12:00) A Defect-Aware Approach for Mapping Reconﬁgurable Single-Electron Transistor Arrays ...... 118 *Ching-Yi Huang, Chian-Wei Liu, Chun-Yao Wang (National Tsing Hua Univ., Taiwan), Yung-Chih Chen (Yuan Ze Univ., Taiwan), Suman Datta, Vijaykrishnan Narayanan (Pennsylvania State Univ., U.S.A.)

2S (Special Session) Internet of Things Time: 13:50 - 15:30, Tuesday, January 20, 2015 Location: Room 103 Chair: Li Shang (Univ. of Colorado Boulder, U.S.A.) 2S-1 (Time: 13:50 - 14:20) (Invited Paper) Powering the IoT: Storage-Less and Converter-Less Energy Harvesting ...... 124 *Hyung Gyu Lee (Daegu Univ., Republic of Korea), Naehyuck Chang (KAIST, Republic of Korea) 2S-2 (Time: 14:20 - 14:50) (Invited Paper) Distributed Computing in IoT: System-on-a-Chip for Smart Cameras as an Example ...... 130 *Shao-Yi Chien, Wei-Kai Chan, Yu-Hsiang Tseng (National Taiwan Univ., Taiwan), Chia-Han Lee (Academia Sinica, Taiwan), V. Srinivasa Somayazulu, Yen-Kuang Chen (Intel, U.S.A.) 2S-3 (Time: 14:50 - 15:30) (Invited Paper) Data Sensing and Analysis: Challenges for Wearables ...... 136 James Williamson, Qi Liu, Fenglong Lu, Wyatt Mohrman, Kun Li (Univ. of Colorado Boulder, U.S.A.), Robert P. Dick (Univ. of Michigan, U.S.A.), *Li Shang (Univ. of Colorado Boulder, U.S.A.)

2A NoCS II (Power and Emerging Technology) Time: 13:50 - 15:30, Tuesday, January 20, 2015 Location: Room 102 Chairs: Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany), Tomoya Horiguchi (Toshiba) 2A-1 (Time: 13:50 - 14:15) ShuttleNoC: Boosting On-Chip Communication Eﬃciency by Enabling Localized Power Adaptation ...... 142 Hang Lu (Univ. of Chinese Academy of Sciences, China), *Guihai Yan, Yinhe Han, Ying Wang (Chinese Academy of Sciences, China), Xiaowei Li (Univ. of Chinese Academy of Sciences, China) 2A-2 (Time: 14:15 - 14:40) Energy-Eﬃcient Optical Crossbars on Chip with Multi-Layer Deposited Silicon ...... 148 Hui Li, *Sebastien´ Le Beux (Lyon Institute of Nanotechnology, France), Gabriela Nicolescu (Ecole Polytech- nique de Montreal,´ Canada), Ian O’Connor (Lyon Institute of Nanotechnology, France) 2A-3 (Time: 14:40 - 15:05) Two-Phase Protocol Converters for 3D Asynchronous 1-of-n Data Links ...... 154 Julian Hilgemberg Pontes, *Pascal Vivet, Yvain Thonnart (CEA/LETI, France) 2A-4 (Time: 15:05 - 15:30) Fine-Grained Runtime Power Budgeting for Networks-on-Chip ...... 160 *Xiaohang Wang, Tengfei Wang (Chinese Academy of Sciences, China), Terrence Mak (Chinese Academy of Sciences/Chinese Univ. of Hong Kong, China), Mei Yang, Yingtao Jiang (Univ. of Nevada, Las Vegas, U.S.A.), Masoud Daneshtalab (Royal Inst. of Tech, Sweden/Univ. of Turku, Finland)

32 Tuesday, January 20, 2015

2B Design Automation for Tomorrow’s Circuit Technologies Time: 13:50 - 15:30, Tuesday, January 20, 2015 Location: Room 104 Chairs: Anupam Chattopadhyay (RWTH Aachen Univ., Germany), Shigeru Yamashita (Ritsumeikan Univ.) 2B-1 (Time: 13:50 - 14:15) Nonvolatile Memory Allocation and Hierarchy Optimization for High-Level Synthesis ...... 166 Shuangchen Li (Tsinghua Univ., China/Univ. of California, Santa Barbara, U.S.A.), Ang Li, Yongpan Liu (Tsinghua Univ., China), *Yuan Xie (Univ. of California, Santa Barbara, U.S.A.), Huazhong Yang (Tsinghua Univ., China) 2B-2 (Time: 14:15 - 14:40) Reverse BDD-Based Synthesis for Splitter-Free Optical Circuits ...... 172 Robert Wille, *Oliver Keszocze, Clemens Hopfmuller, Rolf Drechsler (Univ. of Bremen, Germany) 2B-3 (Time: 14:40 - 15:05) Determining the Minimal Number of SWAP Gates for Multi-Dimensional Nearest Neighbor Quantum Circuits ...... 178 Aaron Lye (Univ. of Bremen, Germany), *Robert Wille, Rolf Drechsler (Univ. of Bremen/Cyber Physical Systems, DFKI GmbH, Germany)

2C Emerging Applications Time: 13:50 - 15:30, Tuesday, January 20, 2015 Location: Room 105 Chairs: Juinn-Dar Huang (National Chiao Tung Univ., Taiwan), Youhua Shi (Waseda Univ.) 2C-1 (Time: 13:50 - 14:15) Design and Optimization of 3D Digital Microfluidic Biochips for the Polymerase Chain Reaction ...... 184 Zipeng Li (Duke Univ., U.S.A.), Tsung-Yi Ho (National Chiao Tung Univ., Taiwan), *Krishnendu Chakrabarty (Duke Univ., U.S.A.) 2C-2 (Time: 14:15 - 14:40) An Accurate and Low Cost PM2.5 Estimation Method Based on Artificial Neural Network ...... 190 *Lixue Xia, Rong Luo, Bin Zhao, Yu Wang, Huazhong Yang (Tsinghua Univ., China) 2C-3 (Time: 14:40 - 15:05) Iterative Disparity Voting Based Stereo Matching Algorithm and Its Hardware Implementation ...... 196 Zhi Hu, *Yibo Fan, Xiaoyang Zeng (Fudan Univ., China) 2C-4 (Time: 15:05 - 15:30) Obstacle-Avoiding Wind Turbine Placement for Power-Loss and Wake-Effect Optimization ...... 202 *Yu-Wei Wu (National Cheng Kung Univ., Taiwan), Yi-yu Shi (Missouri Univ. of Science and Tech., U.S.A.), Sudip Roy (National Cheng Kung Univ., Taiwan), Tsung-Yi Ho (National Chiao Tung Univ., Taiwan)

3S (Special Session) New Challenges and Solutions in Nanometer Physical Design Time: 15:50 - 17:30, Tuesday, January 20, 2015 Location: Room 103 Chair: Mark Po-Hung Lin (National Chung Cheng Univ., Taiwan) 3S-1 (Time: 15:50 - 16:15) (Invited Paper) An Eﬃcient Linear Time Triple Patterning Solver ...... 208 Haitong Tian (Univ. of Illinois, Urbana-Champaign, U.S.A.), Hongbo Zhang (Synopsys, U.S.A.), Zigang Xiao, *Martin D. F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.) 3S-2 (Time: 16:15 - 16:40) (Invited Paper) Gate Sizing and Threshold Voltage Assignment for High Performance Microprocessor Designs ...... 214 Tiago Reimann (Univ. Federal do Rio Grande do Sul, Brazil), Cliﬀ C.N. Sze (IBM, U.S.A.), *Ricardo Reis (Univ. Federal do Rio Grande do Sul, Brazil) 3S-3 (Time: 16:40 - 17:05) (Invited Paper) Analytical Placement for Rectilinear Blocks ...... 220 *Yasuhiro Takashima (Univ. of Kitakyushu, Japan)

33 Tuesday, January 20, 2015

3S-4 (Time: 17:05 - 17:30) (Invited Paper) IR to Routing Challenge and Solution for Interposer-Based Design ...... 226 *Eric Jia-Wei Fang, Terry Chi-Jih Shih, Darton Shen-Yu Huang (MediaTek, Taiwan)

3A Circuits for Performance and Reliability Time: 15:50 - 16:40, Tuesday, January 20, 2015 Location: Room 102 Chairs: Sri Parameswaran (Univ. of New South Wales, Australia), Chengmo Yang (Univ. of Delaware) 3A-1 (Time: 15:50 - 16:15) Aging Mitigation in Memory Arrays Using Self-Controlled Bit-Flipping Technique ...... 231 *Anteneh Gebregiorgis (TU Delft, Netherlands), Mojtaba Ebrahimi, Saman Kiamehr, Fabian Oboril (Karl- sruhe Inst. of Tech., Germany), Said Hamdioui (TU Delft, Netherlands), Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany) 3A-2 (Time: 16:15 - 16:40) Design Methodology for Approximate Accumulator Based on Statistical Error Model ...... 237 Chang Liu, *Xinghua Yang, Fei Qiao, Qi Wei, Huazhong Yang (Tsinghua Univ., China)

3B Frontiers in Logic Synthesis Time: 15:50 - 17:30, Tuesday, January 20, 2015 Location: Room 104 Chairs: Robert Wille (Univ. of Bremen, Germany), Yuko Hara-Azumi (Tokyo Inst. of Tech.) 3B-1 (Time: 15:50 - 16:15) Multiple Independent Gate FETs: How Many Gates Do We Need? ...... 243 *Luca Amaru (Integrated Systems Laboratory - EPFL, Switzerland), Gage Hills (Stanford Univ., U.S.A.), Pierre-Emmanuel Gaillardon (Integrated Systems Laboratory - EPFL, Switzerland), Subhasish Mitra (Stanford Univ., U.S.A.), Giovanni De Micheli (Integrated Systems Laboratory - EPFL, Switzerland) 3B-2 (Time: 16:15 - 16:40) Polynomial Time Algorithm for Area and Power Eﬃcient Adder Synthesis in High-Performance Designs ...... 249 Subhendu Roy (Univ. of Texas, Austin, U.S.A.), Mihir Choudhury, Ruchir Puri (IBM, U.S.A.), *David Z Pan (Univ. of Texas, Austin, U.S.A.) 3B-3 (Time: 16:40 - 17:05) Accelerating SAT-Based Boolean Matching for Heterogeneous FPGAs Using One-Hot Encoding and CEGAR Tech- nique ...... 255 *Yusuke Matsunaga (Kyushu Univ., Japan)

3C Energy Optimization for Electric Vehicles and Smart Grids Time: 15:50 - 17:30, Tuesday, January 20, 2015 Location: Room 105 Chairs: Hideki Takase (Kyoto Univ., Japan), Yongpan Liu (Tsinghua Univ., China) 3C-1 (Time: 15:50 - 16:15) Negotiation-Based Task Scheduling and Storage Control Algorithm to Minimize User’s Electric Bills under Dynamic Prices ...... 261 Ji Li, Yanzhi Wang, Xue Lin, Shahin Nazarian, *Massoud Pedram (USC, U.S.A.) 3C-2 (Time: 16:15 - 16:40) Many-to-Many Active Cell Balancing Strategy Design ...... 267 *Matthias Kauer, Swaminathan Narayanaswamy, Sebastian Steinhorst, Martin Lukasiewycz (TUM CREATE, Singapore), Samarjit Chakraborty (TU Munich, Germany) 3C-3 (Time: 16:40 - 17:05) Intra-Vehicle Network Routing Algorithm for Wiring Weight and Wireless Transmit Power Minimization ...... 273 *Ta-Yang Huang, Chia-Jui Chang (National Cheng Kung Univ., Taiwan), Chung-Wei Lin (Univ. of California, Berkeley, U.S.A.), Sudip Roy (National Cheng Kung Univ., Taiwan), Tsung-Yi Ho (National Chiao Tung Univ., Taiwan)

34 Tuesday, January 20, 2015

3C-4 (Time: 17:05 - 17:30) An Autonomous Decentralized Mechanism for Energy Interchanges with Accelerated Diffusion Based on MCMC . . . . 279 *Yusuke Sakumoto (Tokyo Metropolitan Univ., Japan), Ittetsu Taniguchi (Ritsumeikan Univ., Japan) SRF ACM SIGDA Student Research Forum at ASP-DAC2015 Time: 18:00 - 20:00, Tuesday, January 20, 2015 SRF-1: A Fast Process Variation and Pattern Fidelity Aware Mask Optimization Algorithm Ahmed Awad (Tokyo Institute of Technology) SRF-2: Energy Efficient Cache Memories in Deeply-Scaled Technologies Alireza Shafaei (University of Southern California) SRF-3: Energy Efficient System Design for Neural Networks Boxun Li (Tsinghua University) SRF-4: Analysis and Power Optimization for Probabilistic Boolean Circuits Ching-Yi Huang (National Tsing Hua University) SRF-5: Power Consumption Characterization, Modeling and Estimation of Electric Vehicles Donkyu Baek (KAIST) SRF-6: A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delays for Yield Improvement Hayato Mashiko (University of Aizu) SRF-7: Reconfigurable PV Powered Full Electric Vehicles Jaemin Kim (Seoul National University, KAIST) SRF-8: Feature Localization and Design Understanding for Hardware Designs Jan Malburg (University of Bremen) SRF-9: Designing Efficient On-chip Networks: Mapping, Management, and Routing Jinho Lee (Seoul National University) SRF-10: Development of A Design Environment for Asynchronous Circuits with Bundled-data Implementation on FPGAs Keitaro Takizawa (University of Aizu) SRF-11: Endurance and Energy Aware Optimizations for Phase Change Memory Mengying Zhao (City University of Hong Kong) SRF-12: vFlash: Unied Non-Volatile Memory and NAND Flash Memory Architecture in Smartphones Renhai Chen (Hong Kong Polytechnic University) SRF-13: Robust Clock Network Synthesis Rickard Ewetz (Purdue University) SRF-14: Physical Design Optimization Using Lithography Defect Probability Seongbo Shim (KAIST) SRF-15: Contactless Pre-Bond TSV Test and Diagnosis Using Ring Oscillators and Multiple Voltage Levels Sergej Deutsch (Duke University) SRF-16: Multi-objective P/G TSV Planning in 3D-ICs Shengcheng Wang (Karlsruhe Institute of Technology) SRF-17: Fast Error Rate Estimation with Stochastic Modeling for Adaptive Speed Controlled Circuit Shoichi Iizuka (Osaka University) SRF-18: Design and Optimization for Digital Microfluidic Biochips Trung Anh Dinh (Ritsumeikan University,) SRF-19: Learning Mechanisms with High Power Efficiency Design Wan-Yu Wen (National Tsing Hua University) SRF-20: Demystify Energy Usage in Smartphones Xiang Chen (University of Pittsburgh) SRF-21: A High-Efficiency Dual-Channel Photovoltaic Power System for Nonvolatile Sensor Nodes Xiao Sheng (Tsinghua University) SRF-22: Understanding Swapping in Mobile Systems Xiao Zhu (Chongqing University) SRF-23: A Contact-Imaging Based Microfluidic Cytometer with Machine-Learning for Single-Frame Super-Resolution Processing Xiwei Huang (Nanyang Technological University) SRF-24: Model-based Design for Mixed-Criticality Systems Zaid Al-bayati (McGill University)

35 Wednesday, January 21, 2015

2K Keynote II Time: 9:00 - 9:50, Wednesday, January 21, 2015 Location: International Conference Room Chair: Kunio Uchiyama (Hitachi) 2K-1 (Time: 9:00 - 9:50) (Keynote Address) Programmable Network ...... 285 *Atsushi Takahara (NTT, Japan)

4S (Special Session) Machine Learning in EDA: Promises and Challenges in Selected Ap- plications Time: 10:15 - 12:20, Wednesday, January 21, 2015 Location: Room 103 Chair: Li-C. Wang (Univ. of California, Santa Barbara, U.S.A.) 4S-1 (Time: 10:15 - 10:45) (Invited Paper) Machine Learning and Pattern Matching in Physical Design ...... 286 Bei Yu, *David Z. Pan (Univ. of Texas, Austin, U.S.A.), Tetsuaki Matsunawa (Toshiba, Japan), Xuan Zeng (Fudan Univ., China) 4S-2 (Time: 10:45 - 11:15) (Invited Paper) Self-Learning and Adaptive Board-Level Functional Fault Diagnosis ...... 294 Fangming Ye, *Krishnendu Chakrabarty (Duke Univ., U.S.A.), Zhaobo Zhang, Xinli Gu (Huawei Technolo- gies, U.S.A.) 4S-3 (Time: 11:15 - 11:45) (Invited Paper) Fast Statistical Analysis of Rare Failure Events for Memory Circuits in High-Dimensional Variation Space ...... 302 Shupeng Sun, *Xin Li (Carnegie Mellon Univ., U.S.A.) 4S-4 (Time: 11:45 - 12:20) (Invited Paper) Data Mining in Functional Test Content Optimization ...... 308 *Li-C. Wang (Univ. of California, Santa Barbara, U.S.A.)

4A Eﬃcient NVM Management, from Register to Disk Time: 10:15 - 12:20, Wednesday, January 21, 2015 Location: Room 102 Chairs: Kyoungwoo Lee (Yonsei Univ., Republic of Korea), Koji Nii (Renesas Electronics) 4A-1 (Time: 10:15 - 10:40) Checkpoint-Aware Instruction Scheduling for Nonvolatile Processor with Multiple Functional Units ...... 316 Mimi Xie, Chen Pan, *Jingtong Hu (Oklahoma State Univ., U.S.A.), Chengmo Yang (Univ. of Delaware, U.S.A.), Yiran Chen (Univ. of Pittsburgh, U.S.A.) 4A-2 (Time: 10:40 - 11:05) Balloonﬁsh: Utilizing Morphable Resistive Memory in Mobile Virtualization ...... 322 Linbo Long, Duo Liu, *Xiao Zhu, Kan Zhong (Chongqing Univ., China), Zili Shao (Hong Kong Polytechnic Univ., Hong Kong), Edwin H.-M. Sha (Chongqing Univ., China) 4A-3 (Time: 11:05 - 11:30) A Three-Stage-Write Scheme with Flip-Bit for PCM Main Memory ...... 328 Yanbin Li, *Xin Li, Lei Ju, Zhiping Jia (Shandong Univ., China) 4A-4 (Time: 11:30 - 11:55) A Garbage Collection Aware Stripping Method for Solid-State Drives ...... 334 *Min Huang (Harbin Inst. of Tech., China), Yi Wang (Shenzhen Univ./Hong Kong Polytechnic Univ., China), Zhaoqing Liu, Liyan Qiao (Harbin Inst. of Tech., China), Zili Shao (Hong Kong Polytechnic Univ., Hong Kong)

36 Wednesday, January 21, 2015

4A-5 (Time: 11:55 - 12:20) Uniﬁed Non-Volatile Memory and NAND Flash Memory Architecture in Smartphones ...... 340 *Renhai Chen (Hong Kong Polytechnic Univ., Hong Kong), Yi Wang (Shenzhen Univ., China), Jingtong Hu (Oklahoma State Univ., U.S.A.), Duo Liu (Chongqing Univ., China), Zili Shao (Hong Kong Polytechnic Univ., Hong Kong), Yong Guan (Capital Normal Univ., China)

4B Robust Timing, and P/G Modeling and Design Time: 10:15 - 12:20, Wednesday, January 21, 2015 Location: Room 104 Chairs: Ray Cheung (City Univ. of Hong Kong, Hong Kong), Fan Yang (Fudan Univ., China) 4B-1 (Time: 10:15 - 10:40) A Retargetable and Accurate Methodology for Logic-IP-Internal Electromigration Assessment ...... 346 Palkesh Jain (Qualcomm India Pvt, India), *Sachin S. Sapatnekar (Univ. of Minnesota, U.S.A.), Jordi Cor- tadella (Univ. Politecnica` de Catalunya, Spain) 4B-2 (Time: 10:40 - 11:05) New Electromigration Modeling and Analysis Considering Time-Varying Temperature and Current Densities ...... 352 Hai-Bao Chen, *Sheldon X.-D. Tan, Xin Huang (Univ. of California, Riverside, U.S.A.), Valeriy Sukharev (Mentor Graphics, U.S.A.) 4B-3 (Time: 11:05 - 11:30) Generating Circuit Current Constraints to Guarantee Power Grid Safety ...... 358 *Zahi Moudallal, Farid N Najm (Univ. of Toronto, Canada) 4B-4 (Time: 11:30 - 11:55) BEE: Predicting Realistic Worst Case and Stochastic Eye Diagrams by Accounting for Correlated Bitstreams and Coding Strategies ...... 366 Aadithya Karthik (UC Berkeley, U.S.A.), Sayak Ray (Princeton Univ., U.S.A.), *Jaijeet Roychowdhury (UC Berkeley, U.S.A.) 4B-5 (Time: 11:55 - 12:20) A Fast Parallel Approach for Common Path Pessimism Removal ...... 372 *Chung-Hao Tsai, Wai-Kei Mak (National Tsing Hua Univ., Taiwan)

4C New Issues in Placement and Routing Time: 10:15 - 12:20, Wednesday, January 21, 2015 Location: Room 105 Chairs: Shigetoshi Nakatake (Univ. of Kitakyushu, Japan), Yuzi Kanazawa (Fujitsu Labs.) 4C-1 (Time: 10:15 - 10:40) Detailed-Routing-Driven Analytical Standard-Cell Placement ...... 378 *Chau-Chin Huang, Chien-Hsiung Chiou, Kai-Han Tseng, Yao-Wen Chang (National Taiwan Univ., Taiwan) 4C-2 (Time: 10:40 - 11:05) An Approach to Anchoring and Placing High Performance Custom Digital Designs ...... 384 *Shih-Ying Liu (National Chiao Tung Univ./MediaTek, Taiwan), Tung-Chieh Chen (Synopsys, Taiwan), Hung-Ming Chen (National Chiao Tung Univ., Taiwan) 4C-3 (Time: 11:05 - 11:30) Non-Stitch Triple Patterning-Aware Routing Based on Conﬂict Graph Pre-Coloring ...... 390 *Po-Ya Hsu, Yao-Wen Chang (National Taiwan Univ., Taiwan) 4C-4 (Time: 11:30 - 11:55) Cut Mask Optimization with Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing ...... 396 *Shao-Yun Fang (National Taiwan Univ. of Science and Tech., Taiwan) 4C-5 (Time: 11:55 - 12:20) A Length Matching Routing Method for Disordered Pins in PCB Design ...... 402 *Ran Zhang, Tieyuan Pan, Li Zhu, Takahiro Watanabe (Waseda Univ., Japan)

37 Wednesday, January 21, 2015

5S (Designers’ Forum ) Car Electronics Time: 13:50 - 15:30, Wednesday, January 21, 2015 Location: Room 103 Organizer: Shinichi Shibahara (Renesas Electronics, Japan), Chair: Koji Inoue (Kyushu Univ., Japan) 5S-1 (Time: 13:50 - 14:20) (Invited Paper) Systems Modeling for Additional Development in Automotive E/E Architecture ...... 408 *Hidekazu Nishimura (Keio Univ., Japan) 5S-2 (Time: 14:20 - 14:50) (Invited Paper) Implementation and Evaluation of Image Recognition Algorithm for An Intelligent Vehicle using Het- erogeneous Multi-Core SoC ...... 410 *Nau Ozaki, Masato Uchiyama, Yasuki Tanabe, Shuichi Miyazaki, Takaaki Sawada, Takanori Tamai, Moriyasu Banno (Toshiba, Japan) 5S-3 (Time: 14:50 - 15:20) (Invited Paper) Trend in Power Devices for Electric and Hybrid Electric Vehicles ...... 416 *Khalid Hussein, Akira Fujita, Katsumi Sato (Mitsubishi Electric, Japan)

5A Optimization and Exploration for Caches Time: 13:50 - 15:30, Wednesday, January 21, 2015 Location: Room 102 Chairs: Hiroyuki Tomiyama (Ritsumeikan Univ., Japan), Lin Meng (Ritsumeikan Univ., Japan) 5A-1 (Time: 13:50 - 14:15) Multilane Racetrack Caches: Improving Eﬃciency Through Compression and Independent Shifting ...... 417 *Haifeng Xu (Univ. of Pittsburgh, U.S.A.), Yong Li (VMware, U.S.A.), Rami Melhem, Alex K. Jones (Univ. of Pittsburgh, U.S.A.) 5A-2 (Time: 14:15 - 14:40) Managing Hybrid On-Chip Scratchpad and Cache Memories for Multi-Tasking Embedded Systems ...... 423 Zimeng Zhou, *Lei Ju, Zhiping Jia, Xin Li (Shandong Univ., China) 5A-3 (Time: 14:40 - 15:05) Optimizing Thread-to-Core Mapping on Manycore Platforms with Distributed Tag Directories ...... 429 *Guantao Liu, Tim Schmidt, Rainer Doemer (Univ. of California, Irvine, U.S.A.), Ajit Dingankar, Desmond Kirkpatrick (Intel, U.S.A.) 5A-4 (Time: 15:05 - 15:30) Accelerating Non-Volatile/Hybrid Processor Cache Design Space Exploration for Application Speciﬁc Embedded Sys- tems ...... 435 *Mohammad Shihabul Haque, Ang Li, Akash Kumar (National Univ. of Singapore, Singapore), Qingsong Wei (Data Storage Institute, Singapore)

5B CAD for Analog/RF/Mixed-Signal Design Time: 13:50 - 15:30, Wednesday, January 21, 2015 Location: Room 104 Chairs: Sheldon Tan (Univ. of California, Riverside, U.S.A.), Mark Po-Hung Lin (National Chung Cheng Univ., Taiwan) 5B-1 (Time: 13:50 - 14:15) Accurate Passivity-Enforced Macromodeling for RF Circuits via Iterative Zero/Pole Update Based on Measurement Data ...... 441 Ying-Chih Wang, Shihui Yin, Minhee Jun, *Xin Li, Lawrence T. Pileggi, Tamal Mukherjee, Rohit Negi (Carnegie Mellon Univ., U.S.A.) 5B-2 (Time: 14:15 - 14:40) Physical Veriﬁcation Flow for Hierarchical Analog IC Design Constraints ...... 447 *Volker Meyer zu Bexten, Markus Tristl (Inﬁneon Technologies AG, Germany), Goran¨ Jerke (Robert Bosch GmbH, Germany), Hartmut Marquardt (Mentor Graphics, Germany), Dina Medhat (Mentor Graphics, Egypt)

38 Wednesday, January 21, 2015

5B-3 (Time: 14:40 - 15:05) Automatic Design for Analog/RF Front-End System in 802.11ac Receiver ...... 454 *Zhijian Pan, Chuan Qin, Zuochang Ye, Yan Wang (Tsinghua Univ., China) 5B-4 (Time: 15:05 - 15:30) SIPredict: Eﬃcient Post-Layout Waveform Prediction via System Identiﬁcation ...... 460 *Qicheng Huang, Xiao Li, Fan Yang, Xuan Zeng (Fudan Univ., China), Xin Li (Fudan Univ., China/Carnegie Mellon Univ., U.S.A.)

5C Next-Generation Clock Network Synthesis Time: 13:50 - 15:30, Wednesday, January 21, 2015 Location: Room 105 Chairs: Atsushi Takahashi (Tokyo Inst. of Tech.), David Z. Pan (Univ. of Texas, Austin, U.S.A.) 5C-1 (Time: 13:50 - 14:15) Useful Clock Skew Scheduling Using Adjustable Delay Buﬀers in Multi-Power Mode Designs ...... 466 *Juyeon Kim, Taewhan Kim (Seoul National Univ., Republic of Korea) 5C-2 (Time: 14:15 - 14:40) Fast Clock Skew Scheduling Based on Sparse-Graph Algorithms ...... 472 *Rickard Ewetz (Purdue Univ., U.S.A.), Shankarshana Janarthanan (NVIDIA, U.S.A.), Cheng-Kok Koh (Pur- due Univ., U.S.A.) 5C-3 (Time: 14:40 - 15:05) Modeling and Optimization of Low Power Resonant Clock Mesh ...... 478 *Wulong Liu (Tsinghua Univ., China), Guoqing Chen (Research Lab, Advanced Micro Devices, China), Yu Wang, Huazhong Yang (Tsinghua Univ., China) 5C-4 (Time: 15:05 - 15:30) Synthesis of Resonant Clock Networks Supporting Dynamic Voltage / Frequency Scaling ...... 484 *Seyong Ahn, Minseok Kang (Seoul National Univ., Republic of Korea), Marios C. Papaefthymiou (Univ. of Michigan, U.S.A.), Taewhan Kim (Seoul National Univ., Republic of Korea)

6S (Designers’ Forum) Panel Discussion: Challenges in the Era of Big-Data Computing Time: 15:50 - 17:30, Wednesday, January 21, 2015 Location: Room 103 Organizer: Koji Inoue (Kyushu Univ., Japan), Moderator: Koichiro Yamashita (Fujitsu Labs., Japan) 6S-1 (Time: 15:50 - 17:30) (Panel Discussion) Challenges in the Era of Big-Data Computing Panelists: Kento Aida (NII, Japan), Derek Chiou (Microsoft, U.S.A.), Hiroshi Nakamura (Univ. of Tokyo, Japan), Hiroyuki Tanaka (Nippon Telegraph and Telephone, Japan), Iwao Yamazaki (Fujitsu, Japan)

6A Optimization Techniques for Non-Volatile Memory based Systems Time: 15:50 - 17:30, Wednesday, January 21, 2015 Location: Room 102 Chairs: Guangyu Sun (Peking Univ., China), Ju Lei (Shandong Univ.) 6A-1 (Time: 15:50 - 16:15) An Eﬃcient STT-RAM-Based Register File in GPU Architectures ...... 490 Xiaoxiao Liu, Mengjie Mao, Xiuyuan Bi, Hai Li, *Yiran Chen (Univ. of Pittsburgh, U.S.A.) 6A-2 (Time: 16:15 - 16:40) A Bit-Write Reduction Method based on Error-Correcting Codes for Non-Volatile Memories ...... 496 *Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ., Japan) 6A-3 (Time: 16:40 - 17:05) Minimizing MLC PCM Write Energy for Free through Proﬁling-Based State Remapping ...... 502 *Mengying Zhao (City Univ. of Hong Kong, Hong Kong), Yuan Xue, Chengmo Yang (Univ. of Delaware, U.S.A.), Chun Jason Xue (City Univ. of Hong Kong, Hong Kong)

39 Wednesday, January 21, 2015

6A-4 (Time: 17:05 - 17:30) Improving Performance and Lifetime of DRAM-PCM Hybrid Main Memory through a Proactive Page Allocation Strat- egy ...... 508 Hoda Aghaei Khouzani, *Chengmo Yang (Univ. of Delaware, U.S.A.), Jingtong Hu (Oklahoma State Univ., U.S.A.)

6B Test for Higher Quality Time: 15:50 - 17:30, Wednesday, January 21, 2015 Location: Room 104 Chairs: Tomokazu Yoneda (NAIST, Japan), Stefan Holst (Kyushu Inst. of Tech.) 6B-1 (Time: 15:50 - 16:15) Enhanced LCCG: A Novel Test Clock Generation Scheme for Faster-than-at-Speed Delay Testing ...... 514 *Songwei Pei, Ye Geng (Beijing Univ. of Chemical Tech., China), Huawei Li (Key Laboratory of Computer System and Architecture, Institute of Computing Technology, China), Jun Liu (Hefei Univ. of Tech., China), Song Jin (North China Electric Power Univ., China) 6B-2 (Time: 16:15 - 16:40) An Eﬃcient 3D-IC On-Chip Test Framework to Embed TSV Testing in Memory BIST ...... 520 Liang-Che Li, Wen-Hsuan Hsu, *Kuen-Jong Lee (National Cheng Kung Univ., Taiwan), Chun-Lung Hsu (ITRI, Taiwan) 6B-3 (Time: 16:40 - 17:05) An Integrated Temperature-Cycling Acceleration and Test Technique for 3D Stacked ICs ...... 526 *Nima Aghaee, Zebo Peng, Petru Eles (Linkoping¨ Univ., Sweden) 6B-4 (Time: 17:05 - 17:30) Software-Based Test and Diagnosis of SoCs Using Embedded and Wide-I/O DRAM ...... 532 *Sergej Deutsch, Krishnendu Chakrabarty (Duke Univ., U.S.A.)

6C Reliability Time: 15:50 - 17:30, Wednesday, January 21, 2015 Location: Room 105 Chairs: Xuan Zeng (Fudan Univ., China), Martin Wong (UIUC, U.S.A.) 6C-1 (Time: 15:50 - 16:15) Logic-DRAM Co-Design to Eﬃciently Repair Stacked DRAM With Unused Spares ...... 538 Minjie Lv, *Hongbin Sun, Jingmin Xin, Nanning Zheng (Xi’an Jiaotong Univ., China) 6C-2 (Time: 16:15 - 16:40) Electromigration-Aware Redundant via Insertion ...... 544 Jiwoo Pak, Bei Yu, *David Z. Pan (Univ. of Texas, Austin, U.S.A.) 6C-3 (Time: 16:40 - 17:05) Synthesis of Resilient Circuits from Guarded Atomic Actions ...... 550 Yuankai Chen (Synopsys, U.S.A.), *Hai Zhou (Northwestern Univ., U.S.A.) 6C-4 (Time: 17:05 - 17:30) Incremental Latin Hypercube Sampling for Lifetime Stochastic Behavioral Modeling of Analog Circuits ...... 556 Yen-Lung Chen (National Central Univ., Taiwan), Wei Wu (Univ. of California, Los Angeles, U.S.A.), *Chien- Nan Jimmy Liu (National Central Univ., Taiwan), Lei He (Univ. of California, Los Angeles, U.S.A.)

40 Thursday, January 22, 2015

3K Keynote III Time: 9:00 - 9:50, Thursday, January 22, 2015 Location: International Conference Room Chair: Kunio Uchiyama (Hitachi) 3K-1 (Time: 9:00 - 9:50) (Keynote Address) When and How Will an AI Be Smart Enough to Design? ...... 562 *Noriko Arai (NII, Japan) 7S (Special Session) The Future of Emerging ReRAM Technology Time: 10:15 - 12:20, Thursday, January 22, 2015 Location: Room 103 Chairs: Guangyu Sun (Peking Univ., China), Yuan Xie (Univ. of California, Santa Barbara, U.S.A.) 7S-1 (Time: 10:15 - 10:45) (Invited Paper) Toward Large-Scale Access-Transistor-Free Memristive Crossbars ...... 563 Amirali Ghofrani, Miguel Angel Lastras-Montano,˜ *K.-T. Tim Cheng (Univ. of California, Santa Barbara, U.S.A.) 7S-2 (Time: 10:45 - 11:15) (Invited Paper) Read Circuits for Resistive Memory (ReRAM) and Memristor-Based Nonvolatile Logics ...... 569 *Meng-Fan Chang, Albert Lee, Chien-Chen Lin (National Tsing Hua Univ., Taiwan), Mon-Shu Ho (National Chung Hsin Univ., Taiwan), Ping-Cheng Chen (I-Shou Univ., Taiwan), Chia-Chen Kuo, Ming-Pin Chen, Pei- Ling Tseng, Tzu-Kun Ku (ITRI, Taiwan), Chien-Fu Chen, Kai-Shin Li, Jia-Min Shieh (National Nano Device Laboratories, Taiwan) 7S-3 (Time: 11:15 - 11:45) (Invited Paper) 3D ReRAM with Field Assisted Super-Linear Threshold (FASTTM) Selector Technology for Super- Dense, Low Power, Low Latency Data Storage Systems ...... 575 Sung Hyun Jo, Tanmay Kumar, Mehdi Asnaashari, Wei D. Lu, *Hagop Nazarian (Crossbar, U.S.A.) 7S-4 (Time: 11:45 - 12:20) (Invited Paper) Modeling and Design Optimization of ReRAM ...... 576 *J. F. Kang, H. T. Li, P. Huang, Z. Chen, B. Gao, X. Y. Liu (Peking Univ., China), Z. Z. Jiang, H.-S. P. Wong (Stanford Univ., U.S.A.) 7A Ensuring the Correctness of System Integration Time: 10:15 - 12:20, Thursday, January 22, 2015 Location: Room 102 Chairs: Takeshi Matsumoto (Ishitawa National College of Tech.), Akash Kumar (Natioanl Univ. of Singapore, Singapore) 7A-1 (Time: 10:15 - 10:40) Evaluation of Runtime Monitoring Methods for Real-Time Event Streams ...... 582 *Biao Hu, Kai Huang, Gang Chen, Alois Knoll (Technical Univ. of Muenchen, Germany) 7A-2 (Time: 10:40 - 11:05) Automatic Timing-Coherent Transactor Generation for Mixed-Level Simulations ...... 588 *Li-chun Chen, Hsin-I Wu, Ren-Song Tsay (National Tsing Hua Univ., Taiwan) 7A-3 (Time: 11:05 - 11:30) Hybrid Coverage Assertions for Eﬃcient Coverage Analysis Across Simulation and Emulation Environments ...... 594 Hsuan-Ming Chou, Hong-Chang Wu, Yi-Chiao Chen, *Jean Tsao, Shih-Chieh Chang (National Tsing Hua Univ., Taiwan) 7A-4 (Time: 11:30 - 11:55) SWAT: Assertion-Based Debugging of Concurrency Issues at System Level ...... 600 *Luis Gabriel Murillo, Robert´ Lajos Bucs,¨ Daniel Hincapie, Rainer Leupers, Gerd Ascheid (RWTH Aachen Univ., Germany) 7A-5 (Time: 11:55 - 12:20) Communication Protocol Analysis of Transaction-Level Models Using Satisﬁability Modulo Theories ...... 606 *Che-Wei Chang, Rainer Doemer (Univ. of California, Irvine, U.S.A.)

41 Thursday, January 22, 2015

7B Orchestrating Tasks, Cores, and Communication Time: 10:15 - 12:20, Thursday, January 22, 2015 Location: Room 104 Chairs: Zili Shao (Hong Kong Polytechnic Univ., Hong Kong), Masanori Hashimoto (Osaka Univ., Japan) 7B-1 (Time: 10:15 - 10:40) Guiding Fault-Driven Adaption in Multicore Systems through a Reliability-Aware Static Task Schedule ...... 612 Laura A Rozo Duque, *Chengmo Yang (Univ. of Delaware, U.S.A.) 7B-2 (Time: 10:40 - 11:05) Approximation-Aware Scheduling on Heterogeneous Multi-Core Architectures ...... 618 *Cheng Tan, Thannirmalai Somu Muthukaruppan, Tulika Mitra (National Univ. of Singapore, Singapore), Lei Ju (Shandong Univ., China) 7B-3 (Time: 11:05 - 11:30) Composing Real-Time Applications from Communicating Black-Box Components ...... 624 *Martin Becker (Tech. Univ. of Munich, Germany), Alejandro Masrur (Software Technology for Embedded Systems, Technical Univ. Chemnitz, Germany), Samarjit Chakraborty (Tech. Univ. of Munich, Germany) 7B-4 (Time: 11:30 - 11:55) Enhanced Partitioned Scheduling of Mixed-Criticality Systems on Multicore Platforms ...... 630 *Zaid Al-bayati (McGill Univ., Canada), Qingling Zhao (Zhejiang Univ., China), Ahmed Youssef (McGill Univ., Canada), Haibo Zeng (Virginia Tech, U.S.A.), Zonghua Gu (Zhejiang Univ., China) 7B-5 (Time: 11:55 - 12:20) Reducing Dynamic Dispatch Overhead (DDO) of SLDL-Synthesized Embedded Software ...... 636 Jiaxing Zhang, Sanyuan Tang, *Gunar Schirner (Northeastern Univ., U.S.A.)

7C Design for Manufacturability Time: 10:15 - 12:20, Thursday, January 22, 2015 Location: Room 105 Chairs: Shigeki Nojima (Toshiba, Japan), Eric J.-W. Fang (MediaTek, Taiwan) 7C-1 (Time: 10:15 - 10:40) Contact Pitch and Location Prediction for Directed Self-Assembly Template Veriﬁcation ...... 644 Zigang Xiao, Yuelin Du, *Martin D.F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.), He Yi, H.-S. Philip Wong (Stanford Univ., U.S.A.), Hongbo Zhang (Synopsys, U.S.A.) 7C-2 (Time: 10:40 - 11:05) Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography ...... 652 *Yunfeng Yang, Wai-Shing Luk (Fudan Univ., China), Hai Zhou (Fudan Univ., China/Northwestern Univ., U.S.A.), Changhao Yan, Xuan Zeng (Fudan Univ., China), Dian Zhou (Fudan Univ, China/Univ. of Texas, Dallas, U.S.A.) 7C-3 (Time: 11:05 - 11:30) Polynomial Time Optimal Algorithm for Stencil Row Planning in E-Beam Lithography ...... 658 Daifeng Guo, Yuelin Du, *Martin D.F. Wong (Univ. of Illinois, Urbana-Champaign, U.S.A.) 7C-4 (Time: 11:30 - 11:55) Fast Mask Assignment Using Positive Semideﬁnite Relaxation in LELECUT Triple Patterning Lithography ...... 665 *Yukihide Kohira (Univ. of Aizu, Japan), Tomomi Matsui (Tokyo Inst. of Tech., Japan), Yoko Yokoyama, Chikaaki Kodama (Toshiba, Japan), Atsushi Takahashi (Tokyo Inst. of Tech., Japan), Shigeki Nojima, Satoshi Tanaka (Toshiba, Japan) 7C-5 (Time: 11:55 - 12:20) Layout Decomposition for Spacer-is-Metal (SIM) Self-Aligned Double Patterning ...... 671 *Shao-Yun Fang (National Taiwan Univ. of Science and Tech., Taiwan), Yi-Shu Tai, Yao-Wen Chang (National Taiwan Univ., Taiwan)

42 Thursday, January 22, 2015

8S (Designers’ Forum) Technology Trend toward 8K Era Time: 13:50 - 15:30, Thursday, January 22, 2015 Location: Room 103 Organizer: Hiroe Iwasaki (NTT, Japan), Chair: Masaitsu Nakajima (Panasonic, Japan) 8S-1 (Time: 13:50 - 14:15) (Invited Paper) The Prospects of Next Generation Television - Japan’s Initiative to 2020 - ...... 677 *Keiya Motohashi (NetTV Forum, Japan) 8S-2 (Time: 14:15 - 14:40) (Invited Paper) 8K LCD : Technologies and Challenges toward the Realization of SUPER Hi-VISION TV ...... 680 *Takeshi Kumakura (SHARP, Japan) 8S-3 (Time: 14:40 - 15:05) (Invited Paper) The World’s 1st Complete-4K SoC Solution with Hybrid Memory System ...... 684 *Daisuke Murakami, Yuki Soga, Daisuke Imoto, Yoshiharu Watanabe, Takashi Yamada (Panasonic, Japan) 8S-4 (Time: 15:05 - 15:30) (Invited Paper) H.265/HEVC Encoder for UHDTV ...... 687 *Mitsuo Ikeda (NTT, Japan)

8A Exploring Better Architecture of Your Systems Time: 13:50 - 15:30, Thursday, January 22, 2015 Location: Room 102 Chairs: Rainer Doemer (Univ. of California, Irvine, U.S.A.), Hoeseok Yang (Ajou Univ., Republic of Korea) 8A-1 (Time: 13:50 - 14:15) An Accurate ACOSSO Metamodeling Technique for Processor Architecture Design Space Exploration ...... 689 *Hongwei Wang (Beijing Key Laboratory of Mobile Computing and Pervasive Device/Chinese Academy of Sciences/Univ. of Chinese Academy of Sciences, China), Ziyuan Zhu, Jinglin Shi, Yongtao Su (Beijing Key Laboratory of Mobile Computing and Pervasive Device/Chinese Academy of Sciences, China) 8A-2 (Time: 14:15 - 14:40) Speeding Up Single Pass Simulation of PLRUt Caches ...... 695 *Josef Schneider, Jorgen Peddersen, Sri Parameswaran (Univ. of New South Wales, Australia) 8A-3 (Time: 14:40 - 15:05) ADAPT: An ADAptive Manycore Methodology for Software Pipelined ApplicaTions ...... 701 *Xi Zhang, Haris Javaid (Univ. of New South Wales, Australia), Muhammad Shaﬁque (Karlsruhe Inst. of Tech., Germany), Jude Angelo Ambrose (Univ. of New South Wales, Australia), Jorg¨ Henkel (Karlsruhe Inst. of Tech., Germany), Sri Parameswaran (Univ. of New South Wales, Australia) 8A-4 (Time: 15:05 - 15:30) A Trace-Driven Approach for Fast and Accurate Simulation of Manycore Architectures ...... 707 *Anastasiia Butko, Rafael Garibotti, Luciano Ost, Vianney Lapotre, Abdoulaye Gamatie, Gilles Sassatelli (LIRMM/CNRS/Univ. of Montpellier II, France), Chris Adeniyi-Jones (ARM, U.K.)

8B Circuit-Level Modeling and Simulation Time: 13:50 - 15:30, Thursday, January 22, 2015 Location: Room 104 Chairs: Luca Daniel (Massachusetts Inst. of Tech., U.S.A.), Takashi Sato (Kyoto Univ.) 8B-1 (Time: 13:50 - 14:15) Compact Modeling of Microbatteries Using Behavioral Linearization and Model-Order Reduction ...... 713 Mohammed Shemsu Nesro (Masdar Inst. of Tech., United Arab Emirates), Lizhong Sun (Applied Materials, U.S.A.), *Ibrahim (Abe) M. Elfadel (Masdar Inst. of Science and Tech., United Arab Emirates) 8B-2 (Time: 14:15 - 14:40) GPU-Accelerated Parallel Monte Carlo Analysis of Analog Circuits by Hierarchical Graph-Based Solver ...... 719 Yan Zhu, *Sheldon X.-D. Tan (Univ. of California, Riverside, U.S.A.)

43 Thursday, January 22, 2015

8B-3 (Time: 14:40 - 15:05) Automated Generation of Hybrid System Models for Reachability Analysis of Nonlinear Analog Circuits ...... 725 *Hyun-Sek Lukas Lee (Leibniz Univ. Hannover, Germany), Matthias Althoff (Tech. Univ. Munchen,¨ Ger- many), Stefan Hoelldampf, Markus Olbrich, Erich Barke (Leibniz Univ. Hannover, Germany) 8B-4 (Time: 15:05 - 15:30) Area Efficient Device-Parameter Estimation Using Sensitivity-Configurable Ring Oscillator ...... 731 *Shoichi Iizuka, Yuma Higuchi, Masanori Hashimoto, Takao Onoye (Osaka Univ., Japan)

8C Reliable and Trustworthy Electronics Time: 13:50 - 15:30, Thursday, January 22, 2015 Location: Room 105 Chairs: Takashi Aikyo (STARC, Japan), Eishi Ibe (Hitachi) 8C-1 (Time: 13:50 - 14:15) On Test Syndrome Merging for Reasoning-Based Board-Level Functional Fault Diagnosis ...... 737 Zelong Sun (Chinese Univ. of Hong Kong, Hong Kong), *Li Jiang (Shanghai Jiao Tong Univ., China), Qiang Xu (Chinese Univ. of Hong Kong, Hong Kong), Zhaobo Zhang, Zhiyuan Wang, Xinli Gu (Huawei Technolo- gies, U.S.A.) 8C-2 (Time: 14:15 - 14:40) Event-Driven Transient Error Propagation: A Scalable and Accurate Soft Error Rate Estimation Approach ...... 743 Mojtaba Ebrahimi, Razi Seyyedi, Liang Chen, *Mehdi Tahoori (Karlsruhe Inst. of Tech., Germany) 8C-3 (Time: 14:40 - 15:05) A Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurement ...... 749 *Daisuke Fujimoto, Makoto Nagata (Kobe Univ., Japan), Shivam Bhasin, Jean-Luc Danger (Telecom Paris- tech, France) 8C-4 (Time: 15:05 - 15:30) Hardware Trojan Detection Using Exhaustive Testing of k-bit Subspaces ...... 755 Nicole Lesperance, Shrikant Kulkarni, *Kwang-Ting Cheng (UC Santa Barbara, U.S.A.)

9S (Designers’ Forum) Panel Discussion: IP Base SoC Design and IP Design Innovation Time: 15:50 - 17:30, Thursday, January 22, 2015 Location: Room 103 Organizer: Nobuyuki Nishiguchi (Cadence Design Systems, Japan), Moderator: Toshihiro Hattori (Renesas System Design, Japan) 9S-1 (Time: 15:50 - 17:30) (Panel Discussion) IP Base SoC Design and IP Design Innovation Panelists: Hironori Ando (Synopsys, Japan), Kevin Yee (Cadence, U.S.A.), Randy Smith (Sonics, U.S.A.), Neil Parris (ARM, U.K.)

9A Power/Thermal Management and Modeling Time: 15:50 - 17:30, Thursday, January 22, 2015 Location: Room 102 Chairs: Donghwa Shin (Yeungnam Univ., Republic of Korea), Takashi Nakada (Univ. of Tokyo, Japan) 9A-1 (Time: 15:50 - 16:15) AROMA: A Highly Accurate Microcomponent-Based Approach for Embedded Processor Power Analysis ...... 761 Zih-Ci Huang, *Chi-Kang Chen, Ren-Song Tsay (National Tsing Hua Univ., Taiwan) 9A-2 (Time: 16:15 - 16:40) Battery-Aware Mapping Optimization of Loop Nests for CGRAs ...... 767 *Yu Peng, Shouyi Yin, Leibo Liu, Shaojun Wei (Tsinghua Univ., China) 9A-3 (Time: 16:40 - 17:05) THOR: Orchestrated Thermal Management of Cores and Networks in 3D Many-Core Architectures ...... 773 *Jinho Lee, Junwhan Ahn, Kiyoung Choi (Seoul National Univ., Republic of Korea), Kyungsu Kang (Samsung Electronics, Republic of Korea)

44 Thursday, January 22, 2015

9A-4 (Time: 17:05 - 17:30) Early Stage Real-Time SoC Power Estimation Using RTL Instrumentation ...... 779 Jianlei Yang (Tsinghua Univ./Intel, China), *Liwei Ma, Kang Zhao (Intel, China), Yici Cai (Tsinghua Univ., China), Tin-Fook Ngai (Intel, China)

9B (Special Session) System-Level Designs and Tools for Multicore Systems Time: 15:50 - 17:30, Thursday, January 22, 2015 Location: Room 104 Chair: Chung-Ta King (National Tsing Hua Univ., Taiwan) 9B-1 (Time: 15:50 - 16:15) (Invited Paper) Heterogeneous Architecture Design with Emerging 3D and Non-Volatile Memory Technologies ...... 785 Qiaosha Zou, Matthew Poremba (Pennsylvania State Univ., U.S.A.), Rui He, Wei Yang, Junfeng Zhao (Huawei Shannon Lab, China), *Yuan Xie (Univ. of California, Santa Barbara, U.S.A.) 9B-2 (Time: 16:15 - 16:40) (Invited Paper) Alleviate Chip I/O Pin Constraints for Multicore Processors through Optical Interconnects ...... 791 *Zhehui Wang, Jiang Xu, Peng Yang, Xuan Wang, Zhe Wang, Luan H.K. Duong, Zhifei Wang, Haoran Li, Rafael K.V. Maeda, Xiaowen Wu (Hong Kong Univ. of Science and Tech., Hong Kong), Yaoyao Ye, Qinfen Hao (Huawei Technologies, China) 9B-3 (Time: 16:40 - 17:05) (Invited Paper) A Fast and Accurate Network-on-Chip Timing Simulator with a Flit Propagation Model ...... 797 Ting-Shuo Hsu, Jun-Lin Chiu, Chao-Kai Yu, *Jing-Jia Liou (National Tsing Hua Univ., Taiwan) 9B-4 (Time: 17:05 - 17:30) (Invited Paper) Application-Level Embedded Communication Tracer for Many-Core Systems ...... 803 *Chih-Tsun Huang, Kuan-Chun Tasi, Jun-Shen Lin, Hsiao-Wei Chien (National Tsing Hua Univ., Taiwan)

9C Building Secure Systems Time: 15:50 - 17:30, Thursday, January 22, 2015 Location: Room 105 Chairs: Wenjing Rao (Univ. of Illinois, Chicago, U.S.A.), Sandip Ray (Intel, Portland, U.S.A.) 9C-1 (Time: 15:50 - 16:15) Timing-Based Anomaly Detection in Embedded Systems ...... 809 Sixing Lu, Minjun Seo, *Roman Lysecky (Univ. of Arizona, U.S.A.) 9C-2 (Time: 16:15 - 16:40) Satisﬁability Don’t Care Condition Based Circuit Fingerprinting Techniques ...... 815 *Carson J Dunbar, Gang Qu (Univ. of Maryland, U.S.A.) 9C-3 (Time: 16:40 - 17:05) IC Piracy Prevention via Design Withholding and Entanglement ...... 821 Soroush Khaleghi, Kai Da Zhao, *Wenjing Rao (Univ. of Illinois, Chicago, U.S.A.) 9C-4 (Time: 17:05 - 17:30) Vulnerability Analysis for Crypto Devices against Probing Attack ...... 827 *Lingxiao Wei, Jie Zhang, Feng Yuan, Yannan Liu (Chinese Univ. of Hong Kong, Hong Kong), Junfeng Fan (Open Security Research, China), Qiang Xu (Chinese Univ. of Hong Kong, Hong Kong)

45 Supporter’s Exhibition Supporter’s exhibition is held by three companies which support ASP-DAC 2015 and have exhibition booths. The supporter’s exhibition is presented at International Conference Hall 1F Lobby from January 20 through January 22.

Exhibit Hours: 10:00 – 17:30, January 20 / 10:00 – 17:30, January 21 / 10:00 – 16:00, January 22 Location: 1F Lobby System Design Enablement by Cadence Multi Domain/Language Simulation Platform Ca- dence Simulation Platform supports wide range of system design domains for automotive, medical, industrial and many more applications. Supported domains: SW/HW co-simulation, Cadence Design Systems, mixed digital/analog mixed design, electronics-mechanics coupled simulation, fault injection, Japan thermal/power/noise analysis, etc. Supported languages: C/C++, SystemC, SystemVerilog, http://www.cadence.co.jp/ VHDL, Verilog, VHDL-AMS, Verilog-AMS and SPICE, etc.

CyberWorkBench has been developed by NEC over the course of twenty years. CyberWork- Bench is a C-based LSI design platform developed around the “All-in-C” paradigm that al- lows high level synthesis and verification of any ANSI-C or SystemC program generating NEC Corporation high quality RTL. For more information, visit us at http://www.cyberworkbench.com/ http://www.nec.co.jp/ Showcased is LAVIS-plus that is a full-chip caliber IC design visualization system having electrical characteristics analysis, verification error display, and simple editing capabilities. LAVIS-plus also provides open APIs for facilitating its customization. The API enables you TOOL CORPORATION to use general syntax and libraries, so that you can easily create all sorts of scripts ranging http://www.tool.co.jp/ from basic ones to advanced ones. Visit our booth and learn more about our EDA solutions. Zuken will exhibit at ASP-DAC their next generation EDA solution, CR-8000 Design Force. Design Force enables system-level co-design of the chip, package, and board with a native 3D database, and offers automated features to conduct upfront trade-off studies. Top-down and bottom-up flows can be managed with ease with Design Force by creating any simple or advanced hierarchical system structures to optimize IO connectivity and signal performance. ZUKEN Inc. Furthermore, Design Force is a new system developed for the latest hardware, software and http://www.zuken.co.jp/ 3D graphic technologies, so design teams can innovate with the highest performing and quality software, and reduce the product development time for any technology, including 2.5/3D IC, system-in-package (SiP), and embedding active devices within the substrate. JEITA EDA Technical Committee is involved in promoting technologies and international standards related to the Electronic Design Automation (EDA) for designing semiconductor devices, electronic devices and systems, as a part of the activities of JEITA (the Japan Elec- tronics and Information Technology Industries Association). At ASP-DAC2015, we show one of our standardization activities in IEEE, “P2401- Standard Format for LSI-Package- Board Interoperable Design.” The general purpose of this standard is to develop a common format that LSI-Package-Board (LPB) design tools can use to exchange information/data JEITA EDA Technical Commit- ff tee seamlessly, as opposed to having to work with multiple di erent input and output formats. http://www.jeita.or.jp/ The format provides a common way to specify information/data about the project management, net lists, components, design rules, and geometries used in LSI-Package-Board (LPB) designs. For more information, please visit at http://www.jeita-edatc.com/ and http://standards.ieee.org/develop/project/2401.html . Toppan Technical Design Center Co., Ltd. (TDC) ,as a LSI designing partner for leading semiconductor manufacturers and as a Turnkey partner for electrical, industrial, and medical equipment manufacturers, has been providing a design and a development of LSI for over the past forty years. We provide a variety of LSI designing such as from logic to analog, from circuit to layout, from 28nm to 1um.We also provide Turnkey solutions to our customers TOPPAN PRINTING CO., with analog/mixed-signal design technology as our core competence. Our turnkey business LTD. is the one stop solution. We provide either simple shuttle service or a full service option that http://www.toppan.co.jp/ ranges from prototyping to production and includes selection of the optimum silicon foundry, support for packaging and testing, process management and quality assurance. Making use of our analog/mixed-signal LSI design know-how, we have had accumulated experience in sensing, data transfer, RF, power management and many other specialized IC applications. Open Processor Foundation (OPF): A public benefit nonprofit organization is dedicated to promote the universal freedom to create, distribute and modify microprocessor design. Clean-Room Design: The first open source CPU core is called “J1 core” together with asso- ciated logic. 32/64bit J series processors leverage 20+ year old technologies and cutting edge Open Processor Foundation design tools, process and methodologies. J series users can leverage software tools, OSes and (OPF) http://∅pf.org/ applications accumulated over 20 years.

46 IEEE CASS/CEDA Luncheon Presentations

IEEE CASS/CEDA Joint Seminar at 20th Anniversary of ASP-DAC

Date and Time: 12:30-13:35, January 22, 2015 Location: General Purpose Room (1F)

Meeting Agenda:

(1) Lecture 1: 12:35-13:05 Title: My Take on ASP-DAC at its 20th Anniversary Speaker: David Z. Pan (The University of Texas at Austin) (2) Lecture 2: 13:05-13:35 Title: Design for Manufacturability for the Next Decade and Beyond Speaker: Yao-Wen Chang (National Taiwan University) sponsored by IEEE CASS Japan/Fukuoka/Kansai/Shikoku Chapters, IEEE CEDA All Japan Joint Chapter No Admission Charge. Limited Lunch (probably 50 box-lunches) will be served on a ﬁrst-come-ﬁrst-serve basis.

47 Information

Proceedings: ASP-DAC 2015 will be producing an authority to access the download site for the conference proceedings. The site will be open on Jan. 19, 2015. Please note that neither CD-ROM nor USB memory are provided.

Banquet: Conference registrants are invited to attend a banquet to be held on January 21, 2015. The banquet will be held from 18:00 to 20:00 at the Convention Hall A. Regular Member and Non-member Conference registrants receive a ticket to the banquet when they register at the conference. Full-time students, Designers’ Forum-only registrants, and Tutorial-only registrants wishing to attend the banquet will be required to pay 5,000 yen for a ticket when they register on site.

Climate: The temperature in Chiba/Tokyo during the period of the Conference ranges between 5◦C and 12◦C.

Currency Exchange: Only Japanese yen (JPY, Y) is acceptable at regular stores and restaurants. Certain foreign currencies may be accepted at a limited number of hotels, restaurants and souvenir shops. You can buy yen at foreign exchange banks and other authorized money exchangers on presentation of your passport.

Travelers checks and credit cards: Travelers checks are accepted only by leading banks and major hotels in principal cities, and the use of travelers checks in Japan is not as popular as in some other countries. VISA, MasterCard, Diners Club, and American Express are widely accepted at hotels, department stores, shops, restaurants and nightclubs.

Tipping: In Japan, tips are not necessary anywhere, even at hotels and restaurants.

Electricity: Electric voltage is uniformly 100 volts, AC, throughout Japan, but with two diﬀerent cycles: 50 in Eastern Japan*, and 60 in Western Japan**. Leading hotels in major cities have two outlets of 100 and 220 volts but their sockets usually accept a two-leg plug only. *Eastern Japan :Tokyo, Chiba, Yokohama, Tohoku, Hokkaido **Western Japan :Nagoya, Osaka, Kyoto, Hiroshima, Shikoku, Kyushu

Shopping: Shops and other sales outlets in Japan are generally open on Saturdays, Sundays and national holidays as well as weekdays from 10:00 to 20:00. Department stores, however, are closed on one weekday, diﬀering by store, and certain specialty shops may not open on Sundays and national holidays.

Other Information:

JAPAN NATIONAL TOURISM ORGANIZATION http://www.jnto.go.jp/ NARITA AIRPORT http://www.narita-airport.jp/en/ HANEDA AIRPORT http://www.haneda-airport.jp/en/ YES ! TOKYO http://tcvb.or.jp/en/ CHIBA, JAPAN TRAVEL GUIDE http://japan-chiba-guide.com/en/

48 Author Index

A Chen, Badong ...... p.29 (1S-9) Chen, Badong ...... p.29 (1S-10) Adeniyi-Jones, Chris ...... p.43 (8A-4) Chen, Chi-Kang ...... p.44 (9A-1) Aghaee, Nima ...... p.40 (6B-3) Chen, Chien-Fu ...... p.41 (7S-2) Aghaei Khouzani, Hoda ...... p.40 (6A-4) Chen, Gang ...... p.41 (7A-1) Ahn, Junwhan ...... p.44 (9A-3) Chen, Guoqing ...... p.39 (5C-3) Ahn, Seyong ...... p.39 (5C-4) Chen, Hai-Bao ...... p.37 (4B-2) Aida, Kento ...... p.39 (6S-1) Chen, Hung-Ming ...... p.37 (4C-2) Al-bayati, Zaid ...... p.42 (7B-4) Chen, Li-chun ...... p.41 (7A-2) Al-bayati, Zaid ...... p.35(SRF-24) Chen, Liang ...... p.44 (8C-2) Alnajjar, Dawood ...... p.29 (1S-7) Chen, Ming-Pin ...... p.41 (7S-2) Althoﬀ, Matthias ...... p.44 (8B-3) Chen, Ping-Cheng ...... p.41 (7S-2) Amaki, Takehiko ...... p.29 (1S-2) Chen, Renhai ...... p.37 (4A-5) Amaru, Luca ...... p.34 (3B-1) Chen, Renhai ...... p.35(SRF-12) Ambrose, Jude Angelo ...... p.43 (8A-3) Chen, Shuang ...... p.31 (1B-1) Ando, Hironori ...... p.44 (9S-1) Chen, Tung-Chieh ...... p.37 (4C-2) Aoki, Takafumi ...... p.30 (1S-13) Chen, Xiang ...... p.35(SRF-20) Arai, Noriko ...... p.41 (3K-1) Chen, Yen-Kuang ...... p.32 (2S-2) Ascheid, Gerd ...... p.41 (7A-4) Chen, Yen-Lung ...... p.40 (6C-4) Asnaashari, Mehdi ...... p.41 (7S-3) Chen, Yi-Chiao ...... p.41 (7A-3) Awad, Ahmed ...... p.35 (SRF-1) Chen, Yiran ...... p.36 (4A-1) Chen, Yiran ...... p.39 (6A-1) B Chen, Yuankai ...... p.40 (6C-3) Baek, Donkyu ...... p.35 (SRF-5) Chen, Yung-Chih ...... p.32 (1C-4) Banno, Moriyasu ...... p.38 (5S-2) Chen, Z...... p.41 (7S-4) Barke, Erich ...... p.44 (8B-3) Cheng, K.-T. Tim ...... p.41 (7S-1) Becker, Martin ...... p.42 (7B-3) Cheng, Kwang-Ting ...... p.44 (8C-4) Benini, Luca ...... p.31 (1B-2) Chien, Hsiao-Wei ...... p.30 (1S-12) Bhasin, Shivam ...... p.44 (8C-3) Chien, Hsiao-Wei ...... p.45 (9B-4) Bi, Xiuyuan ...... p.39 (6A-1) Chien, Shao-Yi ...... p.32 (2S-2) Bucs,¨ Robert´ Lajos ...... p.41 (7A-4) Chiou, Chien-Hsiung ...... p.37 (4C-1) Burg, Andreas ...... p.31 (1B-2) Chiou, Derek ...... p.39 (6S-1) Butko, Anastasiia ...... p.43 (8A-4) Chiu, Jun-Lin ...... p.45 (9B-3) Choi, Kiyoung ...... p.44 (9A-3) Chou, Hsuan-Ming ...... p.41 (7A-3) C Choudhury, Mihir ...... p.34 (3B-2) Cai, Yici ...... p.45 (9A-4) Cortadella, Jordi ...... p.37 (4B-1) Cao, Yu ...... p.31 (1C-2) Chakrabarty, Krishnendu ...... p.33 (2C-1) Chakrabarty, Krishnendu ...... p.36 (4S-2) D Chakrabarty, Krishnendu ...... p.40 (6B-4) Daneshtalab, Masoud ...... p.32 (2A-4) Chakraborty, Samarjit ...... p.34 (3C-2) Danger, Jean-Luc ...... p.44 (8C-3) Chakraborty, Samarjit ...... p.42 (7B-3) Datta, Suman ...... p.32 (1C-4) Chan, Wei-Kai ...... p.32 (2S-2) De Micheli, Giovanni ...... p.34 (3B-1) Chang, Che-Wei ...... p.41 (7A-5) Deng, Chenchen ...... p.31 (1A-1) Chang, Chia-Jui ...... p.34 (3C-3) Deng, Wei ...... p.29 (1S-1) Chang, Meng-Fan ...... p.41 (7S-2) Deng, Wei ...... p.30 (1S-19) Chang, Naehyuck ...... p.32 (2S-1) Deng, Wei ...... p.30 (1S-22) Chang, Shih-Chieh ...... p.41 (7A-3) Deutsch, Sergej ...... p.40 (6B-4) Chang, Yao-Wen ...... p.37 (4C-1) Deutsch, Sergej ...... p.35(SRF-15) Chang, Yao-Wen ...... p.37 (4C-3) Diao, Shengxi ...... p.30 (1S-20) Chang, Yao-Wen ...... p.42 (7C-5) Dick, Robert P...... p.32 (2S-3)

49 Dingankar, Ajit ...... p.38 (5A-3) Hao, Qinfen ...... p.45 (9B-2) Dinh, Anh, Trung ...... p.35(SRF-18) Haque, Mohammad Shihabul ...... p.38 (5A-4) Doemer, Rainer ...... p.38 (5A-3) Hasegawa, So ...... p.30 (1S-24) Doemer, Rainer ...... p.41 (7A-5) Hasegawa, Yuya ...... p.30 (1S-17) Drechsler, Rolf ...... p.33 (2B-2) Hashiba, Junki ...... p.30 (1S-17) Drechsler, Rolf ...... p.33 (2B-3) Hashimoto, Masanori ...... p.29 (1S-2) Du, Yuelin ...... p.42 (7C-1) Hashimoto, Masanori ...... p.29 (1S-7) Du, Yuelin ...... p.42 (7C-3) Hashimoto, Masanori ...... p.44 (8B-4) Dunbar, Carson J ...... p.45 (9C-2) Hayashi, Yu-ichi ...... p.30 (1S-13) Duong, Luan H.K...... p.45 (9B-2) He, Lei ...... p.40 (6C-4) He, Rui ...... p.45 (9B-1) E Henkel, Jorg¨ ...... p.43 (8A-3) Ebrahimi, Mojtaba ...... p.34 (3A-1) Higuchi, Yuma ...... p.44 (8B-4) Ebrahimi, Mojtaba ...... p.44 (8C-2) Hilgemberg Pontes, Julian ...... p.32 (2A-3) Eles, Petru ...... p.40 (6B-3) Hills, Gage ...... p.34 (3B-1) Elfadel, Ibrahim (Abe) M...... p.43 (8B-1) Hincapie, Daniel ...... p.41 (7A-4) Enomoto, Tadayoshi ...... p.29 (1S-5) Hirao, Tomoya ...... p.31 (1A-3) Ewetz, Rickard ...... p.39 (5C-2) Hirose, Tetsuya ...... p.30 (1S-16) Ewetz, Rickard ...... p.35(SRF-13) Ho, Mon-Shu ...... p.41 (7S-2) Ho, Tsung-Yi ...... p.33 (2C-1) F Ho, Tsung-Yi ...... p.33 (2C-4) Ho, Tsung-Yi ...... p.34 (3C-3) Fan, Junfeng ...... p.45 (9C-4) Hoelldampf, Stefan ...... p.44 (8B-3) Fan, Yibo ...... p.33 (2C-3) Homma, Naofumi ...... p.30 (1S-13) Fang, Eric Jia-Wei ...... p.34 (3S-4) Hopfmuller, Clemens ...... p.33 (2B-2) Fang, Shao-Yun ...... p.37 (4C-4) Hsu, Chun-Lung ...... p.40 (6B-2) Fang, Shao-Yun ...... p.42 (7C-5) Hsu, Li-Chung ...... p.30 (1S-24) Fang, Yiming ...... p.30 (1S-21) Hsu, Po-Ya ...... p.37 (4C-3) Firouzi, Farshad ...... p.31 (1B-4) Hsu, Ting-Shuo ...... p.30 (1S-12) Fujimoto, Daisuke ...... p.30 (1S-13) Hsu, Ting-Shuo ...... p.45 (9B-3) Fujimoto, Daisuke ...... p.44 (8C-3) Hsu, Wen-Hsuan ...... p.40 (6B-2) Fujita, Akira ...... p.38 (5S-3) Hu, Biao ...... p.41 (7A-1) G Hu, Jingtong ...... p.36 (4A-1) Hu, Jingtong ...... p.37 (4A-5) Gaillardon, Pierre-Emmanuel ...... p.34 (3B-1) Hu, Jingtong ...... p.40 (6A-4) Gamatie, Abdoulaye ...... p.43 (8A-4) Hu, Zhi ...... p.33 (2C-3) Gao, B...... p.41 (7S-4) Huang, Chau-Chin ...... p.37 (4C-1) Garibotti, Rafael ...... p.43 (8A-4) Huang, Chih-Tsun ...... p.30 (1S-12) Gebregiorgis, Anteneh ...... p.34 (3A-1) Huang, Chih-Tsun ...... p.45 (9B-4) Geng, Ye ...... p.40 (6B-1) Huang, Ching-Yi ...... p.32 (1C-4) Ghofrani, Amirali ...... p.41 (7S-1) Huang, Ching-Yi ...... p.35 (SRF-4) Gu, Peng ...... p.31 (1C-2) Huang, Darton Shen-Yu ...... p.34 (3S-4) Gu, Xinli ...... p.36 (4S-2) Huang, Kai ...... p.41 (7A-1) Gu, Xinli ...... p.44 (8C-1) Huang, Min ...... p.36 (4A-4) Gu, Zonghua ...... p.42 (7B-4) Huang, P...... p.41 (7S-4) Guan, Yong ...... p.37 (4A-5) Huang, Qicheng ...... p.39 (5B-4) Guo, Daifeng ...... p.42 (7C-3) Huang, Ta-Yang ...... p.34 (3C-3) Guo, Jing ...... p.30 (1S-14) Huang, Xin ...... p.37 (4B-2) Huang, Xiwei ...... p.30 (1S-14) H Huang, Xiwei ...... p.35(SRF-23) Hamada, Taisuke ...... p.30 (1S-21) Huang, Zih-Ci ...... p.44 (9A-1) Hamdioui, Said ...... p.34 (3A-1) Hussein, Khalid ...... p.38 (5S-3) Han, Jie ...... p.31 (1A-1) Han, Yinhe ...... p.32 (2A-1)

50 I Kim, Jaemin ...... p.35 (SRF-7) Kim, Juyeon ...... p.39 (5C-1) Iizuka, Shoichi ...... p.44 (8B-4) Kim, Taewhan ...... p.39 (5C-1) Iizuka, Shoichi ...... p.35(SRF-17) Kim, Taewhan ...... p.39 (5C-4) Ikeda, Mitsuo ...... p.43 (8S-4) Kimura, Kento ...... p.30 (1S-22) Ikeda, Sho ...... p.30 (1S-21) Kimura, Shinji ...... p.39 (6A-2) Imagawa, Takashi ...... p.29 (1S-7) Kirkpatrick, Desmond ...... p.38 (5A-3) Imoto, Daisuke ...... p.43 (8S-3) Knoll, Alois ...... p.41 (7A-1) Inoue, Koji ...... p.31 (1A-3) Kobayashi, Kazutoshi ...... p.29 (1S-7) Ishihara, Noboru ...... p.30 (1S-21) Kobayashi, Nobuaki ...... p.29 (1S-5) Ishihara, Tohru ...... p.31 (1B-3) Kodama, Chikaaki ...... p.42 (7C-4) Ishikawa, Yosuke ...... p.30 (1S-21) Koh, Cheng-Kok ...... p.39 (5C-2) Ishikuro, Hiroki ...... p.30 (1S-17) Kohira, Yukihide ...... p.42 (7C-4) Ito, Hiroyuki ...... p.30 (1S-21) Kondo, Masaaki ...... p.31 (1A-3) Ito, Ryusuke ...... p.29 (1S-5) Kondo, Satoshi ...... p.29 (1S-1) Iwamoto, Mitsugu ...... p.29 (1S-3) Kondo, Satoshi ...... p.30 (1S-22) Izumi, Shintaro ...... p.29 (1S-4) Konoura, Hiroaki ...... p.29 (1S-7) Izumi, Shintaro ...... p.29 (1S-8) Kosuge, Atsutake ...... p.30 (1S-23) Kosuge, Atsutake ...... p.30 (1S-24) J Ku, Tzu-Kun ...... p.41 (7S-2) Jain, Palkesh ...... p.37 (4B-1) Kulkarni, Shrikant ...... p.44 (8C-4) Janarthanan, Shankarshana ...... p.39 (5C-2) Kumakura, Takeshi ...... p.43 (8S-2) Javaid, Haris ...... p.43 (8A-3) Kumar, Akash ...... p.38 (5A-4) Jerke, Goran¨ ...... p.38 (5B-2) Kumar, Tanmay ...... p.41 (7S-3) Jia, Zhiping ...... p.36 (4A-3) Kuo, Chia-Chen ...... p.41 (7S-2) Jia, Zhiping ...... p.38 (5A-2) Kuroda, Tadahiro ...... p.30 (1S-23) Jiang, Li ...... p.44 (8C-1) Kuroda, Tadahiro ...... p.30 (1S-24) Jiang, Yingtao ...... p.32 (2A-4) Kuroki, Nobutaka ...... p.30 (1S-16) Jiang, Z. Z...... p.41 (7S-4) Jin, Song ...... p.40 (6B-1) Jo, Sung Hyun ...... p.41 (7S-3) L Jones, Alex K...... p.38 (5A-1) Lai, Jyun-Long ...... p.30 (1S-12) Ju, Lei ...... p.36 (4A-3) Lapotre, Vianney ...... p.43 (8A-4) Ju, Lei ...... p.38 (5A-2) Lastras-Montano,˜ Miguel Angel ...... p.41 (7S-1) Ju, Lei ...... p.42 (7B-2) Le Beux, Sebastien´ ...... p.32 (2A-2) Jun, Minhee ...... p.38 (5B-1) Lee, Albert ...... p.41 (7S-2) Junaidi, Abdul Raziz ...... p.30 (1S-23) Lee, Chia-Han ...... p.32 (2S-2) Lee, Hyun-Sek Lukas ...... p.44 (8B-3) K Lee, Hyung Gyu ...... p.32 (2S-1) Kadamoto, Junichiro ...... p.30 (1S-24) Lee, Jinho ...... p.44 (9A-3) Kanaya, Haruichi ...... p.30 (1S-18) Lee, Jinho ...... p.35 (SRF-9) Kanbara, Hiroyuki ...... p.29 (1S-7) Lee, Kuen-Jong ...... p.40 (6B-2) Kanemoto, Daisuke ...... p.30 (1S-18) Lee, Sang yeop ...... p.30 (1S-21) Kang, J. F...... p.41 (7S-4) Lesperance, Nicole ...... p.44 (8C-4) Kang, Kyungsu ...... p.44 (9A-3) Leupers, Rainer ...... p.41 (7A-4) Kang, Minseok ...... p.39 (5C-4) Li, Ang ...... p.33 (2B-1) Karthik, Aadithya ...... p.37 (4B-4) Li, Ang ...... p.38 (5A-4) Kauer, Matthias ...... p.34 (3C-2) Li, Boxun ...... p.31 (1C-2) Kawaguchi, Hiroshi ...... p.29 (1S-4) Li, Boxun ...... p.35 (SRF-3) Kawaguchi, Hiroshi ...... p.29 (1S-8) Li, Chen ...... p.31 (1A-2) Kawajiri, Toru ...... p.30 (1S-17) Li, H. T...... p.41 (7S-4) Keszocze, Oliver ...... p.33 (2B-2) Li, Hai ...... p.31 (1C-1) Khaleghi, Soroush ...... p.45 (9C-3) Li, Hai ...... p.39 (6A-1) Kiamehr, Saman ...... p.34 (3A-1) Li, Haoran ...... p.45 (9B-2)

51 Li, Huawei ...... p.40 (6B-1) Lysecky, Roman ...... p.45 (9C-1) Li, Hui ...... p.32 (2A-2) Li, Ji ...... p.34 (3C-1) M Li, Kai-Shin ...... p.41 (7S-2) Ma, Liwei ...... p.45 (9A-4) Li, Kun ...... p.32 (2S-3) Ma, Sheng ...... p.31 (1A-2) Li, Liang-Che ...... p.40 (6B-2) Machida, Takanori ...... p.29 (1S-3) Li, Shuangchen ...... p.33 (2B-1) Maeda, Rafael K.V...... p.45 (9B-2) Li, Xiao ...... p.39 (5B-4) Mak, Terrence ...... p.32 (2A-4) Li, Xiaowei ...... p.32 (2A-1) Mak, Wai-Kei ...... p.37 (4B-5) Li, Xin ...... p.36 (4S-3) Malburg, Jan ...... p.35 (SRF-8) Li, Xin ...... p.36 (4A-3) Mao, Mengjie ...... p.39 (6A-1) Li, Xin ...... p.38 (5A-2) Marquardt, Hartmut ...... p.38 (5B-2) Li, Xin ...... p.38 (5B-1) Mashiko, Hayato ...... p.35 (SRF-6) Li, Xin ...... p.39 (5B-4) Masrur, Alejandro ...... p.42 (7B-3) Li, Yanbin ...... p.36 (4A-3) Masu, Kazuya ...... p.30 (1S-21) Li, Yong ...... p.38 (5A-1) Matsui, Tomomi ...... p.42 (7C-4) Li, Zipeng ...... p.33 (2C-1) Matsunaga, Yusuke ...... p.34 (3B-3) Lin, Chien-Chen ...... p.41 (7S-2) Matsunawa, Tetsuaki ...... p.36 (4S-1) Lin, Chung-Wei ...... p.34 (3C-3) Matsuzawa, Akira ...... p.29 (1S-1) Lin, Fujiang ...... p.30 (1S-20) Matsuzawa, Akira ...... p.30 (1S-19) Lin, Jun-Shen ...... p.45 (9B-4) Matsuzawa, Akira ...... p.30 (1S-22) Lin, Xue ...... p.34 (3C-1) Medhat, Dina ...... p.38 (5B-2) Liou, Jing-Jia ...... p.30 (1S-12) Meinerzhagen, Pascal ...... p.31 (1B-2) Liou, Jing-Jia ...... p.45 (9B-3) Melhem, Rami ...... p.38 (5A-1) Liu, Chang ...... p.34 (3A-2) Meyer zu Bexten, Volker ...... p.38 (5B-2) Liu, Chian-Wei ...... p.32 (1C-4) Mi, Fan ...... p.31 (1C-1) Liu, Chien-Nan Jimmy ...... p.40 (6C-4) Mitra, Subhasish ...... p.34 (3B-1) Liu, Duo ...... p.36 (4A-2) Mitra, Tulika ...... p.42 (7B-2) Liu, Duo ...... p.37 (4A-5) Mitsuyama, Yukio ...... p.29 (1S-7) Liu, Geng ...... p.30 (1S-11) Miura, Noriyuki ...... p.30 (1S-13) Liu, Guantao ...... p.38 (5A-3) Miyazaki, Shuichi ...... p.38 (5S-2) Liu, Jun ...... p.40 (6B-1) Mohrman, Wyatt ...... p.32 (2S-3) Liu, Leibo ...... p.31 (1A-1) Motohashi, Keiya ...... p.43 (8S-1) Liu, Leibo ...... p.44 (9A-2) Moudallal, Zahi ...... p.37 (4B-3) Liu, Qi ...... p.32 (2S-3) Mukherjee, Tamal ...... p.38 (5B-1) Liu, Shih-Ying ...... p.37 (4C-2) Murakami, Daisuke ...... p.43 (8S-3) Liu, Wulong ...... p.39 (5C-3) Murillo, Luis Gabriel ...... p.41 (7A-4) Liu, X. Y...... p.41 (7S-4) Liu, Xiaoxiao ...... p.39 (6A-1) Liu, Yannan ...... p.45 (9C-4) N Liu, Yongpan ...... p.33 (2B-1) Nagai, Takahiro ...... p.30 (1S-16) Liu, Zhaoqing ...... p.36 (4A-4) Nagata, Makoto ...... p.30 (1S-13) Long, Linbo ...... p.36 (4A-2) Nagata, Makoto ...... p.44 (8C-3) Lu, Fenglong ...... p.32 (2S-3) Najm, Farid N ...... p.37 (4B-3) Lu, Hang ...... p.32 (2A-1) Nakai, Yozaburo ...... p.29 (1S-8) Lu, Hongyi ...... p.31 (1A-2) Nakamura, Hiroshi ...... p.39 (6S-1) Lu, Sixing ...... p.45 (9C-1) Nakano, Masanao ...... p.29 (1S-8) Lu, Wei D...... p.41 (7S-3) Narayanan, Vijaykrishnan ...... p.32 (1C-4) Luk, Wai-Shing ...... p.42 (7C-2) Narayanaswamy, Swaminathan ...... p.34 (3C-2) Lukasiewycz, Martin ...... p.34 (3C-2) Nazarian, Hagop ...... p.41 (7S-3) Luo, Rong ...... p.33 (2C-2) Nazarian, Shahin ...... p.34 (3C-1) Lv, Minjie ...... p.40 (6C-1) Negi, Rohit ...... p.38 (5B-1) Lye, Aaron ...... p.33 (2B-3) Nesro, Mohammed Shemsu ...... p.43 (8B-1) Ngai, Tin-Fook ...... p.45 (9A-4)

52 Nguyen, Xuan-Thuan ...... p.29 (1S-6) Qu, Gang ...... p.45 (9C-2) Nicolescu, Gabriela ...... p.32 (2A-2) Nishimura, Hidekazu ...... p.38 (5S-1) R Nojima, Shigeki ...... p.42 (7C-4) Rao, Wenjing ...... p.45 (9C-3) Numa, Masahiro ...... p.30 (1S-16) Ray, Sayak ...... p.37 (4B-4) O Reimann, Tiago ...... p.33 (3S-2) Reis, Ricardo ...... p.33 (3S-2) O’Connor, Ian ...... p.32 (2A-2) Ren, Pengju ...... p.29 (1S-9) Oboril, Fabian ...... p.31 (1B-4) Ren, Pengju ...... p.29 (1S-10) Oboril, Fabian ...... p.34 (3A-1) Ren, Pengju ...... p.30 (1S-11) Ochi, Hiroyuki ...... p.29 (1S-7) Ren, Xiaowei ...... p.29 (1S-9) Okada, Akira ...... p.30 (1S-23) Ren, Xiaowei ...... p.29 (1S-10) Okada, Kenichi ...... p.29 (1S-1) Ren, Yu ...... p.31 (1A-1) Okada, Kenichi ...... p.30 (1S-19) Rossi, Davide ...... p.31 (1B-2) Okada, Kenichi ...... p.30 (1S-22) Roy, Subhendu ...... p.34 (3B-2) Olbrich, Markus ...... p.44 (8B-3) Roy, Sudip ...... p.33 (2C-4) Onodera, Hidetoshi ...... p.29 (1S-7) Roy, Sudip ...... p.34 (3C-3) Onodera, Hidetoshi ...... p.31 (1B-3) Roychowdhury, Jaijeet ...... p.37 (4B-4) Onoye, Takao ...... p.29 (1S-2) Rozo Duque, Laura A ...... p.42 (7B-1) Onoye, Takao ...... p.29 (1S-7) Onoye, Takao ...... p.44 (8B-4) S Oshiro, Keigo ...... p.30 (1S-18) Ost, Luciano ...... p.43 (8A-4) Sakiyama, Kazuo ...... p.29 (1S-3) Ozaki, Nau ...... p.38 (5S-2) Sakumoto, Yusuke ...... p.35 (3C-4) Ozaki, Toshihiro ...... p.30 (1S-16) Sapatnekar, Sachin S...... p.37 (4B-1) Sasaki, Hiroshi ...... p.31 (1A-3) P Sassatelli, Gilles ...... p.43 (8A-4) Sato, Katsumi ...... p.38 (5S-3) Pak, Jiwoo ...... p.40 (6C-2) Sawada, Takaaki ...... p.38 (5S-2) Pan, Chen ...... p.36 (4A-1) Schirner, Gunar ...... p.42 (7B-5) Pan, David Z ...... p.34 (3B-2) Schmidt, Tim ...... p.38 (5A-3) Pan, David Z...... p.36 (4S-1) Schneider, Josef ...... p.43 (8A-2) Pan, David Z...... p.40 (6C-2) Seo, Minjun ...... p.45 (9C-1) Pan, Tieyuan ...... p.37 (4C-5) Seyyedi, Razi ...... p.44 (8C-2) Pan, Zhijian ...... p.39 (5B-3) Sha, Edwin H.-M...... p.36 (4A-2) Papaefthymiou, Marios C...... p.39 (5C-4) Shafaei, Alireza ...... p.31 (1B-1) Parameswaran, Sri ...... p.43 (8A-2) Shafaei, Alireza ...... p.35 (SRF-2) Parameswaran, Sri ...... p.43 (8A-3) Shaﬁque, Muhammad ...... p.43 (8A-3) Parris, Neil ...... p.44 (9S-1) Shang, Li ...... p.32 (2S-3) Peddersen, Jorgen ...... p.43 (8A-2) Shao, Zili ...... p.36 (4A-2) Pedram, Massoud ...... p.31 (1B-1) Shao, Zili ...... p.36 (4A-4) Pedram, Massoud ...... p.34 (3C-1) Shao, Zili ...... p.37 (4A-5) Pei, Songwei ...... p.40 (6B-1) Sheng, Xiao ...... p.35(SRF-21) Peng, Yu ...... p.44 (9A-2) Shi, Jinglin ...... p.43 (8A-1) Peng, Zebo ...... p.40 (6B-3) Shi, Yi-yu ...... p.33 (2C-4) Pham, Cong-Kha ...... p.29 (1S-6) Shieh, Jia-Min ...... p.41 (7S-2) Pileggi, Lawrence T...... p.38 (5B-1) Shih, Terry Chi-Jih ...... p.34 (3S-4) Poremba, Matthew ...... p.45 (9B-1) Shim, Seongbo ...... p.35(SRF-14) Puri, Ruchir ...... p.34 (3B-2) Shimada, Hajime ...... p.29 (1S-7) Shiomi, Jun ...... p.31 (1B-3) Q Siriburanon, Teerachot ...... p.29 (1S-1) Qiao, Fei ...... p.34 (3A-2) Siriburanon, Teerachot ...... p.30 (1S-22) Qiao, Liyan ...... p.36 (4A-4) Smith, Randy ...... p.44 (9S-1) Qin, Chuan ...... p.39 (5B-3) Soga, Takeshi ...... p.31 (1A-3)

53 Soga, Yuki ...... p.43 (8S-3) U Somayazulu, V. Srinivasa ...... p.32 (2S-2) Somu Muthukaruppan, Thannirmalai . . . . . p.42 (7B-2) Uchiyama, Masato ...... p.38 (5S-2) Steinhorst, Sebastian ...... p.34 (3C-2) Ueno, Tomohiro ...... p.29 (1S-1) Su, Yongtao ...... p.43 (8A-1) Ueno, Tomohiro ...... p.30 (1S-22) Sugii, Toshihiro ...... p.29 (1S-4) Umeki, Yohei ...... p.29 (1S-4) Sukharev, Valeriy ...... p.37 (4B-2) Sun, Guangyu ...... p.31 (1C-1) V Sun, Hongbin ...... p.40 (6C-1) Vivet, Pascal ...... p.32 (2A-3) Sun, Lizhong ...... p.43 (8B-1) Sun, Shupeng ...... p.36 (4S-3) W Sun, Zelong ...... p.44 (8C-1) Wakabayashi, Kazutoshi ...... p.29 (1S-7) Sze, Cliﬀ C.N...... p.33 (3S-2) Wang, Chenluan ...... p.30 (1S-20) Wang, Chun-Yao ...... p.32 (1C-4) Wang, Hongwei ...... p.43 (8A-1) T Wang, Li-C...... p.36 (4S-4) Tahoori, Mehdi ...... p.34 (3A-1) Wang, Peng ...... p.31 (1A-2) Tahoori, Mehdi ...... p.44 (8C-2) Wang, Shengcheng ...... p.31 (1B-4) Tahoori, Mehdi B...... p.31 (1B-4) Wang, Shengcheng ...... p.35(SRF-16) Tai, Yi-Shu ...... p.42 (7C-5) Wang, Tengfei ...... p.32 (2A-4) Takahara, Atsushi ...... p.36 (2K-1) Wang, Xiaohang ...... p.32 (2A-4) Takahashi, Atsushi ...... p.42 (7C-4) Wang, Xuan ...... p.45 (9B-2) Takashima, Yasuhiro ...... p.33 (3S-3) Wang, Yan ...... p.39 (5B-3) Takayasu, Motohiro ...... p.30 (1S-21) Wang, Yanzhi ...... p.31 (1B-1) Take, Yasuhiro ...... p.30 (1S-23) Wang, Yanzhi ...... p.34 (3C-1) Take, Yasuhiro ...... p.30 (1S-24) Wang, Yi ...... p.36 (4A-4) Takizawa, Keitaro ...... p.35(SRF-10) Wang, Yi ...... p.37 (4A-5) Tamai, Takanori ...... p.38 (5S-2) Wang, Ying ...... p.32 (2A-1) Tan, Cheng ...... p.42 (7B-2) Wang, Ying-Chih ...... p.38 (5B-1) Tan, Sheldon X.-D...... p.37 (4B-2) Wang, Yu ...... p.31 (1C-2) Tan, Sheldon X.-D...... p.43 (8B-2) Wang, Yu ...... p.33 (2C-2) Tanabe, Yasuki ...... p.38 (5S-2) Wang, Yu ...... p.39 (5C-3) Tanaka, Hiroyuki ...... p.39 (6S-1) Wang, Zhe ...... p.45 (9B-2) Tanaka, Satoshi ...... p.42 (7C-4) Wang, Zhehui ...... p.45 (9B-2) Tang, Sanyuan ...... p.42 (7B-5) Wang, Zhifei ...... p.45 (9B-2) Tang, Tianqi ...... p.31 (1C-2) Wang, Zhiying ...... p.31 (1A-2) Taniguchi, Ittetsu ...... p.35 (3C-4) Wang, Zhiyuan ...... p.44 (8C-1) Tasi, Kuan-Chun ...... p.45 (9B-4) Watanabe, Takahiro ...... p.31 (1A-4) Tawada, Masashi ...... p.39 (6A-2) Watanabe, Takahiro ...... p.37 (4C-5) Teman, Adam ...... p.31 (1B-2) Watanabe, Yoshiharu ...... p.43 (8S-3) Tharayil Narayanan, Aravind ...... p.30 (1S-19) Wei, Lingxiao ...... p.45 (9C-4) Thonnart, Yvain ...... p.32 (2A-3) Wei, Qi ...... p.34 (3A-2) Tian, Haitong ...... p.33 (3S-1) Wei, Qingsong ...... p.38 (5A-4) Togawa, Nozomu ...... p.39 (6A-2) Wei, Shaojun ...... p.31 (1A-1) Tristl, Markus ...... p.38 (5B-2) Wei, Shaojun ...... p.44 (9A-2) Tsai, Chung-Hao ...... p.37 (4B-5) Wen, Wan-Yu ...... p.35(SRF-19) Tsao, Jean ...... p.41 (7A-3) Wille, Robert ...... p.33 (2B-2) Tsay, Ren-Song ...... p.41 (7A-2) Wille, Robert ...... p.33 (2B-3) Tsay, Ren-Song ...... p.44 (9A-1) Williamson, James ...... p.32 (2S-3) Tseng, Kai-Han ...... p.37 (4C-1) Wolz, Udo ...... p.29 (1K-1) Tseng, Pei-Ling ...... p.41 (7S-2) Wong, H.-S. P...... p.41 (7S-4) Tseng, Yu-Hsiang ...... p.32 (2S-2) Wong, H.-S. Philip ...... p.42 (7C-1) Tsubaki, Keishi ...... p.30 (1S-16) Wong, Martin D. F...... p.33 (3S-1) Tsunoda, Koji ...... p.29 (1S-4) Wong, Martin D.F...... p.42 (7C-1)

54 Wong, Martin D.F...... p.42 (7C-3) Ye, Yaoyao ...... p.45 (9B-2) Wu, Chao-Chieh ...... p.30 (1S-12) Ye, Zuochang ...... p.39 (5B-3) Wu, Hong-Chang ...... p.41 (7A-3) Yee, Kevin ...... p.44 (9S-1) Wu, Hsin-I ...... p.41 (7A-2) Yi,He ...... p.42 (7C-1) Wu,Wei ...... p.40 (6C-4) Yin, Shihui ...... p.38 (5B-1) Wu, Xiaowen ...... p.45 (9B-2) Yin, Shouyi ...... p.31 (1A-1) Wu, Yu-Wei ...... p.33 (2C-4) Yin, Shouyi ...... p.44 (9A-2) Yokoyama, Yoko ...... p.42 (7C-4) X Yonezawa, Shin ...... p.30 (1S-21) Yoshida, Keiji ...... p.30 (1S-18) Xia, Lixue ...... p.33 (2C-2) Yoshimoto, Masahiko ...... p.29 (1S-4) Xiao, Zigang ...... p.33 (3S-1) Yoshimoto, Masahiko ...... p.29 (1S-8) Xiao, Zigang ...... p.42 (7C-1) Yoshimoto, Shusuke ...... p.29 (1S-4) Xie, Mimi ...... p.36 (4A-1) Youssef, Ahmed ...... p.42 (7B-4) Xie, Yuan ...... p.32 (1C-3) Yu, Bei ...... p.36 (4S-1) Xie, Yuan ...... p.33 (2B-1) Yu, Bei ...... p.40 (6C-2) Xie, Yuan ...... p.45 (9B-1) Yu, Chao-Kai ...... p.45 (9B-3) Xin, Jingmin ...... p.40 (6C-1) Yu, Hao ...... p.30 (1S-14) Xu, Cong ...... p.32 (1C-3) Yu, Jiang ...... p.30 (1S-11) Xu, Haifeng ...... p.38 (5A-1) Yu, Qihang ...... p.29 (1S-9) Xu, Jiang ...... p.45 (9B-2) Yu, Qihang ...... p.29 (1S-10) Xu, Qiang ...... p.44 (8C-1) Yu, Shimeng ...... p.31 (1C-2) Xu, Qiang ...... p.45 (9C-4) Yuan, Feng ...... p.45 (9C-4) Xue, Chun Jason ...... p.39 (6A-3) Xue, Yuan ...... p.39 (6A-3) Z Y Zeng, Haibo ...... p.42 (7B-4) Yamada, Takashi ...... p.43 (8S-3) Zeng, Lian ...... p.31 (1A-4) Yamamoto, Dai ...... p.29 (1S-3) Zeng, Xiaoyang ...... p.33 (2C-3) Yamashita, Ken ...... p.29 (1S-8) Zeng, Xuan ...... p.36 (4S-1) Yamazaki, Iwao ...... p.39 (6S-1) Zeng, Xuan ...... p.39 (5B-4) Yan, Changhao ...... p.42 (7C-2) Zeng, Xuan ...... p.42 (7C-2) Yan, Guihai ...... p.32 (2A-1) Zhang, Chao ...... p.31 (1C-1) Yan, Mei ...... p.30 (1S-14) Zhang, Hongbo ...... p.33 (3S-1) Yanagida, Koji ...... p.29 (1S-4) Zhang, Hongbo ...... p.42 (7C-1) Yanagisawa, Masao ...... p.39 (6A-2) Zhang, Jiaxing ...... p.42 (7B-5) Yang, Chengmo ...... p.36 (4A-1) Zhang, Jie ...... p.45 (9C-4) Yang, Chengmo ...... p.39 (6A-3) Zhang, Jili ...... p.30 (1S-20) Yang, Chengmo ...... p.40 (6A-4) Zhang, Ran ...... p.37 (4C-5) Yang, Chengmo ...... p.42 (7B-1) Zhang, Weiqi ...... p.31 (1C-1) Yang, Dongsheng ...... p.29 (1S-1) Zhang, Xi ...... p.43 (8A-3) Yang, Fan ...... p.39 (5B-4) Zhang, Xin ...... p.30 (1S-11) Yang, Huazhong ...... p.31 (1C-2) Zhang, Zhaobo ...... p.36 (4S-2) Yang, Huazhong ...... p.33 (2B-1) Zhang, Zhaobo ...... p.44 (8C-1) Yang, Huazhong ...... p.33 (2C-2) Zhao, Bin ...... p.33 (2C-2) Yang, Huazhong ...... p.34 (3A-2) Zhao, Junfeng ...... p.45 (9B-1) Yang, Huazhong ...... p.39 (5C-3) Zhao, Kai Da ...... p.45 (9C-3) Yang, Jianlei ...... p.45 (9A-4) Zhao, Kang ...... p.45 (9A-4) Yang, Mei ...... p.32 (2A-4) Zhao, Mengying ...... p.39 (6A-3) Yang, Peng ...... p.45 (9B-2) Zhao, Mengying ...... p.35(SRF-11) Yang, Wei ...... p.45 (9B-1) Zhao, Qingling ...... p.42 (7B-4) Yang, Xinghua ...... p.34 (3A-2) Zhao, Weisheng ...... p.31 (1C-1) Yang, Yunfeng ...... p.42 (7C-2) Zheng, Nanning ...... p.29 (1S-9) Ye, Fangming ...... p.36 (4S-2) Zheng, Nanning ...... p.29 (1S-10)

55 Zheng, Nanning ...... p.40 (6C-1) Zhu, Li ...... p.37 (4C-5) Zheng, Yang ...... p.32 (1C-3) Zhu, Xiao ...... p.36 (4A-2) Zhong, Kan ...... p.36 (4A-2) Zhu, Xiao ...... p.35(SRF-22) Zhou, Dian ...... p.42 (7C-2) Zhu, Yan ...... p.43 (8B-2) Zhou, Hai ...... p.40 (6C-3) Zhu, Ziyuan ...... p.43 (8A-1) Zhou, Hai ...... p.42 (7C-2) Zou, Qiaosha ...... p.45 (9B-1) Zhou, Zimeng ...... p.38 (5A-2)