A course on field programmable logic
Citation for published version (APA): van der Eijnden, P. M. C. M. (1985). A course on field programmable logic. (EUT report. E, Fac. of Electrical Engineering; Vol. 85-E-148). Eindhoven University of Technology.
Document status and date: Published: 01/01/1985
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Download date: 25. Sep. 2021 A Course on Field Programmable Logic
By P.M.C.M. van den Eijnden
EUT Report 85-E-148 ISBN 90-6144-148-X ISSN 0167-9708 April 1985 Eindhoven University of Technology Research Reports EINDHOVEN UNIVERSITY OF TECHNOLOGY
Department of Electrical Engineering
Eindhoven The Netherlands
A COI}RSE ON FIELD PROGRAMr~ABLE LOGIC
by
P.M.C.M. van den Eijnden
EUT Report 85-E-148 ISBN 90-6144-148-X ISSN 0167-9708 Coden: TEUEDE
Eindhoven Apri 1 1985 i i
First printing January 1983. Second printing April 1985. Third printing July 1985.
CIP-GEGEVENS KONINKLIJKE BIBLIOTHEEK, DEN HAAG Eijnden, P.M.C.M. van den A course on field programmable logic / by P.M.C.t'l. van den Eijnden. - Eindhoven: University of Technology. - Fig. - (Eindhoven University of Technology research reports / Department of Electrical Engineering, ISSN 0167-9708; 85-E-148) r4et lit. opg., reg. ISBN 90-6144-148-X SISO 664.2 UDC 681.325.65.02 UGI 650 Trefw.: schakeltechniek/ programmeerbare logicabouwstenen. iii
Acknowledgements In these course notes logic diagrams of available programmable devices are used in order to clarify the structures of these devices. For the diagrams of IFL devices the "Signetics Integrated Fuse Logic" handbook (Ref. 1) of Phil ips has been used. The diagrams of the PAL's are from the "PAL Handbook" (Ref. 2) of Monol ithic Memories Inc. (MMI). Signetics Corporation, 811 East Arques Avenue, P.O. Box 409, Sunnyvale, CA 94086
Monolithic Memories, 2175 Mission College Blvd., Santa Clara, CA 95050 iv
ABSTRACT
This report gives a survey of programmable logic components that can be used to real ize both combin,atlonal and sequential logic circuits. A general structure for these components is determined starting with boolean equations and state diagrams respectively. The considerations with respect to optimization and decomposition of a'circuit, that play an important role when designs are made with these components are discussed. To complete the survey several commercially available products are passed in review.
Eijnden, P.M.C.M. van den A COURSE ON FIELD PROGRAMMABLE LOGIC. Department of Electrical Engineering, Eindhoven University of Technology (Netherlands), 1985. EUT Report 85-E-148
Address of the author: ir. P.M.C.M. van den Eijnden, Digital Systems Group, Department of Electrical Engineering, Eindhoven University of Technology, P.O. Box 513, 5600 MB EINDHOVEN, The Netherlands v
CONTENTS
1. INTRODUCTION 1
2. COMBINATIONAL LOGIC 3
3. REALIZATION OF SWITCHING FUNCTIONS 5
3.1 Singular standard gates 5 3.2 Hypothetical programmable array for logic functions 5 3.3 Programmable arrays versus standard parts 21 3.4 Programming the array 23
4. AVAILABLE PROGRAMMABLE ARRAYS 34
4. 1 (P) ROM 34 4.2 (F) PLA 36 4.3 (F)PGA 46 4.4 PAL (HAL) 51
5. DESIGN PROBLEMS USING PROGRAMMABLE ARRAYS 65
5.1 Product term expansion 65 5.2 Output expansion 73 5.3 Input expansion 75
6. SEQUENTIAL LOGIC 81
6.1 General model for sequential circuits 81 6.2 Memory elements 82 6.3 Synchronous and asynchronous sequential circuits 84 6.4 Representation of synchronous sequential systems 86
7. REALIZATION OF A SYNCHRONOUS CIRCUIT 91
7.1 Singular gates 91 7.2 Progammable arrays 92 7.3 Hypothetical programmable array with state register 97
8. AVAILABLE PROGRAMMABLE SEQUENCERS 99
8.1 (F)PLS 99 8.2 PAL (HAL) III
REFERENCES 119 1
1. INTRODUCTION
Until now digital circuits for small production volumes could economically be realized only using so called standard parts: small scale and medium scale integration (SSI/MSI). At the moment however new components are available which may be regarded as a replacement of the parts mentioned above. They all have got a matrix structure and are known as:
Programmable Arrays.
Because digital circuitry can be divided into two major categories:
Combinational Sequential the total number of arrays may also be grouped according to this classification. Therefore these course notes have also been divided in two major parts. The first part (chapter 1 - 5) deals with combinational logic. the second part (chapter 6 - 9) with sequential logic. However before going into detail about the components (arrays) we will first have to study the reasons for using them and the logical reasoning that is behind their structure. Hence part one starts with a short overview of combinational logic. From this a general array structure is determined. Knowing this general structure available components will be studied. The second part has been arranged in the same way. In this part we start with a short overview of sequential logic from which a general sequencer structure is determined. Then the available sequencers are studied. 2 3
2. COMBINATIONAL LOGIC
From switching theory it is known that any sWitching function of n variables f(xi ,x2' •••• ,xn) may be expressed as a sum of products, where in each product every input variable appears in either its true or complemented form.
Example: f (xl ,x2,x3,x4) xlx2 x 3x 4 + xlx2x3x4 +
xlx2 x 3x 4 + --xlx2 x 3x 4 +
xlx2 x 3x 4 + xlx2 x 3x 4
This form is called: standard normal form, full disj unctive normal form or sum of minterms, and is generally expressed as:
mt = minterm; 81 = 0, 1
It is also known, that because of the duality principle, any switching function of n variables f(xi ,x2' •••• ,xn) may be expressed as a product of sums, where in each sum every input variable appears in either its true or complemented form.
Example:
The function of the previous example may also be written as:
f(xI,X2,X3,X4) (xl + x2 + x3 + x4) •
(xl + x2 + x3 + x4) •
(xl + x2 + x3 + x4)·
(xl + x2 + x3 + x4)·
(xl + x2 + x3 + x4) •
(xl + x2 + x3 + x4) •
(xl + x2 + x3 + x4) •
(xl + x2 + x3 + x4)·
(xl + x2 + x3 + x4)·
(xl + x2 + x3 + x4) 4
This form is known as: stan,dard product of sums, full conjunctive normal form or product of maxterms, aQd is generally written as:
Mi = Maxterm; Gi Z 0, !
Neither of these standard forms is minimal. That is to say the number of product terms or sum terms as well as the nU!q}).e.r Q-f variables contained in these product terms or sum terms may be reduced. The mathematical rules according to which thi~ reduction may be accomplished are given by Boolean alg~b~~. Applying these rules to the example given above leads tQ:
or 5
3. REALIZATION OF SWITCHING FUNCTIONS
3.1 Singular standard gates
It may be stated that any switching function can be implemented using standard (TTL) AND, OR and NOT gates. The function of our example may be realized as:
f
(a)
f
(b)
Figure 3.1 Realization of example function (a) sum of products (b) product of sums
3.2 Hypothetical programmable array for logic functions
3.2.1 General Considerations
Considering the statement of paragraph 3.1, we may say it really would be practical to have one standard part only which comprises a number of the three types of gates in such a way that any switching function can be realized with this device by some wiring. Such a standard part might be realized in three stages. Stage 1 consists of a set of inverters (NOT) to generate the complemented form of input variables. The next stsge uses the output sigma1s of the first stage. This stage consists of a number of AND gates. These NOT-AND combinations generate the product terms. The third stage consists of an OR gate using the product terms and generating the desired function. The signals 6 from one stage may be used as input signals for the next stagE!' The signals are applied to the next stage by means of switches. When a switch is closed a term is appl ied to the next stagE!. when it is open no signal is applied. The structure is shown in figure 3.2. The switches allow for selective (programmable) connections. With this device the example function may be realized as shown in figure 3.3
11 .l{:)')o-t-r-----t-r----t-r--- 12 4>~+-+-t---+-H'-r---+++-r---
In L.{>::»+t-+t--f-1r-++H--t-T---++++--+t-- I I 'tY-- ,\1' l'\I"~ -_ 1\' y -- F
Figure 3.2 General structure of a device which can realize any logical function 7
l{) 1- "- /' L v" L i'- /'
In l{)
,\ ,,, ,\ ,I, ,\,1 ,\ II" -- --
Xl~X3 X3 X4 -- I f
Figure 3.3 The example function realized with the general device 8
If more than one function has to be realized simultanously, the previous structure can easily be expanded to more outputs. Figure 3.4 shows the general device structure for a multiple output configuration.
l{>- 4>
In It I .\,\(- ,\ I' , ,\ " ,\ ,\ 1\ , ''/'(. I '\I\I~------
-- --. - - , ,I - , fm
Figure 3.4 General device structure for a multiple output configuration 9
So far a programmable (switch selectable) device has been studied in which three stages can be recognized, viz:
1. Input stage 2. Programmable AND gates (switches + AND gates) 3. Programmable OR gates (switches + OR gates)
3.2.2. Realization of the programmable array
The problem we are now dealing with is: I1How can this switch structure be realized in One part only'l?
3.2.2.1 The programmable AND gates
Let us first consider the AND part of the total scheme. An AND function of two variables can easily be built by means of a simple diode network as shown in figure 3.5.
+
P!roduct term)
Figure 3.5 Two input AND function with diodes
Expansion for more variables can be done by adding more diodes, see figure 3.6 The (programmable) switches may be implemented by means of fuses which can be blown. Figure 3.7 shows this idea. 10
+
12
In
P(roduct term)
P=lr 12.13 ·In
Figure 3.6 n-input AND function with diodes
+
12
In
fuse P
Figure 3.7 Programmable n-input AND gate 1 1
For example product term P = is now realized as follows:
+
12 13-kJ-
Figure 3.8 Implementation of a product term 12
Repetition of the structure of figure 3.7 leads to a programmable AND array, see figure 3.9.
+ + + +
In---4~--+-~----r-~---+------~--~
Figure 3.9 Programmable AND array 13
For convenience of drawing the conventions for arrays shown in figure 3.10 could be used. With these conventions a very simple drawing for the programmable AND array results (see figure 3.11).
replace
with
and
Figure 3.10 Drawing conventions for diode crossings
+ + + +
[ [ ------[
I I I I I I I In
Figure 3.11 The programmable AND array drawn according to new conventions 14
3.2.2.2 Input stage (inverters)
The input stage should consist of inverting and non inverting lines. Inverters may simply be added to the inputs. This leads to the general structure of figure 3.12. All possible input combinations per input variable on a product line are summarized in figure 3.13. + + + + ~JJ ------0 .4) I{;
,I , , , , I I In It>
Figure 3.12 Programmable AND array with inverters
Figure 3.13 Input combinations per input variable on A product line 15
Any combination of product terms can be realized with this AND array. For example the two product terms of the example function:
are implemented like shown in figure 3.14. Note that all fuses of unused P-terms (product terms) are left intact. This means that the output of these P-terms is always "Q", because both xi and it appear 1n these P-terms (compare figure 3.13).
+ + + + 1 1 ------x, 4> lr> 4> lr> I I I I I I I I 4> P, P2 P3 Pp
P,=X,X2 X3; P2=X3~; P3=··· .=Pp=O
Figure 3.14 Realization of two product terms with the programmable AND array 16
3.2.2.3 The programmable OR gates
The same procedure used for AND gates is applicable to the OR gates. An OR function of two variables can be realized by means of a simple diode network as shown in figure 3.15.
~4 O(r term)
Figure 3.15 Two input OR function with diodes
Expanding this structure in two dimensions leads to more input variables and more output functions respectively. Again fuses are connected in series with the diodes to make a programmable OR array (see figure 3.16). Using drawing conventions indicated in figure 3.17 greatly simplifies the drawing of the OR array as may be seen from figure 3.18. 1 7
o o o o
A2--~--~~--~~---+------~---r
Ap--~---+--~--+-~--~------4----~
°1
Figure 3.16 Programmable OR array 18
replace .,," ---+
and .,," ---+
Figure 3.17 Drawing conventions for diode crossings
o 0 0 o J [ -- - - ~- - - ~ -
I
I I I I I I
Figure 3.18 The programmable OR array drawn according to new conventions 19
3.2.2.4 The complete array
The AND- and OR-array may be put together now by assigning:
Both arrays cannot be directly connected. Buffering is required. because of the load of the OR-array on the AND-array. Buffering of the outputs of the OR-array is also required because of the load of other parts of a total circuit on this array. This buffering leads to the following structure (with all fuses intact):
+ + + + 1 1 1 ------
4) Y? I I I I I I I In l-£) P. ~buffers I \ /\ /\/ A- I 7· o 0, o ~ °2 I I I I I I I I o---I Om
Figure 3.20 The complete array 20
The example function
might be implemented as shown 1n figure 3.21.
+ + + + 0[0 ------4> 4> 4> 4> 1 I I I I I I I In 4> V\/'/ o1--1 O,=f o1--1 I °2 I I I I I I I o -l Om
Figure 3.21 Example function realized 1n the complete array 21
3.3 Programmable arrays versus standard parts
Now that a programmable array has been developed, let us look at the sdvantages such an array has over the well known standard parts/singular gates (eg. 7400 series). Standard parts have a few advantages. One of these advantages is that they are very cheap because of large production volumes. A second advantage is that a circuit may be realized very fast. Not only because one can buy standard parts almost anywhere, but particularly because a large variety of components is available (AND, OR, NOT, NAND, NOR, EX-OR etc). However, this last point may also be seen as a disadvantage. The more components there are the more random a choice of components is done .. Often you see a deSigner turn Over the leaves of his databook chOOSing randomly gates that best fit to a certain part of his circuit (random logic). This design method leads to non-structured deSigns or realizations. Testability and reliability of non-structured designed circuits are often poor. Circuits require many interconnecting Wires, due to the fact that only a few singular gates are available within one package. Each wire is a possible error source. If a non structured circuit with many interconnecting wires is malfunctioning testing may be a hard job. This extensive wiring has another consequence. Circuits are generally realized using printed circuit boards (PCB's). Design of these PCB's is expensive, because many inter connections require a complex PCB layout in more layers. A great deal of expensive PCB-area is lost to the wiring. Summarizing the advantages and disadvantages of standard parts leads to the following table:
advantage: cheap almost anywhere for sale fast circuit realization
ad van tage/ disadvantage: large variety of components
disadvantage: non-structured design many packages per circuit poor testability poor reliability expensive and comlex PCB's
Table 3.1 Advantages and disadvantages of standard parts 22
All the advantages mentioned for standard parts apply to programmable arrays as well. However, for programmable arrays the disadvantages may be strongly reduced. Designs may be well structured using programmable arrays because gates are not randomly chosen. PCB's are less complex and expensive. This is due to the fact that wiring is brought onto the chip. A reduction of the chip count of 1:6 - 1:20 is possible. Pin assignment for input variables and output functions may be done to make the best fit to the PCB layout. The reliability of a circuit increases because the number of interconnecting wires becomes much less. A small disadvantage of programmable arrays is the fact that special programming equipment is needed to blow the fuses of the array. This programming is discussed in the next paragrsph. 23
3.4 Programming the array
3.4.1 Programmer
As was pOinted out in the previous paragraphs programming of an array means "blowing fuses according to a given fuse pattern". To program our logic array we need special equipment: "a programmer" which accepts as its input the designed fuse pattern (for the logical function) and generates programming pulses to blow the fuses in the logic array. Figure 3.22 illustrates the programmer concept.
DESIRED DEVICE LOGIC FUSE TO BE PROGRAMMER PATTERN PROGRAMMED
programmlng programming intor ...,ation signals
Figure 3.22 The Logic Programmer concept
This leaves us two problems, viz:
1. How can the programmer be loaded with the desired fuse pattern? 2. In what format should the fuse pattern be presented to the programmer?
3.4.2 Editor and format
The first problem hss been solved by building the pro grammer using a microprocessor and memory_ The microprocessor program accepts input from a keyboard, terminal or host computer. This program is generally called an: "editor". One way to enter the programming data is manually by typing a datatable in the form of one's and zero's. A· one might for example mean: "blow fuse" and a zero: "don't blow fuse". A program table would thus look like the one shown in figure 3.23. In this table two example functions have already been entered, viz:
fl = xl x 2 x 3 + xl x 4 £2 = xl x 3 + x2 x 4 24
AND-ARRAY OR-ARRAY
1 f . . . I f I f I f I I F ... F F F n n 3 3 2 Z I I 0 0 m 2 I 0
Po I I I I 0 I 0 I 0 I 0 0 1 0 PI 1 1 0 1 I I I I 0 1 0 0 I 0 Pz 1 I I I 0 1 I I I 0 0 0 0 I P3 1 1 I 0 I I 0 I [ I 0 0 0 I P4 0 0 0 0 0 0 0 0 a a 0 0 0 0,
Pp 0 0 0 0 0 0 0 0 0 0 0 0 a 0
u u x it x it x it x it U U f f 4 4 3 3 2 2 I [ 2 I
Figure 3.23 Program table (U denotes unused)
Each entry in this table corresponds to a specific fuse in the complete array. A row in the AND-array table represents a product term (P). A "0" in a row in the OR-array table selects the product term to be used in a specific function. So FO contains Po and PI. and F[ contains P2 and P3 in the given example. Note that the fuses of unused inputs and product terms are left intact (0). so design changes may be done if necesssry. Filling out a table with one's and zero's is a boring task and is prone to errors. This table of course must be present in the programmer to be able to blow the fuses. However we would like to have another coding scheme to tell the programmer what to do. A built in translation program can then translate this "higher level coding scheme" into a table containing one's and zero"s only.
3.4.3 Higher level coding scheme
Let us now look for a more sophisticated coding scheme. For one input varisble four different combinations. indicating fuses blown or unblown. might occur. These are summarized in figure 3.24 together with their one/zero codes from our first program table. 25
'~- :: 00 P=I·I =0 '~ = 01 P=I '~- =10 P=I
:: 1 1
P=don'! care
Figure 3.24 The possible input combinations per input variable on a product line together with their one/zero coding
Interpreting the codes by means of this figure leads to the following shorthand notation to code the different fuse patterns:
00 = both fuses unblown. So the input variable is inactive. Let us denote this with an "0". 01 = the input variable is present in the product term in its true form. In other words the variable is active high. Let us denote this with an "H". 10 = low active state of input variable. So let us assign the code "L" to this state. 11 = don't care for the input variable. Both fuses are blown, so the variable is not present in the product term. This will be indicated with a "-"
Figure 3.25 summarizes this short hand coding. 26
P=don't care
Figure 3.25 The possible combinations per input variable on a product line together with the short hand coding
For the output functions two possible situations may occur. A fuse is to be blown or not. Figure 3.26 illustrates the coding we have used in our first programming table.
Figure 3.26 The possible combinations per product term on an output line together with their one/zero coding 27
An unblown fuse indicates that the product term is present in the output function. In other words the product term is active for that funtion. We will code this with an "A" (Active). A blown fuse indicates that that product term is not present in that specific function (inactive). This will be indicated by means of a "." (dot). Figure 3.27 summarizes this coding for the OR-array.
•
Figure 3.27 The possible combinations per product term on an output line together with the short hand coding
With this short hand coding we have created the program table shown in figure 3.28. Again the same two example functions are already entered in this table.
I . . . I I I I F ... F F F n 3 2 1 0 m 2 1 0
Po - - H H H A A . A PI - H - - H A A . A P2 - - H - L A A A . P3 - L - H - A A A . P4 0 0 0 0 0 A A A A
Pp 0 0 0 0 0 A A A A
U x x x x U U f f 4 3 2 I 2 1 .-
Figure 3.28 Program table with new conventions (U denotes unused) 28
3.4.4 Boolean assembler
We now might go one step further and not even enter a table at all. Why not installing a translator program that accepts Boolean expressions as its input and translates them to a table consisting of one's and zero's. Let us call this translator program "Boolean translator". The three programs are linked as indicated in figure 3.29. MANUAL INPUT FROM KEYBOARD, TERMINAL OR HOST COMPUTER IN FORM OF BOOLEAN EXPRESSIONS
EDITOR
FILE WITH BOOLEAN EXPRESSIONS
BOOLEAN ASSEMBLER
PROGRAM TABLE / < "1", "0") 1
PROGRAMMER
PROGRAMMED / DEVICE / Figure 3.29 Different programs required in the logic programmer 29
We are now left with a new problem:
The Boolean assembler only knows physical pin names, eg 10' I l' FO' Fl etc. Would it be posible to use symbolic (user defined) names, eg. Xl' x2' f etc.
Adding more intelligence to the assembler enables us to use symbolic names. Now the input for the assembler consists of different parts, viz:
1. COMMENT part
This is a number of lines in which the user may describe for example what the functions of the circuit are.
2. INPUT PIN ASSIGNMENT part
In this part user defined input names are assigned to physical pin names.
3. OUTPU.T PIN ASSIGNMENT part
In this part user defined function names are assigned to output pins.
4. BOOLEAN EXPRESSION part
In this part of the input the Boolean expressions are given as statements.
The structure of such a description for the two example functions might thus look like shown on the next page. 30
BEGIN
COMMENT
This is an example to indicate a possible circuit description which might be used as input for a Boolean assembler
INPUT PIN ASSIGNMENT
10 := xl 11 : - x2 12 := x3 13 : = x4 14 : = unused
In := unused
OUTPUT PIN ASSIGNMENT
FO :- fl Fl := f2 F2 :- unused
Fm := unused
BOOLEAN EXPRESSIONS
END 31
Now we have got a nice solution of the array programming problem. However there are still two problems left to solve:
1. Checking for typing errors or even worse design errors 2. Testing of the programmed device to verify whether it functions correct or not
3.4.5 Simulation and test
Checking for typing errors may partly be taken care of by the editor. For example suppose no other operators as +, := and. are allowed. A simple syntax check might look for undefined operators. However an erroneously interchanging of xl and x2 for example, can not be discovered by the syntax checker. The result is that a complete different circuit has been defined.
3.4.5.1 Simulation
A simulation program is required to detect this kind of errors. This program uses two kinds of input, viz:
1. Boolean expressions after they have been translated 2. Testpatterns (input/output patterns)
The first of these two is the output generated by the Boolean assembler. The second input part must be provided for by the user. In a testpattern a user defines an input combination together with the desired output pattern. Suppose for example that the following two functions are entered into the system:
fl = xl x 2 x 3 + xlx4
f2 m xlx3 + x2x4
Possible testpatterns for these two functions might look like:
x x x x f f 4 3 2 1 2 1
0 0 0 0 0 0 testpattern I 1 0 0 1 0 1 test pattern 2 0 1 0 0 I 0 testpattern 3
The simulator uses the given Boolean expressions and input patterns and calculates the resulting values for the output functions. The resulting output patterns are compared to those given by the user in the testpatterns. If they match simulation continues else errors are listed. From the output of the simulator a user may determine whether his circuit is correctly functioning or not. 32
For example during the problem definition phase a user has got a truth table. From this table he determined a set of minimal Boolean expressions. He thinks these expressions are correct. Suppose no typing errors are made. The next step is to present the truth table from the problem definition stage to the simulator. As a result the simulator detects output patterns that are not matching the original truth table and lists the errors. The user may now go back to the original truth table and try to find the correct Boolean expressions. The simulator may thus be run on the program table before the actual programming is done. Possible typing errors or design errors may be discovered prior to programming the device.
3.4.5.2 Testing
After the device has been programmed one would like to test the programmed device to verify whether it is a good device or not. So another program is required with which we can test a programmed device. This test program uses two kinds of input, viz:
1. The programmed device 2. Test pst terns
The testpatterns may be the same as those used by the simulator. The test program applies the given input patterns to the programmed device. The output patterns that the test program reads from the programmed array are compared with those given in the testpatterns. If both are equal the device is correctly functioning, else errors will be listed. Linking it all together we get the following overall picture: 33
MANUAL INPUT FROM KEYBOARD, TERMINAL OR HOST COMPUTER IN FORM OF BOOLEAN EXPRESSIONS
. EDITOR
FILE WITH BOOLEAN EXPRESS IONS
BOOLEAN ASSEMBLER
PROGRAM TABLE (111"1"0" ) er o .... s
CORRECT PROGRAM TABLE
er .... ors
GOOD DEVICE
Figure 3.30 Overview of software needed in the Logic Programmer 34
4. AVAILABLE PROGRAMMABLE ARRAYS
In the previoua chapter we have developed the general structure for a programmable array to implement combinational logic. In practice four major types of programmable arrays are available, resulting from different design strategies or applications. These are:
(P) ROM (Programmable) Read Only Memory (F)PLA (Field) Programmable Logic Array (F)PGA (Field) Programmable Gate Array PAL / HAL Programmable Array Logic / Hard Array Logic
These components will now be discussed to see where they are based on and what applications they are best suited for.
4.1 (P)ROM
A (P)ROM is a memory device in which the selection of the words is implemented, using all minterms of a given number of input variables. The minterms are realized in the AND-field. The AND-array is therefore fixed. The minterms are connected to a programmable OR-array. In case of a ROM this OR-array is programmed by the manufacturer according to a pattern defined by the user. Programming is done in that case during production (mask programming). A PROM may be programmed by the user (in the field) by blowing fuses. The structure of a PROM is given in figure 4.1- So one or more functions may be realized in their standard normal form by means of a PROM. As we know the standard normal form is not optimal. So because of redundancy a lot of chip area is lost when realizing switching functions with PROM's. Only switching functions where no real reduction by combination of minterms is possible (EX-OR like functions) are optimally realized using PROM's. Applications of PROM's are thus limited to:
Memory EX-OR like functions
(P)ROM's are offered by many manufacturers, ego Intel, Motoro1s, Texas Instruments, Signetics, Monolithic Memories Inc., National Semiconductors etc. PROM programming is usually done using a microcomputer development system expanded with s PROM programming module. A program developed with the system is loaded into Random Access Memory (RAM) and then copied into PROM. 35
+ + + + + + + + + i 00 r' [ 1 Lc 12 l£) fixe d 4> It \/\/\/\/\/\/\/\/ mo m7 m, o [>-,°1 ol---l t>-, Oz 1 I I I I I I I o ~ Om
Figure 4.1 Logic diagram of a PROM 36
4.2 (F)PLA
The design strategy for (Field) Programmable Logic Arrays is exactly the same we have seen in chapter 2. The AND- and OR array are both programmable. PLA's are programmed during production by the manufacturer according to a pattern defined by the user (mask programming). FPLA 's may be programmed by the user (in the field). There are several manufacturers of FPLA 's. The leading ones are: Signetics, Texas Instruments, Fairchild and National Semiconductor. Their FPLA's only differ in the number of input and output pins or product terms. For example Signetics/Philips offers two FPLA's:
82S100 / 82S101 82S152 / 82S153
4.2.1 82S100 / 82S101
4.2.1.1 Logic diagram
The 82S 100/82S 101 is a 28-pins device. There are only a few minor differences between the hypothetical array of chapter two and these devices as may be seen from figure 4.2 (next page) which shows the logic diagram of the 82S100/82S101. Note that in this logic diagram though all fuses are originally intact no dots are indicated. This enables the user to use this logic diagram as a programming scheme. 37
, , ~, , ' , , _+' tl H-il'~ , '. B 'T .'; , fi1- -t:J:~~, ~~ ~1~ - - , , f'1- ~~ ~ - . . . " t ~ , " '"~ " [D-. "
" f'1-
'I '"~ - t- , " El- '. ~ ... e
'II r,;> ~
'II ~ , " ~ I t , 'I' r;;\- '" f;O\-J.
~... -',D-,,-----Ei" , I , , ... ~,~~, , I , o--+---GJ ~2 , o--+---GJ'l t . I ., It=f ,I r t c-' i~Ji D-+-@F., i' * , j-II , !I,"'+l!# I I!:j- h+,: ~~; ii' , I I' iI I I''I"I'! I I I I '111'1'"i I I ,I 'I I 1+ ,l,~ ~-t-:-J -j-I1' -c +-j tl i- r~~ di'l';D-t~ -l + +-i ~ ~'6 ! I I ! I, I . I Ii,' 'II"• I I I 'I'I I 'I'I'" I· I I' I ",'i 'II .. - i , 'I ,! I I I ' I ' !; i: i , :; l', 'I I'I I' I 'I: I I j!" I I I, ! " I,I -+ 1 • j j I" I I ' ' I I , 1 t r D, J I Fl. I I , I ~ ."., , , I 'I -~"--,--",. I I., I", , Ga7 j D -[>- GJ',
lLoe:..e 11-~"'S-"1 • 0'''01<5 "~EO <:O .....(:TIO ..
Figure 4.2 FPLA 82S100/82S101 Logic diagram 38
The first difference we note is the output configuration. The FPLA is provided with a programmable output stage. Output functions may be programmed independently active high or active low. This is done using an Exclusive-OR as indicated in figure 4. 3.
S_~) )>---F
(a) active high
S~) )~F
(b) active low
Figure 4.3 (a) active high programming of output (b) active low programming of output
As an extra feature the outputs may be tri-state (828100) or open collector (828101). The tri-state outputs are well suited to be used in bus organized systems. Open collector outputs may be connected in parallel (wired-OR). In this way the number of product terms msy be expanded (see paragraph 5.1.1). 8een from another point of view, a common signal line may be driven by several open collector outputs without further requirements (e.g. think of bus-request line in multiple processor applications). Another difference from the hypothetical array may be seen in the implementation of the FPLA (figure 4.4). In this figure we see that the non-inverted input lines are also buffered. This buffering reduces the load on previous circuits. The delay times for inverted and non-inverted inputs are now equal. Another difference is the absence of separate buffers between the AND- and OR-array. Buffering is now accomplished by means of the transistors of the OR-array. 39
."Ol>uCI "~I"" 1.()SI1f~1 AND ""n~,
"."v~: "
P" ____ PRODUG11ERMS
~
8 OUTPUT fll"ClIO,"S D--tt:-"" , I
SlI" ..... IR .. "'OSHIVE 011' GAllS, ~
Figure 4.4 Implementation of the FPLA 82S100/82S101
The example functions:
f1 = x1 x 2x 3 + x1 x 4
f2 x1x3 + x2 x 4 may be implemented (using the 82S100/82S101) as shown in figure 4.5 40
, . I, ,-• ± - C H S- -lH- +LLdi'l-L-'-'~-r'T'"C +'1 '! 'iT'" .' 1 '-1-I --__ Hf"+-. I· lH-' , H- ~j 1 n- t I : ; r"l-+-- t ._- - ~ . (11 1 '" --I- - - ~ -t- ) '1'."'I'---t-! T ~ 1 L L-I l + +- ______,_ ~+q_l l ;. ;,! 1 _ +_ '"~ , '0'~ ------fE tl~~Jr-h-- ~1~ s- - _ -+--T _i-t- - -rt- •• , - .. • .,,1 , ~ " 1 0- ~ " 1 I +-+ : • -t " ~ 'I [;;1.1 I ------!- •• ~ I ,I , ';;' r- - '" = , 'n [3- I I 'n n I I (i;J. i - , 'n -t i , , i , ", '"'~ I H- .. ,';;' 1 l- = I I 61)61 • 9 -- ? , 1 "'T I ' j '~ ! -1 I I 1 I It I , -0 -! I "'TI I I ! I I i I i II 1 II I I i I H-++ -, II r;'J..r!J.!J, "'~ Ii: ' ! Iii I r t: I! I:! ... -!-' :1_1. ' rut !'1J_'_ ! IT • L\I+(+_ II--D-±J 1 I . • - , I Lltl-ILH: ,I II i I I' I I I.. . '"i~ ," itT· TTl III~::II: i II : I II '-1 _ ____ " ~:II I " I :. I ,", . , -'_,. +.. t - ·t-·. -'-'-"-'.. 1._, l ..~ : ii' : . ' , +i-i~-:-;' , i• ~~! ' I'" 1 I ,I Iii ."-
• u,,,,,!!~,,"[lC<)"'UL1'tm
Figure 4.5 Realization of the example functions:
f1 = X1 X2 X3 + X1 X4
f2 X1 X3 + x2 x 4 using the FPLA 82S100/82S101 41
4.2.1.2 Program table
Programming specification for the FPLA 825100/825101 is in accordance with the high level coding we have seen in paragraph 3.4.3. 5ymbolic notations are used to indicate a certain fuse configuration. The coding conventions used for this FPLA are summarized in figure 4.6 In future (4th quarter 1983) it will be possible to specify the programming pattern for the FPLA in Boolean expressions which will be translated by a Boolean assembler. Figure 4.7 shows the program table used for the FPLA 825100/825101. In this table the two example functions:
f1 = x1 x 2x 3 + x1 x 4
f2 = x1 x 3 + xZ x 4 have been programmed.
"AND" ARRAY - (I)
STATE CODe STATE STATE STATE INACTIVE o DON'T CARE
"OR" ARRAY - (F)
PnSTAnn coo< Pn 8UTUS ",'" 'C~ A lNACTtYE •
EX-OR ARRAY-(F)
ACTIYI! LEVEL COo< ACTlVI! U!VO!L coo<
H .... H L
Figure 4.6 Coding conventions for the FPLA 825100/82S101 42
PROGRAM TABLE ENTRIES INPUT VARIABLE OUTPUTFUNCT.~IO~N~ ____~~O~U~T~P~U~T~A~C~T~IV~E~LE~V~E~L~-< Prod Term Prod Term Not Active Active 1m 1m Don t Care Present In ~p Present In Fp High Low H L - !daS~h~)_+-____ ~A ____-i ___ .~IP~e~'~'O~d~) __~ __~~H~ __~ ____~L ____~ NOTE r..IorE<: "'OTES
Enter H lor unused Inputs of used 1 Entr"·~ '''''l''P''''~h.nt ,)1 lJ"!~,,t p PRODUCT TERM' INPUT VARIABLE' - -~-- NO 1 1 1 1 1 1 ------5 , 3 2 1 0 9 8 7 6 5 4 3 2 1 0 0 - -- - I-tH i.., 1 -1101 -- I-t • I,A. - _ ~ _ L 2 - -- A • 3 - L. H 1.11 • 4 -- 5 6 7 8 9 10 11 12 13 14 15 16i 17 i 18i 19 20 , i 21 22 I 23 24 25 26 27 28 29 30 31 32 33 ·3' 35 36 37 38 39 40 41 42 43 44 45 46 47 Figure 4.7 Program table for the FPLA 82S100/82S101 with example functions entered. 43 4.2.2 82S152 / 82S153 The 825152/82S153 is another FPLA offered by Signetics. It is a 20 pins device. The 825152 has open collector outputs whereas the 82S 153 has tri-state outputs. Figure 4.8 shows the logic diagram. The programming options are equal to those of the FPLA 82S100/82S101 (figure 4.6). As may be seen in the logic diagram bidirectional I/O lines are now available giving more flexibility to the designer. The bidirectional I/O lines may be controlled independently by special product lines of the AND. array (Control Terms). This provides for the possibility to use these lines as input or output depending on Some input combination. Of course bidirectional I/O lines may be programmed to be fixed input or output lines. The designer then has a maximum of 17 input lines and 1 output line, or 8 input lines and 10 output lines. Multilevel networks and asynchronous sequential circuits (see chapter 6) may be realized without loosing input pins, because if a line is programmed as an output line, it is still available in the AND array part of the circuit. Figure 4.9 shows the program table for this device. Note that the influence of the control terms on the behaviour of the circuit may easily be determined from this table (product terms DO_ 9) • 44 'LOGIC TUil~S-PI Lcr)NI~tJl 1£f JIJI')1!I182126252. 231]217019'81'1615141311111098 }., 5 ~ J) 1 0 I),. ()~ 1)/ I>~ [)~O. 010] 0,00 • I " ~ i I -;..l I , " ~ , ., , ~. I " • m.l I " ~ 1 - @ ------r- " -- 1-- " 0- ~• " .. - " ~ ., I l , I " 1 I .. l , " , 1 " " " j " I , , JOOC , ~O I r--. T I " " ~ -ioil ~ " r--. -G " I 1 -ioil ~ " -GJ r--. 1 -f.'l i ~ .. I ~ 1-'1>- -G " I ! ~ , ~ ., I .~ " I ; I -R , 1-'1>- ~ " j I I , I I I I ~ , , , , , , , , I ~ I I 1: " Figure 4.8 Logic diagram of the FPLA 828152/82S153 45 PROGRAM TABLE ENTRIES: i j NOTES 1.8(1) 1. The FPlA IS shipped With all links Intact Thus a background 01 enlnes "., "., I correspondmg to stales 01 virgin links eXists in the lable. sho..... " BLANK "'""'" '. I for clan'Y '" , UO "13 I. i ,." ; 17 ,. i ,. ; - 20 ! 21 "23 2' ..25 27 28 2. 30 31 DO - DO TT 07 DO o. D4 03 02 01 DO PIN 8 7 3 2 1 I. 18117 ,. 15 I. 13 11 • • • " • Figure 4.9 Program table for the FPLA 82S 152/82S 153 46 4.3 (F)PGA Sometimes we are dealing with switching functions consisting of one product term only. A good example of this is a chip select signal in computer circuitry. In this case the use of an FPLA would not be economically. For this reason a special array has been designed which does not have the OR-field, and can perform single level AND logic functions. This array is called: (Field) Programmable Gate Array «F)PGA). The PGA again is the mask programmable device. FPGA's serve as universal logic elements and may be applied in: machine state decoders fault monitors code detectors peripheral selectors Signetics/Philips offers this array in its 28 pin series as part no. 82S102(0.C.)/82S103(T.S.) and in its 20 pin series as 82S150(0.C.)/82S151(T.S.). Figures 4010 and 4.11 show the logic diagrams of the 82S102/82S103 and 82S150/82S151 respectively. As an example the logic programming options and program table of the 82S150/82S151 are shown in figures 4.12 and 4.13 respectively. Note that the programming options for the outputs (active high/active low) are opposite to those of the FPLA's, due to the presence of NAND gates rather than AND gates. As may be seen from their respective logic diagrams the 828150/82S151 is much more flexible than the 825102/825103. The 828150/828151 has bidirectional I/O lines and the output lines may be controlled in groups of four, whereas the 82S102/825103 has a common CE signal. 47 1-" " • -v , 1-" " .... l", " • v , 1-" " -v .I.", " · -v , 1", v , 1-" '. -v , 1", " v 1 '. " v ~ 1-" '. v ~ 1 ", v 1 ", " v 1" '" " v 1-" ", " v 1-,,- '" " v .1.-" '" ro .... ( , , , , , , ILOGICGAHS-G, • • . ~ :: := '=' = = = '=' '=' " -".... ~~ ----'; ~---'; ~--.l\ l--..3i l--..li '1-----'; ~---l\ ~---'; 7 • " " " " " " " .," " " " " " " Figure 4.10 Logic diagram of the FPGA 828102/828103 48 " '0 9 , o. , I ~ 1=-- I T-: • '" " .,.l2J- " c " .!J .. ;:::: I / I I (' (' (' (' , ,11 I I I I -4----~ I II I I L'L------"-I--I-+I-+!-l-I--l--l--l---r.l~ ~ao I i -WB, I II I I I L ~-----~4+!-++-l+++-0~:: , ------++l-l-+-+-i-B- I, I I ------~ i-+H++-['~'·" I , L ___~~~~=_~-~-~~~~~~~~_~~===_=__=__=_-_~"-_ o-f--I-f-i-l-ftf-i-l---{i]-@R:: ~' LI------4+1-01::;,"· ,i ;::: I ~ft L______-:::! 8'0 '.. • Ol .. OH5"XfOCO>< .. lCTlON Figure 4.11 Logic diagram of the FPGA 82S150/82S151 49 "AND" ARRAY-(I.B) .-----+- •.• .----4-1.• .-----t- I•• .---4--1.• I •• o--4--q,;>-~~ j,B I •• o--...... - STATE STATE STATE STAlE INACTIVE I•• j,B 171 EX-OR ARRAY-(B) ACTIVE LEVEl ""'.E LEVa. H1GH LOW I~I 1/0 DIRECTION-(B) ~. ~. DOECT1OH OUTPIIT Figure 4.12 Programming options for the FPGA 825150/825151 50 PROGRAM TABLE ENTRIES: -j NOTES " 1. The FPGA il with ,II linh In'let. Thu •• bllckground of • 0 0(01 II) 0(0111, I .hlp~ , I ~I"" corr.lponding to stat.. 01 Y).-gln link. Ixia'i In 1M lab'-. -.. i. I lhown BLANK lor cllrlty. i,a ., G AND P D P , • , 0 T • E R. L. • 2 , 0 '0 ,1, , 0 ~ 'J-, " • -' ~ • I • • : i : • 00 : i : 1 0, : i : 8 02 : -:- : • 03 ~ : : : : : " .. ! : : 12 05 : : : ,. .. : ; : 01 ; i ; : ;- : '5 .. : : : ,. 00 : -:- : 11 '0 : : : ,. " : i : PIN 5 2 , ,. ,. ,. I '5 ,. ,. , 1 .L> " I ,. . " I • • Figure 4.13 Program table for the FPGA 828150/828151 51 4.4 PAL (HAL) The maj or problems in designing with (P)ROM's were the non optimal realization of functions (min terms) and the presence of glitches in the output. This is due to the fact that the AND array is fixed and different propagation delays exist from inputs to the outputs, because address decoders often are used instead of a real AND-array. Both problems can be eliminated by making the AND-array programmable too, like in FPLA's. However making both arrays (AND and OR) programmable resulted in a large chip area. Furthermore the programmable OR-array is not optimally used if the output functions realized, have no product terms in common. From these considerations Monolithic Memories Inc. (MMI) decided to develop a device with a programmable AND-array and a fixed OR-array. MMI called their products Programmable Array Logic (PAL). They also started the production of mask programmable devices fully compatible with their PAL's and called these Hard Array Logic (HAL) (Compare with PROM and ROM). Nowadays PAL's are offered by other manufacturers like Advanced Micro Devices (AMD) , National Semiconductor and Texas Instruments (TI). The strategy behind the PAL's is the same. Here we will study the PAL's offered by MMI. 4.4.1 Logic diagram of PAL's Because of the fixed OR-array a lot of flexibility is lost. To meet this shortcoming a whole family of different PAL's has been designed. Two different PAL's with Active High and Active Low outputs are available, as well as PAL's with complementary outputs (true and inverted output). PAL's are available in two pin configurations, viz: 20 pins and 24 pins. These three PAL types all have totem-pole outputs, shown in figure 4.14. 40" NOM ---0 OUTPUT Figure 4.14 Totem-pole outputs present with active high and active low PAL's and PAL's with complementary output Figures 4.15 gives an overview of all active high PAL's that are available to implement combinational logic (only in 20 pin series) • 52 Logic: I)/aOr8fII PAL t OHI Logic D.....-. PAL12H1 --1:< -=--=' .. i'" -1'>-- :' :' , ,I I I .... ··'V' --1:$.= l[i~t~= -~ ~ 1.' 1 --- - -ca·D- if' I ' : I Illi , II" -= -- .. -'<>-->- : , - "'-0--·-·- --= -iii I 1:$'-- - , , . .. ,. III II -t -- j'-7"OO l , I' I I H ' I I - " mi1 1 __t<=-- ' 'I II ' , , - -~~ - ==0-- -- I -" I I : II - , II 1r I ---1:>= I ,. F - - - r-- -t:<--_ .. -- - -- , . - ==0--- -- 1 . _. t:<-- _C_. : :- I II -- :J, f - , c-:::--4-- .- s'D -- l- If -~l I ; I' III .~. - t - >3- -- I I II iji .. r j II .[:> ._,,- ,-I, ';'·1't -th' ' Jj II: ---::.:1-- l.oe'c ~ PALt4N4 , .. _. " ", ... ,-- '''' """,. """j """" - = I il , . ==l--- = - =====.:1--- - --t:o=: -·fIl1-1111-'lilMf H~Ilf~lC:-l!l!'-Ill11J1l'==~- --1"'-_ -- jjJ!-_.tllHJj,H!~1 . =jh=t::> -- ==.:1----- 11 -I I I I' I, -J;$. ,:-t\ll 'I~ I IT]ill j ==1---- 'I· 1[, I ,', , Ii I: 111 ,', fill i il , ,,: iii: 'Iii ,:1 :111 ' 'I 1,1 '" " " Figure 4.15 Logic diagrams of all active high PAL's to implement combinational functions 53 The logic diagrams shown in figure 4.15 may be used as coding schemes. Now the "x" symbol is used to indicate a fuse that is left intact. The symbology used with PAL's is summarized in figure 4.16. A short hand notation is given in this figure for product lines that have all fuses intact. Conventional Symbology ::--.-[-Fj---;g-----r) --)--" i2.;'" PAL Symbology LOGIC STATE 1FUSE BLOWN vee H L L H PRODUCT WITH ALL FUSES INPUT BLOWN REMAINS HIGH t j! / ''---'fA) FUSE NOT BLOWN HIGH L--{::E==t4 ~ ALWAYS --:i" -+1W:i""~'"---l H --1-1- 1112+1112 INPUT L--t:~=::j:+W "-- PRODUCT WITH ALL FUSES " *-Tt -r lOW'::" INTACT REMAINS lOW ALWAyS SHORTHAND NOTATION_\ FOR ALL FUSES INTACT \ :-~lD " .. " III~ Figure 4.16 PAL symbology The two example functions: are implemented in the PAL12H6 as indicated in figure 4.17. 54 Logic Diagram PAL 12H6 I! ' , : I i ! I II ' , , , ! i ' ' ill '" I i : , ! I I I' ' i' II I' " i I ,; ; I t i , ' ' I, I! I: ! i I! : I , ' ,!, II ! , , , " " ; , *P i I ; i,Ill Ii I ! Il, 'i i: I, ' ' : i I I!: I' ' I: 11 • 'I ,I I ! II' ,i i II!: i: 'i III ~ " , I[! I I i! I', I 11 '--' ! II ' I I I -----iX= I !I II i III I, I , i II I I! Ii ~ "'I I 'iIi ITI I II II i Ii i I I ... ,- - - ::= ~ -- ~j~! - ' ~.. I Ii I! ! III , I I' I , I, .. I II i i I I , ...... ~ i I , I I [ I ! .." " I' :I=P ,I I I , I I I II +1 .," .,.' ,. "" """" """"" Figure 4.17 Implementation of two example functions in a PAL 55 Figure 4.18 gives an overview of all available 20 pin active low PAL's. Note that the logic stuctures of the PAL's of figure 4.15 and 4.18 are completely equal, only the output polarity is different. 56 ---c.===#jj" " .. " .... •. •. •...... = ---c.===#jj"" ".. "...... •••• •••• 'I -t=-= I I! I 11 I - 4------, -,... -- I - - - - ~ .. -- - ._- Co··· 7..-OC-=- . --- - -t:E=-- ;'1 II 0-11-·- );;.1),!i! 'i: 1 . t>-c- , I, _d} '-'--"'I- . -- 'il 'I I, . , I! 1 I, II 'I I' 1,1 Co !!:: . ! dil :! ;[.1 ! ,tiJ t .~ -- . Figure 4.18 Logic diagrams of all active low PAL's from the 20 pin series to implement combinational functions 57 4.4.2 Programming PAL's Together .. ith the PAL's MMI has developed a Boolean assembler. They called this assembler PALASM. In fact PALASM is not only the assembler but also contains the edit and simulation programs. Programming of PAL's may thus be done by giving Boolean expressions as input to PALASM. Together .. ith this input a truth table may be provided .. hich is used by the simulation program. Programming may be done using programming equipment which generates the programming pulses required to blow the fuses. The PAL design specification used with PALASM is given in the following text. Figure 4.19 illustrates the use of PALASM, by means of a brief example. PAL Design Specification OPERATORS (in hierarchy of evaluation) The PAL Design Specification is the input file used with Comment follows PALASM. It is also the recommended data sheet formal 101' Complement. prefix to a pin name. describing the function of a PAL once it has acquired the AND (product) unique personality of a particular fuse pattern, The format for the PAL Design Specification as shown on the OPPosite page is: OR (sum) :+: XOR (excluSive OR) XNOR (exclusive NOR) Line 1 PAL part number left justified followed by PAL DESIGN SPECIFICATION ( ) Conditional three-state (IF STATE. MENT) or fixed symbol Equality Line 2 User's part number followed by originator's name and the dale ReplaCed by after the low to high transition of the clock. Line 3 Device application name Line n FuncUon Table. (optional) Line 4 User's company name, City, stale The function table begins with the keyword, ~FUNCTION TABLE." It is followed by a pin list which may be in a different order and polarity from the pin list in lineS. vee Line 5 Pin Ust and GN~ cannot be listed. The pin list is followed by a The pin list is a sequence of symbolic names separated dashed hne; e.g., ---(length optional), which intum by one or more spaces on one or more lines in order of is followed by a list of vectors, one vector per line. One the device pin numbers. Each symbolic name is unique state must be specified for each pin name and optionally (except for unused prns which may have the same name.) separated by spaces. A vector is a sequence of states All pins including power and ground must be named. listed in the same Ofder as the pin list and followed by an Names may use any printable character except the optional comment. The vector list Is followed by another operator: "=:'+/0". The prefix "t", may be used to logically dashed line. complement the name. Definition of Function Table States: H HIGH LEVEL L LOW LEVEL X IRRELEVANT C TRANSITION FROM LOW TO HIGH LEVEL Li ne m Equatlonl. The transfer function of the device is expressed in the Z OFF (HIGH IMPEDANCE) lollowing three forms: Une a 0e1Cl'lptlon. (Optional if follOWing Function Table) ,. SYMBOL = EXPRESSION This section begins with the keyword. "DESCRIPTION." 2. IF (pRODUCT) SYMBOL = EXPRESSION The device operation and application are described here. 3. SYMBOL: = EXPRESSION Teat The following terms are used to construct the equations: Conditions SYMBOL Pin name with optional prefix, "r. H • 'l'ZST SIGB PRODUCT A sequence of SYMBOLS separated L • TEST LON by the AND operator, "'" X • IRREL!'V1\NT 1 • DRIVE BIGS IF Conditional equality, when the PRO o • Q~~ r,pw DUCT is logically true. Otherwise, C • DRIVE INPUT FROM LOW TO IfIGS high impedance (high--Z). Z • TEST POR SIGB IMPEDIlNCE EXPRESSION A sequence of SYMBOLS separated by operators. Standard 0', 1,i2+1112 PALASM 01 Il*/I2 + /Il*I2 58 PALlOLB PAL DESIGN SPECIFICATION , PO0123 VINCENT COLI 07/08/81 2 EXAMPLE 3 MMI SUNNYVALE, CALIFORNIA 4 ABC NC NC NC NC NC NC GND NC NC NC NC NC NC NC IF NC vec 5 , • A*B + C ,A AND B OR C m FtJIICTION TABLE n AS C F PAL DESIGN SPECIFICATION LLL L ALL LOllS LBL L TEST AND GATE LOW BLL L TEST AND GATE LOW RBL B TEST AND GATE XXB B TEST OR GATE BIGB DESCRIPTION o THIS EXAMPLE ILLCSTRATES TBI! FORHAT or TBI! PAL DESIGN SP!lCIPlCATION. EXAMPLE 1 000XXXXXXXXXXXXXXBX1 2 010XXXXXXXXXXXXXXBX1 FUNCTION 3 100XXXXXXXXXXXXXXB TABLE 4 1l0XXXXlCXXXXXXXXX SIMULATION 5 XX1XXXXXXXXXXXXXXLXl PASS SIMULATION EXAMPLE 11 1111 1111 2222 2222 2233 0123 4567 8901 2345 6789 0123 4567 8901 BRIEF 8 x-x- A'S FUSE PLOT 9 x- C LEGEND: X: FUSE NOT BLOWN (L,N,Q) - : FUSE BLOWN (H,P,l) NUMBER OF FUSES BLOWN = 61 Figure 4.19 Use of PALSM; an example 59 4.4.3 Logic diagrams of other PAL's for combinational logic Figure 4.20 illustrates the logic diagrams of the active low PAL's of the 24 pin series. Note that for these PAL's no active high parts are available. Figure 4.21 shows the logic diagrams of the two PAL's that have the complementary outputs. 60 LoP;.,...,.... PALt2LtO Figure 4.20 Logic diagrams of all active low PAL's from the 24 pin series to implement combinational functions 61 logic Dlag,.m PAL20L2 i: :' ~:;:====.~!=:':!':r::::==l'o::Jl--- , , . ' iii " : I ----crt~~. ~~~=-~--~,:. --:::.:::,;:'i''=t! ;::, ~:±,::::;: ::1,±:, ==·.:llf----- . I . ,I::! ! i I: !: !; '! I' :; 'I' iii I! " ,1" ",' I, '. ,.t"""O~ ~ ,I " .. ~·i~i··iHi'~i'i'~~~·~,~ ii~~~~~··i·'i·il!lili!!il ~<:l=== .. " II~: I!,!" I, ,,:.. :II! !I~: I I Ti, ,.' ,...,...... 4 i' ! : i; Ii!, :! ,I ~.. ,i:ii~': .!':I';'ll , ' ,I , I .. : i , '; ; Ii! ' I, ! i ii : ! i i !II' i 'I' ,:,!, iii I Ii,: II] i I Ii! I:!i ::'i :;;, Ii:: ii: I::! !:ii IIII il!i 1,1, I! I I I "" I I I I I I I I I _ 1 Figure 4.20 continued Logic Diagram PAL18C1 Logic Diagram PAL20C1 ...... :: . ,. ':':"'.' ,. ,'~'.. II I, .i I I I , I :s: .. -t>-J , , .,,. , I , ,. ! i " ,. , , !! ' : , , i ! , ,. , " , ! : .. ~ , , I II ,I; I! I I II.,II i; , Iii I, Ii!: , .. ,I , I I I " I , .. .. Figure 4.21 Logic diagrams of the PALos with complementary output 63 As with FPLA's and FPGA's. PAL's are available with bidirectional I/O lines to provide for more flexibility. The numbers are PAL16L8 and PAL20LIO. Their logic diagrams are shown in figure 4.22. As may be seen in this figure enable signals for the tri-state gates are high active. Logic Diagram PAL18L8 Logic DI.. ,.m PAL20L10 " ,", .. no. "." '" , .. ,',' ","," ~ , .. . A' ." : .. , ' i . : i' , '" I ':a;"'" § .. • : , , <:>+ - , ~. " I, 'I I, : ! " ' , I , --!X: I ", ! I i r I , , ~-~- , ! , ',I , ; " Ii ::g:v--v T ~ ' ! II J I , i'i I ~v , ~ I I" ' I ~ J " f!::R"'" • I I I ! J. , 3:8-/ :B::;:::;:-;J ~ , ~ ~ i I , I -0 I J ~.J.1 ~ • ! ! i : I I: ., b:=-::J 't:: .. , J I ! fl:R'""' ! =l::l=l ,I " ~ .. ~ , -Q , :c; J ! .,.,. , :8=f I I I i " I : :c;: 1 " • " , , =l::l=l I I ~'. 1 :B::;:::;:-;J ~ l , -tH-' :8=t. ~ I , , I ! I , , , 81-- , " :::1 Figure 4.22 Logic diagrsms of PAL's with bidirectional I/O lines 64 65 5. DESIGN PROBLEMS USING PROGRAMMABLE ARRAYS Because of the limited number of input and output pins as well as the number of product terms of a physical device, problems arise in designing circuits with more output functions and input variables. Depending on the specific problem we are dealing with, different design strategies may be followed to solve them. 5.1 Product term expansion One of the possible problems is an insufficient number of product terms of a single FPLA or PAL to realize one or more given functions. In this case more devices must be used. Depending on the output configuration of the device different solutions are possible. 5.1.1 Open collector outputs When open collector outputs are available (82S101, 82S152) all inputs and all outputs of the required number of FPLA's should be connected in parallel. Connecting the open collector outputs looks like shown in figure 5.1 + f----l--F 12 Figure 5.1 Open collector outputs connected Wired-OR The function thus realized (Wired-OR) is: Applying DeMorgan's theorem leads to: 66 So to realize the wired-OR fUnction the outputs must be programmed active low. All CE inputs of the FPLA's used should be connected to ground (always enabled). The total number of product terms when n FPLA's are connected in parallel is: n * p where p is the number of product terms per device. The overall picture is shown in figure 5.2 FPLA 1 0··· .115 " ~ CE I I 1 I I I I I I I I I :=>FO··· .F7 I I I I I I I I I I I I FPLA n .J\. r CE I Figure 5.2 Product term expansion using open collector output devices wired-OR 67 5.1.2 Tri-state outputs When devices with tri-state outputs are used (828100, 825153, PAL16L8, PAL20Ll0) product term expansion is done in a different way. As tri-state devices have an active pull-up, the outputs may be connected in parallel, provided that only one device will be enabled at a time. Let us first look at two devices (FPLA's or PAL's) that are connected in parallel. Enabling can now be accomplished using an input variable to select one of the devices. Therefore this variable is connected to the CE pins of the devices. The input variable is connected to the CE pin of the first device in its true form and to the CE pin of the second device in its complemented form. Figure 5.3 shows this enabling scheme. Note that in this configuration glitches may appear at the output lines during switching from one FPLA (PAL) to the other parallel device. FPLA 10· ·.Ij-l·lj+l·· .In " PAL IV 1 Ij-----l FPLA PAL 2 Figure 5.3 Product term expansion using tri-state devices 68 What in this configuration really has been done is dividing the truth table in two separate parts. One part contains the terms in which li=O (in figure 5.3 realized in the upper FPLA). The other part contains those terms in which li=l (in figure 5.3 realized with the lower device). It should be noted that Ii should not be programmed in any of the FPLA product terms. Product terms with up to n + 1 variables may now be programmed (here n is the number of input pins per device). However we are now left with a new problem: What ine~t variable should be chosen to connect to the CE pins? To find the answer to this question we should note that all product terms containing a don't care for this specific variable must be programmed in both tables that result from partitioning the complete truth table. To reduce the sizes of both tables as much as possible the input variable with the minimum number of don't cares should be chosen. As an example figure 5.4.a illustrates the truth table of a square function (that is the output pattern is the square of the input pattern). Figure 5.4.b illustrates the truth table after optimization (by means of Boolean algebra). From this table it is clear that 12 has the minimum number of don't cares. Therefore this table is partitioned ss indicated by 12' The result of this partitioning is given in figure 5.4.c. Figure 5.5 illustrates how this specific function might be realized using product term expansion_ 69 INPUTS OUTPUTS 13 12 11 10 F7 F. F. F. F3 F2 Fl FO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 1 0 1 1 0 0 0 1 0 0 1 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 1 1 0 0 1 0 0 1 0 0 0 0 1 1 0 1 1 0 1 0 1 0 0 1 1 1 1 0 1 1 0 0 0 1 0 0 1 1 1 1 1 1 1 0 0 0 0 1 (a) INPUTS OUTPUTS p. 13 12 10 F7 F6 F5 F. F3 F2 FI FO 0 X X "X 1 0 0 0 0 0 0 0 1 1 X X 1 0 0 0 0 0 0 1 0 0 2 X 1 0 1 0 0 0 0 1 0 0 0 3 X 0 1 1 0 0 0 0 1 0 0 0 X 1 0 0 0 0 0 1 0 0 0 0 •5 0 1 X 1 0 0 0 1 0 0 0 0 6 1 0 X 1 0 0 0 1 0 0 0 0 7 1 0 1 X 0 0 1 0 0 0 0 0 8 1 1 X 1 0 0 1 0 0 0 0 0 0 1 1 X 0 0 1 0 0 0 0 0 10• 1 0 X X 0 1 0 0 0 0 0 0 11 1 X 1 X 0 1 0 0 0 0 0 0 12 1 1 X X 1 0 0 0 0 0 0 0 (b) P-tlll'ml INPUTS OUTPUTS ...... INPUTS OUTPUTS 13 I, 11 10 F, F, F, F. F3 F, FO 13 I, F, FO 'n 'n " 'n 'n I. '3 ., '1 ,. 0 x 0 X 1 0 0 0 0 0 0 1 Ob X 1 "X 1 " "0 0 0 0 1 • •1 X 1 0 • • • '. 1 X 0 1 0 0 0 0 0 1 0 0 ,. 1 0 0 0 0 0 1 0 0 "3 , X 0 1 1 0 0 •, 0 , , X 1 0 1 0 1 0 • 3 X 1 0 • • • • • 0 3 1 X 1 0 • •1 • 0 0 0 0 0 0 1 0 0 0 0 •5 0 1 X 1 0 , 1 0• 1 X 0• 0 •1 0 • • 0 0 1 0 0 0 0 0 •5 1 1 X 1 0 0 1 0 0 I. •5 1 X X 1 0 • • • • 0 0 0 0 0 1 1 X 0 0 1 0 0 0 0 0 P. 0 1 • 1 X • 1 • • • • 0• • • • • • • • • 11b , 1 1 1 X 0 1 0 0 0 0 0 0 I' 0 1 1 X X 1 0 0 0 0 0 0 0 (c) Figure 5.4 (a) Truth table square function (b) Truth table after optimization (c) Subtables with respect to 12 70 FPLA 1 Fp '0, 1,3." 15 " r-v' CE r FPLA 7 LJ.., 2 .. Fp CE r Figure 5.5 Realization of square function using product term expansion More generally truth table partition looks as indicated in figure 5.6. In this figure 10 contains the least don't care conditions. Blocks A, Band C represent input combinations of remaining input variables (12 •.. 115) for 10 - don't care, "0" and 11111 respect~vely. Blocks P, Q and R represent the output functions for 10 - don't care, "0" and "1" respectively. I o x I 2 o 0 , 1 o x 4 , o I 5 5 o 0 6 6 o , 1 o x a • 9 9 10 10 II II 12 12 Figure 5.6 General truth table partition 71 When more devices are to be connected in parallel the same procedure may be used. In this case, however, a decoder 1s required which selects lout of n (4, 8 or 16 devices), depending on the number of input variables used to select a specific device. Figure 5.7 illustrates an example using 4 FPLA's connected in parallel. In this example a lout of 4 decoder is required. When using decoders the total number of input variables may be equal to: n + i where n is the number of input pins per device and i is the number of variables selecting a device. The best way to choose the selecting variables now is to choose those variables for which the minimum number of don't care conditions occurs. INPUT FPLA OUT PUT v I-- =- cr - FPLA • I-- v I-- cr ~DEC FPLA --" -y I cr FPLA • I--- cr Figure 5.7 Product term expansion using tri-state devices and a decoder 72 5.1.3 Totem-pole outputs When the devices have totem-pole outputs (PALlOH8 PAL16H2, PALIOLB •• PAL16L2, PAL12LI0 •• PAL 20L2), the outputs can not be connected in parallel. Now the same strategy that is used with standard TTL parts may be applied. That is to say: Look at the PAL's as if you had standard AND gates with 20 upto 40 inputs (true and complemented inputs) and OR gates with 2 up to 8 inputs. In other words: A number of singular gates in one package. Suppose for example we have two functions with eight input variables. Each function consists of ten product terms. fl = PIO + Pil + + P 19 f2 = P20 + P21 + + P29 A possible realization using PAL16H2 and PAL12H6 is given in figure 5.B. PAL "- 16H2 v 51 52 PAL 12H6 "- I' fl 51 + P lB + Pl9 f2 = 8 2 + P28 + P29 52 = P 20 + P21 + Figure 5.8 Product term expansion uSing devices with totem-pole outputs 73 5.2 Output expansion When the number of functions that has to be realized is greater than the available number of output pins, it is simply possible to use more devices (FPLA's or PAL's). The inputs of these devices are connected in parallel while the outputs are used separately. Figure 5.9 shows such a configuration using FPLA's. Note that the CE pins are grounded. FPLA 8 CE FPLA 8 CE Figure 5.9 Output expansion using more devices In some cases a more economical method to increase the number of outputs is using a lout of n decoder. This may only be done if the functions realized by the decoder are configured in such a way that for every possible combination of input variables only one of the output functions Is active at a time. The following figure shows a truth table in which this situation appears together with a possible realization using an FPLA and decoder. 74 I I I I I F F F F F F F F F F F 15 14 210 o 1 2 3 456 16 17 18 19 o 0 000 o 1 1 0 000 o 1 000 o 0 001 1001010 o o 0 0 0 o 1 011 1111000 00010 ~ '-----~v,...------J I '\ functions that functions that should be realized may be real ized directly by a decoder ,.. ) v Fa····F:3 direct FPLA outputs la····115~ ,. .. DEC ,.. CE 1 :16 ~ F4····fig 4 " expanded 1 outputs CE 1 Figure 5.10 Output expansion using a decoder 75 Using a lout of 16 decoder leads to a maximum of 16 expanded output functions of which only one can be active at a time. When more than one of the expanded outputs must be activated simultaneously, normal decoders can not be used. In this case a second device is required or if more economical a (P)ROM could be used as shown in figure 5.11. In the (P)ROM a decoder selects one output word. ... direct FPLA " outputs .In -" PAL (.i.4) --I 32xS " CE PROM -,J" expanded 5 r outputs 1 (.i.S) CE 1 Figure 5.11 Output expansion using a (P)ROM 5.3 Input expansion When the number of input variables is greater than the number of input pins of a programmable array we are dealing with the most complex expansion problem in the application of programmable devices. A possible way to expand the number of inputs we have already seen in figure 5.7. There we used a decoder to expand the number of product terms. As was pointed out there the use of s 1 out of n decoder also increased the number of available input pins with 210g n. This method however will not be economical if the number of input variables increases. In case of, for example, 20 input variables and a device with 16 input pins, a number of 16 devices (FPLA's or PAL's) would be required if the strategy of figure 5.7 was used. In this case a more economical solution would be attained using two programmable devices interconnected as given in figure 5.12. In this figure two programmable arrays are assumed that each have 16 inputs and 8 outputs. 76 FPLA 1 FPLA 2 '16· .. ·'23 ~------~~ Figure 5.12 Input expansion using two programmable arrays In this configuration the number of input variables can be expanded to 24. Note that the delay time differs for inputs 10 - 115 and 116 - 1 23, Array 1 reduces the 16 inputs 10 - 115 to the 8 input lines 10 - 17 of array 2. Inputs 116 - 123 are connected directly to input lines IS -I 1S of FPLA 2. The compression given by array 1, however, is only possible if the desired functions satisfy certain restrictions. If "~fa is a function of four variables (xl' x2' x3' x4) and partition of input variables is required, it should be possible to decompose the function. That is to say, thst f, for example, should be written as: 77 Generally, it is not always possible to partition a function into subfunctions, e.g., the function: may be written as: with That is f may be decomposed as: However, decomposition of the form: is not possible. This subj ect has been studied by Ashenhurst and ·Curtis and is generally known as "decomposition theory". It is beyond the scope of these course notes to deal with this theory in more detail. The problem has been mentioned only to indicate that input expansion according to figure 5.12 is not trivial. A second app roach to expand the number of input variables even further is given in figure 5.13. Again arrays are chosen with 16 inputs and 8 outputs. In this configuration the number of input variables can be expanded to 32. Here the delay times of all input variables are the same but twice as long as that of a single device. Again it should be possible to decompose the functions. 78 FPLA 1 8 FPLA 3 FPLA 2 Figure 5.13 Input expansion using three programmable arrays Of course it is not necessary that only different input variables are applied to different arrays. A situation as shown in figure 5.14 might as well occur. 79 FPLA 10 ... 115 F ···F7 1 a FPLA CE 10 ... 17 2 Fa···F7 18 ... 115 CE Figure 5.14 Input expansion using three programmable arrays In this case the output functions again must satisfy the condition that they may be decomposed. With input expansion or decomposition (partition), the total set of input variables is grouped in smaller sets. If these smaller sets have no variables in common (figure 5.12 and 5.13) this is called a: "disjunctive decomposition" (Ashenhurst). The sets may also have some variables in common (figure 5.14) in which case it is called a: "non-disjunctive decomposition" (Curtis). In all configurations seen for input expansion devices with open collector, tri-state or totem-pole outputs may be used. Of course all expansion techniques seen in this paragraph may be combined to complex networks. 80 81 6. Sequential logic 6.1 General model for sequential circuits Up to this point our attention has been focussed on combinational circuits only. In this kind of circuitry the output functions only depend on the present values (state) of the inputs. In practice, however, we are often dealing with systems in which the output functions are not only determined by the present values of the inputs but also by previous values of these inputs (history). In switching theory these systems are generally kno~n as: I'sequential systems". A sequential system is always built with two parts, i.e.: Combinational logic Memory connected as shown in figure 6.1. INPUT COMBINA TIONAL OUTPUT '0 In LOGIC Ys Yp I I I I I I r-- 'Y1 Y, - r - ..... NE PRES ENT( " I I XT STAT E .... - / '- - )STATE '-- f-- MEMORY Figure 6.1 General model for sequential circuits 82 The memory holds information about past events required for proper functioning of the circuit. This information is represented in the form of s binary outputs. Yl' Y2 ••••• Ys known as state variables. Each of the 2s combinations of state variables defines a state of the memory. In general each state corresponds to a particular combination of past events. The combinational logic section receives as inputs the s state variables Yl' Y2' •••• Ys and the n circuit inputs il' i2' •••• in' It generates m outputs fl. f2 ••••• fm and p excitation' vari~bles Yl' Y2' •••• Yp • which specify the next state ·to be stored by the memory. The combinational logic network may be defined by Boolean equations of the standard form. i.e.: i .... 1,2, ..• ,m j = 1,2, ... ,p These are time-dependent equations. i.e •• they are valid when all the inputs and outputs are stable. like in any combinational circuit. 6.2 Memory elements We have not yet specified the relationship between the inputs and outputs of the memory portion. This relationship depends on how the memory is realized. i.e •• as a set of: - feed bsck loops with time delsy - clocked flip-flops When feed back loops are used the memory behaviour may be described by the equation: yt(t+Dt) = Yi(t) If flip-flops are used to realize:the memory the behaviour of the memory may be described by one of four equations depending on which type of flip-flop (FF) (see figure 6.2) is used: D FF Yin + l = Yin T FF Yin + l = Yin R-S FF Yin + l J-K FF Yi n + 1 '. 83 on Q n+l ----'0 o 0 ---<..IC 1 l 1 (a) ----'T (b) n s a R snon+l on+ l=Sn+RnOn 00 On C 01 1 n n ) R ( S ·R =0 1 0 0 1 1 X ( c) J J a n n n n on+~ K o +J 5 00 C 01 K 1 0 1 1 (d) Figure 6.2 (a) D (delay) flip-f!op (b) T (toggle) flip-flop (c) R-S (reset set) flip-flop (d) J-K flip-flop 84 6.3 Synchronous and asynchronous sequential circuits The flip-flops may be clocked in one of two ways, i.e.: all flip-flops are clocked by different pulses that are not periodic in time - all flip-flops are clocked by the same pulse that is periodic in time (clock) When circuits are realiz.d with feed back loops or differently clocked flip-flops they are generally known as: asynchronous. When one periodic pulse (clock) controls the actions of all FF's the system is called: synchronous. In these course notes only synchronous circuits will be discussed because of the following reasons: 1. asynchronous circuits are hard to design and test, because time is a critical factor in these circuit, that is difficult to control. 2. almost all sequential circuits may be built ss synchronous circuits. 3. asynchronous circuits require no new components, i.e. they may be built using combinational logic only. 4. special sequential programmable devices all are synchronous. The general structure of the sequential circuits studied, therefore will be as shown in figure 6.3. 85 '1 f In COMBINATIONAL f m LOGIC ro I- Q C ..... FF 1 .. I I I I I I I I .. Q FF Ci- n .. CLOCK Figure 6.3 General structure for a synchronous sequential system 86 6.4 Representation of synchronous sequential systems Synchronous sequential systems may be represented in two different forms, i.e.: state diagram state table 6.4.1. State diagram A state diagram is s graphical representation of the behaviour of a synchronous sequential system. Each state of the sequential system is represented by a circle. Arrows are used to indicate state transitions. Arrows leave each state for each input and terminate at the appropriate next state. Each arrow is labeled with a transition number Ti (i h 0,1,2, ... ). All transition numbers sre summarized in a separate list together with the input combination that causes the particular transition and the output corresponding to the psrticular present state input combination for which the transition occurs. Example As an example consider a door-lock that releases the door only if the sequence 1-2-4-1-9-8-3 is input into the system. Any wrong combination should immediately reset the system. The block diagram of this door-lock is shown in figure 6.4. iO i 1 . 0 1 2 3 1 SYNCHRONOUS I SEOUENTIAL 4 5 6 7 I SYSTEM r--- LOCK I 8 9 R '9 iR clockI Figure 6.4. Block diagram of a door-lock When a key is pressed the corresponding output line (iO for 0, etc., non-coded keyboard) goes high. The R-key may be used to reset the system, i.e. lock the door. When no key is pressed all input lines are low. The lock-signal is active high, i.e., the door is locked if lock = "I". The state diagram for this system is shown in figure 6.5. 87 Figure 6.5. State diagram of the door-lock 88 TRANSITION STATE iiiiiiiiiii OUTPUT COMMENT NUMBER 01234.S6789R TO X LLLLLLLLLLL H no key pressed, door locked TO 7 LLLLLLLLLLL L no key pressed, door opened Tl 0 L8LLLLLLLLL 8 key 1 pressed, door locked T2 1 LLHLLLLLLLL 8 key 2 pressed, door locked T3 2 LLLL8LLLLLL 8 key 4 pres sed, door locked T4 3 L8LLLLLLLLL 8 key 1 pressed, door locked TS 4 LLLLLLLLL8L H key 9 pressed. door locked T6 5 LLLLLLLL8LL H key S pressed, door locked T7 6 LLL8LLLLLLL L key 3 pres sed, door opened TS 1 LHLLLLLLLLL H key 1 pressed, door locked T9 2 LLHLLLLLLLL H key 2 pres sed, door locked T10 3 LLLLHLLLLLL H key 4 pressed, door locked Tll 4 LHLLLLLLLLL H key 1 pressed, door locked Tl2 5 LLLLLLLLLHL H key 9 pressed. door locked T13 6 LLLLLLLLHLL H key 8 pressed, door locked T14 7 LLLHLLLLLLL L key 3 pressed, door opened TR = TO + Tl + T2 + •.•. + T14 + IR Figure 6.5 continued 89 After initialization the system is in state 0, waiting for the first key closure. As long as key 1 is not pressed the system remains in state 0 (TO' TR ). If key 1 is pressed a transition to state 1 occurs (T 1 ). As long as key 1 is pressed (Ta) or no key is pressed (TO) the system remains in state 1. If key 2 is pressed the system goes to state 2 (T 2 ). If an illegal key closure occurs (more than one key closed at the same time or not key 2 closed or not key 1 closed) the system is reset to state 0 (TR ). Other states and transitions may be interpreted in the same way. Only the reset transition (TR ) and the "no key closure" transition (TO) still require special attention. From each state the system may be forced to go to state 0 by pressing the reset key. Furthermore the system should be reset to state 0 if an illegal transition is present. The reset transition therefore is equal to: TR = TO+Tl+T2+···+T~+IR,. with IR = input combinstion with reset key (R) closed. The TO transition indicates a transition that is to occur when no key is pressed (all inputs low). Because the system should be stable between two key closures (if no key is pressed, the present state must not change) transition TO is present with each state. Note what happens if for example the system is in stste 1 by a closure of key 1. If key 1 is released (no key pressed, TO) and closed again the system remains in state 1, although the closure of key 1 has now become illegal. How this problem is to be solved is left as an exercise to the reader. Another consequence of the solution presented here is that a combination containing a sequence of two or more equal digits cannot be realized. Though this problem looks relatively simple it may be complex due to key bounce. This problem is also left as an exercise to the reader. 6.4.2. State table A state table contains the same information as the state diagram. Now the states, inputs and outputs are grouped in a table. The left column of this table represents the present state of the circuit. At the top of the tsble the different input combinations for which a transition may occur are listed. The entries in the table indicate the next states and outputs (separated by a" ,") for the circuit when a specific state/input combination exists. Figure 6.6 shows the state table for the door-lock. In this figure input combinations are indicated as Ii' e.g.: II LHLLLLLLLLL = Key 1 pressed. In = LLLLLLLLLLL = no key pressed. 90 PRESENT INPUT COMBINATION STATE 10 11 12 13 14 IS 16 17 18 19 IR In Iill 0 0, 1 1 , 1 0,1 0,1 0,1 0,1 0,1 0,1 0,1 0,1 0,1 0,1 0, 1 1 0, 1 1 , 1 2, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 1, 1 0, 1 2 0,1 0, 1 2,1 0,1 3,1 0,1 0,1 0,1 0,1 0,1 0, 1 2,1 0, 1 3 0, 1 4, 1 0, 1 0, 1 3, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 3, 1 0, 1 4 0,1 4, 1 0,1 0,1 0,1 0,1 0,1 0,1 0,1 5,1 0,1 4,1 0, 1 5 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 6, 1 5, 1 0, 1 5, 1 0, 1 6 0,1 0,1 0,1 7,0 0,1 0,1 0,1 0,1 6,1 0,1 0,1 6,1 0, 1 7 0, 1 0, 1 0, 1 7,0 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 0, 1 7,0 0, 1 Figure 6.6 State table for the door-lock 91 7. Realization of a synchronous circuit 7.1 Singular gates Different binary combinations must be assigned to the states and entered in the state table to realize a synchronous circuit. The states S1 of the door-lock might for example be coded as: So 000 Sl 001 S2 010 Entering this code in the state table for the door-lock leads to the table of figure 7.1 (upper numbers indicate states, lower numbers indicate output). PRESENT INPUT COMBINATION STATE 10 II 12 13 14 IS 16 17 IS 19 IR In 1111 0 000 001 000 000 000 000 000 000 000 000 000 000 000 1 1 1 1 1 1 1 1 1 1 1 1 1 1 000 001 010 000 000 000 000 000 000 000 000 001 000 1 1 1 1 1 1 1 1 1 1 1 1 1 2 000 000 010 000 all 000 000 000 000 000 000 010 000 1 1 1 1 1 1 1 1 1 1 1 1 1 3 000 100 000 000 all 000 000 000 000 000 000 all 000 1 1 1 1 1 1 1 1 1 1 1 1 1 4 000 100 000 000 000 000 000 000 000 101 000 100 000 1 1 1 1 1 1 1 1 1 1 1 1 1 5 000 000 000 000 000 000 000 000 110 101 000 101 000 1 1 1 1 1 1 1 1 1 1 1 1 1 6 000 000 000 111 000 000 000 000 110 000 000 110 000 1 1 1 0 1 1 1 1 1 1 1 1 1 7 000 000 000 III 000 000 000 000 000 000 000 III 000 1 1 1 a 1 1 1 1 1 1 1 0 1 Figure 7.1 State table of the door-lock with coded states. 92 Once binary codes have been assigned to states. minimal (optimal) expressions for the input lines of the FF's must be determined. If for example R-S FF's are used optimal expressions for all set and reset input lines of the FF's must be derived from the state table. This is a combinational problem that might be solved by using optimization techniques for multiple output circuits (e.g. Quine-McCluskey). However. because a non-encoded keyboard is used and 3 state FF's are required the total number of inputs to the combinational logic section is 13. while the total number of outputs of the combinational circuit is 7. The combinational problem is thus a 13 input-7 output problem. which is very complex for optimization. even when computers are used. Furthermore state assignments might be of great influence on the optimization results. Even when an encoded keyboard had been used and D FF's instead of R-S FF's the total number of inputs would still have come to 7 (4 encoded lines + 3 Q-outputs) and the number of outputs to 4 (3 D-inputs + lock line). being a 7 input-4 output optimization problem. 7.2 Programmable arrays This kind of complex combinational problems is generally encountered in sequential systems. However, state assignment and optimization are no longer relevant if a programmable array is used to realize the combinational part of the sequential circuit. This may be illustrated by figure 7.2 which illustrates the functional diagram of the door-lock using an FPLA. The direct input-lines i O' i l ••••• i9.iR are presented to the FPLA together with the Q-outputs (states) of the R-S FF's. The FPLA outputs are used to generate the R-S signals for the FF's (next state) and the lock-signal. The number of FF's required as well as the number of input-lines present at the input of the FPLA cannot be reduced by another state assignment or with other optimization tec·hniques. Therefore independent of stste sssignment or optimization almost all pins of the FPLA are used. The only result that may be achieved by optimization is that the number of product lines required to generate the output functions might perhaps be reduced in comparison to direct coding of these product terms. However. because the number of product terms required easily fits in the FPLA. optimization is not necessary and programming of the FPLA may be straight forward. This conclusion generally holds for sequential circuits realized with FPLA's. (Note: The transition term TR • in fact. already was an optimization. However. it is optimal as a consequence of functional thinking rather than using optimization techniques (Boolean algebra)). 93 LOCK FPLA S Q O C-- R S Q, C I- R S Q 2 C- R CLOCK Figure 7.2 Functional diagram of the door-lock using an FPLA The programming of the FPLA may easily be derived diretly from the table given on the next page. This table results from the state diagram of the door-lock, which has been discussed earlier. In the comment part of the table remarks are entered on whether a flip-flop is to be set or reset with a specific state transition. Note that the programming of the FPLA is derived from the state diagram rather than the state table. 94 PRESENT QQQ TRANS IT ION QQQ NEXT COMMEMT STATE 210 210 STATE 0 000 ---> TO ---> 000 0 a 000 ---> Tl ---> 001 1 set FFO a 000 ---> TR ---> 000 a 1 001 ---> TO ---> 001 1 1 001 ---> Ta ---> 001 1 1 001 ---> T2 ---> 010 2 set FF I, reset FFO 1 001 ---> TR ---> 000 a reset FFO 2 010 ---> TO ---> 01(') 2 2 010 ---> T9 ---> 010 2 2 010 ---> T3 ---> all 3 2 010 ---> TR ---> 000 a reset FF 1 3 all ---> TO ---> all 3 3 all ---> TI0---> all 3 3 all ---> T4 ---> 100 4 set FF2, reset FFO, reset FF 1 3 all ---> TR ---> 000 a reset FFI and FFO) 4 100 ---> TO ---> lOa 4 4 100 ---> T 11---> 100 4 4 100 ---> TS ---> 101 S set FFO) 4 100 ---> TR ---> 000 a reset FF2 ) 5 101 ---> TO ---> 101 5 5 101 ---> T12---> 101 5 5 101 ---> T6 ---> 110 6 set FF I, reset FFO) 5 101 ---> TR ---> 000 a reset FF2, and FFO 6 110 ---> TO ---> 110 6 6 110 ---> Tlr--> 110 6 6 110 ---> T7 ---> III 7 set FFO 6 110 ---> TR ---> 000 a reset FF2 and FFI 7 III ---> TO ---> 111 7 7 111 ---> T 14---> 111 7 7 111 ---> TR ---> 000 a reset FFO, FFI and FF2 ) 95 From this table the set and reset conditions for the flip flops may be derived. The set and reset conditions are expressed as functions of transition numbers (Ti) SETO TI + T3 + TS + T7 RESET O = T2 + T4 + T6 + TR SET I T2 + T6 RESETI T4 + TR SET 2 T4 RESET2 TR with TI = QOQIQ2ioiIi2i3i4iSi6i7iSi9iR etc. The programming of the FPLA in accordance with these· expressions is shown in figure 7.3. 96 .--~------.- . ·-~--.:JID---<>--..... " .. " ... ,,, .. .., .. ,...... ,," """" ,',."" """ .. ,."" '. Q S CIo- 2 R Q s C~ 1 R S Q Clo- 0 R clock Figure 7.3 FPLA programming for the door-lock 97 7.3 Hypothetical programmable array with state register Considering the general structure of a synchronous sequential circuit and the statements made with respect to the door-lock example it would be practical to have one component in which a state register is integrated together with a programmable array. The outputs of the register should internally be fed back to the input stage of the array. The general structure of such a device is shown in figure 7.4. Direct circuit inputs and register outputs are connected to the AND-array in their true and complemented form. The OR-array consists of two parts. The outputs of the first part are connected with the set and reset inputs of the flip-flops of the state register. In this part of the array the next states are programmed. The second part of the array provides for outputlines. In this array section the required output functions are programmed. A special line from the OR-array is fed back to the AND array through an inverter. This structure allows for easy programming of a special state transition that should occur if no other legal transitions exist. This transition is generally complementary to all other state transitions (complemented state transition). Compare, e.g., TR of the door-lock example. With this general array structure synchronous sequential systems can be realized easily. 98 10 4> .... I, I I INPUT I Y> I In It .-' 4> .~ PRESENT :4> STATE I Lc> COMPLEMENT \ / V ------'\/ ~ } TRANSITION 0 s ~ C R '--0 S NEXT C STATE R , L.- 0 S c R ~ CLO CK , Figure 7.4 Hypothetical programmable array with state register 99 8. Available programmable arrays with registers In practice two major types of programmable arrays with registers are available: (F)PLS (Field) Programmable Logic Sequencer PAL/HAL Programmable Array Logic/Hard Array Logic 8.1 (F)PLS Field programmable logic sequencers are offered by several manufacturers like: Signetics, Texas Instruments, Fairchild and National Semiconductor. Signetics, for example, offers four different sequencers (O.C. = Open Collector output; T.S. = Tri-State output), viz: 82S104 (O.C.) / 82S105 (T.S.) 82S154 (O.C.) / 82S155 (T. S. ) 82S15X 82S156 (O.C.) / 825157 (T. S. ) { 825158 (O.C.) / 82S159 (T.S.) 8.1.1. 82S104/82S105 8.1.1.1. Logic diagram The logic diagram of this FPLS is shown in figure 8.1. As may be seen from this diagram the 82S104/82S105 contains a 6 bit state register (R-S FF's) that is internally fed back to the AND-array part of the circuit. A complement line is available to allow for easy programming of a complemented state transition. The outputs of this FPLS are not directly generated by the OR array but are the Q-outputs of a second register (output register). Both registers (state and output register) are clocked at the same time with the positive edge of the clock signal. Due to the second register, outputs will be stable between clock pulses. This in contrast to the general device structure described in paragraph 8.3. Depending on how the reset and set lines of the output register are programmed two different output configurations are possible, i.e.: - outputs are functions of both present state and inputs - outputs are functions of present state only. The first output configuration is realized if the set and reset lines of the output flip-flops are programmed as functions of both present state and input combination. In this case the circuit is often called: a Mealy circuit. 100 '2..2... " ~r:::-. '. ,.!... I~ ~ 'e 2.. 'I..!.. 118 19 ~ '" '15 2 --; '- joe I 'i'"Q Po , . ~P' , . p ,I M 2 , • , , " , 0 " , . S Q~ !..!, , , 0 , ,.1--< , '-1 , 0 T • , 0 1 'ii"F , . R " '-1 , 0 I L , . '0 .'.6.~U.J.l.'.0 39J8J1JIJ53.33J2 3'3019282126252_ lJ222'20'9'81116 \~HI3121"Og I 7 e &. J 210 'lOGIC TERMS-T' • OfNOTtS fl)l,(D COIrIOIIECl101r1 Figure 8.1 FPLS 82S104/82S105 Logic diagram 101 Outputs are programmed to be functions of the present state only if the set and reset conditions for the output register are completely equal to the set and reset conditions of the state register. In this case the contents of the output register is merely a copy of the contents of the state register. Circuits with this output configuration are often called: Moore circuits. The registers may be preset asynchronous to the clock. During power on all FF's are preset to "1". The maximum frequency is 11 Mhz if the complement array is not used, else the maximum frequency is 8.3 Mhz. With this FPLS the door-lock may be realized as shown in figure 8.2. 8.1. 1. 2 Program table The FPLS 82S104/82S105 can be programmed by means of logic programming equipment. The desired fuse pattern (programming) is specified in a program table in accordance with the conventions shown in figure 8.3. Figure 8.4 shows the program table in which the programming of the door-lock has been entered. 102 • .T T T T111TTTTT , R4 2 0 8 6 4 2 0 '1/11/ , /l.t , '--LL I I I LLI II 1 I , ' , '- ' ",-,,'r t- iO • h, , , It+- r-::j::; t-~-.!. i2 , i4 , , i6 i8 , iR J " , " , ~ .. , , , 0 " ++~4+++~~~++H4++'~rH++~~+++rrr~+rh4~~Q:rT~~~IOck, , , 0 Lr.. , , ~ , - , 0 , , , 0 , , ~ , , " -I- .'''6''~U''].2''.O l!38J7JftJ53.3332 l']OH282716HH 2312112019181116 '~"'Jll01109 8 1 8 ~.o 1 210 ,UXl,C IfR,,"S- 10 • D£..oH5""lOC~CIlDM Figure 8.2 Realization of the door-lock circuit with the FPLS 103 "AND" ARRAY - (I), (P) ,----1r- '" , ___--;-_ i.p ,----+-" ,----+- ,,' ',' o-"'- STATE STATE STATE cOO< STATE ,,' H i,ji L DON'T CARE "OR" ARRAY - (N), (F) ""-+-i , Q ""-+--1 , o "' -+--1 , Q ""-+-i Q ;;,i-+_-I • ii.i-+--I • • ii,)-+--I • cOO< .,""'" cOO< ACTION o .. , H .,," L NO CHANGE "COMPLEMENT ARRAY" - (e) I I I I I I I I I co'"' cOO< """'" coo< I ACT,OH C"", o GEMERU£ A PfIOPAGAil: • I TRAN$I'AAfNT I PRESET/O.E. OPTION - (PIE) , '0' "''''''' coo< H O.E. L NOTES 3 To prevent simuitaneolls Sel and Reseillip·flop commands. this slate is not allowed 10f" I. This is the .nll181 unprogrammed state of all link pairs It IS normally associated W,lh all Nand F link pairs coupled to 8clt",e gates Tn (see Ilip-lIop truth lables). unused (inactive) AND galas Tn 4. To prevent oscillations, thiS Slale IS not allo_d lor C link pairs coupled to active gales 2 Any gate Tn will be unconditionally Inhibited il anyone of ,IS I 0< P hnl< pairs IS left ,nlaCI Tn. Figure 8.3 Coding conventions for the FPLS 82S104/82S105 104 NOTES PROGRAM TABLE ENTRIES: 1 The f'PlS ,s shIpped with all hnks Initially mtect. Thull. a backvround 01 ·0· lor all C 1m P. H. Fr • Terms, and an MH" lor the PIE option. &lIi,'e in thal.ble, ahoYtn BLANK instead lor ,H SET PRESET 1 H clarity. GENERATE " P ,H " PROPAGATE j,J5 'L RESET , L 'L 2 Unu8ed Cn.lm. and Plio bil8 are normally programmed Dan', e.re I-I. " 3 Unused Irana",on and output Term. can be left blank. TRANSPARENT I DON'T I NO , ,- ,- 4 lettera in v!mable lields are used 88 ldenliliera by logic type progr.mm~. CARE , CHANGE I OPTION (PIE) II... TRANSITION TERM OUTPUT TEAll - .,!NPUT VARIABLe: IIml PRESENT STUe (Pa, NEXT STATE (Na) OUTPUT FUNCTJOIrI "rl NO. --1 - 1 1- --1 --1 1 C. ,-- - --,-- - --,-- 3 2 1 0 -- -8 --, - -- --3 2 --1 --0 5 • --3 2 --1 0 ------, - -- -- ,-r- -- • • • • • • - • • 3 2 1 0 • • •• 2 --1 0 0 - - - L L L. L. L ------, - - L L L L , L L L L - - fL L - 2 - - - L L L l L , ~ L - - L H I. , - - - L I. I. I. l l l L - I- L -~ 4 -- - L L L L L L L - - 5 - L I. L l L L - - - •, -- - - - L I. L L - - - - - l- I. L L L l - - - L. • - - - - l L L L L - - - L 1 - • - - - - - L L l l l ------I. - - - - - L L L L ------L L L L L ------"02 - L L l - .. - -- - - L ------L L L - - - - - ,." - - L L L L '- L L ------OS • ------I L ,. ------L. L. ,." ro 2' 22 23 2. 2. 28 27 2. 2. 30 31 32 33 34 35 30 38" 39 ...4 •, .." '0•• " iiiiiiiiiii I aaa o R9876543210 210 c k Figure 8.4 Program table of the FPLS with door-lock example programmed 105 8.1.2. 82515X The 82515X is a series of other sequencers offered by 5ignetics. They are quite different from the 825104/825105 as may be seen from the logic diagrams shown in figure 8.5 (825154/825155) and figure 8.6 (825156/825157 and 825158/ 825159), respectively. Instead of R-5 flip-flops J-K flip-flops are used in these sequencers. The flip-flop outputs are not only internally fed back to the AND-array part of the circuit, but are also available as output lines. Besides these registered outputs non-registered bidirectional I/O lines are available. The direction of these lines may be controlled by a special part of the AND-array (Control Terms). A J-K flip-flop is the most universal kind of flip-flop. It may be used as an R-5, T (J-K is essentilally R-5 + T FF) or D flip-flop, depending on the functions presented to the J and K inputs, i.e. (compare figure 6.2): {R-5 FF J 5, K = R J-K FF T FF J = K = "1" D FF J = K This optional use of J-K flip-flops allows for flexible and optimal circuit designs. The term "optimal" in connection with FPL5's should be interpreted quite differently than in the context of singular gates~ In connection with singular gates optimal means: The minimal number of gates required to realize a circuit. In other words: The least number of product terms and the least complex product terms. Using FPL5's optimal really means: The minimal number of FPL5's required to realize a circuit. If a circuit may be realized with one FPL5 only, optimization might not even be necessary, seen from the switching theory point of view. Optimization only leads to a reduction of the number of product terms used internally. Therefore optimization is optional if one FPL5 contains enough product terms (and flip-flops) to realize the circuit, with direct coding of the state transitions. Within an FPL5 optimal than means: The least number of product terms used. The complexity of the product terms is not relevant. The following example illustrates what is meant with the statements made in this paragraph. The circuit of this example is only used to demonstrate the term "optimal" in relation to singular gates and FPL5's and has no direct interpretation. 106 'C,-""HIOl HRMS< J\ )(l 29 28 21 16 ]!; 2_ IJ n l' 2Q ,g" 11'6 15 t. 13 12" 10 9 ,~~ • 1 } I 0 I I , , , • . -G " " 0- .. I , .. .. ~ " 0- ...... ;::. I . . .. .-~T ..1- " . - . .-:t+ .-' . .. . - . ~r' t . . . . " lC.r " -+ " , , . I " . , " . . ., ., " " I ~. .." I ", , l p~ Ae +W+U~+W+U~+H~+H+H~~~1l:~ I ~~~~~~~ffH~~:B I _,J 0 , 15 "', . I, " 1 • O'""Tfs .... OC"",... cnO" @ I>t"O'H""R(-OIl Figure 8.5 FPLS 82S154/828155 Logic diagram 828156/157 828158/159 ',., ...... ',' " "' '." '" ~" " ,',.",,"," . r:- t ..~ ,.....'" ...... --1,' ' 'D~ 1 ' r-B" I I r; u 0 0 ., ..... 0. .•. 0 ~ ....0 •••• !, .(1., •• [] FJ L;", ., ~"I.~.~ Il" .,. e,.··u .' ....8 -- ---____-~'rl'J J 11- .'" ¢.·.O· --~--~" • ~ .. []. ___ I . 0 [I T Figure 8.6 FPL5 825156/825157, 825158/825159 Logic diagrams 108 Example Consider the sequential circuit that is defined by the state diagram and state table of figure 8.7. The circuit has two inputs "X" and "yn. In the state diagram the arrows are labeled with the input combination "Xyll that causes the particular transition. PRESENT INPUT COMBINATION (XY) STATE 00 01 11 10 DD 0 0 2 3 1 DV' 1 1 3 2 0 2 0 0 1 1 3 0 0 1 1 (a) (b) Figure 8.7 A sequential system (a) state diagram (b) state table Assigning bitcombinations to the states leads to tbe state table of figure 8.8 PRESENT INPUT COMBINATION (XY) STATE Q 1 QO 00 01 11 10 0 - 00 00 10 11 01 1 = 01 01 11 10 00 2 = 10 00 00 01 01 3 = 1 1 00 00 01 01 Figure 8.8 State table with coded states 109 Using optimization techniques (Karnaugh-maps) leads to the minimal expressions: J-K FF: J o = X KO = Q1X + Ih x D FF: DO = Q1(QOX + QOX) + Q1 X D1 Q1 Y J-K flip-flops would be used if this circuit was to be realized with standard gates, because the expressions for the J and K inputs are less complex than those for the D-inputs of the D FF's. Using an FPLS, however, both solutions are equally optimal. In both cases the total number of product terms is 4. Note, that a product term is required, even when only one variable is applied to a flip-flop input. If the state transitions were coded directly, this circuit would still easily fit into one FPLS. The number of product terms used would then amount to 16 (= number of state transitions if transitions labeled with two input combinations are counted twice). This number is less than the number of product terms in one FPLS (32). Programming of the flip-flops of the 82S15X as J-K flip flop (R-S and T FF) or D FF, respectively, is shown in figure 8.9. All flip-flops are clocked at the same time with the positive edge of the clock. The flip-flops asynchronously may be preset or reset. During power on all flip-flop outputs are set to "1". The maximum clock frequency is 15 Mhz if the complement array is not used, else the maximum frequency is 13 Mhz. 110 "OR" ARRAY· (0 TYPE) "OR" ARRAY· (0 = DJ I I '. I " I 0 I 0 o I 0 I I I I I I • I I I I """'" """' I "'OON C",,", Tn STATUS COD< I Ttl STATUS COD< D-"", A I H • ACTIVE ('-I) I INACTIVE (~) I I I I "OR" ARRAY· (0 = J-KJ '. I '. I '. I '. I o I 0 o I 0 I I I I I I I I I I ACTIOI\I ""'~ COD< I ACTICH COD< COD< I COD< TOGGLE 0 I H RESET L I "0<0 I '" F I "'- Figure 8.9 Programming options for J-K flip-flops 111 8.2 Registered PAL/HAL Registered PAL's offered by MMI, National Semiconductor and Texas Instruments may be grouped into three subclasses: PAL's with registered outputs PAL's with Exclusive-OR PAL's with arithmetic gated feedback In all these PAL's the registers are implemented with D type positive edge triggered flip-flops. 8.2.1. PAL's with registered outputs PAL's with registered outputs only differ in the number of available FF's as may be seen in figure 8.10. The PAL16R8 contains the maximum number of FF's (8). With this PAL each output pin is connected to the Q-output of a D flip-flop. In the PAL16R4, which has only 4 flip-flops, 4 registered output1ines and 4 bidirectional I/O lines are present. The (i-outputs of the D-FF's are fed back to the input stage of the programmable AND array. D-inputs may thus be programmed to be a function of both present state and input. The maximum number of product terms directly available for a D-input is 8. Optimization is only necessary if the number of product terms in an expression for a D-input is greater than the available number. Else optimization is optional. If after optimization the number of product terms is still greater than 8, a bidirectional I/O line could be used to expand the number of available product terms for a D-input. In that case an extra delay of 25 ns is introduced, because the function is realized with an extra AND-OR stage (the bidirectional I/O line). The maximum clock frequency for which proper functioning of these PAL's is guarenteed is 16 Mhz if no bidirectional I/O lines are used for extra product terms. Logic DI.grllm PAL taRS 112 v , ,::: " "',., '" """" ""'" ,',"," '" s:r :B:::i .L ~ -'" • I r " fEl--., ~ ~rt ~ ~ =8=l U1 == ~ P1 ~ C>- :B::I'" '01 ~ =B=t- r-c Pl -j; = ,.-~ ~ n- " .i ~ I ,-< " ,i,i, ,',;, ;,' , ;,' Logic DIal...... PAL1 ...... ~ " , , .L -<->--t ~ I -'" .a ~ .1 :e:::r- J == .--:1f11- -<>- ~ Figure 8.10 ...... , "J.. Logic diagrams of ~ =r all PAL's with ~ registered outputs ::c:t ~ M .- , '18-...... , "J.. ~ I , LL1 -<> J , J , ' , , g::J .J. X ,-:g:= - I --- ~~'" ~ i~',,' ,11t !H I" I <- ~, •• 113 8.2.2. PAL's with Exclusive-OR In the PAL's with registered outputs the number of product terms in the expression for a D-input should be less than eight. unless bidirectional 1/0 lines are available and extra delays are allowed. To get around this problem other PAL's have been designed. In these PAL's the D-input of a flip-flop is generated by an Exclusive-OR function of two sum terms. Each sum term is built of two product terms (see figure 8.11). ,Jill n!IIII~~lillllllll~· P2 P3 Figure 8.11 General structure of aD-input of a flip-flop in the PAL's with Exclusive-OR By this Exclusive-OR configuration complex switching functions may be realized for the D-input of a flip-flop. In this structure the general expression for a D-input is: D = (P 0 + PI) $ (P 2 + P 3) (1) Working out the Exclusive-OR function leads to: This expression may be further expanded by noting. that Pi is a product term. As an example let: Po AB Po A + ii PI = CD PI C + ii P 2 = EF P2 E + F P3 = GH P3 G + ii 114 Then: D KeEF + KiiEF + BeEF + BiiEF + KeGH + KiiGH + BeGH + iiiiGH + ABEG + ABEH + ABFG + ABFH + CDEG + CDEH + CDFG + CDFH (3) The D-input of a flip-flop may thus be realized as a large sum of product terms. However, it should be noted that in practice the first expression (1) should be derived from the third (3). This derivation is not trivial snd may be a laborious task. Sometimes the Exclusive-OR function may be recognized at the outset. This for example is the case with counter circuits. In counters no external inputs, except the clock signal, are required. Coding of the states is generally such that Exclusive -OR functions are required at the D-inputs of the flip-flops. In sequential circuits that have external inputs, triggering the state transitions, Exclusive-OR functions may be present (compare the example shown in the previous paragraph) but are generally harder to detect. Figure 8.12 shows the logic diagrams of the three PAL's that have the Exclusive-OR function integrated. The maximum clock frequency for these PAL's is 14 Mhz. This frequency is lower than the frequency guaranteed for the PAL's with registered outputs. This is due to the presence of the Exclusive-OR gate between the (fixed) OR-array and D-inputs which causes an extra delay of 10 to 15 ns. Logic Diagram PAL20X10 115 Logic Diagram PAL20X 8 !>- ... ' , .--j...... "II : ~:: ,tr---+~ :.l:4-4~, . ' D " J " , . LI1'B- , , , , , ': I , ", " , ,.~. , , :11" I I, :-I' IT '''''Tr , I :RJ>., ~ " +11=+" i. I .. =;+r=t1 ...... -+- t1i-f-" . h";+'''''--+-r g'B-!I" , I' ,: ~ " :l , "",~, t-:. '~l----.:I-- -- ~ ! ~·-.:~rl-l""' ~4"t tt, ' 'tEE f1 ~--'-j-t-- :.:-: , l' ~-1i:Rn. " , ~jr 'r-i"' 1+-. :..;;.r:. ,JL>-~ ~ , ' I , "I , ' .".~ '~ II I ...J , , ~ Ii===="l ttT ,! " Logic Diagram PAL20X4 Figure 8.12 Logic diagrams of the PAL's wi th Exclusive-OR 116 8.2.3 PAL's with arithmetic gated feedback In the PAL's with arithmetic gated feedback the Q-outputs of the FF's are not directly fed back to the programmable AND array. In these PAL's each Q-output is connected with a two input combinational network that realizes all 4 combinations (maxterms) of two input variables, viz: A + B A + B A + ii A + B The second input variable of this network is a direct input line of the PAL. The 4 outputs of this combinational network are presented as inputs to the programmable AND-array. Figure 8.13 illustrates the logic diagrams of the two PAL's of this category. Because of the special combinational circuitry each of the 16 possible functions of two variables may be reslized with one productline only as indicated in figure 8.14. This feature allows for the possibility to program arithmetic functions that normally would require several PAL's, with one PAL only. For an example the reader is refered to the "PAL programmable array logic handbook" of MMI, which comprizes an ALU/accumulator application realized with the PAL16A4. Note that there is no real difference between the PAL16X4 and PAL16A4 except the preprogrammed functions present in the PAL16A4. Due to this preprogrammed functions it was possible to realize the ALU/accumulator application with one PAL. For the PAL's with arithmetic gated feedback a maximum clock frequency of 12.5 Mhz is gusranteed. Logic Diagram PAL18X4 Logic Diagram PAL1 8A4 {>--- --~ v ,," .. " """ """" """" ',"""- ""." " .. " b l R • i " ~ ~J[ " ~D~'J" ; r.t" " ~D c ~ ~ R" :"~ . h ": ~lD !§ ~ : " : ~ !,~ ~ n" =8=r r'-' ~ =J-.J §-,J ! i ." =J-. J i " " ~ '" ", Figure 8.13 Logic diagrams of the PALos with arithmetic gated feedback 118 }----i+8 f----ii }----l... e f---a }----i·s )----... :+:8 }-___.. a }---A }-__A.I }----. f---A.a )----":.:8 }---i'l }---I f---A_. A_a A_a -A_a Figure 8.14 Realiztion of each of the 16 possible functions of two input variables uaing the special combinational circuitry and a productline 119 REFERENCES (1) INTEGRATED CIRCUITS. Part 10: Signetics integrated fuse logic (IFL). Eindhoven: Philips Electronic Components and Materials Division, May 1983. Philips data handbook, IC 10. (2) Birkner, J.M. and V.J. Coli PAL HANDBOOK: Programma~array logic. 3rd ed. Santa Clara, Calif.: Monolithic Memories, 1983. (3) Larson, T.L. and C. Downey FIELD PROGRAMMABLE DEVICES. Electron. Eng., Vol. 52, No. 633(Jan. 1980), p. 37-54. (4) Ashenhurst, R.L. THE DECOMPOSITION OF SWITCHING FUNCTIONS. Reprint in: H.A. Curtis, A new approach to the design of switching circuits. New York: Van Nostrand, 1962. P. 571-602. (5) Ashenhurst, R.L. NONDISJOINT DECOMPOSITION. Reprint in: H.A. Curtis, A new approach to the design of switching circuits. New York: Van Nostrand, 1962. p. 620-630. (6) Curtis, H.A. A NEW APPROACH TO THE DESIGN OF SWITCHING CIRCUITS. New York: Van Nostrand, 1962. (7) Blakeslee, T.R. DIGITAL DESIGN WITH STANDARD MSI AND LSI: Design techniques for the microcomputer age. 2nd ed. New York: Wiley, 1979. (8) Shen, V. Yun-Shen and A.C. McKellar ~LGORITHM FOR THE DISJUNCTIVE DECOMPOSITION OF SWITCHING FUNCTIONS. IEEE Trans. Comput., Vol. C-19(1970), p. 239-248. EINDHOVEN UNIVERSITY OF TECHNOWGY EINDHOVEN UNIVERSITY OF TECHNOWGY THE NETHERLANDS THE NETHERLANDS DEPARTMENT OF ELECTRICAL ENGINEERING Coden: TEUEDE DEPARTMENT OF ELECTRICAL ENGINEERING Coden: TEUEDE Eindhoven University of Technology Research Reports (ISSN 0167-9708) Eindhoven University of TechnologY Research Reports (ISSN 0167-9708) : ( 127) Damen. A.A.H., P.M.J. Van den ~ and A.K: Haj?asin~ki (138) Nicola, V.F. ~AGE MATRIX: An excellent tool for nOlse fllterlng of Markov A SINGLE SERVER QUEUE WITH MIXED TYPES OF INTERRUPTIONS: parameters, order testing and realization. Application to the modelling of checkpointing and recovery EUT Report 82-E-127. 1982. ISBN 90-6144-127-7 in a transactional system. EUT Report 83-E-138. 1983. ISBN 90-6144-139-2 ( 128) Nicola V.F. ~LAN MODELS OF A TRANSACTIONAL SYSTEM SUPPORTED BY CHECKPOINTING (139) Arts, J.G.A. and W.F.H. Merck AND RECOVERY STRATEGIES. Part I: A model with state-dependent TWO-DIMENSIONAL MHO BO~LAYERS IN ARGON-CESIUM PLASMAS. parameters. EUT Report 83-E-139. 1983. ISBN 90-6144-139-0 EUT Report 82-E-128. 1982. ISBN 90-6144-128-5 (140) Willems, F.M.J. COMPUTATION OF THE WYNER-ZIV RATE-DISTORTION FUNCTION. ( 129) Nicola, V.F. NG MARKOVIAN MODELS OF A TRANSACTIONAL SYSTEM SUPPORTED BY CHECKPOINTl EUT Report 83-E-140. 1983. ISBN 90-6144-140-4 AND RECOVERY STRATEGIES. Part 2: A model with a specified number of completed transactions between checkpoints. (141) Heuvel, W.M.C. van den and J.E. Daalder, M.J.M. Boone, L.A.H. Wilmes EUT Report 82-£-129. 1982. ISBN 90-6144-129-3 INTERRUPTION OF A DRY-TYPE TRANSFORMER IN NO-LOAD BY A VACUUM CIRCUIT-BREAKER. EUT Report 83-£-141. 1983. ISBN 90-6144-141-2 (130) LP.mmens, W.J.M. ~ p~PROCESSOR: A precompiler for a language for concurrent processing on a multiprocessor system. (142) Fronczak, J. EUT Report 82-E-130. 1982. ISBN 90-6144-130-7 DATA COMMUNICATIONS IN THE MOBILE RADIO Cr.A~'NEL. EUT Report 83-E-142. 1983. ISBN 90-6144-142-0 (!31l Eijnden, p.M.e.M. van den, H.M.J.M. Dortmans, J.P. Kemper and (143) Stevens, M.P.J. en M.P.H. van Loon M.P.J. Stevens EEN MULTIFUNCTIONELE IjO-BOUWSTEEN. JOBHAND~ A NETWORK OF DISTRIBUTED PROCESSORS. EUT Report 84-E-143. 1984. ISBN 90-6144-143-9 'EUT Report 82-E-131. 1982. ISBN 90-6144-131-5 (144) Dijk, J. and A.P. Verlijsdonk, J.e. ~ ( 132) Verlijsdonk, A.P. DIGITAL TRANSMISSION EXPERIMENTS WITH THE ORBITAL TEST SATELLITE. ON THE APPLICATION OF BIPHASE CODING IN DATA COMMUNICATION SYSTEMS. EUT Report 84-E-144. 1984. ISBN 90-6144-144-7 EUT Rf'port 82-E-132. 1982. ISBN 90-6144-132-3 (145) ~, M.J.M. van (133 ) Hei1nen, e.J.H. en B.H. van ~ MINIMALISATIE VAN PROGRAMMABLE LOGIC ARRAYS. METEN EN BEREKENEN VAN PARAMETERS BIJ HET SILDX-DIFFUSIEPROCES. EUT Report 84-E-145. 1984. ISBN 90-6144-145-5 EUT Report 83-E-133. 1983. ISBN 90-6144-133-1 (146) Jochems, J.e. en P.M.C.M. van den Eijnden ~Z:rn:; IN SE;XJENl'IELE CllCUITS. ~, Th.G. van de and S.C. van Sameren Greve ( 134) EUT Report 65-E-146. 1965. ISBN 90-6144-146-3 A METHOD FOR SOLVING BOLTZMANN'S EQUATION IN SEMICONDUCTORS BY EXPANSION IN LEGENDRE POLYNOMIALS. (147) Rozendaal, L.T. en M.P.J. Stevens, P.M.e.l.t. van den Eijnden EUT Report 83-£-134. 1983. ISBN 90-6144-134-X DE REALISATIE VAN BEN MULTlFUNCTIONELE I/O-CONTROLLER MET BEHULP VAN &EN GATE-ARRAY. (135) Ven. H.H. van de EUT Report 85-&-147. 1985. ISBN 90-6144-147-1 TIME-OPTIMAL CONTROL OF A CRANE. EUT Report 83-E-135. 1983. ISBN 90-6144-135-8 I, i 36) Huber C. and W.J. Bogers ~~HULER PRINCIPLE: A discussion of some facts and misconceptions. EUT Report 83-E-136. 1983. ISBN 90-6144-136-6 ( 137) Daalder, J.E. and E.F. Schreurs ~PHENOMENA IN HIGH VOLTAGE FUSES. EUT Report 83-E-137. 1983. ISBN 90-6144-137-4