A course on field programmable logic Citation for published version (APA): van der Eijnden, P. M. C. M. (1985). A course on field programmable logic. (EUT report. E, Fac. of Electrical Engineering; Vol. 85-E-148). Eindhoven University of Technology. Document status and date: Published: 01/01/1985 Document Version: Publisher’s PDF, also known as Version of Record (includes final page, issue and volume numbers) Please check the document version of this publication: • A submitted manuscript is the version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. 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If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the “Taverne” license above, please follow below link for the End User Agreement: www.tue.nl/taverne Take down policy If you believe that this document breaches copyright please contact us at: [email protected] providing details and we will investigate your claim. Download date: 25. Sep. 2021 A Course on Field Programmable Logic By P.M.C.M. van den Eijnden EUT Report 85-E-148 ISBN 90-6144-148-X ISSN 0167-9708 April 1985 Eindhoven University of Technology Research Reports EINDHOVEN UNIVERSITY OF TECHNOLOGY Department of Electrical Engineering Eindhoven The Netherlands A COI}RSE ON FIELD PROGRAMr~ABLE LOGIC by P.M.C.M. van den Eijnden EUT Report 85-E-148 ISBN 90-6144-148-X ISSN 0167-9708 Coden: TEUEDE Eindhoven Apri 1 1985 i i First printing January 1983. Second printing April 1985. Third printing July 1985. CIP-GEGEVENS KONINKLIJKE BIBLIOTHEEK, DEN HAAG Eijnden, P.M.C.M. van den A course on field programmable logic / by P.M.C.t'l. van den Eijnden. - Eindhoven: University of Technology. - Fig. - (Eindhoven University of Technology research reports / Department of Electrical Engineering, ISSN 0167-9708; 85-E-148) r4et lit. opg., reg. ISBN 90-6144-148-X SISO 664.2 UDC 681.325.65.02 UGI 650 Trefw.: schakeltechniek/ programmeerbare logicabouwstenen. iii Acknowledgements In these course notes logic diagrams of available programmable devices are used in order to clarify the structures of these devices. For the diagrams of IFL devices the "Signetics Integrated Fuse Logic" handbook (Ref. 1) of Phil ips has been used. The diagrams of the PAL's are from the "PAL Handbook" (Ref. 2) of Monol ithic Memories Inc. (MMI). Signetics Corporation, 811 East Arques Avenue, P.O. Box 409, Sunnyvale, CA 94086 Monolithic Memories, 2175 Mission College Blvd., Santa Clara, CA 95050 iv ABSTRACT This report gives a survey of programmable logic components that can be used to real ize both combin,atlonal and sequential logic circuits. A general structure for these components is determined starting with boolean equations and state diagrams respectively. The considerations with respect to optimization and decomposition of a'circuit, that play an important role when designs are made with these components are discussed. To complete the survey several commercially available products are passed in review. Eijnden, P.M.C.M. van den A COURSE ON FIELD PROGRAMMABLE LOGIC. Department of Electrical Engineering, Eindhoven University of Technology (Netherlands), 1985. EUT Report 85-E-148 Address of the author: ir. P.M.C.M. van den Eijnden, Digital Systems Group, Department of Electrical Engineering, Eindhoven University of Technology, P.O. Box 513, 5600 MB EINDHOVEN, The Netherlands v CONTENTS 1. INTRODUCTION 1 2. COMBINATIONAL LOGIC 3 3. REALIZATION OF SWITCHING FUNCTIONS 5 3.1 Singular standard gates 5 3.2 Hypothetical programmable array for logic functions 5 3.3 Programmable arrays versus standard parts 21 3.4 Programming the array 23 4. AVAILABLE PROGRAMMABLE ARRAYS 34 4. 1 (P) ROM 34 4.2 (F) PLA 36 4.3 (F)PGA 46 4.4 PAL (HAL) 51 5. DESIGN PROBLEMS USING PROGRAMMABLE ARRAYS 65 5.1 Product term expansion 65 5.2 Output expansion 73 5.3 Input expansion 75 6. SEQUENTIAL LOGIC 81 6.1 General model for sequential circuits 81 6.2 Memory elements 82 6.3 Synchronous and asynchronous sequential circuits 84 6.4 Representation of synchronous sequential systems 86 7. REALIZATION OF A SYNCHRONOUS CIRCUIT 91 7.1 Singular gates 91 7.2 Progammable arrays 92 7.3 Hypothetical programmable array with state register 97 8. AVAILABLE PROGRAMMABLE SEQUENCERS 99 8.1 (F)PLS 99 8.2 PAL (HAL) III REFERENCES 119 1 1. INTRODUCTION Until now digital circuits for small production volumes could economically be realized only using so called standard parts: small scale and medium scale integration (SSI/MSI). At the moment however new components are available which may be regarded as a replacement of the parts mentioned above. They all have got a matrix structure and are known as: Programmable Arrays. Because digital circuitry can be divided into two major categories: Combinational Sequential the total number of arrays may also be grouped according to this classification. Therefore these course notes have also been divided in two major parts. The first part (chapter 1 - 5) deals with combinational logic. the second part (chapter 6 - 9) with sequential logic. However before going into detail about the components (arrays) we will first have to study the reasons for using them and the logical reasoning that is behind their structure. Hence part one starts with a short overview of combinational logic. From this a general array structure is determined. Knowing this general structure available components will be studied. The second part has been arranged in the same way. In this part we start with a short overview of sequential logic from which a general sequencer structure is determined. Then the available sequencers are studied. 2 3 2. COMBINATIONAL LOGIC From switching theory it is known that any sWitching function of n variables f(xi ,x2' •••• ,xn) may be expressed as a sum of products, where in each product every input variable appears in either its true or complemented form. Example: f (xl ,x2,x3,x4) xlx2 x 3x 4 + xlx2x3x4 + xlx2 x 3x 4 + --xlx2 x 3x 4 + xlx2 x 3x 4 + xlx2 x 3x 4 This form is called: standard normal form, full disj unctive normal form or sum of minterms, and is generally expressed as: mt = minterm; 81 = 0, 1 It is also known, that because of the duality principle, any switching function of n variables f(xi ,x2' •••• ,xn) may be expressed as a product of sums, where in each sum every input variable appears in either its true or complemented form. Example: The function of the previous example may also be written as: f(xI,X2,X3,X4) (xl + x2 + x3 + x4) • (xl + x2 + x3 + x4) • (xl + x2 + x3 + x4)· (xl + x2 + x3 + x4)· (xl + x2 + x3 + x4) • (xl + x2 + x3 + x4) • (xl + x2 + x3 + x4) • (xl + x2 + x3 + x4)· (xl + x2 + x3 + x4)· (xl + x2 + x3 + x4) 4 This form is known as: stan,dard product of sums, full conjunctive normal form or product of maxterms, aQd is generally written as: Mi = Maxterm; Gi Z 0, ! Neither of these standard forms is minimal. That is to say the number of product terms or sum terms as well as the nU!q}).e.r Q-f variables contained in these product terms or sum terms may be reduced. The mathematical rules according to which thi~ reduction may be accomplished are given by Boolean alg~b~~. Applying these rules to the example given above leads tQ: or 5 3. REALIZATION OF SWITCHING FUNCTIONS 3.1 Singular standard gates It may be stated that any switching function can be implemented using standard (TTL) AND, OR and NOT gates. The function of our example may be realized as: f (a) f (b) Figure 3.1 Realization of example function (a) sum of products (b) product of sums 3.2 Hypothetical programmable array for logic functions 3.2.1 General Considerations Considering the statement of paragraph 3.1, we may say it really would be practical to have one standard part only which comprises a number of the three types of gates in such a way that any switching function can be realized with this device by some wiring. Such a standard part might be realized in three stages. Stage 1 consists of a set of inverters (NOT) to generate the complemented form of input variables. The next stsge uses the output sigma1s of the first stage. This stage consists of a number of AND gates. These NOT-AND combinations generate the product terms. The third stage consists of an OR gate using the product terms and generating the desired function. The signals 6 from one stage may be used as input signals for the next stagE!' The signals are applied to the next stage by means of switches.