A Vhsic Hardware Description Language Compiler for Logic Cell Arrays
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A VHSIC HARDWARE DESCRIPTION LANGUAGE COMPILER FOR LOGIC CELL ARRAYS by Bing Liu A thesis presented to the university of Mânitoba in partial fulfillment of úe requirements of the degree of Maste¡ of Science in Elecrical and Computel Engineering Winnipeg, Manitoba, Canada @ Bing Liu, January 1990 Bibliothèque nat¡onale rE fr"3""i"i;tjo'",' du Canada Canadian Theses Serv¡ce Service des thèses canadiennes Otta'¿/ã. Can¿da Kl A ON¡ The author has granted an inevocable non' L'auteur a accordé une licence iffévocable et exclusive licence allowing the National Library non exclusive permettant à h Bibliothèque of Canada to reproduce, loan, distribute or sell nationale du Canada.de reproduire, prêter, copies of his/her thesis by any means and in distribuer ou vendre des copies de sa thèse any form or format, making this thesis avaihble de quelque manière et sous quelque forme to ¡nterested persons. que ce soit pour mettre des exemplaires de cette thèse à la disposition des personnes intéressées. The author retains ownership of the copyright L auteur conserve la propriété du droit d'auteur in his/her thesis. Neither the thesis nor qui protà?e sa thèse. Ni la thèse ni des extraits substantial extracts from it may be printed or substantiels de celle-ci ne doivent être otherw¡se reproduced without his/her per' imprimés ou autrement reproduits sans son mission. autorisation. ISBN ø-315-7 r7s t -3 Canadä A VHSIC HARDWARE DESCRIPTION I.ANGUAGE COMPILER FOR LOG]C CEI,L ARRAYS BY BING LIU A thesis subnrined lo thc Fact¡lty of Crâduate Studies of the University of M¿nitoba in partial fulfìllment of the requirenrents of the degree of MASTM O¡' SC]MICE o 1990 Permission has becn granted to the L¡BRÁRY OF THE UNIVER' SITY OF MANITOBA to lend o¡ sell copies of tlt¡s thesis. to the NATIONAL LIBRARY OF CANADA to tnicrofilm this thesis arìd to lend o¡ sell copies oí the film, and UNIVERSITY MICROFILMS to publish an abstract of ¡his thesis. Thc author rcscrves other publication righls, and neither thc thesis nor cxtensive extrects from it may be printeC or other' wise reproduced without the âuthor's written permission. ABSTRACT This thesis pfesents a development of a vHSIC Hardware Description Language (VHDL) compiler for Logic Cell Anays (LCAs). First, the concept of electronic circuit engineering and the electronic circuit development cycle using computer aided engineering (cAE) tools a¡e reviewed; and the motivation of this ¡esea¡ch work is provided. Then' the afchitecrure, design methodology and the significance of LCA a¡e described. Thirdly' the VHDL is briefly reviewed and a VHDL architectural description subset fo¡ LCA is defined as the input of the compiler; the Xilinx Netlist Format (XNF) is chosen as the target of the compiler. Finally, the development, testing and verification of the vHDL compiler for LCA is described. Two of the examples implemented from the vHDL descriptions are presented to demonsEate the compiler. ACKNOWLEDGEMENTS I wish to express my sincere thanks to Dr. Witold Kinsner, my advisor' and Dr. Robert D. Mclæod for their excellent guidance, endurable motivation and consistent support throughout the course of this lesea¡ch' My thanks go to Dr. William L. Kocay for his comments and suggestions on my rhesis. I am also grateful to M¡. J. Dickson, who helped me to simulate one of the examples, and all the other fellow students for their help. I would also like to thank my wife who helped me a geåt deai during my writing of this thesis, my pa¡ents, and family for their encouragement. The financial support of this research work provided by the National Science and Engineering Research council (NSERC) of canada thfough Dr. Kinsner's glant and Dr. Mcleod's $ant, canadian Microelectronics corporation, and the university of Manitoba is gratefutly acknowledged. The LCA Xilinx Netlist Format Specification and the LCA External Netlist Tool Kit provided by xilinx Inc. is also acknowledged. -lU- TABLE OF CONTENTS Pa ge ABSTRACT ii ACKNOWLEDGEMENT " iii TABLE OF CONTENTS """"""""' iv LIST OF FIGURES vl LIST OF TABLES vl11 LIST OF ABBREVIATIONS """""" ix CHAPTER 1: INTRODUCTION I J 1.1. Electronic Circuit Engineering """""""' J 1.1.1. Electronic Circuit Design '7 1.1.2. Programmable l,ogic Devices """"""" 1.1.3. Prototyping """""""' 8 1.2. Motivation 9 1.3. Thesis Objectives 10 1.4. Thesis Structure 11 t2 CHAPTER 2: XILINX LOGIC CELL ARRAYS """""""' 13 2. 1. A¡chitecure of Xilinx Logic Cell Arrays 2.1.1. Configurable Logic Blocks """"' 18 2.1.2. lnpuV0utput Blocks 18 18 2.1.3. Programmable Interconnections " " " " " " " 2.2. Xilinx LCA Devices 19 MethodologY 21 2.3. LCA Design 7) 2.3.1. Design Entries """""' 24 2.3.2. Design Implementation 25 2.3.5. Design Verification 26 2.4. Summary CHAFIER 3: THE VHSIC HARDWARE DESCRIPTION LANGUAGE 27 28 3. 1. Features of VHDL 29 3.1.1. Design EntitY """"" -lV- 29 3.1.2. Interface DescriPtion 3.1.3. Body DescriPtión " 30 30 3.1.3.1. A¡chiæctural Description 3.1.3.2. Dataflow DescriPtion 31 3.1.3.3. Behavioural Description ''"'""'""" 32 3.1.4. Types 34 3.1.5. Signals 35 3.1.6. Paikages 36 3.2. SupportedfuLSubset """"""""r"' """"""""""' 37 :.2.ì. InpuVOuçutP¡nDescription """""""" 37 38 3.2.2. Präefined TYPes for LCA 3.3. Summary 38 CHAPTER 4: A VHDL COMPILER FOR LCA DESIGN 40 4.1. læxical Analysis """""' 44 4.1.1. LEX A læxical Analyzer Generator 45 47 4.2. Parsing - 4.2.1. Y ACC Another Compiler Compiler 47 -Yet 49 4.3. Stack Machine .'"""""" 4.3.1. Stack Machine Instructions 50 4.3.2. Internal VHDL Representation (IVHDL) 53 4.4. Xilinx Netlist Format Generation 54 4.4.1. Intemal Xilinx Netlist Format (D(NF) and WriteNet 54 4.5 Flattening 54 CHAPîER 5: IMPLEMENTATION, TESTING AND VERIFICATION 56 5.1. Test 1: lGbit Liner Feedback Shift Regrster """""' 57 5.2. Test2: 4-bit ALU 61 CHAPTER 6: CONCLUSIONS AND RECOMMENDATIONS 67 REFERENCES 70 APPENDD( A: EXAMPLES AND SIMULATION RESULTS ""'""" 74 APPENDIX B: VHDL USER'S GUIDE 97 APPENDIX C: KEYVyORD LIST .."...".' 111 APPENDIX D: GRAMMAR OF SUPPORTED VHDL SUBSET """'' LT2 APPENDIX E: STANDARD XNF LIBRARIES LIST 116 120 APPENDIX F: PROGRAM LIST ..,..".... LIST OF FIGURES Figure Page 1 . I . Electronic circuit design process ''''"''''''' 4 1.2. Electronic circuit development cycle using CAE tools 6 2.1. The a¡chitectu¡e of Logic Cell Arrays 14 2.2. Configurable Logic Block (CLB): 3000 Series """"""' 15 2.3. Configurable Inpuy'Output Block (IOB): 3000 Series """""""' 16 2.4. hogrammable Interconnections: 3000 Se¡ies " " " " "'':' l7 2.5. LCA design process .. ' ." " " " ' ' 23 3. I . Interface description of a full adder " ' ' ' ' ' ' ' ' ' ' 30 3.2. Body descriptions of design entity JU 3.3. Architectural body description of a full adder " " " " "' 3i 3.4. Dataflow body descriptions of a full adder " " " " " ' 32 3.5. Behaviou¡al body description of a AND gate with interface description ' ' ' ' ' ' JJ 3 .6. VHDL t¡pe classification tree 34 3.7. Type declaration 35 3,8. Signal declaration .".".' " " "' 36 3.9. Package declaration """"""" 36 3. 10. Interface desøiption of a full adder with pin æsociation 38 4.1 The position of the VHDL compiler in the LCA design process " " " " " " " 4l 4.2 The structure of the VHDL compiler for LCA design "'"""' 43 4.3 The lexical analyzer of the VHDL compiler 45 4.4 The parser of the VHDL compiler 48 4.5 The stack machine of the VHDL compiler 5 1 4.6 Intemal VHDL representation 53 4.7 XiÏnx Netlist Format generation 56 5.1 The schematic of the 16-bit LFSR """""""' 58 5.2 The graphic ouçut of the simulation the 16-bit LFSR implemented from the schematic 59 5.3 The layout of the lGbit LFSR implemented from the VHDL description "' 60 5.4 The graphic output of the simulation of 16-bit LFSR implemented from the VHDL description 61 63 5 .5 The schematic of the 4-bit ALU 5.6 The graphic ouçut of the simulation of the 4-bit ALU implemented from the schematic 64 5.7 Thá layout of the 4-bit ALU implemented from the VHDL description ' ' ' ' ' 65 5.8 The graphic output of the simulation of 4-bit ALU implemented from the VHDL description 66 LIST OF'TABLES Table Pa ge z1 2.1 Xilinx l,ogic Cell Array device table " " " " ' 52 4.1 Stack machine instruction øble 62 5.1 The operation of the 4-bit ALU """""""' -vul- LIST OF ABBREVIATIONS ASIC Application Specific Integrated Circuit CÄD ComPuter Aided Design CAE Computer Aided Engineering CAT Computer Aided Testing CAV ComPuter Aided Verification CLB Configurable l,ogic Block. DRC Design Rule Checker IC Integrated Circuit IOB InpulOutPut Block MDL Intemal VHDL representation IXNF Intemal Xilinx Netlist Formåt HDL Ha¡dwa¡e Description Language LCA l,ogic Cellfr AnaY LFSR Linea¡ Feedback Shift Register. PAL Programrnable ArraY hgic PCB Printed Circuit Boa¡d PLD Programmable logic Device SMB Surface Mount Board VHSIC Very High Speed Integrated Circuit VHDL VHSIC Ha¡dware Desøiption Language VLSI Very Large Scale lntegration X N F Xilinx Netlist Format CHAPTER 1 INTRODUCTION The design of elecronic systems always involves the design of electronic ci¡cuits' (WSÐ often in the form of either integrated circuits (Cs) using very large scale integration design process of or very high speed ICs (VI{SIC)' or printed circuit boa¡ds (PCBs)' The description of the elecEonic ci¡cuits can be considered as a transformadon of a behaviourat A circuit concepts into a physical description of the ci¡cuits suitable for implementation. functional behavioural description is the highest level of abstraction, providing only the For example, the cha¡acteristics of ci¡cuits with no specified way of implementing them.