COPPER SULFIDE RESISTANCE CHANGE MEMORY

AND ITS SCALABILITY

A DISSERTATION

SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING

AND THE COMMITTEE ON GRADUATE STUDIES

OF STANFORD UNIVERSITY

IN PARTIAL FULFILLMENT OF THE REQUIREMENTS

FOR THE DEGREE OF

DOCTOR OF PHILOSOPHY

Sung-Woo Kim

June 2013

© 2013 by Sung-Woo Kim. All Rights Reserved. Re-distributed by Stanford University under license with the author.

This work is licensed under a Creative Commons Attribution- Noncommercial 3.0 United States License. http://creativecommons.org/licenses/by-nc/3.0/us/

This dissertation is online at: http://purl.stanford.edu/pr873fs7042

ii I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy.

Yoshio Nishi, Primary Adviser

I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy.

Paul McIntyre

I certify that I have read this dissertation and that, in my opinion, it is fully adequate in scope and quality as a dissertation for the degree of Doctor of Philosophy.

Philip Wong

Approved for the Stanford University Committee on Graduate Studies. Patricia J. Gumport, Vice Provost Graduate Education

This signature page was generated electronically upon submission of this dissertation in electronic format. An original signed hard copy of the signature page is on file in University Archives.

iii

Abstract

The increase of portable electronic devices such as cellular phones, digital cameras, and mp3 players is driving a rapid growth of the market for nonvolatile memories (NVMs). Today's most established NVM technologies are based on charge storage method. However, the scaling of current NVM technologies beyond 32 nm node of International Technology Roadmap for Semiconductors (ITRS) poses severe problems such as poor retention and unacceptable cross-talks among devices. To overcome these disadvantages and achieve high-speed, high-density, long-retention, and low-power NVMs, several new memory materials and technologies have been extensively investigated. Among new emerging materials and concepts, we investigate copper sulfide resistance change memory, which is one of the most promising candidates for future NMV, whose electrical resistance can be changed reversibly between two stable states.

In the first part of the study, we report fabrication and electrical characterization of micrometer-scale copper sulfide NVM devices. We have achieved synthesis of stoichiometric Cu2S using anodic polarization whose composition is analyzed by Rutherford backscattering (RBS), and fabricated μm-sized NVM devices in the sandwiched structure of a Cu/Cu2S/top electrode. The resistive switching is consistent and reproducible over 50 cycles for large-area devices and 200 cycles for small-area devices. Low SET and RESET voltages below 0.3 V for switching and a high OFF-state resistance to ON-state resistance ratio over 105 have been achieved.

iv

The ON-state resistance value, RON, does not change as the size of the devices shrinks indicating the conduction is localized while the OFF-state resistance, ROFF, increases with the device scaling. As a result, we can obtain a fascinating scaling result that

ROFF/RON ratio increases as the devices scale down.

In the second part of the study, we present for the first time a simple fabrication method of copper sulfide nanopillar arrays with a high aspect ratio using nanoporous templates created from self-assembled nanostructures of block copolymers (BCP) for NVM applications. With our proposed process, the high aspect ratio of copper sulfide nanopillars with 25 nm in diameter and 170 nm in height is generated. Due to the small distance of 40 nm between the nanopillars, characterization is performed using conductive atomic force microscope (CAFM). Our

7 nanopillar arrays exhibit a huge ROFF/RON ratio of 10 at a 2 μA current level. This low level of switching current demonstrates the possibility of low-power NVM devices.

v

Acknowledgements

Needless to say, this research would not have been possible without the support, encouragement, and guidance of many people. I would like to take this opportunity to express my appreciation to all those who in one way or another have contributed and extended their invaluable assistance throughout my fruitful graduate life at Stanford.

First and foremost, I would like to express my most sincere gratitude to my adviser, Professor Yoshio Nishi, for his kind continuous support and encouragement I can never forget. His kindness and calm smile with cheer has always been inspiring as

I hurdled all the obstacles in the completion of this work. His enthusiasm to research, his devotion to students, and his temperate life style will continue to serve as a role model for me in the future life. I have been very fortunate to have the best adviser anyone could hope for, and it was a great honor to have a chance to learn from him.

I would like to thank my co-adviser, Professor Paul McIntyre. He has provided valuable feedbacks on material analyses since the early stages of my researches. His expertise and insight on material science has really been crucial for this study. I would also like to thank another committee member, Professor H.-S. Philip Wong. Not only in project meetings, but also in a classroom has he provided me with key concepts and research trend of nonvolatile memories. I am also very thankful to Professor Samira

Guccione for agreeing to chair my oral defense.

vi

I am also grateful to Dr. James McVittie and Dr. Peter Griffin for their patient help. Dr. James McVittie was of particular help in building an electrochemical unit for anodic polarization and electroplating. Dr. Peter Griffin has helped me to solve many problems in device fabrication throughout my experiments. I also wish to acknowledge with gratitude the support of all Stanford Nanofabrication Facility staffs.

I am deeply indebted to Dr. Ho-Cheol Kim and Dr. Oun-Ho Park for the fabrication of block copolymer templates. Without their guidance, the scalability study of copper sulfide would not have been possible.

I have been fortunate to receive help from a number of amazing friends and colleagues throughout the years at Stanford. I am very thankful for their encouragement and companionship, without which I would have experienced a lot of struggles in settling down in USA.

No words could express my deepest thanks and love to my parents and sisters, especially to my mother. Her endless prayers, unconditional love, devotion, and hope have made what I am.

Finally, I cannot express enough gratitude and love to my wife, Jeesun. She always gives me absolute trust with bright smiles ever since our first date despite her own challenges in her career. Thank you for standing by me and believing in me always.

vii

Table of Contents

List of Tables x

List of Figures xi

1. Introduction 1

1.1. Market Trend of Portable Electronics and Semiconductor Memories ∙∙∙∙ 2

1.2. Successes of Flash Memory Scaling ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 5

1.3. Thesis Organization ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 7

2. Basics of Resistance Change Memory 10

2.1. Scaling Problems of Flash Memory ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 10

2.2. Basics of Resistance Change Memory ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 14

2.2.1. Cell Structure and Electrical Switching Behaviors ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 16

2.2.2. Basic Principles of Resistance Switching Mechanisms ∙∙∙∙∙∙∙∙∙∙ 20

2.3. Summary ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 25

3. Micrometer-Scale Copper Sulfide Resistance Change Memory Devices 30

3.1. Copper Sulfide Nanometer Switch ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 30

3.2. Large-Area Devices and Their Properties ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 33

3.2.1. Copper Sulfide Growth by Sputtering ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 33

3.2.2. Copper Sulfide Growth by Anodic Polarization ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 38

viii

3.3. Small-Area Devices and Their Properties ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 43

3.4. Summary ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 49

4. Copper Sulfide Nanopillar Arrays for NVM Applications 53

4.1. Basics of Block Copolymer ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 53

4.2. Cu2S Nanopillar Array Fabrication ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 55

4.2.1. BCP Template Fabrication ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 56

4.2.2. Cu Electroplating and Sulfidization ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 60

4.3. CAFM Measurements ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 64

4.3.1. CAFM Results of Cu2S Nanopillars with Template ∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 64

4.3.2. CAFM Results of Cu2S Nanopillars without Template ∙∙∙∙∙∙∙∙∙ 68

4.4. Summary ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 70

5. Conclusions 73

5.1. Summary of Dissertation ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 73

5.2. Future Works ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 75

ix

List of Tables

1.1 Key innovations of each technology node ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 6

2.1 Comparison between flash memory and alternatives ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 16

x

List of Figures

1.1 Global shipment of mobile phones ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 3

1.2 Global shipment of personal computers ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 3

1.3 Bit growth of NAND flash and DRAM ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 4

2.1 Schematic of flash memory cell ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 11

2.2 Basic operation of flash memory ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 12

2.3 Scaling trend of tunnel oxide thickness ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 13

2.4 FG coupling ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 14

2.5 Classification of memory technologies ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 15

2.6 Diagram of resistance change memory cell ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 17

2.7 Different types of switching behaviors ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 19

2.8 Classification of various switching effects ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 21

2.9 Switching mechanism based on ECM effect ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 23

3.1 Copper sulfide nanometer switch ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 32

3.2 Process flow of large-area devices ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 34

3.3 I-V characteristic of sputtered copper sulfide in a linear scale ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 35

3.4 Phase diagram of copper sulfide ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 37

3.5 Conductivity variation of bulk Cu2-xS with deviation from stoichiometry ∙∙∙∙ 37

3.6 Cu2S synthesis using anodic polarization ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 39

xi

3.7 XPS depth profile of as-grown Cu2S ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 41

3.8 SEM images of as-grown Cu2S by anodic polarization ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 41

3.9 I-V characteristics of Cu2S grown by anodic polarization ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 42

3.10 Process flow of small-area devices ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 45

3.11 I-V characteristics of small-area devices with 50 nm-thick Cu2S and Ti/Pt top

electrodes ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 47

3.12 RON, ROFF, and ROFF/RON ratio as a function of device size ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 48

3.13 RON, ROFF, and ROFF/RON ratio with different compliance currents ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 49

4.1 Schematics of BCPs ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 54

4.2 Cu2S nanopillar array fabrication flow ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 56

4.3 BCP template fabrication ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 58

4.4 45-tilted SEM images of templates etched by O2 plasma ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 59

4.5 Cross-sectional SEM images of the nanoporous template ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 60

4.6 Electrochemical processes for deposition and sulfidization of Cu ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 61

4.7 SEM images of Cu nanopillars after electroplating in 70 nm thick template on

a Pt substrate ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 62

4.8 SEM images of template-removed Cu2S nanopillars on Cu substrate ∙∙∙∙∙∙∙∙∙∙ 63

4.9 SEM images of Cu nanopillars remained on Pt substrate after template removal

∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 63

4.10 CAFM results of Cu2S nanopillars with 25 nm in diameter and an aspect ratio

over 6 in template ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 65

xii

4.11 Resistance vs. voltage of Cu2S nanopillars with 25 nm in diameter and an

aspect ratio over 6 in template ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 67

4.12 Retention characteristics of Cu2S nanopillars ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 68

4.13 CAFM results of template-removed Cu2S nanopillars with 25 nm in diameter

and an aspect ratio over 6 ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 69

4.14 I-V curves of Cu2S blanket film of which the surface has undergone the same

process as the template removal ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙ 70

xiii

Chapter 1

Introduction

As all of us have experienced during the past decade, one of the most relevant phenomena and changes in the consumer electronics market are the explosive growth of the portable and handheld electronics segment. Cellular phones, laptop computers, universal serial bus (USB) memory drives, digital camcorders and digital music players are some of the most obvious examples of the electronic gadgetry that are filling consumers’ pockets. This dramatic change in our daily lives has been enabled by consistent technology development of the flash memory, a type of nonvolatile memories (NVMs). Keeping pace with the increasing demand of the consumer electronics market, flash memories has become one of the main market segments in semiconductor industry. In spite of this rapid and phenomenal growth, however, the development is facing increasing level of technology challenges in shrinking down the size of devices.

This chapter begins with a brief overview of how the flash memory technology has obtained its importance in the semiconductor industry with the expansion of the portable electronics market. And we also explain the technical challenges of the flash memory technologies in terms of the scalability. Finally the contents of this dissertation will be introduced.

1. Introduction

1.1. Market Trend of Portable Electronics and

Semiconductor Memories

Over the past three decades, the semiconductor industry has grown and flourished with continuous and exponential increase of revenue [1.1]. This growth of the semiconductor industry was mainly spurred by the huge demand of the personal computer (PC) in the late 1980s and early 1990s [1.2]. However, this PC-dependent semiconductor market has started to face a significant turning point with the rise of the portable electronics market as new applications since the late 1990s. During past 10 years, various kinds of portable electronic devices such as cellular phones and notebook computers became widespread and are continuing to grow strongly. This market trend is illustrated clearly in Figure 1.1 and Figure 1.2 which show demands of mobile phones and computers respectively. In 2010, for example, 307 million units of smart phones were shipped showing 71% increase of the year-over-year growth rate and the demand of mobile PC’s already surpassed that of desktop PC’s [1.3].

2 1. Introduction

Figure 1.1 Global shipment of mobile phones [1.3]

Figure 1.2 Global shipment of personal computers [1.3]

As the primary driver of end-use demand in the semiconductor industry, the emergence of the consumer electronics market requires a new type of memories which can bring portability to electronic products, a key defining feature of most consumer electronics today. In order to equip electronic products with portability, new types of memory devices must have some essential key attributes such as nonvolatility, the

3 1. Introduction capability to retain data even when the electrical power is removed. For example, cellular phones, one of the most popular portable electronics of nowadays, need data storage to save and store called numbers of favorites which would be erased without the nonvolatility of memories.

This new need for nonvolatility has promoted the tremendous growth of flash memory market and made the flash memory a leading technology driver of the semiconductor industry. The rise of the flash memory market is represented apparently in Figure 1.3 showing that the bit growth of flash memories already exceeded that of dynamic random access memories (DRAM’s) in 2006 and is increasing at an unprecedented pace in response to the demand of the market. In addition to the nonvolatility, it is the scalability of the device that has enabled this outstanding market growth. The next section will review shortly continuous successes of flash memory scaling.

Figure 1.3 Bit growth of NAND flash and DRAM [1.3]

4 1. Introduction

1.2. Successes of Flash Memory Scaling

We saw in the preceding section that during the past decade the demand of portable electronics have expanded enormously and now dominate the overall consumer electronics market. And this remarkable change has been expedited by the continuous development of flash memories which allowed previous electronic products to adopt mobile and miniature qualities they did not have before.

Figure 1.4 Scaling history of flash memories

Historically the development of flash memory technology has been focused mainly on how to integrate more device cells in the same silicon area, that is, increasing the memory density. Figure 1.4 presents the scaling history of the flash

5 1. Introduction memory with a cross-section image of each technology generation. Every technology node, of course, requires a number of significant innovations. Table 1.1 lists some key examples of these innovations [1.4]. Thanks to the continuous and relentless efforts for the device scaling, the cell size was shrunk down by about 3 orders during past 20 years as denoted in the figure. Consequently, the incredible reduction of cost per bit has been made; the price for flash memory dropped from approximately $80,000 per gigabyte in 1987 to less than $1.5 per gigabyte in 2008 [1.5].

Table 1.1 Key innovations of each technology node [1.4]

6 1. Introduction

With the device size being scaled down to the sub-100 nm regime, however, the geometrical shrinkage of the device faces more serious and fundamental challenges. Some of the crucial limitations are scaling of the channel length and the tunneling oxide thickness, which will affect badly the nonvolatile characteristic of the flash memory [1.6]. Therefore, it has become increasingly important to find alternative

NVM technologies that can potentially replace conventional flash memories when they reach their limits. This study will investigate electrical and material properties of copper sulfide resistance change memory, one promising candidate of these alternatives, highlighting its scalability.

1.3. Thesis Organization

This dissertation is organized into 5 chapters, beginning with the current chapter introducing the semiconductor market trend.

In Chapter 2, scaling problems as well as basic functioning of flash memory cell are introduced and the concept of resistance change memory including typical electrical switching behaviors and their mechanisms are explained.

Chapter 3, starting with a brief introduction of copper sulfide memories, explains how micrometer-scale devices are fabricated in our study and shows their characteristics.

7 1. Introduction

After demonstration of resistance switching in Chapter 3, the scalability of the copper sulfide is explored in Chapter 4 using block copolymer templates.

Finally Chapter 5 summarizes our whole investigation on the copper sulfide resistance change memory.

8 1. Introduction

References

[1.1] M. L. Hammond, “Semiconductor Device Revenue: 1950-2010,”

Semiconductor International, p. 102, July 2004.

[1.2] R. Gordon, “Semiconductor Market Trends,” SiliconIndia, p. 30, September

2006.

[1.3] Gartner Dataquest, September, 2011.

[1.4] S. K. Lai, “Flash memories: Successes and challenges,” IBM Journal of

Research and Development, vol. 52, p. 529, 2008.

[1.5] S. K. Lai, “Non-volatile Memory Technologies: The Quest for Ever Lower

Cost,” IEEE International Electron Devices Meeting, 2008.

[1.6] A. Fazio, “Flash Memory Scaling,” MRS Bulletin, 2004.

9

Chapter 2

Basics of Resistance Change Memory

As reviewed in Chapter 1, the explosive growth of portable electronics market has been sustained by the continuous development of flash memory technologies, particularly represented by successes in scaling of the device. However, further scaling to satisfy increasing demand from the market is being challenged by several fundamental issues.

We begin this chapter with an introduction of these problems as well as basic functioning of flash memory cell, and explain the concept of resistance change memory including typical electrical switching behaviors and their mechanisms.

2.1. Scaling Problems of Flash Memory

2. Basics of Resistance Change Memory

Figure 2.1 Schematic of flash memory cell

A conventional flash memory cell is shown schematically in Figure 2.1. As it can be easily recognized in the schematic, the device structure is basically similar to a standard metal-oxide-semiconductor field effect transistor (MOSFET) except that it has an additional gate called a floating gate (FG) and another dielectric separating the

FG from the control gate (CG). The floating gate is electrically isolated so that it can work as a storing electrode of the electrons injected from the substrate. The dielectric between the FG and the CG is typically formed by a triple layer of oxide-nitride-oxide

(ONO) layers, and generally called an inter-poly dielectric (IPD) as a whole because the gates are usually made of poly-silicon [2.1].

Since the electron charges can be retained in the FG, one bit of data can be stored in the memory cell by simply adding or removing electrons as illustrated in

Figure 2.2. The operations adding and removing electrons are called ‘programming’ and ‘erasing’, respectively.

11 2. Basics of Resistance Change Memory

Figure 2.2 Basic operation of flash memory (a) programming by FN tunneling or hot carrier injection (b) erasing by FN tunneling

For programming operation, two methods, hot carrier injection or Fowler-

Nordheim (FN) tunneling, are commonly used to inject electrons from the substrate through the tunneling oxide, depending upon the memory array architectures [2.1, 2.2].

For erasing operation, on the other hand, removing electrons from the FG is achieved by the FN tunneling regardless of the architectures [2.1, 2.2].

The concept of storing data in the FG and the mechanisms of programming and erasing start to cause serious problems in scaling as the device size and the distance between cells shrinks down to the nanometer regime. Since the data are stored in the

FG, the tunneling oxide must be thick enough to prevent the leakage of charges; otherwise, the data might be lost or changed. Figure 2.3 shows clearly that the thickness is not scalable, saturated at around 6 – 8 nm [2.3]. Moreover, as the memory cell is scaled down, the cell capacitance is decreased, resulting in a decrease of stored charge. Thus, the scaling of the tunnel oxide thickness exacerbates the reliability of data with the cell scaling.

12 2. Basics of Resistance Change Memory

Figure 2.3 Scaling trend of tunnel oxide thickness [2.3]

Another significant limiter of scaling is the high voltage necessary for the hot carrier injection. In order to generate hot electrons to overcome the energy barrier between the substrate and the tunneling oxide, a voltage of more than 3.2V is required between the drain and the source [2.4]. Therefore, scaling the gate length will be limited to the channel length that can endure the high programming voltage.

In conjunction with the problems from the cell size scaling as explained above, cell-to-cell interference, represented by capacitances in Figure 2.4 (a), becomes more severe with scaling of the distance between cells [2.5]. As the FG-to-FG space becomes closer, parasitic capacitive coupling among neighboring cells increases provoking undesirable fluctuations in the state of the cell such as a threshold voltage

(Vt) shift. Figure 2.4 (b) shows that the interference approaches 50 percent of the total

Vt shift of the cell in the 20 nm node [2.6]. Especially, this scaling problem is more

13 2. Basics of Resistance Change Memory troublesome with the advent of multi-level cells (MLCs) which require tighter control of Vt distributions.

.

Figure 2.4 FG coupling (a) diagram showing FG coupling (b) cell-to-cell interference as a function of technology node [2.6]

2.2. Basics of Resistance Change Memory

Despite remarkable and continuous successes in the device scaling during past

20 years, further scaling of the flash memory has some inherent limits in both the thickness of the tunneling oxide and the gate length as discussed in the previous section. Since these problems originate from the basic concept of the flash memory, numerous novel memory technologies with different approaches and materials have been studied extensively as candidates for next generation NVMs. Some candidates

14 2. Basics of Resistance Change Memory include phase change memory (PCM), ferroelectric random access memory (FeRAM), magnetoresistive random access memory (MRAM), resistance change memory (also termed resistive random access memory, short RRAM), and so forth. Figure 2.5 shows various memories categorized by the International Technology Roadmap of

Semiconductor (ITRS).

Figure 2.5 Classification of memory technologies [2.7]

Among these NVMs, FeRAM and MRAM technologies were highlighted and investigated earlier due to inherent fast switching speed. However, the fabrication of the devices is not compatible with the standard CMOS technology. Most of all, large unit cell areas over 10 F2 where F is the minimum feature size, as compared in the

Table 2.1, limit their applications only to niche markets [2.8]. On the other hand,

15 2. Basics of Resistance Change Memory resistance change memory with a new concept based on electrically switchable resistance has demonstrated its excellent scalability potential, attracting considerable attention as a promising candidate for future NVMs.

Table 2.1 Comparison between flash memory and alternatives [2.9]

This section discusses the resistance change memory device structure and typical electrical switching characteristics, followed by introducing the resistive switching mechanisms, particularly the mechanism involving reduction-oxidation reactions and ionic transport processes although some of them are still poorly understood.

2.2.1. Cell Structure and Electrical Switching Behaviors

16 2. Basics of Resistance Change Memory

Basically a switching memory cell of resistance change memory is a simple capacitor-like structure where a resistive switching material is sandwiched between two metal electrodes as shown in Figure 2.6. Because of the structure simplicity, a large number of materials have been explored and reported to show the resistive switching. The switching materials include binary and multinary metal oxides (e.g.

NiO, TiO2, SrTiO3) [2.10 – 2.12], solid electrolytes (e.g. Ag2S, Cu2S, AgGeSe) [2.13

– 2.15], and even organic polymers [2.16].

Figure 2.6 Diagram of resistance change memory cell

The resistance change memory cell has at least two distinctive resistance states, a high resistance state (HRS) and a low resistance state (LRS). They are commonly referred to as an OFF-state and an ON-state, respectively. Its resistance state can be changed back and forth between the two states by applying appropriate electrical signals such as voltage pulses. The operation switching the HRS to the LRS is termed

‘SET’ or ‘WRITE’ and the reverse switching operation ‘RESET’ or ‘ERASE’.

Typical DC current-voltage (I-V) characteristics of resistance change memory devices are sketched in Figure 2.6. When the voltage between two electrodes is

17 2. Basics of Resistance Change Memory

increased beyond a threshold level, normally called a SET voltage (VSET) or an ON voltage (VON), the device changes its resistance state abruptly from OFF-state to ON- state. It stays in the ON-state until a voltage larger than another threshold level, called a RESET voltage (VRESET or VOFF) is applied. When the voltage is swept over VRESET, the device in the conducting state is reset back to the OFF-state. During the SET and

RESET processes, the current is usually limited by the current compliance (cc) of the connected circuit or the measuring equipment in order to prevent the device from over-programming or burning.

18 2. Basics of Resistance Change Memory

Figure 2.7 Different types of switching behaviors (a) unipolar switching (b) bipolar switching

The switching modes of most resistance change memory devices can be grouped into two types with respect to the electrical polarity: unipolar switching and bipolar switching as shown in Figure 2.7 (a) and (b), respectively. In the unipolar switching, the switching behavior does not depend on the polarity of VSET and VRESET, and the VSET is always larger than the VRESET [2.17]. In contrast, the switching behavior is called bipolar when the set operation occurs on one polarity of the voltage and the reset operation requires the reversed polarity; the polarities of VSET and VRESET

19 2. Basics of Resistance Change Memory are different from each other. The resistance change memory cells showing the bipolar switching tend to have some asymmetry in the device configuration such as different electrode materials.

2.2.2. Basic Principles of Resistance Switching Mechanisms

Historically the first report on resistance switching phenomenon in oxide insulators dates back to the early 1960s [2.18]. In this paper, Hickmott reported that hysteresis of I-V curves can be observed in metal-insulator-metal (MIM) structures of

Al/Al2O3/Al, explaining applied electric field causes the hysteretic switching. This observation triggered many researches on resistive switching of a variety of materials in the MIM structure. In spite of huge amounts of publication about the resistance switching, unfortunately, their mechanisms have not been elucidated yet, and occasionally controversial interpretations were proposed in the literature.

Identifying the exact mechanism of the resistance switching is a really difficult task because various physical and chemical effects can provoke the resistance switching of materials as listed in the examples in Figure 2.7. Moreover, some of the effects may come into play in the switching phenomena simultaneously, making it more challenging to find out which one is a dominant origin.

20 2. Basics of Resistance Change Memory

Figure 2.7 Classification of various switching effects [2.8]

Among several switching mechanisms proposed in the papers, the mechanism involving ion migration will be introduced in this section, with more emphasis on the mechanism with cation migration and redox processes because it provides a decisive mechanism for the bipolar resistive switching of copper sulfide resistance change memories.

Resistive switching materials relying on the migration of anions are usually transition metal oxides. Since oxygen ion related defects, typically oxygen vacancies,

21 2. Basics of Resistance Change Memory are much more mobile than cations in most of the transition metal oxides [2.18], the switching is believed to be activated by the transport of oxygen ions inducing local changes of the material properties such as stoichoimetry and defects distribution.

Although numerous different models have been proposed regarding the details of these changes, the exact microscopic processes are still not clear. Among these, one prevailing model is formation and rupture of local conduction filaments during the switching.

For this type of switching, an electroforming process is initially performed to the virgin sample by applying high electrical stress. The electroforming process puts the device in the ON-state by a filamentary breakdown of the metal oxide. During the

RESET process, Joule heating disrupts the filaments thermally switching the device to the OFF-state. The device can be switched back to the ON-state by applying a voltage larger than VSET. Since the electrical breakdown and Joule heating do not depend on the voltage polarity, the transition metal oxides show the unipolar switching behavior.

Meanwhile, the bipolar switching of copper sulfide can be explained more clearly by the electrochemical metallization (ECM) mechanism [2.8]. In short, the switching operation of the ECM cell is based on mobile cation migration and electrochemical reactions to form and destruct electrically conductive bridges between two electrodes. Therefore, one of the two electrodes of the memory cell is made of an electrochemically active metal such as silver (Ag) and copper (Cu), and materials having good ion mobility are inserted between two electrodes so that the cations can be migrated by applied voltage. Solid electrolytes, known as super-ionic conductors, are good examples of resistive switching materials used in most ECM memory devices.

22 2. Basics of Resistance Change Memory

The counter electrode (CE) where the reduction process of the migrated metal cation occurs is generally composed of inert metals such as gold (Au) and platinum (Pt).

Figure 2.8 Switching mechanism based on ECM effect

Figure 2.8 schematically explains the basic principle of switching operations along with a typical I-V characteristic of the ECM memory cell. Initially, the memory cell has high resistance and stays in the OFF-state until positive voltage is applied to the active metal electrode. When positive voltage is applied to the active electrode

23 2. Basics of Resistance Change Memory

(AE), the electrochemically active metal atoms (M) start to be oxidized and dissolved into the solid electrolyte according to the oxidation reaction:

M  Mz+ + ze-

where z represents the number of valence electrons. The oxidized cations, Mz+, migrate across the solid electrolyte film under the electric field and are reduced or neutralized on the surface of the CE by the reduction process:

Mz+ + ze-  M

As the applied voltage increases, the oxidation and reduction processes get enhanced and lead to formation of metal filaments that grow from the CE toward the AE. When the voltage reaches to VSET, a metal filament electrically connects the two electrodes, that is, the memory cell switches its state to the ON-state with an abrupt increase of current by a few orders as shown in Figure 2.8. The On-state can be retained unless the metal filament is disconnected by a sufficient voltage of opposite polarity, VRESET.

The voltage with the opposite polarity electrochemically dissolves the metal atoms at the edge of the filament and eventually breaks the conductive path between the electrodes resetting the memory cell back to the OFF-state. Applying a positive bias to the active electrode again can repair the ruptured filament switching the device conductive.

24 2. Basics of Resistance Change Memory

From the switching mechanism explained above, several essential properties of the ECM resistive switching memories can be derived. First, it is very obvious that the switching mode must be bipolar; opposite voltage polarities are definitely necessary for both SET and RESET processes. Secondly, the OFF-state resistance (ROFF) is largely governed by the bulk property of the solid electrolyte material in the cell because the electronic current through the whole area contributes to ROFF. On the other hand, it is the localized metal filament that dominantly determines the ON-state resistance (RON) of the memory since two electrodes of the cell become electrically short through the filament during the ON-state. Furthermore, localization of the conduction path is an exceptional key feature differentiating the ECM memory from other NVM candidates in terms of the scalability. Ideally, the ECM memory devices can be scaled down to the atomic size of the metal assuming single atomic chain of the metal filament.

2.3. Summary

At the beginning of this chapter, the basic operation of the flash memory cell is introduced. Due to the concept of storing electrons in the FG, fundamental problems in scaling of the gate length and the tunnel oxide thickness cannot be avoided. Besides, the unwanted crosstalk among devices becomes another formidable obstacle as the devices get closer to each other. These hurdles of the flash memory scaling have

25 2. Basics of Resistance Change Memory spurred a flurry of research activities on different types of NVMs. Among these emerging new memories, the resistance change memory is being considered as a promising future NVM candidate in terms of the scalability.

The later part of this chapter describes the device structure of the resistance change memory, their typical switching behaviors, and switching mechanisms especially in which redox processes and mobile ionic motion on the nanometer scale play the key role of the electrical switching phenomenon. The unique concept of filamentry switching suggests that this type of resistance change memory has a great scaling potential, which is ideally scalable down to the atomic size.

26 2. Basics of Resistance Change Memory

References

[2.1] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to Flash

Memory,” Proceedings of the IEEE, 91, 4, 2003.

[2.2] S. Aritome, “Advance Flash memory technology and trends for file storage

application,” IEDM Tech Dig., 763–766, 2000.

[2.3] C. Lam, “Flash Memory Short Course,” VLSI-TSA, April, 2006.

[2.4] G. Atwood, “Future Directions and Challenges for ETox Flash Memory

Scaling,” IEEE Trans. Device Material Rel. 4, No. 3, 301–305, 2004.

[2.5] J.-D. Lee, S.-H. Hur, and J.-D. Choi, “Effects of Floating-Gate Interference on

NAND Flash Memory Cell Operation,” IEEE Electron Device Letters, vol. 23, p.

264, 2002.

[2.6] K. Prall, “Scaling Non-Volatile Memory Below 30nm,” IEEE Non-Volatile

Semiconductor Memory Workshop, p. 5, 2007.

[2.7] International Technology Roadmap of Semiconductor, 2009.

[2.8] R. Waser, R. Dittmann, G. Staikov, and K. Szot, “Redox-Based Resistive

Switching Memories – Nanoionic Mechanisms, Prospects, and Challenges,”

Advanced Materials, vol. 21, p. 2632, 2009.

[2.9] R. Bez and A. Pirovano, “Non-volatile memory technologies: emerging

concepts and new materials,” Materials Science in Semiconductor Processing, vol.

7, p. 349, 2004.

27 2. Basics of Resistance Change Memory

[2.10] S. Seo, M. J. Lee, D. H. Seo, E. J. Jeoung, D.-S. Suh, Y. S. Joung, and I. K.

Yoo, I. R. Hwang, S. H. Kim, I. S. Byun, J.-S. Kim, J. S. Choi, and B. H. Park,

“Reproducible resistance switching in polycrystalline NiO films”, Appl. Phys. Lett.

85, 5655-5657, 2004.

[2.11] J. J. Yang, M. D. Pickett, X. Li, D. A. A. Ohlberg, D. R. Stewart, and R. S.

Williams, “Memristive switching mechanism for metal/oxide/metal nanodevices”,

Nature Nanotechnology, vol. 3, p. 429, 2008.

[2.12] D. Choi, D. Lee, H. Sim, M. Chang, and H. Hwang, “Reversible resistive

switching of SrTiOx thin films for nonvolatile memory applications”, Appl. Phys.

Lett., vol. 88, 2006.

[2.13] K. Terabe, T. Hasegawa, T. Nakayama, and, M. Aono, “Quantized

conductance atomic switch,” Nature, vol. 433, p. 47, 2005.

[2.14] T. Sakamoto, H. Sunamura, H. Kawaura, T. Hasegawa, T. Nakayama, and M.

Aono, “Nanometer-scale switches using copper sulfide,” Applied Physics Letter,

vol. 82, p. 3032, 2003.

[2.15] M. N. Kozicki, M. Park, and M. Mitkova, “Nanoscale memory elements based

on solid-state electrolytes”, IEEE Trans. Nanotechnology, vol. 4, p. 331, 2005.

[2.16] R. Müller, R. Naulaerts, J. Billen, J. Genoe, and P. Heremans, “CuTCNQ

resistive nonvolatile memories with a noble metal bottom electrode,” Appl. Phys.

Lett., vol. 90, 2007.

[2.17] T. W. Hickmott, “Low-frequency negative resistance in thin anodic oxide

films,” J. Appl. Phys., 33, 2669–2682, 1962.

28 2. Basics of Resistance Change Memory

[2.18] R. Waser and M. Aono, “Nanoionics-based resistive switching memories,”

Nature Materials, vol. 6, p. 833, 2007.

29

Chapter 3

Micrometer-Scale Copper Sulfide Resistance Change Memory Devices

This chapter begins with introducing the resistive switching of copper sulfide nanometer switches studied by Sakamoto [3.1], which motivated a great academic interest in copper sulfide as a future NVM material.

To demonstrate consistent electrical switching of the material, two methods for film synthesis are studied, sputtering and anodic polarization. After that, we investigate the scaling trend, that is, how the device characteristics change as the device size is shrinking down. The effects of applied operation current are presented as well.

For device fabrication, we use a shadow mask to pattern devices larger than

150 micrometer (μm) in diameter, which will be called ‘large-area devices’. A contact mask is used to pattern devices with diameters smaller than 50 μm, called ‘small-area devices’.

3.1. Copper Sulfide Nanometer Switch

3. Micrometer-Scale Copper Sulfide Resistance Change Memory Devices

Before attracting intense attention as promising materials for future NVMs, originally solid electrolytes have been extensively investigated for other various applications that require high ion conductivity such as batteries, fuel cells, and sensors

[3.2]. Likewise, copper sulfide has not been considered as a future candidate of NVMs although its ion conduction mechanism was first investigated in 1851 [3.3]. Instead, most of the work and expectations for this material have focused on its possible use in thin-film photovoltaic cells. Its use in a heterojunction with cadmium sulfide (CdS) as a solar cell material was widely studied between the 1960s and 1980s [3.4 – 3.6].

The recent remarkable interest in copper sulfide as an NVM device material was motivated when Sakamoto published a paper demonstrating its resistive switching behaviors [3.1]. They fabricated nanometer-scale switching devices using copper sulfide film sandwiched between Cu and non-Cu containing metal electrodes as shown in the cross-section schematic in Figure 1(a). The copper sulfide film was grown by sulfidizing Cu using anodic polarization, which will be explained in next section. The composition ratio of Cu and S in the sulfidized film was 2:1, suggesting that the phase of the deposited copper sulfide was stoichiometric chalcocite, Cu2S. After the growth of the Cu2S, an insulating layer was made from a chloromethylated calixarene film, which is an electron beam (EB) negative resist. EB lithography patterned the contact area of the devices ranging from 30 nm to 300 nm in diameter.

31 3. Micrometer-Scale Copper Sulfide Resistance Change Memory Devices

Figure 3.1 Copper sulfide nanometer switch [3.6]

The I-V characteristics of their device, as shown in Figure 3.1(c), exhibit typical bipolar switching behavior similar to other ECM resistive memories. Before the voltage is biased, the device has very a high ROFF larger than 100 MΩ. By sweeping the voltage to negative polarity with the Cu electrode grounded, the device can be switched from the OFF-state to the ON-state at VSET of -0.28V. Subsequent voltage sweep back to positive polarity changes its state back to the OFF-state at

6 VRESET of 0.066V. Sakamoto et al. demonstrated large ROFF/RON ratio of about 10 with the ON-state operation current of a few milliampere (mA).

32 3. Micrometer-Scale Copper Sulfide Resistance Change Memory Devices

3.2. Large-Area Devices and Their Properties

3.2.1. Copper Sulfide Growth by Sputtering

Historically, numerous techniques of thin film deposition have been utilized for copper sulfide synthesis. As early as in 1851, Hittorf [3.2] prepared copper sulfide using repeated high temperature fusion of copper and sulfur in order to study the temperature effects on conductivity of copper sulfide. Later, various different synthesis approaches have been employed such as radio-frequency (RF) reactive sputtering [3.7], vacuum evaporation [3.8], chemical bath deposition [3.9], and successive ionic layer adsorption and reaction (SILAR) [3.10].

Among these methods, RF sputtering was first adopted for the preparation of copper sulfide film at the initial phase of this study. Large-area device structures using the sputtered copper sulfide thin film are similar to the reported samples in [3.6]. The fabrication process flow of the large-area device is depicted in Figure 3.2.

33 3. Micrometer-Scale Copper Sulfide Resistance Change Memory Devices

Figure 3.2 Process flow of large-area devices

The devices were fabricated on 4-inch silicon (Si) wafers with 250 nm thick thermally grown silicon dioxide (SiO2), which isolated electrically the devices from the Si substrate underneath. A uniform layer of metal was deposited on top of the whole surface of SiO2 by dc-sputtering or e-beam evaporation. This metal layer works as the common bottom electrode. For a good adhesion of the bottom electrode to SiO2, a thin titanium (Ti) layer with a few-nm thickness was deposited. Upon the bottom electrode, active copper sulfide films with various thicknesses from 100 nm to 300 nm were prepared by RF-sputtering. In order to achieve the desired film stoichiometry, a

1-inch stoichiometric Cu2S sputtering target was used for the deposition. Finally,

34 3. Micrometer-Scale Copper Sulfide Resistance Change Memory Devices circular top electrodes with 4 different sizes, 100, 150, 200 and 250 μm in diameter were patterned by using a shadow mask. Like in the bottom electrode deposition, dc- sputtering or e-beam evaporation can be used for the top metal growth.

Figure 3.3 shows the linear I-V curve of a device with a diameter of 100 μm, made of a sputtered 300 nm-thick copper sulfide film. The device has Pt and Cu as bottom and top electrode, respectively. When the voltage was swept between -0.4 V and 0.4 V with 20 mA current compliance, no electrical switching was observed from the sputtered film. The device stayed in a very low resistance state with less than 20 Ω during the DC I-V measurement.

Figure 3.3 I-V characteristic of sputtered copper sulfide in a linear scale

35 3. Micrometer-Scale Copper Sulfide Resistance Change Memory Devices

To investigate such a large electrical conductance of the device, the composition of the as-deposited copper sulfide thin film was analyzed by Rutherford backscattering (RBS). It was estimated to be Cu1.85S, manifesting that the sputtered film is nonstoichometric and has substantial Cu vacancies compared with stoichiometric Cu2S. At room temperature, copper sulfide is known to have five stable phases: covellite (CuS), anilite (Cu1.75S), digenite (Cu1.8S), djurleite (Cu1.95S), and chalcocite (Cu2S) [3.11]. Figure 3.4 shows the phase diagram of the copper sulfide.

Two of them, CuS and Cu2S, are stoichiometric, and the others nonstoichiometric.

Besides these five phases, Cu and S also form a number of mixed phases. And chalcocite, djurleite, digenite, and anilite are p-type semiconductors in which copper vacancies act as acceptors contributing to electronic hole conductivity [3.12]. Hence, the hole conductivity of copper sulfide depends strongly upon the molar ratio of Cu and S. Figure 3.5 shows the conductivity variation clearly as a function of deviation from stoichiometric Cu2S.

36 3. Micrometer-Scale Copper Sulfide Resistance Change Memory Devices

Figure 3.4 Phase diagram of copper sulfide [3.11]

37 3. Micrometer-Scale Copper Sulfide Resistance Change Memory Devices

Figure 3.5 Conductivity variation of bulk Cu2-xS with deviation from stoichiometry [3.12]

In our experiments, the preferential sputtering of S from the Cu2S target was responsible for the severe discrepancy in stoichiometry. The same phenomenon during

RF-sputtering of copper sulfide has been reported in 1987 [3.13]. The preferential extraction of S atoms resulted in significant Cu vacancies in the films forming a copper-flake ring on top of the Cu2S sputtering target after the deposition.

Consequently, all devices were highly conductive showing no consistent switching characteristics even under the current compliance of 100 mA.

3.2.2. Copper Sulfide Growth by Anodic Polarization

The previous sub-section presented the electrical properties of the RF-sputtered copper sulfide films whose compositions were examined by the RBS analysis. Due to the preferential sputtering of S and consequent nonstoichiometry of the films, no electrical switching was demonstrated from the sputtered films. Since small deviations from stoichiometry lead to pronounced changes in the electrical conductivity, the synthesis of stoichiometric Cu2S film is most essential to the performance of the device such as ROFF/RON ratio.

While flowing hydrogen sulfide (H2S) gases during the sputtering or annealing

Cu-deficient samples in H2S ambient can obtain the stoichiometric chalcocite film,

38 3. Micrometer-Scale Copper Sulfide Resistance Change Memory Devices careful control of the toxic gas as well as many sputtering parameters is an inevitable major challenge.

Another alternative approach that we employed for the growth of stoichiometric Cu2S was anodic polarization. Anodic polarization is cheaper and simpler process than other thin-film synthesis techniques. In addition, the synthesis is extremely selective to metals, which makes self-alignment process possible.

For the Cu2S film growth using the anodic polarization, a 200 nm-thick Cu layer was evaporated on the thermally grown SiO2. The Cu film was immersed in a 0.2 percent sodium sulfide (Na2S) aqueous solution. We applied positive bias between

0.15 V and 0.3 V to the film for several minutes while grounding the immersed Pt counter-electrode. Since positive voltage is applied to the Cu layer, negatively charged sulfur ions are attracted to and adsorbed on the surface, as shown in Figure 3.6 (a).

Subsequently, the Cu layer is sulfidized electrochemically.

39 3. Micrometer-Scale Copper Sulfide Resistance Change Memory Devices

Figure 3.6 Cu2S synthesis using anodic polarization (a) schematic diagram of

Cu2S growth in an aqueous Na2S bath; (b) current transient characteristics of Cu2S growth

Figure 3.6 (b) shows typical current transient responses for various voltages during the sulfidization. The general shape of the transients is characteristic of a nucleation and growth process. In very short time, double-layer charging takes place on the surface of the Cu layer, followed by an increase of current due to the formation and growth of nuclei [3.14]. To remove the native copper oxide on the Cu surface, negative voltage was applied for several seconds before sulfidizing Cu. After the growth of Cu2S by sulfidizing the bottom Cu electrode, top metal electrodes such as Ti and Au were deposited directly on the blanket Cu2S film and patterned using a shadow mask for large-area devices. The top metal electrodes were deposited in the Metalica sputter of the Stanford Nanofabrication Facilities (SNF) using a DC power of 100 W at a pressure of 5 mT, and a gas flow of 30 sccm argon (Ar).

The composition of the as-grown sulfidized film was Cu2S, analyzed by the

RBS analysis. Depth profiling using X-ray photoelectron spectroscopy (XPS) also confirmed the stoichiometry of the film as shown in Figure 3.7. From the cross- sectional scanning electron microscope (SEM) images in Figure 3.8, the Cu2S film is observed to have a columnar structure along the film thickness unlike the sputtered copper sulfide film.

40 3. Micrometer-Scale Copper Sulfide Resistance Change Memory Devices

Figure 3.7 XPS depth profile of as-grown Cu2S

Figure 3.8 SEM images of as-grown Cu2S by anodic polarization (a) top view

(b) cross-sectional view

41 3. Micrometer-Scale Copper Sulfide Resistance Change Memory Devices

The DC I-V characteristics of the devices were measured similarly as explained in the previous section. The voltage sweeps were carried out starting from 0

V in the positive direction, sweeping reversely through zero to the negative bias, and then sweeping back to 0 V. When the voltage sweep initially started to the negative direction, no change in the resistance was observed; it stays at the OFF-state until the voltage polarity changes to the opposite. All measurements were done at room temperature.

Figure 3.9 I-V characteristics of Cu2S grown by anodic polarization. The film thickness is 50 nm and the diameter of the device 150 μm.

42 3. Micrometer-Scale Copper Sulfide Resistance Change Memory Devices

In Figure 3.9, typical I-V characteristics of the Cu2S devices with Ti and Au electrode are plotted in a logarithmic scale on the y-axis to show the ROFF/RON ratio visibly. The devices switch from OFF-state to ON-state around 0.1 V (VSET) and switch back to OFF-state around -0.08 V (VRESET), showing consistent and reproducible bipolar switching behavior up to 50 cycle sweeps. This voltage polarity dependence of switching phenomena suggests that the switching mechanism is associated with copper ions drifting to form conduction paths. The OFF-state resistance, ROFF, is over 10 kΩ, much more insulating than that of the sputtered film since the anodic polarization provides excellent stoichiometry of copper sulfide. RON, determined mainly by the current compliance, was as low as 10 Ω. Thus, a large

3 ROFF/RON ratio of 10 was obtained for the large-area devices. Devices with different metals (e.g., Pt, Ni) for the top electrode showed similar results.

3.3. Small-area devices and their properties

In the previous section we presented electrical properties of copper sulfide resistance change memory devices patterned by the shadow mask. Two methods, sputtering and anodic polarization, were used for the growth of copper sulfide films and the film synthesized by the anodic polarization showed consistent and reproducible switching characteristics due to its excellent stoichiometry. Once growth

43 3. Micrometer-Scale Copper Sulfide Resistance Change Memory Devices of the stoichiometric film has been achieved, it will be investigated how scaling of the device characteristics will evolve as the device size gets scaled down to a few µm.

For this study, the process flow is modified as shown in Figure 3.10. We start with Cu bottom electrode deposited on thermally grown SiO2. The Cu2S film is grown by partially sulfidizing the Cu bottom electrode as described in the section 3. During the sulfidization process, the Cu film was immersed in a 0.2 percent Na2S aqueous solution under 0.15 V for 4 minutes. After the Cu2S synthesis, another SiO2 isolation layer is formed by sputtering. The 20 nm-thick SiO2 sputtering was performed in the

AJA ATC 1800-F sputter under 5 mT in an Ar ambient with a 30 sccm flow rate using

100 W RF forward power for 10 minutes. Then, lithography using a contact mask aligner and subsequent etch process define device areas as shown in Figure 3.10 (c). 1

µm of Shipley SPR 955 i-line photoresist was coated by a Silicon Valley Group (SVG) coater, followed by a 110 °C soft bake. The photoresist exposure was performed on a

KarlSuss contact mask aligner with an exposure of 15mW/cm2. The exposed photoresist was developed on a SVG Developer track, using Baker Chemical LDD-26

W positive resist stripper after a 60 seconds, 115 °C post exposure bake. The etch process was carried out in the Applied Materials Precision 500 Etcher under a pressure of 250 mT, a forward power of 200 W, and flow rates of 15 sccm for CHF3, 30 sccm for CF4, and 100 sccm for Ar. The device sizes vary from 50 µm to 2 µm in diameter.

Finally, a top metal electrode is deposited by dc-sputtering, followed by a lift-off process. For the lift-off, the wafer was immersed in a solvent over 12 hours.

44 3. Micrometer-Scale Copper Sulfide Resistance Change Memory Devices

Figure 3.10 Process flow of small-area devices (a) Cu deposition on thermal SiO2

(b) Cu2S synthesis by anodic polarization (c) Lithography and etch of sputtered SiO2 to define device areas (d) Top metal electrode deposition and lift-off

Figure 3.11 shows the I-V characteristics of devices with 20, 10, and 5 µm in diameter under a compliance current of 1 mA. The devices exhibit instantaneous resistance switching from OFF-state to ON-state around 0.16V, and switching back to

OFF-state around -0.1V, requiring larger bias voltage for turning on the devices.

Jameson [3.15] explains the cause of this asymmetry in operation voltages proposing a quantum point contact model for the conducting filament rather than a classical conductor model obeying the equation R = ρL/A. For the quantum point contact, it is

45 3. Micrometer-Scale Copper Sulfide Resistance Change Memory Devices understood that the electrical resistance arises from inelastic scattering of electrons conducted ballistically across a point contact. During OFF to ON switching, the kinetic energy of electrons acquired from a bias voltage is deposited into the anode, whereas during ON to OFF switching it is deposited into the filament. Since heat conduction is faster in the anode than the filament surrounded by an insulator, the ON to OFF switching therefore produces a larger increase in temperature in the filament, which activates atomic rearrangement driven by ion migration for switching under a lower bias voltage.

Another crucial property which can be hinted from Figure 3.11 is regarding the scaling trend, in other words, how the current values of ON and OFF states change with the device sizes. There is little fluctuation of the ON-state current among the devices with different contact areas while the OFF-state current decreases as the device size gets smaller.

46 3. Micrometer-Scale Copper Sulfide Resistance Change Memory Devices

Figure 3.11 I-V characteristics of small-area devices with 50 nm-thick Cu2S and

Ti/Pt top electrodes

These interesting scaling-down effects are well-illustrated in Figure 3.12 where

RON and ROFF values measured at 0.1V are plotted with ROFF/RON ratios. As the device size is scaled down from 50 μm to 2 μm, the ROFF increases from 20 kΩ to 20 MΩ. In contrast, the RON is almost independent of the device area, staying around 100 Ω with little variation. Consequently, we can obtain a larger ROFF/RON ratio by scaling down the devices. This indicates that ROFF is mainly determined by the bulk properties whereas a tiny local filament within the device is responsible for switching it on.

47 3. Micrometer-Scale Copper Sulfide Resistance Change Memory Devices

Figure 3.12 RON, ROFF, and ROFF/RON ratio as a function of device size

Using different compliance currents, we also examined the dependence of the electrical characteristics of devices upon programming current. Figure 3.13 exhibits how RON, ROFF, and their ratio change with three different levels of compliance current,

0.01 mA, 0.1 mA, and 1 mA. The resistances were measured at 0.1 V from the devices with 5 μm in diameter. Since the compliance current does not change bulk properties significantly, differences in ROFF values are negligible. On the other hand, RON shows high dependency on the compliance current, decreasing with larger compliance current.

This observation suggests that we can obtain multiple ON-states from a single device by altering the programming current. Therefore, multi-level cell (MLC) operation of the device can be achieved by a fine control of the programming current.

48 3. Micrometer-Scale Copper Sulfide Resistance Change Memory Devices

Figure 3.13 RON, ROFF, and ROFF/RON ratio with different compliance currents

3.4. Summary

A simple device fabrication process using the shadow mask was introduced to evaluate two film growth methods, sputtering and anodic polarization. Due to the preferential sputtering of sulfur atoms, Cu-deficient nonstoichiometric films were grown by sputtering. On the contrary, an excellent stoichiometry of the film was achieved using anodic polarization. Moreover, anodic polarization offers simpler and more reliable synthesis process.

49 3. Micrometer-Scale Copper Sulfide Resistance Change Memory Devices

The memory devices fabricated through anodic polarization have shown very interesting properties. It was observed that ROFF is inversely proportional to the size of the devices, which indicates that the OFF state current flows across the whole device area. RON, on the other hand, remains almost unchanged despite scaling down of the devices suggesting that the ON state current is confined in very tiny filament paths.

Thus, it has been demonstrated that ROFF/RON ratio improves as the memory device scales down. In addition to this scaling trend, the feasibility of MLC operation has been also confirmed in this work.

50 3. Micrometer-Scale Copper Sulfide Resistance Change Memory Devices

References

[3.1] T. Sakamoto, H. Sunamura, H. Kawaura, T. Hasegawa, T. Nakayama, and M.

Aono, “Nanometer-scale switches using copper sulfide,” Applied Physics Letter,

vol. 82, p. 3032, 2003.

[3.2] P. Knauth and H. Tuller, “Solid-state ionics: roots, status, and future prospects,”

Journal of the American Ceramic Society, vol. 85, p. 1654, 2002.

[3.3] W. Hittorf, “Über das elektrische Leitungsvermögen des Schwefelsilbers und

Halbschwefelkupfers,” Ann. Phys. Chem. , vol. 84, p. 1, 1851.

[3.4] A. Rothwarf and A. Barnett, “Design analysis of the thin-film CdS-Cu2S solar

cell ,” IEEE Trans. Electron Devices, vol. 24, p. 381, 1977.

[3.5] S. Banerjee and H. Saha, “Role of impurities in sintered CdS/Cu2S solar cells,”

J. Phys. D: Appl. Phys., vol. 16, p. 185, 1983.

[3.6] L. H. Allen and E. Buhks, “Copper electromigration in polycrystalline copper

sulfide,” J. Appl. Phys., vol. 56, p. 327, 1984.

[3.7] J. Leong and J. Yee, “Hall effect in reactively sputtered Cu2S,” Appl. Phys.

Lett. , vol. 35, p. 601, 1979.

[3.8] B. Bezig, S. Duchemin, and F. Guastavino, “Evaporated layers of cuprous

sulfides: technology and methods of characterization,” Solar Energy Materials, vol.

2, p. 53, 1979.

51 3. Micrometer-Scale Copper Sulfide Resistance Change Memory Devices

[3.9] A. Varkey, “Chemical bath deposition of CuxS thin films using

ethylenediaminetetraacetic acid (EDTA) as complexing agent,” Solar Energy

Materials, vol. 19, p. 415, 1989.

[3.10] S. D. Sartale and C. D. Lokhande, “Growth of copper sulphide thin films by

successive ionic layer adsorption and reaction (SILAR) method,” Materials

Chemistry and Physics, vol. 65, p. 63, 2000.

[3.11] D. J. Chakrabarti and D. E. Laughlin, in Binary Alloy Phase Diagrams, edited

by T. B. Massalski, American Society of Metals, p. 953, 1986.

[3.12] K. Okamoto and S. Kawai, “Electrical conduction and phase transition of

copper sulfides,” Japanese Journal of Applied Physics, vol. 12, p. 1130, 1973.

[3.13] J. Santamaria, E. Iborra, I. Martil, G. Gonzalez-Diaz, and F. Sanchez-Quesada,

“Sputtering process of Cu2S in an Ar atmosphere,” Vacuum, vol. 37, p. 433, 1987.

[3.14] G. Gunawardena, G. Hills, I. Montenegro, and B. Scharifker, “Electrochemical

nucleation: Part I. General considerations,” Journal of Electroanalytical Chemistry

and Interfacial Electrochemistry, vol. 138, p. 225, 1982.

[3.15] J. Jameson and M. V. Buskirk, “Science and application of conductive-bridge

memory (CBRAM),” 2013.

52

Chapter 4

Copper Sulfide Nanopillar Arrays for NVM Applications

In this chapter, we present a viable and simple technique for fabricating metal sulfide nanopillar devices with a high aspect ratio using electroplating and anodic polarization with nano-templates from block copolymer (BCP) self-assembly.

Subsequently, we demonstrate reproducible resistance switching of Cu2S nanopillars with a high aspect ratio using a conductive atomic force microscope (CAFM).

4.1. Basics of Block Copolymer

Basically, BCPs are macromolecules made up of two or more dissimilar homopolymer chains, or blocks, covalently linked to one another [4.1]. The most common and simplest form of BCPs is the linear diblock, containing a long sequence of type A monomers covalently bound to a chain of type B monomers as shown in

Figure 4.1 (a). The unique and crucial feature of the BCP is that they can self- assemble collectively to produce periodic nanostructures through microphase separation. The microphase separation is driven by chemical incompatibilities between

4. Copper Sulfide Nanopillar Arrays for NVM Applications the dissimilar blocks, A and B. Were it not for the covalent bonding between the blocks, the thermodynamic forces contributed by incompatibilities of the blocks would lead to macrophase separation like oil and water. During the self-assembly of BCPs, the thermodynamic forces driving separation are counterbalanced by the forces from covalent linkages [4.2], which enables the formation of nanoscopic domains as in the schematic of Figure 4.1 (b). Depending on the ratio of A and B block lengths, several morphologies can be obtained. Figure 4.1 (c) shows the most frequently observed diblock morphologies, spheres, cylinders, and lamellae. In our work, the spherical morphology, the first one in Figure 4.1 (c), is adopted to fabricate Cu2S nanopillar arrays.

Figure 4.1 Schematics of BCPs (a) diblock copolymer (b) nanoscopic domains after phase separation (c) various morphologies formed by diblock copolymers

54 4. Copper Sulfide Nanopillar Arrays for NVM Applications

4.2. Cu2S Nanopillar Array Fabrication

Figure 4.2 depicts our proposed fabrication flow of Cu2S nanopillar arrays with a high aspect ratio. At first, a metal substrate is prepared on 4-inch Si wafers as shown in Figure 4.2 (a). This metal layer serves as a cathode in electroplating and an anode in the subsequent sulfidization process. On the metal substrate, a BCP template is fabricated to generate high aspect ratio cylindrical pores oriented perpendicular to the substrate as shown in Figure 4.2 (b). Details of the template fabrication are described in Section 4.2.1. Figure 4.2 (c) shows the next step of electroplating which electrodeposits Cu into these nanoscopic cylindrical pores. As a final step presented in

Figure 4.2 (d), anodic polarization follows to sulfidize Cu nanopillars in the template.

55 4. Copper Sulfide Nanopillar Arrays for NVM Applications

Figure 4.2 Cu2S nanopillar array fabrication flow (a) metal substrate deposition

(b) BCP template preparation (c) Cu electroplating (d) Cu2S nanopillar growth by anodic polarization

4.2.1. BCP Template Fabrication

For preparation of BCP templates illustrated in Figure 4.3, we used a bilayer approach consisting of a top self-assembled layer which serves as a high silicon- containing etch mask (hereafter called the pattern layer) and an underlying organic polymer layer (called the transfer layer) into which the nanopatterns from the pattern layer are transferred.

56 4. Copper Sulfide Nanopillar Arrays for NVM Applications

A transfer layer is first deposited onto a substrate as shown in Figure 4.3 (a).

This transfer layer can be easily deposited on a variety of substrates (e.g., silicon wafers, metals, nitrides, silicides, crosslinked polymers, and so on.) with controlled thickness. For this experiment, thickness-controllable organic polymer layer

(polydimethylglutarimide, PMGI, MicroChem) is coated on the metal. After depositing the transfer layer solution onto metal substrates, the samples are baked for

1 min at 190C. Then, a thin self-assembled pattern layer is spin-coated directly on top of the transfer layer. The pattern layer is diblock copolymer containing hybrid which provides well-defined dot nanopatterns on the surface as shown in Fig. 4.3 (b). This hybrid is a mixture of a poly(styrene-b-ethylene oxide) (PS-b-PEO) and an oligomeric organosilicate (OS) which is selectively miscible with PEO [4.3]. With the molecular weight of PS19k-b-PEO12.3k used in this fabrication, the PS microdomains are ~25 nm in diameter and ~40 nm in center-to-center distance. Since the self-assembled pattern layer in this study contains silicon, it gives sufficient oxygen plasma etching contrast to etch very deep pores into the transfer layer. Fig. 4.3 (c) shows the next step of a one-step oxygen plasma etching which removes the PS domains from the hybrid layer and subsequently transfers the porous pattern in the hybrid layer into an organic polymer layer, thus generating porous templates containing oriented cylindrical pores.

57 4. Copper Sulfide Nanopillar Arrays for NVM Applications

Figure 4.3 BCP template fabrication (a) thickness-controllable organic polymer layer (PMGI) coating on the metal substrate, (b) BCP spin-casting which creates well- ordered microdomains, (c) nanopores with high aspect ratio generated by plasma etch

Figure 4.4 shows the result of the etching process. The oxygen plasma etching was performed in a reactive ion etcher in Stanford Nanofabrication Facility under 5mT base pressure, 100 W power, and 20 sccm O2. Figure 4.4 (a) and (b) are 45-tilted

SEM images of the nanoporous template with different thickness on Pt and Cu substrates, respectively. It is clear from both images that pores with 20 – 30 nm in diameter are oriented perpendicular to the substrate and well-ordered over a large area.

Since the diameters and center-to-center distances of the pores scale with the

58 4. Copper Sulfide Nanopillar Arrays for NVM Applications molecular weight of the PS-b-PEO [4.3], our approach can provide nanoporous templates with holes less than 20 nm in diameter by simply controlling the molecular weight of PS-b-PEO in the pattern layer as shown in Figure 4.5 [4.4].

Figure 4.4 45-tilted SEM images of templates etched by O2 plasma (a) ~70nm thick template on Pt substrate (b) ~170nm thick template on Cu substrate

59 4. Copper Sulfide Nanopillar Arrays for NVM Applications

Figure 4.5 Cross-sectional SEM images of the nanoporous template with (a) 25 nm, (b) 15 nm, and (c) 8 nm in diameters. (d) A tilted SEM image of the nanoporous template with pore diameter of 15 nm [4.4]

4.2.2. Cu Electroplating and Sulfidization

An experimental setup for the Cu electroplating into the cylindrical nanopores is very similar to that used for the anodic polarization as schematically compared in

60 4. Copper Sulfide Nanopillar Arrays for NVM Applications

Figure 4.6. The negative voltage needs to be applied at the metal substrate of the template to attract dissolved Cu ions toward the bottom electrode filling nanopores. In the experiment, we applied negative voltage of 0.1 – 0.2 V at the bottom electrode for

10 – 20 seconds while immersing the templates in the standard copper bath, the mixture of 20 gram of copper sulfate (CuSO4), 5 milliliter of sulfuric acid (H2SO4) and

650 milliliter of water.

Figure 4.6 Electrochemical processes for deposition and sulfidization of Cu (a)

Cu electroplating; negative voltage applied to sample (b) Cu sulfidization by anodic polarization; positive voltage applied to sample

61 4. Copper Sulfide Nanopillar Arrays for NVM Applications

The SEM images in Figure 4.7 show Cu nanopillars grown in the template after the electroplating. It is observed from the images that very few pores are left unfilled despite the irregular heights of nanopillars.

Figure 4.7 SEM images of Cu nanopillars after electroplating in 70 nm thick template on a Pt substrate. Most holes are filled with nanopillars. (a) top view (b)

45-tilted view

After successfully creating Cu nanopillars using electroplating, we sulfidized the Cu nanopillars in a 0.2% Na2S aqueous solution holding positive 0.15 V at the bottom electrode for several seconds. Figure 4.8 is the image of Cu2S nanopillars where the template is removed by HF dip in a 10:1 buffered oxide etchant for 10 seconds and O2 plasma etching explained in the previous section. The images demonstrate that the nanopillars with a high aspect ratio over 6 and diameters smaller than 25 nm can be fabricated using BCP templates.

62 4. Copper Sulfide Nanopillar Arrays for NVM Applications

Figure 4.8 SEM images of template-removed Cu2S nanopillars on Cu substrate

It is noted that the selection of metal substrate affects the adhesion of pillars to the substrate. As shown in Figure 4.9 below, adhesion between Cu pillars and Pt surface is not strong enough for surviving during the process such as O2 plasma and

HF dip. Most pillars disappeared due to the poor adhesion to the Pt substrate.

Figure 4.9 SEM images of Cu nanopillars remained on Pt substrate after template removal

63 4. Copper Sulfide Nanopillar Arrays for NVM Applications

4.3. CAFM Measurements

CAFM was used for electrical measurements of the nanopillars because of the dense spacing between pillars as small as 40 nm. We measured the I-V characteristics of the Cu2S nanopillars fabricated on the Cu substrates for two structures where the

BCP template is present and where the template is removed by HF dip for the pattern layer and O2 plasma for the transfer layer.

4.3.1. CAFM Results of Cu2S Nanopillars with Template

Figure 4.10 and 4.11 show the results for the structure with the BCP template.

For the measurement, we first scan the surface of the samples in tapping mode as shown in Figure 4.10 (b), then locate the Pt-coated CAFM tip of 40nm diameter on one of the nanopillars. We applied a voltage sweep over the range 10 V to the bottom

Cu substrate with reference to the CAFM tip while measuring the current up to a compliance value of 2 μA. All measurements have been done at room temperature.

Figure 4.10 (c) shows dc I-V switching results of Cu2S nanopillars obtained in our measurements. Before the voltage is swept in the positive direction, the nanopillars begin with and remain in the high resistance state. As the voltage with reference to the tip is increased from 0 to 10 V, the current level increases abruptly

64 4. Copper Sulfide Nanopillar Arrays for NVM Applications around 0.5 V, at which point the current reaches its compliance limit of 2 μA. After reaching the low resistance state, the nanopillar stays in this state until we sweep back the voltage in the opposite direction beyond -0.05 V, where the device returns to the high resistance state. As was the case for µm-scale devices, the observed resistance switching depends on the voltage polarity. The switching behavior was observed for more than 50 cycles under 2 μA operating current.

65 4. Copper Sulfide Nanopillar Arrays for NVM Applications

Figure 4.10 CAFM results of Cu2S nanopillars with 25 nm in diameter and an aspect ratio over 6 in template (a) SEM top-view image of the sample (b) AFM image. CAFM tip was positioned on the bright spot (in the circle) of the image for the

I-V measurement after the surface scan. (c) I-V characteristics under a programming current of 2 μA

Figure 4.11 shows the measured resistance over the sweeping voltage. At 0.1 V, the nanopillar has RON and ROFF of about 10 kΩ and 100 GΩ, respectively. Thus, we

7 obtain a huge ROFF/RON ratio larger than 10 at a 2 μA current level. A higher

ROFF/RON is achievable if the current compliance of CAFM is increased because RON drops as the current level increases as demonstrated in the previous chapter.

66 4. Copper Sulfide Nanopillar Arrays for NVM Applications

Figure 4.11 Resistance vs. voltage of Cu2S nanopillars with 25 nm in diameter and

7 an aspect ratio over 6 in template. RON ≈ 10 kΩ, ROFF ≈ 100 GΩ, and ROFF/RON > 10 at 0.1 V at a compliance current of 2 µA

In addition to the I-V characteristics, we measured the retention properties.

Because it is practically impossible to relocate the CAFM tip on the same nanopillar once the sample has been unmounted, in the retention measurement we lifted up the tip for some hours after writing, then lowered the tip to read its resistance state. The

RON of the pillars remained nearly unchanged for more than 2 hours as shown in

Figure 4.12.

67 4. Copper Sulfide Nanopillar Arrays for NVM Applications

Figure 4.12 Retention characteristics of Cu2S nanopillars

4.3.2. CAFM Results of Cu2S Nanopillars without Template

In Figure 4.13, the measurement results are shown for the template-removed

Cu2S nanopillars. One distinguishing feature of the I-V curve is that the VSET and

VRESET have significantly increased to values higher than 1 V with a wide distribution of the amount of increase. To further investigate the root-cause of VSET and VRESET increases, we fabricated a reference device with Cu2S blanket film structure and applied to its surface the same HF dip and O2 plasma treatment that has been used for template removal in our nanopillar structure.

68 4. Copper Sulfide Nanopillar Arrays for NVM Applications

Figure 4.13 CAFM results of template-removed Cu2S nanopillars with 25 nm in diameter and an aspect ratio over 6 (a) SEM top-view image of the sample (b) AFM image (c) I-V characteristics

The CAFM measurement results of the reference device in Figure 4.14 show a similar phenomenon of significant increase in VSET and VRESET, suggesting that the

69 4. Copper Sulfide Nanopillar Arrays for NVM Applications possible potential barrier formed on the pillar surface during the template removal may be causing the VSET and VRESET shifts. With a tight control of the template etching process, the programming voltages could be manipulated for a desirable operation range for circuit designers.

Figure 4.14 I-V curves of Cu2S blanket film of which the surface has undergone the same process as the template removal

4.4. Summary

As explained at the beginning of this dissertation, the most important feature that future NVM candidates must demonstrate is their scalability. In order to explore the scalability of the Cu2S resistance change memory, the self-assembly of BCPs was

70 4. Copper Sulfide Nanopillar Arrays for NVM Applications exploited to pattern nm-scale devices rather than electron-beam lithography. By employing BCP patterning method, we could achieve a very simple and cost-effective patterning of the nano-devices with high density. A recent report of BCP directed self- assembly (DSA) demonstrated wafer-level performances as a future manufacturing lithography technology [4.5].

It has been demonstrated that using the bilayer approach described in Section

4.2.1, we can build well-ordered BCP templates with high aspect ratio. The template has cylindrical nanopore arrays with 25 nm in diameter and 170 nm in height. The following process, electroplating, has shown its capability of filling the high aspect ratio nanopores with good selectivity.

The fabricated Cu2S nanopillars, with a diameter smaller than 25 nm and a high aspect ratio larger than 6, exhibit reproducible switching characteristics with a

7 high RON/ROFF ratio up to 10 under a programming current level as low as 2 μA.

Therefore, their scalability under 25 nm and possibility of low-power operation under

2 µA range have been demonstrated in this chapter.

71 4. Copper Sulfide Nanopillar Arrays for NVM Applications

References

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72

Chapter 5

Conclusions

With the flash memory approaching its inherent scaling limit, resistance change memories have attracted significant attention due to their scalability and simplicity of device configuration. This work investigated electrical and material characteristics of copper sulfide resistance change memory and demonstrated its scalability. This chapter summarizes several key findings from our research presented in this dissertation.

5.1. Summary of Dissertation

As introduced in Chapter 1, the importance of the consumer electronics market has grown dramatically over the past three decades. This remarkable change has been enabled by the continuous successes in scaling of flash memories. The cell size of the flash memory has been shrunk down by three orders of magnitude during the past 20 years, dropping down the cost per bit incredibly [5.1]. However, scaling of conventional flash memories has inherent limits in both the thickness of the tunneling oxide and the gate length.

5. Conclusions

These challenges are addressed in Chapter 2 with a brief explanation of the flash memory basics. And the device structure, typical electrical switching characteristics, and the switching mechanism of the resistance change memory are described later.

In Chapter 3, μm-scale memory devices are fabricated to investigate their electrical and material properties. For the synthesis of the stoichiometric Cu2S film, sputtering and anodic polarization are studied and compared. While the preferential sputtering results in the growth of Cu-deficient films which do not show any resistive switching phenomena, the anodic polarization generates the film of excellent stoichiometry from which consistent electrical switching is obtained. The memory devices with different sizes exhibit impressive electrical characteristics. It is observed that the ROFF is inversely proportional to the size of the devices while RON remains almost unchanged regardless of scaling down of the devices. This implies that the OFF state current flows across the whole device area whereas the ON state current is confined in very tiny local filaments. As a result, Cu2S resistance change memories show the surprising scaling capability that the ROFF/RON ratio improves as the memory device scales down.

The scalability of Cu2S memories is explored in Chapter 4 where we present a viable and simple technique for fabricating the nanopillar devices with high aspect ratio using electroplating and anodic polarization with nano-templates from BCP self- assembly. We demonstrate the fabrication of Cu2S nanopillars with 25 nm in diameter and 170 nm in height. The Cu2S nanopillars exhibit remarkable features. First, they prove that Cu2S can be scaled below 25 nm with reproducible electrical switching

74 5. Conclusions

behaviors. Second, it is demonstrated that Cu2S possesses its electrical switching properties even when it is confined to nanoscale cylinders with aspect ratio over 6 whereas other previous works on Cu2S presented the resistance switching of only the

7 blanket film [5.2, 5.3]. Third, a high RON/ROFF ratio over 10 is achieved under a programming current level as low as 2 μA. Hence, it is believed that Cu2S nanopillars have desirable properties for low-power NVM applications.

5.2. Future Works

As demonstrated in this work, the copper sulfide resistance change memory has several advantages such as excellent scalability and low-power operation for the next generation NVM. However, further investigations need to be performed for entering the semiconductor market. Most crucial obstacle that must be addressed is thermal instability of copper sulfide. Since the resistance switching involves the transport and electrochemical reaction of Cu ions which are temperature-sensitive, thermal fluctuation may induce severe problems such as significant shift of the switching parameters and retention degradation. For example, VSET and VRESET of

Cu2S memories increase exponentially with the inverse of temperature [5.4].

In addition to the thermal instability, the bipolar nature of the switching requires development of bipolar access devices. Although MOSFET can flow current bi-directionally, it occupies larger device area impeding the scalability of the copper

75 5. Conclusions sulfide memory cell. Therefore, more research effort is needed to develop two- terminal access devices which can drive current bi-directionally as well as minimizing cross-talks and disturbs from other cells. Recent work on the two-terminal Mixed

Ionic Electronic Conduction (MIEC) device by IBM is a good example showing great promise for meeting requirements to serve as an access device [5.5].

76 5. Conclusions

References

[5.1] S. K. Lai, “Non-volatile Memory Technologies: The Quest for Ever Lower

Cost,” IEEE International Electron Devices Meeting, 2008.

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Aono, “Nanometer-scale switches using copper sulfide,” Applied Physics Letter,

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Hasegawa, K. Terabe, T. Nakayama, and M. Aono, “A Nonvolatile Programmable

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Jurich, B. Jackson, A. M. Friz, T. Topuria, P. M. Rice, and B. N. Kurdi, “Highly-

scalable novel access device based on Mixed Ionic Electronic conduction (MIEC)

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77