MICROPROCESSOR TECHNOLOGY
Assis. Prof. Hossam El-Din Moustafa Lecture 11 Ch.5 The 8086, 8088 Microprocessors
18-Mar-15 1 Chapter Objectives
. Describe the function of each 8086, 8088 pin . Use the clock generator 8284A to provide the clock of the microprocessor. . Connect buffers and latches to the buses. . Interpret the timing diagrams . Explain the difference between minimum and maximum mode operation.
18-Mar-15 2 M / IO
The Pin-Out
. Both the 8086 and the 8088 microprocessors are packaged in 40 pin dual-in-line packages (DIP’s) . The 8086 is a 16 bit microprocessor with a 16 bit data bus (AD0 AD15). . The 8088 is a 16 bit microprocessor with a 8 bit data bus (AD0 AD7). . The 8086 has an M/IO pin and the 8088 has an IO/M pin . Pin 34 is SS0 pin in 8088 but in 8086 it is BHE/S7 pin.
18-Mar-15 3 Power Supply Requirements
. +5.00 Volt ± 10% . The 8086 uses a maximum supply current of 360 mA . The 8088 uses a maximum current of 340 mA . Operating temperature between 32 F and 180 F. . The CMOS versions 80C86, 80C88 require only 10 mA and work in temperature range -40F 225F.
18-Mar-15 4 DC Characteristics
. Input characteristics: ------Logic level Voltage Current ------0 0.8 V max. 10µA max. 1 2.0 V min. 10µA max. ------
18-Mar-15 5 DC Characteristics (Cont.)
Output characteristics: ------Logic level Voltage Current ------0 0.45V max. 2mA max. 1 2.4V min. -400µA max. ------Noise immunity = 0.8 - 0.45 = 0.35 V (Standard = 0.4)
18-Mar-15 6 Pin Connections
. AD0 AD7 address/data bus lines compose the address bus of the 8088 and contain the rightmost 8 bits of the memory address when ALE=1 or data when ALE=0 . AD8 AD15 Upper multiplexed address/data bus on the 8086. . A8 A15 The 8088 address bus provides the upper-half memory address bits that are present throughout a bus cycle.
18-Mar-15 7 Pin Connections (Cont.)
. A16/S3 – A19/S6 Address/Status bus bits are multiplexed to provide address signals A16A19 and also status bits S3S6. Status bit S6 always remains a logic 0, bit S5 indicates the condition of the IF flag bits and S3, S4 show which segment is accessed during the current bus cycle. (See Table 5-4 page 105) . RD When the read signal = 0, data bus is receptive to data from memory or I/O device.
18-Mar-15 8 Pin Connections (Cont.)
. READY Used to insert wait states into the timing of the microprocessor. If READY=0, the µP is idle. If READY=1, no effect on the µP operation. . INTR Interrupt request is used to request a hardware interrupt. . TEST the Test pin is an input that is tested by the WAIT instruction. . NMI The Non-Maskable Interrupt is similar to INTR except that NMI does not check to see whether the IF flag bit = 1. If the NMI is activated, interrupt vector 2 is used.
18-Mar-15 9 Pin Connections (Cont.)
. RESET It causes the µP to reset itself if this pin is held high for 4 clock cycles (min.). The µP begins executing instructions at memory location FFFF0H, the IF flag is cleared (disable interrupts). . CLK Clock pin provides the basic timing signal to the microprocessor. (Duty cycle = 33%, high for 1 third of the clocking period and low for 2 thirds). . VCC Power supply input +5V ± 10%
18-Mar-15 10 Pin Connections (Cont.)
. GND The ground connection (Pins 1, 20) . MN/MX Minimum/Maximum mode selection pin. If minimum mode selected, this pin must be connected to +5V directly. . BHE/S7 The bus high enable pin is used in 8086 to enable the most significant data bus bits (D8D15). S7=1 forever.
18-Mar-15 11 Minimum Mode Pins
. IO/M or M/IO This pin selects memory or I/O. It indicates that the bus contains either a memory address or an I/O port address. . WR The write line indicates that the µP is outputting data to a memory or I/O device. . INTA The interrupt acknowledge signal is a response to the INTR pin. It gates the interrupt vector number onto the data bus in response to the interrupt request.
18-Mar-15 12 Minimum Mode Pins (Cont.)
. ALE The Address Latch Enable shows that the address bus contains address information. . DT/R The Data Transmit/Receive signal shows that the µP data bus is transmitting DT/R=1 or receiving DT/R=0. It is used to enable external data bus buffers. . DEN Data Bus Enable activates external data bus buffers.
18-Mar-15 13 Minimum Mode Pins (Cont.)
. HOLD The Hold input requests a DMA. If HOLD=1, the µP stops software execution, places its address, data, and control bus into high impedance state. If HOLD=0, the µP executes software normally. . HLDA Hold Acknowledge indicates that the µP has entered the hold state. . SS0 It is combined with IO/M and DT/R to decode the function of the current bus cycle.
18-Mar-15 14 Maximum Mode Pins
. In order to achieve maximum mode for operation with external coprocessors, connect the MN/MX pin to ground. . S0, S1, and S2 Status bits that indicate the function of the current bus cycle. See Tables (5-5 and 5-6) page 107 . RO/GT1 and RO/GT0 The request grant pins request DMA during maximum mode operation. They are bi-directional.
18-Mar-15 15 Maximum Mode Pins (Cont.)
. LOCK The Lock output is used to lock peripherals of the system using the LOCK: prefix of any instruction. . QS0 and QS1 The queue status bits show the status of the internal instruction queue. They are provided for access by the numeric coprocessor 8087. See Table (5-7) page 107
18-Mar-15 16 Clock Generator (8284A)
. The 8284A is an 18-pin IC that provides the following basic functions or signals: 1. Clock generation 2. RESET synchronization 3. READY synchronization 4. TTL-level peripheral clock signal
18-Mar-15 17 Pin Functions of The 8284A
. AEN1 and AEN2 The Address Enable pins are provided to quantify the bus ready signals RDY1 and RDY2. . RDY1 and RDY2 The bus ready inputs are provided in conjunction with AEN1 and AEN2 pins to cause wait states. . ASYNC The ready synchronization selection input selects either 1 or 2 stages of synchronization for the RDY1 and RDY2.
18-Mar-15 18 Pin Functions of The 8284A
. X1 and X2 The crystal oscillator pins connect to an external crystal used as the timing source for the clock generator. . F/C The Frequency/Crystal select input chooses the clocking source for the 8284A . . EFI The External Frequency Input is used when the F/C is high. . CLK The clock output pin provides the CLK signal to the µP and other system components. The CLK output signal is 1/3 of the crystal freq. with 33% duty cycle.
18-Mar-15 19 Pin Functions of The 8284A
. PCLK The Peripheral clock signal is 1/6 the crystal or EFI input frequency and has 50% duty cycle. . OSC The Oscillator O/P is a TTL-level signal that is at the same frequency as the crystal or EFI I/P . RES The Reset input is an active-low input to the 8284A. It is often connected to the RC network that provides power-on resetting. . RESET Connected to the µP RESET input pin.
18-Mar-15 20 Pin Functions of The 8284A
. CSYNC The clock synchronization pin is used when the EFI I/P provides synchronization in multiple processor systems. If the internal crystal oscillator is used, this pin is grounded. . GND The ground pin . VCC the power supply pin that connects to +5V±10%.
18-Mar-15 21 Bus Buffering and Latching
. The address/data bus on the 8086/8088 is multiplexed (shared) to reduce the number of pins required. . Why not leave the buses multiplexed? . Memory and I/O require the address remains valid and stable throughout the read or write cycle. . If buses are multiplexed, the address changes at the memory and I/O which causes them to read or write in wrong locations.
18-Mar-15 22 Demultiplexing the 8088
. Two 74LS373 transparent latches are used to demultiplex the address/data bus connections AD0 AD7 and the multiplexed address/status connections A16/S3 A19/S6 . We have separate address bus with connections A0 A19 that allow 8088 to address 1MB of memory space. See Fig. (5-5) Page 111
18-Mar-15 23 Demultiplexing the 8086
. Three 74LS373 transparent latches are used to demultiplex the address/data bus connections AD0AD15 and the multiplexed address/ status connections A16/S3A19/S6 and BHE/S7 . We have separate address bus with connections A0A19 that allow 8086 to address 1MB of memory space, 16-bit address bus D0D15, and 3 line control bus. See Fig. (5-6) Page 112
18-Mar-15 24 The Buffered System
. If more than 10 unit loads are attached to any bus pin, the entire system must be buffered. . The Fully Buffered 8088: Requires two 74LS373, two 74LS244, and one 74LS245 See Fig. (5-7) page 113 . The Fully Buffered 8086: Requires three 74LS373, one 74LS244, and two 74LS245 See Fig. (5.8) page 114
18-Mar-15 25 Thank You
With all best wishes !!
18-Mar-15 26