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DSP56824DS, DSP56824 16-Bit Digital Signal Processor Technical Freescale Semiconductor, Inc... configuration (see Figure (see configuration 1). onperipheral depending lines, (GPIO) Input/Output Purpose General thirty-two to and sixteen lines interrupt dedicated external two provides also DSP56824 The DSPs. other or microprocessors, codecs, as such devices, external multiple interfacing for support provides ports and peripherals ofprogrammable set rich The cycle. instruction RAM per data on-chip the from accessed be can operands data Two memories. orexternal internal either from execution program supports The DSP56824 CCompilers. for efficient highly also is set instruction The code. control DSP and compact efficient, of generation straightforward allow set instruction optimized and model programming MPU-style The cycle. instruction per operations six manyas as allowing parallel, in operating units execution three of consists core DSP56800 The cameras. digital and modems, phones, machines/feature answering digital messaging, wireless digital as such applications, cost-sensitive for well-suited is DSP56824 the code, program compact and flexibility, configuration cost, low ofits Because functions. and control processing signal for solution cost-effective excellent an it making flexibility, configuration with power processing DSPcombines purpose general This (DSPs). Processors Signal Digital of family core-based DSP56800 the of amember is DSP56824 The Processor Signal DSP56824 16-Bit Digital Data Technical DSP56824 Rev. 2.0 Rev. DSP56824 , 01/2000 DS Freescale Semiconductor, Inc. Table of Contents Part 1 Overview . 3 1.1 Data Sheet Conventions . 4 1.2 DSP56824 Features . 5 1.3 Product Documentation . 7 1.4 For the Latest Information . 7 Part 2 Signal/Connection Descriptions . 8 2.1 Introduction . 8 2.2 Power and Ground Signals . 9 2.3 Clock and Phase Lock Loop Signals . 10 2.4 Address, Data, and Bus Control Signals . 10 2.5 Interrupt and Mode Control Signals . 12 . 2.6 GPIO Signals . 13 . 2.7 Serial Peripheral Interface (SPI) Signals . 14 2.8 Synchronous Serial Interface (SSI) Signals . 16 c 2.9 Timer Module Signals . 17 n I 2.10 JTAG/OnCE™ Port Signals . 18 , r Part 3 Specifications . 19 o 3.1 General Characteristics . 19 t 3.2 DC Electrical Characteristics . 20 c 3.3 AC Electrical Characteristics . 21 u 3.4 External Clock Operation . 22 d 3.5 External Components for the PLL . 24 n 3.6 Port A External Bus Synchronous Timing . 26 o 3.7 Port A External Bus Asynchronous Timing . 29 c 3.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing . 30 i 3.9 Port B and C Pin GPIO Timing . 34 m 3.10 Serial Peripheral Interface (SPI) Timing . 36 3.11 Synchronous Serial Interface (SSI) Timing . 41 e 3.12 Timer Timing . 47 S 3.13 JTAG Timing . 48 e l Part 4 Packaging . 51 a 4.1 Package and Pin-Out Information . 51 c 4.2 Ordering Drawings . 57 s e Part 5 Design Considerations . 58 e 5.1 Thermal Design Considerations . 58 r 5.2 Electrical Design Considerations . 60 F Part 6 Ordering Information . 61 2 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Part 1 Overview 16 to 32 GPIO lines 4 8 8 4 4 6 2 Serial Program- Serial Synch. Timer/ Program Data Data Periph. Periph. Serial COP/ Memory Memory Memory mable Event × × × PLL GPIO Interface Interface Interface RTI 32 K 16 ROM 3584 2048 Interrupt (SPI0) Counters × GPIO (SPI1) (SSI) or or GPIO 128 16 RAM 16 RAM 16 ROM or GPIO or GPIO GPIO PAB External Address . Clock 16-bit Address XAB1 Address . Gen. Generation Bus . DSP56800 Unit XAB2 Switch 16 c Core n XDB2 I PGDB , Bit PDB External Data r Manipulation Data o Unit CGDB Bus t Switch 16 c u Data ALU Control JTAG/ × → ™ 16 16 + 36 36-bit MAC Bus d OnCE Program Controller Port Three 16-bit Input Registers Control n 4 Two 36-bit Accumulators o c MODA/IRQA 5 i MODB/IRQB RESET AA1445 m e Figure 1. DSP56824 Block Diagram S e l a c s e e r F DSP56824 Technical Data 3 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 1.1 Data Sheet Conventions This document uses the following conventions: • OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET. • Logic level one is a voltage that corresponds to Boolean true (1) state. • Logic level zero is a voltage that corresponds to Boolean false (0) state. • To set a bit or bits means to establish logic level one. • To clear a bit or bits means to establish logic level zero. • A signal is an electronic construct whose state or changes in state convey information. • A pin is an external physical connection. The same pin can be used to connect a number of signals. • Asserted means that a discrete signal is in active logic state. — Active low signals change from logic level one to logic level zero. c — Active high signals change from logic level zero to logic level one. n I • Deasserted means that an asserted discrete signal changes logic state. , r — Active low signals change from logic level zero to logic level one. o t — Active high signals change from logic level on to logic level zero. c • LSB means least significant bit or bits. MSB means most significant bit or bits. References to low u and high bytes or words are spelled out. d n Please refer to the examples in Table 1. o c Table 1. Data Conventions i m Signal/Symbol Logic State Signal State Voltage e S PIN True Asserted VIL/VOL e PIN False Deasserted V /V l IH OH a PIN True Asserted V /V IH OH c s PIN False Deasserted V /V IL OL e e r F 4 DSP56824 Technical Data For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. DSP56824 Features 1.2 DSP56824 Features 1.2.1 Digital Signal Processing Core • Efficient 16-bit DSP56800 family DSP engine • As many as 35 Million Instructions Per Second (MIPS) at 70 MHz • Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) • Two 36-bit accumulators including extension bits • 16-bit bidirectional barrel shifter • Parallel instruction set with unique DSP addressing modes • Hardware DO and REP loops . • Three internal address buses and one external address bus . c • Four internal data buses and one external data bus n • Instruction set supports both DSP and controller functions I , • Controller style addressing modes and instructions for compact code r o • Efficient C Compiler and local variable support t • Software subroutine and interrupt stack with unlimited depth c u d 1.2.2 Memory n • On-chip Harvard architecture permits as many as three simultaneous accesses to program and data o memory c i.
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