Chapter26 DigitalMultiplexers
In the same way that various analog systems are used to transmit analog signals of different bandwidths, there are various digital trans mission facilities designed to transmit digital signals of different rates. These facilities must be interconnected into a network that allows a digital signal to reach its destination using one or more of these facilities. Interconnections must be flexible enough to provide for alternate transmission paths in case of equipment failures, chang ing traffic patterns, and routine maintenance. Interconnection of fa cilities of the same digital rate involves either manual patching or automatic switching. Interconnection of different digital rates re quires multiplexers that combine several signals to share a higher speed digital facility. Time division multiplexing of several digital signals to produce a higher speed stream can be accomplished by a selector switch that takes a pulse from each incoming line in turn and applies it to the higher speed line. The receiving end will do the inverse of separating the higher speed pulse stream into its component parts and thus recover the several lower speed digital signals. The main problems involved are the synchronization of the several pulse streams so that they can be properly interleaved and the framing of the high-speed signal so that the component parts can be identified at the receiver end. Both of these operations require elastic stores, which constitute important parts of a multiplexer. Elastic stores are also called data buffers. Information pulses arriving at the multiplexer must await their turn to be applied to a higher speed transmission system. Due to delay variations of the incoming lines and to the framing and synchronization operation of the multiplexer terminal, this wait is variable in time.
608 Methods of Synchronization 609
The framing problem is similar to that of digital terminals, and the same techniques are available. For reasons of flexibility, added bit framing is chosen for all multiplexers. This choice assumes no given input signal statistics and leaves the digits intact so that a multiplexer can handle any digital signal regardless of its source.
26. l METHODS OF SYNCHRONIZATION The major problem of multiplexer system design is synchroniza tion. Digital signals cannot be directly interleaved in a way that allows for their eventual identification unless their pulse rates are locked to a common clock. Because the sources of these digital sig nals are often separated by large distances, their synchronization is difficult. Synchronization methods which can be used are: (1) master clock, (2) mutual synchronization, (3) stable clocks, and (4) pulse stuffing.
Master Clock An obvious method of synchronization is the use of a master clock for timing the entire system [1]. One outstanding difficulty of this approach is the vulnerability of the system to failures of either the master clock or the transmission links. A system with enough re dundancy and automatic protection against failures presents a diffi cult design problem and is expensive to establish.
Mutual Synchronization In this method of synchronization (referred to also :as phase averaging), each station or central office has its own clock whose frequency is the average of all the incoming frequencies and a local standard [2]. It can be shown that all stations will approach a com mon steady-state frequency. This method avoids one aspect of the master clock reliability problem since now no one clock or transmis sion path is essential. Further studies are necessary, however, to determine the optimum averaging algorithm for each station such that the network can grow gracefully from a few nodes to a large network and that minor disturbances such as protection switch ing of a transmission link will not cause the system frequency to swing beyond the design limits [3].
Stable Clocks A third method of synchronization is the use of very stable clocks at each office containing digital terminals. Elastic stores are then used 610 Digital Multiplexers Chap. 26 to absorb the very slowly varying phase errors. Since their capacity is finite, these stores must be reset pedodically with some loss of information. With atomic clocks stable to one part in 10 12 and with large enough elastic stores, loss of information will be acceptably infrequent. A combination of the preceding three methods is likely to be used in the future. Each region will have stable clocks supple mented by mutual synchronization while the master clock scheme will be used within each region.
Pulse Stuffing The final method of synchronization is pulse stuffing, presently being used in the design of multiplexers [4]. The concept is to have the outgoing digital rate of a multiplexer higher than the sum of the incoming rates by stuffing in additional pulses. All incoming digital signals are stuffed with a sufficient number of pulses to raise each of their rates to that of the locally generated clock signal, Fig. 26-1.
~~,~ l l \\Original signal l ! \ \ \ i ! ! \
* Stuffed signal to bt, * • Represents stuffed pulses multiplexed
Destuffed signol after smoothing
Fm. 26-1. Pulse stuffing synchronization.
Pulse stuffing is the least complex of the four methods proposed because it needs the least amount of buff er storage. In each of the other methods, even assuming that the clocks are perfectly synchron ous, propagation delay variations may cause a surplus or deficit of pulses at any one location. For example, a 1000-kilometer coaxial cable carry 3 X 10 8 pulses per second will have about one million pulses in transit, each pulse occupying about one meter of the cable. A 0.01 per cent variation of propagation delay, as would be produced Multiplexer System Design 611 by a 1 °F decrease in temperature will result in 100 fewer pulses in the cable; these must be absorbed by elastic stores in the multiplexer. With pulse stuffing, a deficit of one pulse is immediately made up by stuffing so that one cell of storage is all that is needed to handle such variations. Pulse stuffing is done independently for. each multiplexer, and this contributes to system reliability. The pqlse rate on a particular trans mission line is determined locally and will not influence any other clock in the system. Failure of one multiplexer or line will only affect those signals passing through that multiplexer or line. By choosing pulse stuffing, network synchronization is not pre cluded. Asynchronous low-speed digital signals are stuffed in order to use a higher speed transmission line; they are destuffed and the original rate restored before they leave the transmission system. If digital switching is established in the future, the lower speed signals can be made synchronous and the higher speed transmission lines can still be used. Flexibility is thus preserved.
26.2 MULTIPLEXER SYSTEM DESIGN
In addition to pulse stuffing, other design choices must be made to characterize the family of digital multiplexers. When a pulse is stuffed, an additional communication channel is used to inform the receiving terminal of the location of the stuffed pulse. Either this channel ·can be provided separately for each signal being stuffed or a common data channel can be shared. Separate stuff channels would be more flexible but because shared equipment is more economical, stuffing information for all signals entering a multiplexer is processed and transmitted on one channel. This common data channel is multi plexed along with the information pulses for transmission over a higher speed digita1 line. Another choice concerning the system design of the family of multiplexers is the structure of the digital hierarchy. Certain digital rates are designated as belonging to the hierarchy, e.g., 1.544 Mb/s is Tl rate, 6.312 Mb/s is T2, and 46.304 Mb/s is T3. Multiplexers accept signals of one rate and multiplex them only to the next higher rate. To combine .~everal Tl-speed digital signals into a TB rate, it is necessary to go through two multiplexers. Multiplexers are named for the rates they bridge. Multiplexer M12, for example, is designed to combine several Tl signals into a T2 signal. 612 Digital Multiplexers Chap. 26
Signal Format These design choices fix the general structure of the line formats of all multiplexers. Figure 26-2 illustrates a typical format, that of the M12 multiplexer [5]. Digit-by-digit interleaving of four signals at the Tl speed forms the fine structure of the format. After every 48 information time slots, 12 from each of the four Tl signals, a control digit is inserted by the multipllexer. Control digits labeled F are the main framing digits. Between F digits are control digits labeled M and C. Three successive C digits denote the presence or absence of a single stuffed pulse, and the corresponding M digit identifies in which of the four multiplexed Tl signals the stuff occurs. The M digits thus form secondary framing digits and iden tify four subframes. The subscripts of the M and F digits identify the digit as a O or a 1. Thus, F1 is always a 1 and the next control digit is either an M1 or Mo. The three C digits in the subframe follow ing Mo are stuffing indicators for the first T1 signal, three l's for the presence of a stuffed pulse and three O's for no-stuff. If the C digits indicate a stuff, the location of the stuffed pulse is the first informa tion pulse position associated with the first Tl signal following the next F1 pulse. The other sequences of C digits denote stuffing in the second, third, and fourth Tl signal. The use of three digits for a stuff indication provides a single digit error correction code. The demultiplexer at the receiving M12 first searches for the FoF1FoF1 sequence. This establishes identity for the four Tl signals
M,, [48] C1 [48] Fo [48] C1 [48] C1 [48] F, [ 48]
M, [48] Cu [48] Fo [48] Cn [48] Cu [48] F, [48]
M, [48] Cm [48] Fo [48] Cui [ ~18] Cm [48] F, [48]
M, [48] C1v [48] Fo [48] C1v [ ~8] C1v [4a] I F, [48] ----_.J --·- -- I rf1hl11lmlivlilnlm ------hn hvl Location for possible stuffing' pulse for Tl line for his subframe FIG. 26-2. M12 multiplexer format. Multiplexer System Design 613 and also for the M and C control digits. From the MoM1lVliM1se quence, secondary framing of the C digits is established and the four Tl signals are properly demultiplexed and destuffed. This format has two safeguards. The first is framing. It is possible, although un likely, that with just the FoF1FoF1 sequence, one of the Tl signals could contain a similar sequence. The receiver could then lock onto the wrong sequence. Presence of the MoM1M1M1provides verification of the genuine FoF1FoF1 sequence. The second safeguard is the single error correction ability of the stuff indicators. Error rate objectives of digital transmission lines make double errors very unlikely. The capacity of the M12 format to accommodate different input signal digital rates can be calculated from the format. In each M frame, defined as the interval containing one cycle of MoM1M1M1 digits, one pulse can be stuffed in each of four signals. Because each signal has 12 X 6 X 4 or 288 positions in each M frame, it can be incremented by 1.544 Mb/s X 1/288 or 5.4 kb/s, which is much larger than the expected frequency tolerance of the incoming Tl signal. The local clock that determines the outgoing speed alBo deter mines the nominal stuff rate, which must be high enough to accommo date the highest expected incoming rate. In more precise formulation the nominal T2 rate is 49 288 1.544 X 4 X 48 X 288 - S Mb/s where 4 is the number of Tl signals, 49/48 is the ratio of total time slots to information time slots, and S is the ratio of nominal to maxi mum stuffing rates. Choosing an S of 1/2 gives the greatest fre quency tolerance each way from nominal. A lower S reduces the waiting time jitter imparted to the signal as is explained subse quently. It is also desirable to select a nominal T2 clock frequency to be a multiple of 8 kHz. With these considerations, the T2 rate was chosen to be 6.312 megabits per second, and the resulting S is about 1/3. Although it seems that the M12 format has far greater stuffing capability than that warranted by the long-term frequency stability of the terminal, there are reasons for the extra margin. One is that the instantaneous frequency of a signal as it reaches a multiplexer can deviate beyond terminal frequency limits. This deviation is caused by timing jitter of the digital repeaters. In the cas,e of Tl, the instantaneous frequency deviation is estimated to be :±:1 kHz. The main reason for the extra margin, however, relates to the 614 Digital Multiplexers Chap. 26 reframe time of the multiplexer. In Chap. 25, it was seen that reframe time is proportional to the square of N, the number of digits between framing digits. To ensure that reframe time is at least shorter than that of the channel banks, N is constrained to be between 100 and 200. The stuffing control digits M and C are then located in fixed positions between the F' digits, which results in a simple fram ing circuit. These constraints lead to the M12 format which has some extra stuffing margin. Designs with fewer control digits are possible, but the increase in cost of the multiplexer must be weighed against the decrease in re quired channel capacity.
System Block Diagram A typical block diagram of a multiplexer is shown in Fig. 26-3. At the transmitting portion, each incoming pulse stream has a termi nating repeater and code translator. This equipment converts the incoming multilevel pulse signal into binary digits and extracts the timing information. The binary information is then written into individual elastic stores under control of the derived timing signal. The information is read out of the elastic store under control of the local clock in the multiplexer which has a higher frequency than the incoming clock signal. The occupancy of all the input elastic stores is sampled in turn by a common control circuit. The common control contains a local clock and countdown circuitry to time all its operations. When the occupancy of an elastic store is sampled, nothing is done if the state of depletion does not indicate a stuff; otherwise, a stuffing operation will take place as follows. First, a series of l's will be transmitted in the C positions of the format, and then reading of the elastic store will be suspended for one time slot at a predetermined location in the frame. The common control then cycles to sample the next elastic store. The binary digits as assembled by the common control are then converted into an appropriate pulse stream for application to the transmission line. The receiving portion of the multiplexer, Fig. 26--3, has a termi nating repeater and code translator to convert the multilevel pulse signals from the high-speed line back to the binary form. The re ceiving common control contains a clock and countdown circuit, similar to that of the transmitter, for demultiplexing and destuffing operations. A framing circuit keeps the receiving common control in phase with the line format.
~ ~
0 0
C: C:
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3 3
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VI VI VI VI
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cc· cc·
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translator translator
translator translator
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store store
store store
store store
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Elastic Elastic
Elastic Elastic
II II
H H
control control
Common Common
I I I
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Code Code
translator translator
T2 T2
6.312 6.312 Mb/s
-----
M12 M12 digital multiplexer block diagram.
Code Code
translator translator
I I
I I
FIG. 26-3. 26-3. FIG.
J J
control control
Common Common
I I I
11 11
hv1 hv1
~ ~
H H
~ ~
store store
store store
store store
store store
Elastic Elastic
Elastic Elastic
Elastic Elastic
Elastic Elastic
~ ~
H H
H H
H H
Code Code
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translator translator
translator translator
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-
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Tl Tl Tl Tl
Tl Tl Tl Tl 1.544 1.544 Mb/s 616 Digital Multiplexers Chap. 26
The C pulses are accumulated in a register as they arrive. If at least two C's in a subframe are l's, the next available time slot after the F 1 pulse for the appropriate Tl signal is assumed to contain a stuffed pulse that will not be written into the elastic store. Other wise, information is demultiplexed and written into the respective elastic stores for each channel. Since information is put into the elastic stores periodically but with occasional interruptions due to destuffed pulses, a phase-controlled clock is used to read information out of the store as smoothly as possible. After the binary information is read out of the store, it is converted back to a Tl signal.
Elastic Stores In a synchronous network, elastic stores compensate for delay vari ations, and it has been shown that the required size may become very large. In pulse stuffing, the elastic stores can be as small as one cell since single pulses are stuffed. However, other functions in the multiplex require some elastic delay, so elastic stores of four cells or more are usually used. Incoming digits are written into the store under control of the incoming timing clock and read out under control of an independent local clock. Since the number of digits an elastic store can hold is limited by the number of cells provided in the design, the delay between writing and reading is bounded by the store size. Elastic stores can be designed in several ways [6, 7]; one design has the commutator analogy of Fig. 26-4. Segments of the commutator are connected to storage cells. One brush writes into the cells ; another reads out of the cells. The angular velocities of the brushes corre spond to the frequencies of the writing and reading clocks. If the reading clock is slower than the writing clock, then the reading brush will slowly lag behind and eventually be overtaken. When that happens, a block of digits equal to the store size will be lost. Con versely, if reading is faster, reading will overtake writing and a block of digits will be repeated if reading is nondestructive. In both of these situations, the elastic store is said to have spilled. Synchron ization can be thought of as a technique that prevents indiscriminate spilling of elastic stores. Pulse stuffing is in one sense controlled spilling that allows the eventual recovery of the correct sequence of digits. Two conditions are necessary. First, the reading clock must be faster than the writing clock and second, insertion of extra digits must be done at prearranged times to permit proper removal.
:::;-
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0 0
......
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Voltage Voltage
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controlled controlled
Phase Phase
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output output
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Flip-flop Flip-flop
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------
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Phase-locked Phase-locked loop(VCO used in receive elastic store only)
L L
I I
I I
I I
I I
I I
I I
I I
I I
r r
FIG. 26-4. FIG. 26-4. An elastic store.
~~(/ ~~(/
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4 4
2 2
3 3
cell cell
cell cell
cell cell cell cell l
Storage Storage
Storage Storage Storage Storage
Storage Storage
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Writing Writing Writ;-;;,~ Writ;-;;,~ 618 Digital Multiplexers Chap. 26
The first condition is satisfied by assignment of nominal fre quencies and allowed frequency tolerances. The second condition is satisfied by periodically monitoring the delay between writing and reading. When the delay is below a given threshold, reading is caused to dwell at a cell for an additional time slot. This effectively simu lates spilling of an ideal one-cell elastic store. The measurement of the delay between writing and reading is made by a phase comparator as shown in Fig. 26-4. This can be imple mented by a flip-flop that is set when the writing reaches a given cell and reset when the reading reaches the same cell. Under normal con ditions when readings of each cell occur midway between writings, the flip-flop will generate a 50 per cent duty cycle square wave. As the delay of writing and reading changes, the duty cycle will change. The average output of this flip-flop is a measure of the duty cycle and thus of the store occupancy, Fig. 26-5.
Cell 4 Cell 4 write time read time
Elastic store + +
Hall full _J I 11 L_
_r, ____ ,n___ _ Near depletion
Near full ...J LJI L
FIG. 26-5. Phase comparator output.
With pulse stuffing, even when the incoming information stream is uniformly spaced, the outgoing stream is not uniform. It will have occasional interruptions where the information pulses are inter leaved with a stuffed pulse, Fig. 26-1. Thus, even after successful removing of stuffed pulses, the received information digits have jitter which must be smoothed before the-digits can be processed further. Smoothing of this jitter is the function of a receiving elastic store and its phase-locked loop. Multiplexer System Design 619
Phase-Locked Loop In order to smooth a jittered digital stream, a read clock is needed that has a frequency equal to the average frequency of the incoming jittered clock. Since measuring the frequency of a jitteredl clock is difficult, the read clock can only make the best running estimate of the average input frequency. Such a read clock can be generated by a phase-locked loop.
Phase comparator Voltage Filter v, (t) o( t) controlled H(s) oscillator
FIG. 26-6. Phase-locked loop.
A phase-locked loop, Fig. 26-6, consists of a voltage controlled oscillator (VCO) whose frequency is a function of a voltage, and a phase comparator whose output voltage is proportional to the phase difference between the incoming sinusoid and the sinusoid of the VCO. A filter is used between the phase comparator and the VCO to improve performance. The phase comparator is the same as that used in the transmitting portion to measure elastic store occupancy. The output voltage for the phase comparator is [8]
/ cf>e(t) I 3 = _a3 Vi(s) H (s) (26-2) 8 where Since q>ecannot exceed N'TT',the phase-locked loop can only lock onto a finite range of input frequencies. From Eq. (26-4) this range is (26-5) Steady-state error is undesirable because it causes the loop and the elastic store to operate away from thEi desired half-full quiescent level. The margin against spilling will thus be reduced. The steady-state phase error can be reduced by increasing a, but good filtering requires a small a. ThEi trade-off situation can be improved by using a phase lag filter. 2 H(s) = a2G(s) = a:z i ! ST (26-6) 8T1 The loop response is now Without changing a, the output filter bandwidth can be reduced by suitable choices of r1 and r2. However, other undesirable effects appear and must be recognized in arriving at a compromise ri and r2. The use of a filter can introduce enhancement of jitter in certain frequency bands. When many multiplexers are used in cascade, this enhancement accumulates. Another possible consequence of add ing a filter is the overshoot of the VCO output frequency in response to rapid changes in input frequency. This can cause spilling of the elastic store and must be considered in the overall design. The lock range of the loop is determined by Eq. (26-5). However, when a filter is present, Eq. (26-5) is valid only if the loop is initially locked. The range of mistuning for which lock is possible under any initial condition is smaller than that indicated by Eq. (26-5)1. This pull-in range depends on r1 and r2 and should exceed the expected frequency deviations of both the VCO and the incoming signal. If pulses are stuffed one at a time, the maximum jitter is one time slot. To smooth this jitter an ideal one-cell store is needed. It has already been shown that because of constraints of phase-locked loop design, more than one cell is needed to accommodate frequency off set and possible overshoots. Digital signals arriving at a multiplexer from a long transmission line can have phase jitter, which produces instantaneous frequency deviations. The phase-locked loop can be designed either to smooth or to pass this line jitter. The first choice requires additional elastic storage capacity and small a, while the second choice requires a large a and smaller storage capacity. Other functions of the demultiplexing operation also require their share of s,torage. Practical electronic circuits take finite time to oper ate and place minimum phase separation requirements between writ ing and reading clocks. Insertion and deletion of control pulses also require storage. Finally, there is waiting time jitter, which is treated in more detail in Section 26.3. Taking all this into account, an estimated requirement on storage capacity can be made. For example, the following allocations for the M12 result in a four-cell elastic store: Read-write time 0.25 cells Control pulses 0.25 Stuffing jitter 1.00 Waiting time jitter 0.50 Frequency offset 1.00 Line jitter 1.00 Total 4.00 cells 622 Digital Multiplexers Chap. 26 26.3 DIGITAL MULTIPLEXER IMPAIRMENTS Impairments arise when digital signals are processed by multi plexers. These impairments must be understood, and the multiplexers must be designed for negligible degradation to the original signal. Two significant impairments are waiting time jitter and multiplexer reframes. Waiting Time Jitter While it is obvious that pulse stuffing produces jitter of one time slot, there is a more subtle jitter caused by the fact that stuffing takes place only in certain allowed time slots [9]. This process can be demonstrated by a few simple examples. A simple case occurs when the frequencies of the write and read clocks are such that stuffing takes place every third allowed time slot. This is called a stuffing ratio of 1 ::3. Consider the waveform of the phase comparator at the transmitting multiplex, and assume an ideal two-cell elastic store with writing immediately following the reading of a cell. The store is now full; however, it will slowly deplete because the read clock is faster. When the first opportunity for stuff ing arrives, the store has depleted by only 1/3 of a cell; therefore, stuffing does not take place. At the second stuffing opportunity, the store has depleted by 2/3 of a cell, and stuffing still does not take place. At the third opportunity, the store has depleted one full cell so that stuffing can take place. After Btuffing, writing immediately follows reading again and the cycle repeats. The phase comparator waveform, which is also the jitter imparted to the signal, is a saw tooth as shown in Fig. 26-8. For this ca8e, a one-cell ideal store would be sufficient. If the initial condition is such that writing occurs 1/6 time slot after reading, then at the second stuffing opportunity the store will be depleted by 5/6 of a cell. When depletion reaches one cell, stuffing Stuffing opportunities Full 1 e-m-pt-yc-.=1::ll ,------,,~----.=------==----;JS----=:,---J::5..--..--,-.:::----- 2 empty cells FIG. 26-8. Jitter due to stuffing at 1/3 of maximum rate. Digital Multiplexer Impairments 623 cannot take place until the next allowed stuffing time. By that time, the depletion has reached 1-1/6 cells. The conclusion is that because of various initial conditions, at least 1-1/3 cells of elastic store are needed to stuff at one-third the maximum stuff rate. Next, consider the case where the correct amount of stuffing is 5/14 of the maximum. The slope of the phase comparator is such that at the first stuffing opportunity, 5/14 of a cell is depleted. Initially, stuffing takes place at every third opportunity. However, since store depletion is slightly faster than 1/3 of a cell for each stuffing possibility, there is a gradual buildup of excess depletion whfoh after 14 stuffing opportunities causes stuffing to be spaced by only two periods instead of three. This is shown in Fig. 26-9. Since stuffing has occurred five times in 14 intervals, the deficit has been made up exactly and the cycle repeats. What has been demonstrated is the phenomenon of waiting time jitter, which is a lower frequency jitter envelope superimposed on the faster jitter. It can be shown that if the nominal stuffing ratio, S, is n/m, where n and m are relatively prime, the period of the waiting time jitter is m stuffing intervals long. The ratios of two uncontrolled frequencies are, in general, irrational; therefore, the nominal stuffing ratios are irrational. Wait ing time jitter is thus expected to have components down to zero frequency. The peak-to-peak waiting time jitter is S; thus a lower stuffing ratio results in lower waiting time jitter. Stuffing opportunities Full 1 empty eel~,-...... , ,-...... , ,-...... , ~ ,-...... __ 2 empty cells "~~-...... ~ FIG. 26-9. Jitter due to stuffing at 5/14 of maximum rate. The elastic store at the demultiplexer is designed to :filter all jitter; however, since waiting time jitter extends to zero frequency, it will not be completely eliminated. For this reason pulse stuffing invariably imparts to the digital signal some low-frequency jitter which by design can be made insignificant. Usually, the low-frequency component of waiting time jitter tends to accumulate linearly with the number of tandem multiplexers. This will not cause any difficulty in digital transmission because low-frequency jitter is preserved by the stuffing operations, the phase-locked loops, and the digital repeaters. 624 Digital Multiplexers Chap. 26 This low-frequency jitter is passed on to the decoded baseband analog signal and, as long as the frequencies of the residual jitter are held low enough, negligible degradation to the signal results. Multiplex Reframe In a digital hierarchy, framing serves to hold the structure to gether so that each digit can be correctly demultiplexed. Since the impairment to the baseband signal due to loss of frame has no counterpart in analog transmission systems, it is important to recog nize its effect in digital systems. If a channel bank loses frame, all channels served by the bank will have unintelligible signals until frame is reestablished. The requirement that a channel bank re frame within 50 milliseconds is based both on practicality and the impairment to message service, i.e., message signals and signaling. Reframe time is usually fast enough so that the impairments to message signals are inconsequential; however, some signaling may be affected. To minimize these impairments, either the reframe time must be short enough to have no effect or the incidents must be infrequent. In a digital network the overall signal outage due to reframe anywhere in the network must be considered. Multiplexer reframes are particularly important for the following reasons: 1. Multiplexers serve a large number of circuits .. 2. Multiplexer reframe causes loss of pulse stuffing information, which results in loss of frame for all individual signals. 3. Multiplexers are connected by higher speed digital lines which tend to be long and prone to protection switching and lightning hits. In the worst case, each multiplexer waits until all of the higher speed multiplexers reframe and then incurs the maximum reframe time itself. The signal outage in this case becomes the sum of the maximum reframe times. To reduce total reframe time, two ap proaches can be taken. In the first, both multiplexers and channel banks are designed for a very short reframe time. In the second approach, the channel banks are allowed a long reframe time, but each multiplexer in the hierarchy is designed to aid the reframe of terminals connected to it and of lower speed multiplexers. As an example of the second approach, the M12 multiplexer, when it re frames, produces higher than the nominal pulse rate, which is equiva lent to adding pulses to the bit stream. The assumed framing pulse position at a channel bank then occurs before the true framing pulse. Multiplexer Performance Monitoring 625 Normal search procedure of the channel bank will then test the next pulse positions for possible framing position. If the multiplexer reframe is fast and the number of pulses added is small, the chan nel banks need to search only a few positions before finding the true framing pulse. 26.4 MULTIPLEXER PERFORMANCE MONITORING Since both inputs and outputs of a digital multiplexer are digital signals, precise monitoring of the performance of a multiplexer can be accomplished by putting another multiplexer in parallel and comparing the signals digit by digit. The second multiplexer is called a monitoring unit and is time shared by many multiplexers. To monitor the transmitting part of the multiplexer, the higher rate digital output is demultiplexed by the monitoring unit and the resultant signal compared digit by digit with the input. To monitor the receiving part, the incoming digital signal is demultiplexed by the monitoring unit, and the resultant signal is compared with that of the multiplexer being monitored. An elastic store is used to adjust the relative delays. The time necessary for the monitoring unit to cycle through each of the multiplexers in a bay determines the maximum time that a failure goes undetected. Failure of the monitoring unit itself is indicated by apparent failures in all the multiplexers. REFERENCES 1. Darwin, G. P. and R. C. Prim. "Synchronization in a System of Intercon nected Units," U.S. Patent 2986723, May 1961. 2. Runyon, J. P. "Reciprocal Timing of Time Division Switching Centers," U.S. Patent 3050586, August 21, 1962. 3. Pierce, J. R. "Synchronizing Digital Networks," Bell System Tech. J., vol. 48 ( Mar. 1969), pp. 615-636. 4. Graham, R. S. "Pulse Transmission System," U.S. Patent 3042751, 1962. 5. Bruce, R. A. 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