DOCSLIB.ORG

Digital Signal Processing Applications and Implementation for Accelerators

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Digital Signal Processing Applications and Implementation for Accelerators EUROPEAN ORGANIZATION FOR NUCLEAR RESEARCH CERN − SL DIVISION CERN-SL-2002-047 (HRF) Digital Signal Processing Applications and Implementation for Accelerators Digital Notch Filter with Programmable Delay and Betatron Phase Adjustment for the PS, SPS & LHC Transverse Dampers V. Rossi Abstract In the framework of the LHC project and the modifications of the SPS as its injector, I present the concept of global digital signal processing applied to a particle accelerator, using Field Programmable Gate Array (FPGA) technology. The approach of global digital synthesis implements in numerical form the architecture of a system, from the start up of a project and the very beginning of the signal flow. It takes into account both the known parameters and the future evolution, whenever possible. Due to the increased performance requirements of today's projects, the CAE design methodology becomes more and more necessary to handle successfully the added complexity and speed of modern electronic circuits. Simulation is performed both for behavioural analysis, to ensure conformity to functional requirements, and for time signal analysis (speed requirements). The digital notch filter with programmable delay for the SPS Transverse Damper is now fully operational with fixed target and LHC- type beams circulating in the SPS and is a successful implementation of this concept. The transfer function is programmable and therefore the same equipment can be reprogrammed for use in future projects. General concept and digital notch filter with programmable delay presented at Workshop on DSP Applications in the SL Division. CERN-SL, 5th November 2001 Geneva, Switzerland July 2002 2 Abstract 1. INTRODUCTION 2. FROM REQUIREMENTS TO DESIGN 2.1 Required bandwidth 2.2 Number of bits 3. DATA CONVERSION 3.1 ADC module 3.2 DAC module 3.3 Test set-up 4. TRANSVERSE FEEDBACK SYSTEM 5. DIGITAL NOTCH FILTER AND ONE TURN DELAY 5.1 Digital Notch Filter with programmable delay for the SPS 5.2 Gating 5.3 Modes of operation 6. METHOD FOR IMPLEMENTATION OF THE DIGITAL SIGNAL PROCESSING 7. TRANSFER FUNCTION IMPLEMENTATION 7.1 Synchronous design 7.2 Delay function 7.3 Arithmetic Logic Unit 7.4 User Module Interface and Look-up table 7.5 I2C Controller & Reset 8. FINE DELAY 8.1 I2C interface 8.2 Conversion algorithm 8.3 Interlock 9. DESIGN ENTRY 10. SCHEMATIC DIAGRAM 11. SIGNAL INTEGRITY 12. BOARD MANUFACTURING 13. LABORATORY TEST 14. RESULTS WITH BEAM 3 15. BETATRON PHASE ADJUSTMENT 15.1 Hilbert filter 15.2 Realisation 15.3 MD results 16. CONCLUSIONS 17. FUTURE DEVELOPMENTS References Acknowledgements 4 Digital Signal Processing Applications and Implementation for Accelerators Digital Notch Filter with Programmable Delay and Betatron Phase Adjustment for the PS, SPS & LHC Transverse Dampers Vittorio Rossi, CERN, SL-HRF Abstract In the framework of the LHC project and the modifications of the SPS as its injector, I present the concept of global digital signal processing applied to a particle accelerator, using Field Programmable Gate Array (FPGA) technology. The approach of global digital synthesis implements in numerical form the architecture of a system, from the start up of a project and the very beginning of the signal flow. It takes into account both the known parameters and the future evolution, whenever possible. Due to the increased performance requirements of today's projects, the CAE design methodology becomes more and more necessary to handle successfully the added complexity and speed of modern electronic circuits. Simulation is performed both for behavioural analysis, to ensure conformity to functional requirements, and for time signal analysis (speed requirements). The digital notch filter with programmable delay for the SPS Transverse Damper is now fully operational with fixed target and LHC-type beams circulating in the SPS and is a successful implementation of this concept. The transfer function is programmable and therefore the same equipment can be reprogrammed for use in future projects. 1. INTRODUCTION As a general rule, signals, derived from the beam or from equipment through transducers, are processed either for observation or they are injected into feedback loops, figure 1. Fig. 1 – Block diagram of closed loop response for a feedback system. The response of the system is: R(s) G(s) W (s) = = (1) P(s) 1− H 1(s)⋅ H 2(s)⋅G(s) Where: W (s) system response R(s) resulting beam position P(s) perturbation G(s) beam response H 1(s) low level response H 2(s) power amplifier response The system is stable if the real part of H 1(s)⋅ H 2(s)⋅G(s) is less than +1. 5 Treating the low level signals in the digital domain allows flexibility for the subsequent treatment. Fig. 2 presents the overall concept layout: a single Digital Signal Processing Unit (DSPU) performs all the numerical treatment necessary to implement the H 1(s) transfer function. The DSPU is preceded by an Analog to Digital Converter and followed by a Digital to Analog Converter. To achieve behaviour independent from the sampling rate, the clock is fed to the ADC and routed, together with the data, to the following DSPU and DAC, with identical delay. The ADC-DSPU-DAC combination possesses a unity gain; its intrinsic bandwidth is from DC up to the Nyquist limit. Following the requirements of the project, amplification and filtering can be added before and/or after the data conversion or implemented in the DSPU. Clock Analog DSPU Analog input ADC Data Data DAC output Clock Clock Fig. 2 – Digital Signal Processing Unit associated to data conversion. In view of the LHC requirements and to minimise the noise injected to the stored beams, decreasing its lifetime, the quantisation error introduced by the data conversion should be reduced to a minimum. This requirement defines the minimum number of bits in the conversion and in the processing. Fast applications involving beam control on a bunch-by-bunch basis suggest the choice of a hardware-based digital signal processing solution compared to a software-program approach. Fast processing speed motivates the implementation in a Field Programmable Gate Array rather than in a floating point Digital Signal Processor. Transfer functions can thus be designed and synthesised in VHDL and implemented in programmable devices. Simulation of the FPGA is performed both for behavioural analysis (conformity to project requirements) and time analysis (speed requirements). Implementation in digital form in modern electronic circuits is realised through routing tools preserving the signal integrity (delay, crosstalk etc.). A different transfer function can be calculated for a different application and loaded in the programmable device. Within the limits of the maximum system gates and the data conversion range, the same equipment can be employed for several applications. An example of such a procedure is presented in the following sections 2 and 3 using LHC requirements and parameters to provide concrete numbers. The detailed design of a system for the SPS transverse damper for multi-cycling applications is presented in section 4-15. 2. FROM REQUIREMENTS TO DESIGN 2.1 Required bandwidth The system under consideration is a bunch-by-bunch feedback with bunch spacing Tb and bandwidth W =1 2Tb . For LHC, where Tb is 25 ns, the required bandwidth is 20 MHz for the whole system. The low-level part is over designed, with sampling rate up to 120 MSPS, a three times over sampling at the 40 MHz LHC bunch frequency that allows a Nyquist bandwidth up to 60 MHz. To minimize the emittance blow-up at injection, the damping time has to be shorter than the beam decoherence time and the system should be able to damp the coherent motion of each individual batch. In this case the required bandwidth is less and it is determined by the batch spacing (not the bunch spacing). 6 2.2 Number of bits When sampling is considered, an infinite number of bits are theoretically required to represent each value. Physical limitations preclude sampling with infinite precision and a system with a finite number b of bits is assumed. With digital signal processing of the signal, the main source of noise is assumed to be the quantisation noise. For the LHC stored beams, it is proposed to reduce the quantisation error below the minimum acceptable value, to reduce the injected noise and increase the beam lifetime. From [1], the transverse emittance growth rate for a beam of transverse rms size ±σ, depends on tune spread and quantisation error, as follows: 1 4 = f ⋅α 2 ⋅δQ 2 (2) τ 0 x 2 3 1 −()− where defines the transverse emittance blow-up rate, f the revolution frequency, α = 2 b 1 the τ 0 x 2 quantisation width and δQ the tune spread. = δ ≈ −2 Taking the example for the LHC: f0 11 kHz , Q 10 and an 11 bit effective, 12 bit ADC with −()b−1 1 α = 2 = , one obtains a transverse emittance growth time τ 2 = 200 hours, which is satisfactory. 1024 x Sampling rate up to 120 MSPS and a resolution of 12 bit are the features chosen to design the DSPU, complying with the LHC-type beam requirements. 3. DATA CONVERSION The data conversion is fundamental for the precision of the complete system. The purpose of the development is the realisation of data conversion building blocks with high precision in the analog section and high resolution and speed in the digital section. State of the art devices have been targeted, 12 bit, (with further evolution in mind, 14-bit) and sampling rate up to 120 MSPS. In this way future evolution and reuse in other projects is possible. 3.1 ADC module Analog to digital conversion can be performed up to 120 MHz. The heart of the circuit is the AD9432, from Analog Devices, a monolithic 12 bit ADC with integral track and hold circuit and an integral non-linearity of ± 0.5 LSB (data sheet: see http://www.analog.com ).
Load more

Recommended publications
  • Design and Evaluation of a Clock Multiplexing Circuit for the SSRL Booster Accelerator Timing System
    SLAC-TN-15-018 Design and Evaluation of a Clock Multiplexing Circuit for the SSRL Booster Accelerator Timing System Million Araya† August 21, 2015 Seattle Central Community College, Seattle, WA CCI Program, SLAC National Accelerator Laboratory SPEAR3 is a 234 m circular storage ring at SLAC’s synchrotron radiation facility (SSRL) in which a 3 GeV electron beam is stored for user access. Typically the electron beam decays with a time constant of approximately 10hr due to electron lose. In order to replenish the lost electrons, a booster synchrotron is used to accelerate fresh electrons up to 3GeV for injection into SPEAR3. In order to maintain a constant electron beam current of 500mA, the injection process occurs at 5 minute intervals. At these times the booster synchrotron accelerates electrons for injection at a 10Hz rate. A 10Hz 'injection ready' clock pulse train is generated when the booster synchrotron is operating. Between injection intervals-where the booster is not running and hence the 10 Hz ‘injection ready’ signal is not present-a 10Hz clock is derived from the power line supplied by Pacific Gas and Electric (PG&E) to keep track of the injection timing. For this project I constructed a multiplexing circuit to 'switch' between the booster synchrotron 'injection ready' clock signal and PG&E based clock signal. The circuit uses digital IC components and is capable of making glitch-free transitions between the two clocks. This report details construction of a prototype multiplexing circuit including test results and suggests improvement opportunities for the final design. I. Introduction The ultimate purpose of a synchrotron radiation facility is to generate stable, high-power beams of light spanning from the Infrared to x-ray portion of the electromagnetic spectrum.
    [Show full text]
  • Radar Transmitter/Receiver
    Introduction to Radar Systems Radar Transmitter/Receiver Radar_TxRxCourse MIT Lincoln Laboratory PPhu 061902 -1 Disclaimer of Endorsement and Liability • The video courseware and accompanying viewgraphs presented on this server were prepared as an account of work sponsored by an agency of the United States Government. Neither the United States Government nor any agency thereof, nor any of their employees, nor the Massachusetts Institute of Technology and its Lincoln Laboratory, nor any of their contractors, subcontractors, or their employees, makes any warranty, express or implied, or assumes any legal liability or responsibility for the accuracy, completeness, or usefulness of any information, apparatus, products, or process disclosed, or represents that its use would not infringe privately owned rights. Reference herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise does not necessarily constitute or imply its endorsement, recommendation, or favoring by the United States Government, any agency thereof, or any of their contractors or subcontractors or the Massachusetts Institute of Technology and its Lincoln Laboratory. • The views and opinions expressed herein do not necessarily state or reflect those of the United States Government or any agency thereof or any of their contractors or subcontractors Radar_TxRxCourse MIT Lincoln Laboratory PPhu 061802 -2 Outline • Introduction • Radar Transmitter • Radar Waveform Generator and Receiver • Radar Transmitter/Receiver Architecture
    [Show full text]
  • V850 Standby Modes
    Application Note V850 Standby Modes V850ES/SG2 V850ES/SJ2 Document No. U18825EE1V0AN00 Date Published June 2007 © NEC Electronics Corporation June 2007 Printed in Germany NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
    [Show full text]
  • Lecture 11 : Discrete Cosine Transform Moving Into the Frequency Domain
    Lecture 11 : Discrete Cosine Transform Moving into the Frequency Domain Frequency domains can be obtained through the transformation from one (time or spatial) domain to the other (frequency) via Fourier Transform (FT) (see Lecture 3) — MPEG Audio. Discrete Cosine Transform (DCT) (new ) — Heart of JPEG and MPEG Video, MPEG Audio. Note : We mention some image (and video) examples in this section with DCT (in particular) but also the FT is commonly applied to filter multimedia data. External Link: MIT OCW 8.03 Lecture 11 Fourier Analysis Video Recap: Fourier Transform The tool which converts a spatial (real space) description of audio/image data into one in terms of its frequency components is called the Fourier transform. The new version is usually referred to as the Fourier space description of the data. We then essentially process the data: E.g . for filtering basically this means attenuating or setting certain frequencies to zero We then need to convert data back to real audio/imagery to use in our applications. The corresponding inverse transformation which turns a Fourier space description back into a real space one is called the inverse Fourier transform. What do Frequencies Mean in an Image? Large values at high frequency components mean the data is changing rapidly on a short distance scale. E.g .: a page of small font text, brick wall, vegetation. Large low frequency components then the large scale features of the picture are more important. E.g . a single fairly simple object which occupies most of the image. The Road to Compression How do we achieve compression? Low pass filter — ignore high frequency noise components Only store lower frequency components High pass filter — spot gradual changes If changes are too low/slow — eye does not respond so ignore? Low Pass Image Compression Example MATLAB demo, dctdemo.m, (uses DCT) to Load an image Low pass filter in frequency (DCT) space Tune compression via a single slider value n to select coefficients Inverse DCT, subtract input and filtered image to see compression artefacts.
    [Show full text]
  • Generate a Clock Signal from a Crystal Oscillator
    www.ti.com Product Overview Generate a Clock Signal from a Crystal Oscillator Clocked Device U CLK Figure 1-1. Using an Unbuffered Inverter and Schmitt-Trigger Inverter to Generate a Clock Signal From a Crystal Oscillator Design Considerations • Drive crystal oscillators directly • Can be disabled with added logic • Allows for selectable system clocks with multiple crystals • Outputs a clean and reliable square wave • See the Use of the CMOS Unbuffered Inverter in Oscillator Circuits Application Report for more information about this use case. • Need additional assistance? Ask our engineers a question on the TI E2E™ logic support forum Recommended Parts Part Number Automotive Qualified VCC Range Features SN74LVC2GU04-Q1 ✓ 1.65 V — 5.5 V Dual unbuffered inverter SN74LVC2GU04 SN74AHC1GU04 2 V — 5.5 V Single unbuffered inverter SN74AUC1GU04 0.8 V — 2.7 V Single unbuffered inverter SN74LVC1G17-Q1 ✓ 1.65 V — 5.5 V Single Schmitt-trigger buffer SN74LVC1G17 For more devices, browse through the online parametric tool where you can sort by desired voltage, channel numbers, and other features. SCEA099 – OCTOBER 2020 Generate a Clock Signal from a Crystal Oscillator 1 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products.
    [Show full text]
  • (MSEE) COMMUNICATION, NETWORKING, and SIGNAL PROCESSING TRACK*OPTIONS Curriculum Program of Study Advisor: Dr
    MASTER OF SCIENCE IN ELECTRICAL ENGINEERING (MSEE) COMMUNICATION, NETWORKING, AND SIGNAL PROCESSING TRACK*OPTIONS Curriculum Program of Study Advisor: Dr. R. Sankar Name USF ID # Term/Year Address Phone Email Advisor Areas of focus: Communications (Systems/Wireless Communications), Networking, and Digital Signal Processing (Speech/Biomedical/Image/Video and Multimedia) Course Title Number Credits Semester Grade 1. Mathematics: 6 hours Random Process in Electrical Engineering EEE 6545 3 Select one other from the following Linear and Matrix Algebra EEL 6935 3 Optimization Methods EEL 6935 3 Statistical Inference EEL 6936 3 Engineering Apps for Vector Analysis** EEL 6027 3 Engineering Apps for Complex Analysis** EEL 6022 3 2. Focus Area Core Courses: 15 hours (Select a major core with 2 sets of sequences from groups A or B and a minor core (one course from the other group) A. Communications and Networking Digital Communication Systems EEL 6534 3 Mobile and Personal Communication EEL 6593 3 Broadband Communication Networks EEL 6506 3 Wireless Network Architectures and Protocols EEL 6597 3 Wireless Communications Lab EEL 6592 3 B. Signal Processing Digital Signal Processing I EEE 6502 3 Digital Signal Processing II EEL 6752 3 Speech Signal Processing EEL 6586 3 Deep Learning EEL 6935 3 Real-Time DSP Systems Lab (DSP/FPGA Lab) EEL 6722C 3 3. Electives: 3 hours A. Communications, Networking, and Signal Processing Selected Topics in Communications EEL 7931 3 Network Science EEL 6935 3 Wireless Sensor Networks EEL 6935 3 Digital Signal Processing III EEL 6753 3 Biomedical Image Processing EEE 6514 3 Data Analytics for Electrical and System Engineers EEL 6935 3 Biomedical Systems and Pattern Recognition EEE 6282 3 Advanced Data Analytics EEL 6935 3 B.
    [Show full text]
  • VLSI Digital Signal Processing
    CLOCKS Clocks in Digital Systems • Why are clocks and clocked memory registers needed inside digital systems? • Clocks pace the flow of data inside digital processors • The exact speed of data through circuits is impossible to predict accurately due to factors such as: – Fabrication process variations – Supply voltage variations “PVT variations” – Temperature variations – Countless parasitic effects (e.g., wire-to-wire capacitances) – Data-dependent variations (e.g., calculating 1 OR 1 = 1 requires a different delay than 1 OR 0 = 1) © B. Baas 322 Clocks in Digital Systems • Clocked memory elements slow down the fastest signals, wait until all signals have finished propagating through the combinational logic in the stage*, and then release them into the next stage simultaneously, controlled by the active edge of the clock signal • * This is why we care about clock only the single slowest signal in a block (max propagation delay) when finding the maximum clock frequency © B. Baas 323 Clocks in Digital Systems • All paths within a digital system consist of an input register, (optionally) followed by combinational logic, followed by an output register • Therefore: – If we can make this structure work under all conditions, we can build a robust digital system – We should analyze this structure carefully clock a combinational out b logic c_p1 c_p3 © B. Baas c_p2 324 Robust Clock Design • Edge-triggered memory elements (flip-flops) are generally more robust than level-sensitive memory elements (transparent latches) • Always follow these rules in this class, and for the most robust designs: 1. Only clock signals may connect to flip-flop or latch clock inputs • A simpler circuit may sometimes be possible if a logic signal is connected to a clock input, but do not do it for robustness • always @(posedge key) begin 2.
    [Show full text]
  • Tms320f280x, Tms320c280x, Tms320f2801x Digital Signal Processors
    TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802, TMS320F2809, TMS320F2808, TMS320F2806,TMS320C2801, TMS320F2802, TMS320F28016, TMS320F2801, TMS320F28015TMS320C2802, www.ti.com TMS320C2801,SPRS230P – OCTOBER TMS320F28016, 2003 – REVISED TMS320F28015 FEBRUARY 2021 SPRS230P – OCTOBER 2003 – REVISED FEBRUARY 2021 TMS320F280x, TMS320C280x, TMS320F2801x digital signal processors 1 Features • Three 32-bit CPU timers • Enhanced control peripherals • High-performance static CMOS technology – Up to 16 PWM outputs – 100 MHz (10-ns cycle time) – Up to 6 HRPWM outputs with 150-ps MEP – 60 MHz (16.67-ns cycle time) resolution – Low-power (1.8-V core, 3.3-V I/O) design – Up to four capture inputs • JTAG boundary scan support – Up to two quadrature encoder interfaces – IEEE Standard 1149.1-1990 Standard Test – Up to six 32-bit/six 16-bit timers Access Port and Boundary Scan Architecture • Serial port peripherals • High-performance 32-bit CPU (TMS320C28x) – Up to 4 SPI modules – 16 × 16 and 32 × 32 MAC operations – Up to 2 SCI (UART) modules – 16 × 16 dual MAC – Up to 2 CAN modules – Harvard bus architecture – One Inter-Integrated-Circuit (I2C) bus – Atomic operations • 12-bit ADC, 16 channels – Fast interrupt response and processing – 2 × 8 channel input multiplexer – Unified memory programming model – Two sample-and-hold – Code-efficient (in C/C++ and Assembly) – Single/simultaneous conversions • On-chip memory – Fast conversion rate: – F2809: 128K × 16 flash, 18K × 16 SARAM 80 ns - 12.5 MSPS (F2809 only) F2808: 64K × 16
    [Show full text]
  • Phase Alignment of Asynchronous External
    PHASEALIGNMENTOFASYNCHRONOUSEXTERNALCLOCK CONTROLLABLEDEVICESTOPERIODICMASTERCONTROLSIGNALUSING THEPERIODICEVENTSYNCHRONIZATIONUNIT by CharlesNicholasOstrander Athesissubmittedinpartialfulfillment oftherequirementsforthedegree of MasterofScience in ElectricalEngineering MONTANASTATEUNIVERSITY Bozeman,Montana May2009 ©COPYRIGHT by CharlesNicholasOstrander 2009 AllRightsReserved ii APPROVAL ofathesissubmittedby CharlesNicholasOstrander Thisthesishasbeenreadbyeachmemberofthethesiscommitteeandhasbeen foundtobesatisfactoryregardingcontent,Englishusage,format,citation,bibliographic style,andconsistency,andisreadyforsubmissiontotheDivisionofGraduateEducation. Dr.BrockJ.LaMeres ApprovedfortheDepartmentElectricalEngineering Dr.RobertC.Maher ApprovedfortheDivisionofGraduateEducation Dr.CarlA.Fox iii STATEMENTOFPERMISSIONTOUSE Inpresentingthisthesisinpartialfulfillmentoftherequirementsfora master’sdegreeatMontanaStateUniversity,IagreethattheLibraryshallmakeit availabletoborrowersunderrulesoftheLibrary. IfIhaveindicatedmyintentiontocopyrightthisthesisbyincludinga copyrightnoticepage,copyingisallowableonlyforscholarlypurposes,consistentwith “fairuse”asprescribedintheU.S.CopyrightLaw.Requestsforpermissionforextended quotationfromorreproductionofthisthesisinwholeorinpartsmaybegranted onlybythecopyrightholder. CharlesNicholasOstrander May2009 iv TABLEOFCONTENTS 1.INTRODUCTION .......................................................................................................... 1
    [Show full text]
  • 7. Latches and Flip-Flops
    Chapter 7 – Latches and Flip-Flops Page 1 of 18 7. Latches and Flip-Flops Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can store one bit of information. The main difference between latches and flip-flops is that for latches, their outputs are constantly affected by their inputs as long as the enable signal is asserted. In other words, when they are enabled, their content changes immediately when their inputs change. Flip-flops, on the other hand, have their content change only either at the rising or falling edge of the enable signal. This enable signal is usually the controlling clock signal. After the rising or falling edge of the clock, the flip-flop content remains constant even if the input changes. There are basically four main types of latches and flip-flops: SR, D, JK, and T. The major differences in these flip-flop types are the number of inputs they have and how they change state. For each type, there are also different variations that enhance their operations. In this chapter, we will look at the operations of the various latches and flip- flops. 7.1 Bistable Element The simplest sequential circuit or storage element is a bistable element, which is constructed with two inverters connected sequentially in a loop as shown in Figure 1. It has no inputs and two outputs labeled Q and Q’. Since the circuit has no inputs, we cannot change the values of Q and Q’. However, Q will take on whatever value it happens to be when the circuit is first powered up.
    [Show full text]
  • Signal Shorts
    Signal Shorts Bill Fawcett Director of Engineering The Problem WMRA has published a coverage map which shows where we expect our signal to reach, based on formulas devised by the FCC. Yet even within our established coverage area, there are locales in which the signal sounds "fuzzy". In most cases, the topography of the area is causing "multi-path" interference, that is, reflections of the signal off of nearby mountains adds to the direct signal, but delayed somewhat in time, and scrambles the received signal. This is the same phenomenon that causes "ghosts" on your TV (shadow- images on your screen, not the "X-Files"). Multipath is a significant problem along the I-81 corridor North of Harrisonburg to Strasburg. Also at Penn Laird along Route 33. Multipath problems are so site-specific that moving a radio a few feet may make a difference. The next time you get a fuzzy signal at a traffic light you may note that it clears up by advancing a few feet (watch out for the car in front of you, or you may have other, more serious, problems). Switching to mono, if possible, will also help. Other areas suffer from terrain obstructions. This may be noted at Massanutten Resort, and in the UVA area of Charlottesville. For those outside of the predicted coverage area, signal strength (the lack of) may be a problem, as may interference. North of Charlottesville this is a big problem, with interference from a high-power station in Washington D.C. causing problems. Lastly, the downtown Charlottesville area suffers from interference from WCYK's 105.1 translator.
    [Show full text]
  • Introduction (Pdf)
    chapter1.fm Page 1 Thursday, August 17, 2000 4:43 PM CHAPTER 1 INTRODUCTION The evolution of digital circuit design n Compelling issues in digital circuit design n How to measure the quality of digital design n Valuable references 1.1 A Historical Perspective 1.2 Issues in Digital Integrated Circuit Design 1.3 Quality Metrics of A Digital Design 1.4 Summary 1.5 To Probe Further 1 chapter1.fm Page 2 Thursday, August 17, 2000 4:43 PM 2 INTRODUCTION Chapter 1 1.1A Historical Perspective The concept of digital data manipulation has made a dramatic impact on our society. One has long grown accustomed to the idea of digital computers. Evolving steadily from main- frame and minicomputers, personal and laptop computers have proliferated into daily life. More significant, however, is a continuous trend towards digital solutions in all other areas of electronics. Instrumentation was one of the first noncomputing domains where the potential benefits of digital data manipulation over analog processing were recognized. Other areas such as control were soon to follow. Only recently have we witnessed the con- version of telecommunications and consumer electronics towards the digital format. Increasingly, telephone data is transmitted and processed digitally over both wired and wireless networks. The compact disk has revolutionized the audio world, and digital video is following in its footsteps. The idea of implementing computational engines using an encoded data format is by no means an idea of our times. In the early nineteenth century, Babbage envisioned large- scale mechanical computing devices, called Difference Engines [Swade93]. Although these engines use the decimal number system rather than the binary representation now common in modern electronics, the underlying concepts are very similar.
    [Show full text]