EUROPEAN ORGANIZATION FOR NUCLEAR RESEARCH CERN − SL DIVISION CERN-SL-2002-047 (HRF) Digital Signal Processing Applications and Implementation for Accelerators Digital Notch Filter with Programmable Delay and Betatron Phase Adjustment for the PS, SPS & LHC Transverse Dampers V. Rossi Abstract In the framework of the LHC project and the modifications of the SPS as its injector, I present the concept of global digital signal processing applied to a particle accelerator, using Field Programmable Gate Array (FPGA) technology. The approach of global digital synthesis implements in numerical form the architecture of a system, from the start up of a project and the very beginning of the signal flow. It takes into account both the known parameters and the future evolution, whenever possible. Due to the increased performance requirements of today's projects, the CAE design methodology becomes more and more necessary to handle successfully the added complexity and speed of modern electronic circuits. Simulation is performed both for behavioural analysis, to ensure conformity to functional requirements, and for time signal analysis (speed requirements). The digital notch filter with programmable delay for the SPS Transverse Damper is now fully operational with fixed target and LHC- type beams circulating in the SPS and is a successful implementation of this concept. The transfer function is programmable and therefore the same equipment can be reprogrammed for use in future projects. General concept and digital notch filter with programmable delay presented at Workshop on DSP Applications in the SL Division. CERN-SL, 5th November 2001 Geneva, Switzerland July 2002 2 Abstract 1. INTRODUCTION 2. FROM REQUIREMENTS TO DESIGN 2.1 Required bandwidth 2.2 Number of bits 3. DATA CONVERSION 3.1 ADC module 3.2 DAC module 3.3 Test set-up 4. TRANSVERSE FEEDBACK SYSTEM 5. DIGITAL NOTCH FILTER AND ONE TURN DELAY 5.1 Digital Notch Filter with programmable delay for the SPS 5.2 Gating 5.3 Modes of operation 6. METHOD FOR IMPLEMENTATION OF THE DIGITAL SIGNAL PROCESSING 7. TRANSFER FUNCTION IMPLEMENTATION 7.1 Synchronous design 7.2 Delay function 7.3 Arithmetic Logic Unit 7.4 User Module Interface and Look-up table 7.5 I2C Controller & Reset 8. FINE DELAY 8.1 I2C interface 8.2 Conversion algorithm 8.3 Interlock 9. DESIGN ENTRY 10. SCHEMATIC DIAGRAM 11. SIGNAL INTEGRITY 12. BOARD MANUFACTURING 13. LABORATORY TEST 14. RESULTS WITH BEAM 3 15. BETATRON PHASE ADJUSTMENT 15.1 Hilbert filter 15.2 Realisation 15.3 MD results 16. CONCLUSIONS 17. FUTURE DEVELOPMENTS References Acknowledgements 4 Digital Signal Processing Applications and Implementation for Accelerators Digital Notch Filter with Programmable Delay and Betatron Phase Adjustment for the PS, SPS & LHC Transverse Dampers Vittorio Rossi, CERN, SL-HRF Abstract In the framework of the LHC project and the modifications of the SPS as its injector, I present the concept of global digital signal processing applied to a particle accelerator, using Field Programmable Gate Array (FPGA) technology. The approach of global digital synthesis implements in numerical form the architecture of a system, from the start up of a project and the very beginning of the signal flow. It takes into account both the known parameters and the future evolution, whenever possible. Due to the increased performance requirements of today's projects, the CAE design methodology becomes more and more necessary to handle successfully the added complexity and speed of modern electronic circuits. Simulation is performed both for behavioural analysis, to ensure conformity to functional requirements, and for time signal analysis (speed requirements). The digital notch filter with programmable delay for the SPS Transverse Damper is now fully operational with fixed target and LHC-type beams circulating in the SPS and is a successful implementation of this concept. The transfer function is programmable and therefore the same equipment can be reprogrammed for use in future projects. 1. INTRODUCTION As a general rule, signals, derived from the beam or from equipment through transducers, are processed either for observation or they are injected into feedback loops, figure 1. Fig. 1 – Block diagram of closed loop response for a feedback system. The response of the system is: R(s) G(s) W (s) = = (1) P(s) 1− H 1(s)⋅ H 2(s)⋅G(s) Where: W (s) system response R(s) resulting beam position P(s) perturbation G(s) beam response H 1(s) low level response H 2(s) power amplifier response The system is stable if the real part of H 1(s)⋅ H 2(s)⋅G(s) is less than +1. 5 Treating the low level signals in the digital domain allows flexibility for the subsequent treatment. Fig. 2 presents the overall concept layout: a single Digital Signal Processing Unit (DSPU) performs all the numerical treatment necessary to implement the H 1(s) transfer function. The DSPU is preceded by an Analog to Digital Converter and followed by a Digital to Analog Converter. To achieve behaviour independent from the sampling rate, the clock is fed to the ADC and routed, together with the data, to the following DSPU and DAC, with identical delay. The ADC-DSPU-DAC combination possesses a unity gain; its intrinsic bandwidth is from DC up to the Nyquist limit. Following the requirements of the project, amplification and filtering can be added before and/or after the data conversion or implemented in the DSPU. Clock Analog DSPU Analog input ADC Data Data DAC output Clock Clock Fig. 2 – Digital Signal Processing Unit associated to data conversion. In view of the LHC requirements and to minimise the noise injected to the stored beams, decreasing its lifetime, the quantisation error introduced by the data conversion should be reduced to a minimum. This requirement defines the minimum number of bits in the conversion and in the processing. Fast applications involving beam control on a bunch-by-bunch basis suggest the choice of a hardware-based digital signal processing solution compared to a software-program approach. Fast processing speed motivates the implementation in a Field Programmable Gate Array rather than in a floating point Digital Signal Processor. Transfer functions can thus be designed and synthesised in VHDL and implemented in programmable devices. Simulation of the FPGA is performed both for behavioural analysis (conformity to project requirements) and time analysis (speed requirements). Implementation in digital form in modern electronic circuits is realised through routing tools preserving the signal integrity (delay, crosstalk etc.). A different transfer function can be calculated for a different application and loaded in the programmable device. Within the limits of the maximum system gates and the data conversion range, the same equipment can be employed for several applications. An example of such a procedure is presented in the following sections 2 and 3 using LHC requirements and parameters to provide concrete numbers. The detailed design of a system for the SPS transverse damper for multi-cycling applications is presented in section 4-15. 2. FROM REQUIREMENTS TO DESIGN 2.1 Required bandwidth The system under consideration is a bunch-by-bunch feedback with bunch spacing Tb and bandwidth W =1 2Tb . For LHC, where Tb is 25 ns, the required bandwidth is 20 MHz for the whole system. The low-level part is over designed, with sampling rate up to 120 MSPS, a three times over sampling at the 40 MHz LHC bunch frequency that allows a Nyquist bandwidth up to 60 MHz. To minimize the emittance blow-up at injection, the damping time has to be shorter than the beam decoherence time and the system should be able to damp the coherent motion of each individual batch. In this case the required bandwidth is less and it is determined by the batch spacing (not the bunch spacing). 6 2.2 Number of bits When sampling is considered, an infinite number of bits are theoretically required to represent each value. Physical limitations preclude sampling with infinite precision and a system with a finite number b of bits is assumed. With digital signal processing of the signal, the main source of noise is assumed to be the quantisation noise. For the LHC stored beams, it is proposed to reduce the quantisation error below the minimum acceptable value, to reduce the injected noise and increase the beam lifetime. From [1], the transverse emittance growth rate for a beam of transverse rms size ±σ, depends on tune spread and quantisation error, as follows: 1 4 = f ⋅α 2 ⋅δQ 2 (2) τ 0 x 2 3 1 −()− where defines the transverse emittance blow-up rate, f the revolution frequency, α = 2 b 1 the τ 0 x 2 quantisation width and δQ the tune spread. = δ ≈ −2 Taking the example for the LHC: f0 11 kHz , Q 10 and an 11 bit effective, 12 bit ADC with −()b−1 1 α = 2 = , one obtains a transverse emittance growth time τ 2 = 200 hours, which is satisfactory. 1024 x Sampling rate up to 120 MSPS and a resolution of 12 bit are the features chosen to design the DSPU, complying with the LHC-type beam requirements. 3. DATA CONVERSION The data conversion is fundamental for the precision of the complete system. The purpose of the development is the realisation of data conversion building blocks with high precision in the analog section and high resolution and speed in the digital section. State of the art devices have been targeted, 12 bit, (with further evolution in mind, 14-bit) and sampling rate up to 120 MSPS. In this way future evolution and reuse in other projects is possible. 3.1 ADC module Analog to digital conversion can be performed up to 120 MHz. The heart of the circuit is the AD9432, from Analog Devices, a monolithic 12 bit ADC with integral track and hold circuit and an integral non-linearity of ± 0.5 LSB (data sheet: see http://www.analog.com ).