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DOT/FAA/AR-95/31 Design, Test, and Certification Office of Aviation Research Issues for Complex Integrated Washington, D.C. 20591 Circuits August 1996 Final Report This document is available to the U.S. public through the National Technical Information Service, Springfield, Virginia 22161. U.S. Department of Transportation Federal Aviation Administration Technical Report Documentation Page 1. Report No. 2. Government Accession No. 3. Recipient's Catalog No. DOT/FAA/AR-95/31 5. Report Date 4. Title and Subtitle August 1996 DESIGN, TEST, AND CERTIFICATION ISSUES FOR COMPLEX INTEGRATED CIRCUITS 6. Performing Organization Code 7. Author(s) 8. Performing Organization Report No. L. Harrison and B. Landell 9. Performing Organization Name and Address 10. Work Unit No. (TRAIS) Galaxy Scientific Corporation 2500 English Creek Avenue Building 11 11. Contract or Grant No. Egg Harbor Township, NJ 08234-5562 DTFA03-89-C-00043 12. Sponsoring Agency Name and Address 13. Type of Report and Period Covered U.S. Department of Transportation Final Report Office of Aviation Research Washington, D.C. 20591 14. Sponsoring Agency Code AAR-421 15. Supplementary Notes Peter J. Saraceni. William J. Hughes Technical Center Program Manager, (609) 485-5577, Fax x 4005, [email protected] 16 Abstract This report provides an overview of complex integrated circuit technology, focusing particularly upon application specific integrated circuits. This report is intended to assist FAA certification engineers in making safety assessments of new technologies. It examines complex integrated circuit technology, focusing on three fields: design, test, and certification.. It provides the reader with the background and a basic understanding of the fundamentals of these fields. Also included is material on the development environment, including languages and tools Application specific integrated circuits are widely used in Boeing 777 fly-by-wire aircraft. Safety issues abound for these integrated circuits when they are used in safety-critical applications. Since control laws are now executed in silicon and transmitted from one integrated circuit to another. reliability issues for these integrated circuits take on a new importance. This report identifies certification risks relating to the use of complex integrated circuits in fly-by-wire applications. 17. Key Words 18. Distribution Statement Application specific integrated circuit. Avionics. Certification, This document is available to the U.S. Design for test. Field programmable gate array, Fly-by-wire, public through the National Hardware description language, Reliability. Simulation, Software, Technical Information Service, State machine, Submicron design. Synthesis. Validation, Springfield, Virginia 22161. Verification. 19. Security Classif. (of this report) 20 Security Classif. (of this page) 21. No. of Pages 22. Price Unclassified Unclassified 191 Form DOT F1700.7 (8-72) Reproduction of completed page authorized TABLE OF CONTENTS Page EXECUTIVE SUMMARY xiii 1. INTRODUCTION 1 1.1 New Threats from an Old Technology 1 1.2 Report Overview 4 2. USER-PROGRAMMABLE INTEGRATED CIRCUITS 5 2.1 Programmable Logic Devices 5 2.2 Application Specific Integrated Circuit 16 3. DESIGN ISSUES FOR APPLICATION SPECIFIC INTEGRATED CIRCUITS 23 3.1 Design Philosophy 23 3.2 Logic Design Pitfalls 25 3.3 Design Logic Examples 29 3.4 Metastability 33 3.5 Issues in Submicron Technology 35 3.6 Noise and Ground Bounce 42 3.7 Latch-Up 47 3.8 Single Event Upset of Digital Logic 49 3.9 Considerations for Printed Circuit Boards 50 3.10 Performance Measurement 50 4. TOOLS AND TECHNIQUES FOR HARDWARE INTEGRATED CIRCUIT DESIGN 50 4.1 Early Design Tools 50 4.2 Application Specific Integrated Circuit Tools 51 4.3 Describing the Design 52 4.4 Synthesis of Digital Logic 62 4.5 Electronic Design Automation Tool Standards 85 4.6 Future Design Trends for Hardware 86 5. FABRICATION AND RELIABLITY ISSUES FOR THE PHYSICAL HARDWARE 88 5.1 Application Specific Integrated Circuit Fabrication Issues 88 5.2 Issues in Application Specific Integrated Circuit Reliability 89 iii 6. APPLICATION SPECIFIC INTEGRATED CIRCUIT TEST CONSIDERATIONS 94 6.1 Understanding Test 94 6.2 Test Methodologies 111 7. APPLICATION SPECIFIC INTEGRATED CIRCUIT VERIFICATION AND VALIDATION 139 7.1 The Need for Verification and Validation 139 7.2 Simulation 141 7.3 Additional Considerations for Simulation 144 7.4 Application Specific Integrated Circuit Prototyping and Validation 146 7.5 Formal Methods for Hardware Design 147 7.6 Software Reuse 147 7.7 Regulations and Guidelines 148 7.8 RTCA Special Committee 180 149 8. CONCLUSION 150 8.1 A New Look at an Old Technology 150 8.2 Certification 151 8.3 Design 152 8.4 Testing and Verification 152 8.5 Complexity Issues 154 9. BIBLIOGRAPHY 155 10. GLOSSARY 171 INDEX 177 APPENDIX A -- RTCA SPECIAL COMMITTEE 180 TERMS OF REFERENCES iv LIST OF FIGURES Figure Page 1 Basic Combinatorial Logic Elements 8 2 Section of Programmable Array Logic 9 3 Complex Programmable Logic Device Block Diagram 11 4 Basic Logic Block Elements 12 5 EPLD Block Diagram 13 6 Basic Macrocell Construction 15 7 Gate Array Block Diagram 17 8 Standard Cell Block Diagram 18 9 Gate Array Logic Block 21 10 Field Programmable Gate Array Design Cycle 22 11 Clock Skew Example 26 12 Acceptable Clock Distribution Technique 27 13 A Three-State State Machine Example 28 14 Delay-Dependent Logic 29 15 Clock-Based Independent Delay Logic 30 16 Hold-Time Violation 31 17 Synchronous Design with no Hold-Time Violation 31 18 Glitches Caused by Asynchronous Design 32 19 Bus Contention Due to Faulty Control Design 33 20 Avoiding Bus Contention by Design 33 21 Setup-Time Illustration for Positive Edge Clocked Flip-Flop 34 v 22 Synchronization of Asynchronous Signal 34 23 Layout Iterations Versus Delay Discrepancies 36 24 Interconnect and Gate Delays Versus Device Size 37 25 Interconnect Estimation for Deep Submicron Designs 38 26 Parasitic Silicon Controlled Rectifier Structure 47 27 Moore State Machine 54 28 Mealy State Machine 54 29 Implementing a 4-to- 16 Active-Low Decoder 55 30 Next-State Determination Code 59 31 Verilog Hardware Description Language Coding Example 61 32 Logic Synthesis Process 64 33a Hierarchical Flattening 65 33b Boolean Flattening 65 34 High-Level Synthesis Tool Functionality 67 35 Data Flow Graph 68 36 Control-Data Flow Graph 69 37 A Three-Bus Design Implementation 71 38 A Two-Bus Design Implementation Using Pipelining 72 39 Scheduler Example 75 40a Graph of Nodes and Neighbors 77 40b Possible Cliques Based on 40a 77 41 Adder Carry Implementations 80 vi 42 Grouping Effects on Implementations 80 43 Adder Resource Sharing 81 44 Reliability Life Curve 91 45 Percent of Undetectable Defective Devices 99 46 Economic Trade-Off for Testable Designs - 106 47 Test Pattern Generation Time 107 48 Complexity Versus Cost 108 49 Test Development Time Versus Fault Coverage 109 50 Revenue Versus Time to Market 110 51 Scabbiest Block Diagram 113 52 MUX-Scan Circuit Configuration 116 53 Level Sensitive Scan Design Scan Register Configuration 117 54 Level Sensitive Scan Design Scan Register Timing Diagram 118 55 Scan Chain Configuration 119 56 Scan Control Configuration 120 57 Boundary Scan Configuration 124 58 Boundary Scan Test Input Cell Configuration 125 59 Boundary Scan Test Output Cell Configuration 126 60 CrossCheck™ Configuration 128 61 IDDQ Signature Patterns 133 62 Bridging Fault 134 63 Missing Contact Fault 137 vii 64 Resistive Via Fault 138 65 Gate to Drain Short 138 66 Coupling Between Circuits 139 LIST OF TABLES Table Page 1 Combinatorial Logic Functions 9 2 Gate Array and Standard Cell Comparison 7 3 Currently Available Application Specific Integrated Circuits 5 4 Power Dissipation Examples 41 5 Very High Speed Integrated Circuit Hardware Description Language Construct Examples 56 6 Component Values from Register Transfer Level Library 73 7 Possible Constructions for Speed and Size Trade-Offs 74 8 Active Variables from Figure 39 76 9 Possible Solution Sets for Variables 78 10 Typical Failure Mechanisms for Complementary Metal Oxide Semiconductor Devices 92 11 Percent of Undetectable Defective Devices 99 viii LIST OF ACRONYMS AND ABBREVIATIONS θCA Case-to-Ambient Thermal Resistance θJC Junction-to-Case Thermal Resistance ac Alternating Current AC Advisory Circular ACO Aircraft Certification Office AHDL Analog Hardware Description Language ALU Arithmetic Logic Unit ARINC Aeronautical Radio, Inc. ASIC Application Specific Integrated Circuit ASM Algorithmic State Machine ATE Automatic Test Equipment ATPG Automatic Test Pattern Generation BIST Built In Self-Test BSDL Boundary Scan Description Language BSR Boundary Scan Register BST Boundary Scan Test CAD Computer Aided Design CANCER Computer Analysis of Nonlinear Circuits, Excluding Radiation CDFG Control-Data flow Graph CE Certification Engineer CFI CAD Framework Initiative CMOS Complimentary Metal-Oxide Semiconductor CPLD Complex Programmable Logic Device CPU Central Processing Unit CUT Circuit Under Test dc Direct Current DFG Data Flow Graph DFT Design For Testability DIP Dual In-line Package DMA Direct Memory Access DUT Device Under Test ECL Emitter-Coupled Logic EDA Electronic Design Automation EDAC Error Detection and Correction EDIF Electronic Design Interchange Format EIA Electronic Industries Association EPLD Erasable Programmable Logic Device EPROM Erasable Programmable Read Only Memory ESD Electrostatic Discharge ESDA Electronic System Design Automation ESTA Electronic System Test Automation FAA Federal Aviation Administration
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