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Efficient Processing of Deep Neural Networks Efficient Processing of Deep Neural Networks Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, Joel Emer Massachusetts Institute of Technology Reference: V. Sze, Y.-H.Chen, T.-J. Yang, J. S. Emer, ”Efficient Processing of Deep Neural Networks,” Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2020 For book updates, sign up for mailing list at http://mailman.mit.edu/mailman/listinfo/eems-news June 15, 2020 Abstract This book provides a structured treatment of the key principles and techniques for enabling efficient process- ing of deep neural networks (DNNs). DNNs are currently widely used for many artificial intelligence (AI) applications, including computer vision, speech recognition, and robotics. While DNNs deliver state-of-the- art accuracy on many AI tasks, it comes at the cost of high computational complexity. Therefore, techniques that enable efficient processing of deep neural networks to improve key metrics—such as energy-efficiency, throughput, and latency—without sacrificing accuracy or increasing hardware costs are critical to enabling the wide deployment of DNNs in AI systems. The book includes background on DNN processing; a description and taxonomy of hardware architectural approaches for designing DNN accelerators; key metrics for evaluating and comparing different designs; features of DNN processing that are amenable to hardware/algorithm co-design to improve energy efficiency and throughput; and opportunities for applying new technologies. Readers will find a structured introduction to the field as well as formalization and organization of key concepts from contemporary work that provide insights that may spark new ideas. 1 Contents Preface 9 I Understanding Deep Neural Networks 13 1 Introduction 14 1.1 Background on Deep Neural Networks . 14 1.1.1 Artificial Intelligence and Deep Neural Networks . 14 1.1.2 Neural Networks and Deep Neural Networks . 16 1.2 Training versus Inference . 18 1.3 Development History . 21 1.4 Applications of DNNs . 23 1.5 Embedded versus Cloud . 24 2 Overview of Deep Neural Networks 26 2.1 Attributes of Connections Within a Layer . 26 2.2 Attributes of Connections Between Layers . 27 2.3 Popular Types of Layers in DNNs . 28 2.3.1 CONV Layer (Convolutional) . 28 2.3.2 FC Layer (Fully Connected) . 31 2.3.3 Nonlinearity . 32 2 CONTENTS Sze, Chen, Yang, Emer 2.3.4 Pooling and Unpooling . 33 2.3.5 Normalization . 34 2.3.6 Compound Layers . 35 2.4 Convolutional Neural Networks (CNNs) . 35 2.4.1 Popular CNN Models . 36 2.5 Other DNNs . 44 2.6 DNN Development Resources . 45 2.6.1 Frameworks . 45 2.6.2 Models . 46 2.6.3 Popular Datasets for Classification . 46 2.6.4 Datasets for Other Tasks . 48 2.6.5 Summary . 48 II Design of Hardware for Processing DNNs 49 3 Key Metrics and Design Objectives 50 3.1 Accuracy . 50 3.2 Throughput and Latency . 51 3.3 Energy Efficiency and Power Consumption . 57 3.4 Hardware Cost . 60 3.5 Flexibility . 61 3.6 Scalability . 62 3.7 Interplay Between Different Metrics . 63 4 Kernel Computation 64 4.1 Matrix Multiplication with Toeplitz . 65 4.2 Tiling for Optimizing Performance . 66 3 CONTENTS Sze, Chen, Yang, Emer 4.3 Computation Transform Optimizations . 71 4.3.1 Gauss’ Complex Multiplication Transform . 71 4.3.2 Strassen’s Matrix Multiplication Transform . 72 4.3.3 Winograd Transform . 73 4.3.4 Fast Fourier Transform . 74 4.3.5 Selecting a Transform . 75 4.4 Summary . 75 5 Designing DNN Accelerators 77 5.1 Evaluation Metrics and Design Objectives . 78 5.2 Key Properties of DNN to Leverage . 79 5.3 DNN Hardware Design Considerations . 81 5.4 Architectural Techniques for Exploiting Data Reuse . 82 5.4.1 Temporal Reuse . 82 5.4.2 Spatial Reuse . 83 5.5 Techniques to Reduce Reuse Distance . 85 5.6 Dataflows and Loop Nests . 89 5.7 Dataflow Taxonomy . 95 5.7.1 Weight Stationary (WS) . 97 5.7.2 Output Stationary (OS) . 99 5.7.3 Input Stationary (IS) . 101 5.7.4 Row Stationary (RS) . 101 5.7.5 Other Dataflows . 107 5.7.6 Dataflows for Cross-Layer Processing . 108 5.8 DNN Accelerator Buffer Management Strategies . 109 5.8.1 Implicit versus Explicit Orchestration . 109 4 CONTENTS Sze, Chen, Yang, Emer 5.8.2 Coupled versus Decoupled Orchestration . 110 5.8.3 Explicit Decoupled Data Orchestration (EDDO) . 111 5.9 Flexible NoC Design for DNN Accelerators . 113 5.9.1 Flexible Hierarchical Mesh Network . 115 5.10 Summary . 119 6 Operation Mapping on Specialized Hardware 120 6.1 Mapping and Loop Nests . 121 6.2 Mappers and Compilers . 124 6.3 Mapper Organization . 126 6.3.1 Map Spaces and Iteration Spaces . 126 6.3.2 Mapper Search . 131 6.3.3 Mapper Models and Configuration Generation . 132 6.4 Analysis Framework for Energy Efficiency . 132 6.4.1 Input Data Access Energy Cost . 133 6.4.2 Partial Sum Accumulation Energy Cost . 134 6.4.3 Obtaining the Reuse Parameters . 135 6.5 Eyexam: Framework for Evaluating Performance . 137 6.5.1 Simple 1-D Convolution Example . 137 6.5.2 Apply Performance Analysis Framework to 1-D Example . 138 6.6 Tools for Map Space Exploration . 142 III Co-Design of DNN Hardware and Algorithms 145 7 Reducing Precision 146 7.1 Benefits of Reduce Precision . 146 7.2 Determining the Bit Width . 148 5 CONTENTS Sze, Chen, Yang, Emer 7.2.1 Quantization . 148 7.2.2 Standard Components of the Bit Width . 154 7.3 Mixed Precision: Different Precision for Different Data Types . 157 7.4 Varying Precision: Change Precision for Different Parts of the DNN . 158 7.5 Binary Nets . 161 7.6 Interplay Between Precision and Other Design Choices . 162 7.7 Summary of Design Considerations for Reducing Precision . 163 8 Exploiting Sparsity 164 8.1 Sources of Sparsity . 164 8.1.1 Activation Sparsity . 165 8.1.2 Weight Sparsity . ..
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