Technology for Wireless Communications: An Overview Babak Daneshrad Integrated Circuits and Systems Laboratory UCLA Electrical Engineering Dept. email: [email protected] http://www.ee.ucla.edu/~babak

Abstract: Figure 1 shows a block diagram of a typical wireless com- This paper provides a brief overview of present trends in the develop- munication system. Moreover it shows the partitioning of the ment of integrated circuit technology for applications in the wireless receiver into RF, IF, baseband analog and digital components. communications industry. Through advanced circuit, architectural and In this paper we will focus on two main classes of integrated processing technologies, ICs have helped bring about the wireless revo- circuit technologies. The first is ICs for analog and more lution by enabling highly sophisticated, low cost and portable end user importantly RF communications. In general the technologist as terminals. In this paper two broad categories of circuits are highlighted. The first is RF integrated circuits and the second is digital baseband well as the circuit designer’s challenge here is to first, make the processing circuits. In both areas, the paper presents the circuit design transistors operate at higher carrier frequencies, and second, to challenges and options presented to the designer. It also highlights the integrate as many of the components required in the receiver manner in which these technologies have helped advance wireless com- onto the IC. The second class of circuits that we will focus on munications. are digital baseband circuits. Where increased density and I. Introduction reduced power consumption are the key factors for optimiza- tion. The wireless industry has enjoyed rapid growth over the past Radio Intermediat Baseband Baseband decade and a half. Advances in integrated circuit technology Frequency (RF) Frequency (IF) Analog Digital coupled with novel system level solutions have combined to RSSI A/D give rise to small, low cost, low power and portable units for a A/D host of wireless communication systems. In fact, it is the mar- LNA VGA riage of advanced system design and IC technology that has 90° made anytime anywhere communication a reality. ASIC DSP or A/D Micro Controller LO The low cost paging receiver is a prime example of this mar- Baseband Processor riage. The RF and analog portions of these devices consume a VCO D/A mere 1.5 mW - 5 mW [1]. In the cellular arena, integrated cir- D/A cuits have helped reduce the form factor of the AMPS phones D/A form the bulky boxes introduced in the 80’s to the sleek pocket- sized phones that are becoming a staple in our society. The PA 90° LO move toward second generation digital cellular systems helped underscore the tremendous importance of high speed digital sig- D/A nal processing ICs to perform the operations for both the speech Figure 1. Block diagram of a generic wireless transceiver. coder/decoder, as well as the physical layer. In the case of GSM and IS-136/54, it was found that the general purpose DSP archi- II. CMOS Process Technology tecture coupled with dedicated datapaths for Viterbi decoding Complementary Metal Oxide Semiconductor (CMOS) can meet the processing requirements of these second genera- technology is by far one of the most important IC processing tion systems. However, in the case of IS-95, the tremendous technologies available. The suitability and cost effectiveness of amount of processing needed to implement the rake receivers CMOS technology for the design and development of digital has dictated a different hardware . In these systems circuits has helped accelerate the advancement and maturity of an application specific integrated circuit (ASIC) is used to per- this technology. With the exception of very high speed special- form the baseband signal processing at the chip rate. The role of ized digital circuits, CMOS is the technology of choice for all ASICs in the realization of cellular systems is expected to grow digital circuits. In fact, the rapid pace of development in this as we move towards third generation cellular systems which technology coupled with its cost-effectiveness arrived at partly require more sophisticated baseband processing. through the economies of scale has made CMOS the technol- Indoor wireless systems have also benefited from advance- ogy of choice for analog circuit design as well. ments in integrated circuit technology. The realization of high The tremendous advances in CMOS processing technology speed adaptive equalizer [2], beamforming [3] and FFT based have shown no sign of slowing down. The current commer- ASICs [4] for OFDM based systems are ideal for realizing the cially available minimum size channel length is 0.25 microns physical layer of most high speed wireless indoor links. At high (micro-meters), compared to the 2.0 micron state of the art rates even the MAC layer functionality is typically assigned to technology that was available in 1983 [5]. The stage is set for an ASIC. the predicted 0.1 micron channel lengths to be available around the turn of the century. The ever shrinking transistor sizes trans- clearer in the ensuing section, however, at this point it is worth late into different capabilities for RF and digital circuits. noting that in general GaAs is fast, provides high gain, high In the case of RF circuits, the smaller channel lengths trans- selectivity (high Qs), and has lower noise than silicon based late into higher operating frequencies for the transistors. This circuits, on the other hand Si based circuits are cheaper and can allows CMOS analog circuits to move up the transceiver chain be used in mixed-mode circuits where digital and analog func- towards the RF carrier frequency. Although CMOS process tionality is realized on the same substrate. technology provides low cost and speed, circuit level innova- tions are still needed to meet the desired gain, linearity and noise levels in CMOS RF-IC design. Digital circuits benefit from smaller dimensions, through increased density which implies increase functionality for the same amount of Silicon real-estate. The circuit designers actu- ally have a choice when it comes to taking advantage of the smaller dimension. They can harness the higher speeds provided by smaller transistors to clock the gates faster, or they can reduce the supply power and thus minimize power consumption while keeping the operating frequency the same. III. Technology Trends in RF ICs This section attempts to provide some insights into the cur- rent trends and research in the area of low cost RF front ends. Figure 2. . Block diagram of a recently reported GSM RFIC transceiver implementation in Si bipolar [6]. Note the external SAW Currently, a great amount of research is underway to improve bandpass filters, oscillator and PA, from. the power efficiency and lower the cost of the circuits used in the present generation of wireless products. The general In an attempt to eliminate the need for the GaAs compo- approach taken towards this goal is to move towards higher lev- nents and enjoy the cost savings associated with Silicon based els of integration in cheap silicon based technologies, such as circuits, researchers within industry and universities are look- BiCMOS (combination of bipolar and CMOS transistors on the ing for ways of realizing the same functionality now provided same substrate) and CMOS. There are several factors that con- by GaAs based circuits on a Silicon substrate, at the expense of tribute to the significantly lower cost of circuits manufactured some degradation in the overall performance of the block. This on Silicon substrates compared with other semi-conductor mate- was first initiated with Silicon bipolar circuits due to the tradi- rials, such as GaAs and SiGe. First, processes for CMOS and tionally higher bandwidths of these devices. However, in BiCMOS circuits provide higher yields (fewer defects per recent years advances in the development of CMOS processes wafer). Secondly, the high volume of orders enjoyed by CMOS and circuits have brought bandwidths, fT, of these transistors to fabrication facilities helps reduce the cost of such circuits levels comparable with Silicon bipolar transistors. Conse- through economies of scale. Finally, analog circuits imple- quently, researchers have also started to consider the use mented in CMOS can be easily integrated on the same substrate CMOS at RF. In addition to implementing RF sub-blocks of a with the digital baseband processing circuits for a truly optimal traditional super-heterodyne , researchers are also single chip implementation of the system. investigating a host of alternative transceiver architectures The traditional approach towards the design of wireless which will help eliminate the need for high-Q, lossy, off-chip transceivers has been to use GaAs based circuits for the realiza- filters [9] [10]. Overall, these activities will help take us one tion of the RF components such as power amplifiers, low noise step closer to the ultimate goal of a single chip radio which amplifiers, and switches. Silicon based analog circuits are then integrates, RF, IF, analog-baseband, D/A and all the required used for the IF to baseband sections and possibly the RF mixers. baseband signal processing on the same substrate. Over the In these approaches, band selection at RF and IF are typically past several years, a number of entities have successfully dem- performed using discrete off chip components. This eliminates onstrated CMOS building blocks such as mixers oscillators and the difficulties associated with the realization of high-Q filters amplifiers [11][12][13][14] for operation in the cellular and the on chip. Most conventional approaches also utilize external 900 MHz ISM bands. With the continuing trend towards the tuned LC resonators to provide the tuning element of the VCO. availability of smaller transistor dimensions, this trend is sure The high Qs realized by the external elements are critical in to move towards the PCS bands. ensuring good VCO phase-noise. III.1 Technology Options for RFIC The above mentioned trend is still evident in the latest series The technology choices in Silicon are: CMOS, BiCMOS, of “integrated” transceivers for wireless data applications and Bipolar, while the technologies available in GaAs are: [6][7][8], Figure 2. The reason for this partitioning will become MESFETS, HBT and PHEMT. What differentiates between circuit families on the same semiconductor is the masking steps, 6 the levels of doping used in the realization of the transistors and 5 the manner in which the transistors themselves are created and SiGe HBT used. For example the bipolar transistors available in a BiCMOS 4 process are inferior to those available in a dedicated silicon GaAs HBT bipolar process. 3 GaAs MESFET

The RF designer’s choice of a circuit family is driven by the 2 Si BJT desire to simultaneously meet objectives for low power dissipa- GaAs MESFET tion, speed, yield, component noise, linearity, gain, and effi- Gain/Pdc (dB/mW) 1 Si BJT Si CMOS, 900 MHz ciency. To date there is no single circuit family that will 0 simultaneously satisfy all of these requirements at RF, IF and 0 0.5 1 1.5 2 2.5 3 3.5 4 baseband. Baseband analog circuits that implement filters, Noise Figure (dB) amplifiers, and A/D and D/A’s are dominated by CMOS. IF cir- Figure 3. . Gain to DC power ratio plotted versus Noise Figure for state-of-the-art 2 GHz LNAs [15]. cuits such as mixers and amplifiers, and some filtering opera- tions are realized in a mix of CMOS, BiCMOS and Bipolar better power added efficiencies at the high output power levels technologies. Finally, the power amplifier and the LNA func- typically demanded of such amplifiers. Figure 4. provides a tions are generally realized in GaAs. summary and side-by-side comparison of some recently Traditionally, GaAs has been used for high frequency (RF) reported GaAs based power amplifiers. circuits due to the higher transistor cut-off frequencies (fre- quency at which the transistor gain equals 1). However, in 55 recent years, Silicon based circuits, first bipolar and then MOS GaAs PHEMT have attained similar fT’s which makes them suitable for opera- 50 tion in the frequency range from 1 to 10 GHz [15][16]. It should be noted that the high frequency performance of the silicon 45 devices is generally achieved at higher power dissipation levels GaAs MESFET-5 and lower gains than GaAs devices. In what follows we will GaAs MESFET-2 GaAs MESFET-4 40 look at components of a transceiver and evaluate the relative GaAs MESFET-1 GaAs MESFET-3 merits of the different IC technologies for each application. GaAs HBT-1 35 Low Noise Amplifiers 20 21 22 23 24 25 26 27 28 Power Added Efficiency (%) Efficiency Added Power Apart from the obvious requirement for low noise, LNAs Output Power (dBm) must also be linear, high gain and dissipate little DC power. In Figure 4. . Power amplifier performance, from[15]. [15] a group of 6 LNAs recently reported in the literature are compared side-by-side,. The results are summarized in Figure 3. The push towards low cost solutions has lead designers to and show that noise figures on the order of 1.5-2 dB can be investigate Si-bipolar and CMOS technologies in the design of achieved with Si Bipolar, and GaAs technologies. However, for the power amplifier. A recently reported PA [17] circuit imple- the same amount of DC power dissipation, a GaAs MESFET mented in CMOS and targeted for constant envelope modula- circuit is shown to provide 1.5 dB more gain than that of a Si tion, delivers 1 W of power with a power added efficiency of bipolar circuit, while GaAs HBT technology can provide 5.5 dB 42% and operates within the 800-900 MHz range. A CMOS more gain. The figure also shows that for the same Gain/DC- power amplifier [12] targeted for use in the 900 MHz band only power (dB/mW) ratio as the Si bipolar LNA, a CMOS LNA will delivers 30 mW of output power at an efficiency of 30%. have a worse noise figure by approximately 0.8 dB. In addition to linearity, power consumption, and gain The information provided by the plot of Figure 3. can be requirements of the power amplifier, its integration onto the summarized into a single figure of merit: gain/(Pdc*NF) which same substrate with the rest of the transceiver elements, requires combines DC power dissipation, noise figure and gain of a techniques that protect the other circuits from the large pulls that given LNA. Utilizing this figure of merit, the CMOS and Si- the PA inflicts on the power and ground lines as it sources and bipolar LNA rate at approximately 0.4, while the best GaAs sinks current into and out of the load. In [16] this was accom- LNA achieves a figure of 3.0. plished via fully differential circuit design techniques. Power Amplifiers VCOs The power amplifier is probably one of the last elements to VCOs are perhaps one of the most critical building blocks of be integrated and implemented in a Si-CMOS process. Tradi- RF synthesizers. In [18] an equation for the relative phase noise tionally, the PA consists of discrete GaAs transistors assembled 1 ∆ w 2Pnoise on hybrid modules. Even the papers that report on an integrated of a VCO is given as: ------, where Q is the open 2w P RF transceiver IC [6][7][8] do not include the power amplifier 4Q o carrier ∆ on the Silicon substrate. In general GaAs provides significantly loop quality factor, w is the frequency offset, wo is the center frequency, and Pnoise is the spectral density of each noise source. This equation gives rise to three rules: (1) Use high-Q passive resonators; (2) minimize the number of active (and lossy X-Data Y-Data Program Memory Memory Memory passive) devices in the oscillation path; (3) maximize the oscil- X- Program-Bus lation swing (Pcarrier). Y-Bus A completely monolithic integrated VCO suffers from low- quality monolithic inductors (typical Q-factors are less than 20 17x17 MPY ALU [15] while values as low as 5 [18] are not at all uncommon), Adder RND, SAT Accumulator lossy varactor diodes that exhibit large series resistance, and an inability to trim the center frequency to accommodate its inevi- Barrel Shifter Auxiliary Reg. table drift due to process variations. Despite these drawbacks, substantial progress has recently been made in the development Figure 5. Architecture of a general purpose DSP. of completely monolithic silicon VCOs for wireless communi- cations. Most of the work to date has focused on improved tech- Today’s family of fixed-point DSPs deliver on the order of niques for realizing high-Q monolithic inductors which suffer 40-50 MIPs [22]. This amount of processing power is sufficient from high resistive metal lines as well as capacitive and mag- to realize almost all the needed processing for the physical layer nd netic coupling to the substrate. These efforts include the use of of narrowband 2 generation cellular systems (e.g. GSM and thick gold metallization to reduce the series resistance, bulk IS-136) as well as the speech coding and decoding functionality. micromachinining to etch away the resistive material under- It is interesting to note that the tremendous market potential for neath the inductor and eliminate capacitive coupling to the sub- wireless communication systems has forced manufacturers to strate and create a suspended inductor [20]. The realization of modify the traditional architectures for applications in wireless high-Q VCO circuits are also hampered by the difficulties asso- systems. An example is the TI TMS320C54 processor which ciated with the realization of low resistance, wide range varactor augments the architecture of the c50 processor by adding a dic- tuning capacitance using standard IC technology [19]. tated hardware unit to perform the add-compare-select opera- tions required by the Viterbi decoder operation [25]. In [22] the IV. IC Technologies Digital Baseband Processing MIPs requirements for various algorithms needed in the trans- The ever increasing sophistication of the algorithms realized mission and reception of an IS-136 signal are summarized. It is at the receiver of wireless communication systems is solely due shown that the entire physical layer as well as the speech cod- to recent advances in digital VLSI circuit design, not to mention ing/decoding operations require on the order of 38 MIPS, just fabrication technology. In general, the class of VLSI circuits can enough to fit into a state of the art DSP processor. be divided into three main categories. These are: (a) The attractiveness of DSP based solutions from a terminal programmable VLSI circuits such as DSP chips (i.e. TI vendor’s point of view is quite apparent. A software program- TMS320C54x family, Motorola AD56000 series, etc.) and mable engine can be easily modified and upgraded to target dif- micro-controllers; (b) hardware programmable circuits such as ferent market segments with the same basic hardware programmable logic devices (PLDs) and field programmable component. In fact, as the trend towards denser ICs continues, it gate arrays (FPGAs), and (c) application specific integrated cir- is expected that future DSPs will find applications in more cuits (ASICs) implemented using either Gate Array or standard- demanding systems, with the ultimate goal of replacing ASICs cell technology. The DSPs and the ASICs are by far the most all together. popular for use in wireless communications systems. However, With the move towards higher levels of integration, it is recent trends point to the integration of configurable logic cir- expected that the DSP processor’s architecture will also undergo cuits on the same substrate as DSPs or ASICs. It should be noted transformations. In fact, the TI TMS320C6x [25] processor that the realization of true system on chip for high speed appli- which was introduced in 1996 can deliver 1.6 billion instruc- cations will require coexistence of all three elements in the same tions per second (GIPS). This order of magnitude increase in the circuit. processing power of these chips will enable them to meet base IV.1 DSPs station processing requirements, tackle high bit-rate wireless DSPs are specialized software programmable VLSI circuits systems, find application in DSL services and image processing that are specifically designed to take on signal processing tasks among others. The C6x processor is a very large instruction that require significant amount of multiply-add operations. In word (VLIW) machine which houses multiple parallel process- many ways the DSP is a specialized micro-processor, with a ing units operating off of a 200 MHz clock. The parallel archi- smaller instruction set and a dedicated hardware unit capable of tecture allows it to execute multiple instructions per cycle. The performing multiply-adds in one instruction cycle. Most DSP equivalent operations per seconds specification for the C60 pro- architectures targeted for wireless applications use a Harvard cessor is 400 million operations per second (MOPS) [25], where architecture or a modified version thereof [22] [23]. The main an operation is typically refers to a multiply-add. The C60 pro- feature of this architecture is the separation of data and program cessor is the first of a new generation of high capacity DSP memory and buses which allows parallelism in the fetching and chips that are expected to hit the market in the near future. How- execution of instructions, Figure 5. ever, until the power consumption of these units can be con- tained, their use is in portable terminals will not be widespread. [7] S. Heinen, K. Hadjizada, U. Matter, et. al. “A 2.7V 2.5 GHz Bipo- lar Chipset for Digital Wireless Communication,” in IEEE ISSCC ‘97 IV.2 ASICs Digest, pp. 306-307. In high speed wireless data application such as high speed [8] R. G. Meyer, W. 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