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Prototyping Methodologies and Design of Communication-Centric Heterogeneous Many-Core Architectures

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Prototyping Methodologies and Design of Communication-Centric Heterogeneous Many-Core Architectures Prototyping Methodologies and Design of Communication-centric Heterogeneous Many-core Architectures Zur Erlangung des akademischen Grades eines DOKTOR-INGENIEURS (Dr.-Ing.) von der KIT-Fakultät für Elektrotechnik und Informationstechnik, des Karlsruher Instituts für Technologie (KIT) genehmigte DISSERTATION von Dipl.-Inform. Leonard Jannik Masing geb. in Heidelberg Tag der mündlichen Prüfung: 5.3.2020 Hauptreferent: Prof. Dr.-Ing. Dr. h. c. Jürgen Becker Korreferent: Prof. Dr. sc.techn. Andreas Herkersdorf Abstract The age of parallel processing and heterogeneous architectures is upon us. Fu- eled by the end of Dennard scaling, such architectures are the only way to keep the power wall in check until entirely new technologies such as quantum com- puting or new material breakthroughs might change the entire playing field. High performing heterogeneous many-cores interfaced by scalable networks- on-chips are one promising approach that has emerged in this context. However, these architectures come in many possible variations as the manifold applica- tion domains, from embedded and Internet of Things(IoT) to high performance computing, make customized computing architectures desirable. This in turn raises design efforts and complexity. At the same time, design size, complex interconnects and heterogeneous computing nodes are further straining existing techniques and methodologies for debugging, verification and validation. Inspired by these developments, this work presents novel approaches for de- sign and prototyping of heterogeneous many-core architectures. Three main aspects, not covered sufficiently by the existing state of the art are targeted. These aspects encompass early software development, hardware verification and design automation. A specific scenario that relates to a part in the many- core design process motivates each aspect. An emphasis is put on a novel networks-on-chip extension for low latency interconnects that highlights the major limitation of existing approaches: scalability for large architectures. As a central concept, virtual platforms on the electronic system level are uti- lized for early software development and verification tasks due to their binary compatibility with the target architecture. This allows for software, low-level function calls, drivers and operating system functionality to be developed in parallel to hardware design and verification tasks. A virtual platform envi- ronment is used to model a many-core architecture by extending it towards support for heterogeneous elements, an abstracted interconnect as well as cam- era and video I/O. Virtual platforms play another crucial role as part of the novel multi-level hybrid prototyping methodology that is introduced to provide i abstract a scalable answer for hardware verification tasks. In this approach, a prototype is built consisting of an FPGA part and a virtual part, interfaced by high speed PCIe. It reduces synthesis times and enables prototyping of large architectures that would otherwise not fit on available FPGA-board prototypes. Finally, the hardware/software codesign and design automation are also considered. Specifically, a framework that improves High-Level Synthesis (HLS) flows is introduced. It starts from OpenCL input and automatically generates a virtual platform representation as an intermediate step. This saves costly synthesis time and allows for optimizations on a human readable level in SystemC, as opposed to unintelligible RTL-Code generated by common HLS tools. The framework is enhanced further by providing an automated conversion among real number representations. This data representation forms a major trade-off in the design of customized accelerators, having significant impact on resource and power consumption. In summary, the presented contributions significantly speed up design processes and enable scalable prototyping of large heteroge- neous many-core architectures that was not possible before. ii Zusammenfassung Die Ära der Parallelverarbeitung und des heterogenen Rechnens ist ange- brochen. Bedingt durch das Ende des Dennard Scalings sind solche Architek- turen die einzige Möglichkeit um Leistungssteigerungen trotz der Limitierun- gen durch die Energiedichte zu erreichen, bis völlig neue Technologien wie das Quantenrechnen oder neue Materialien diese Hürde möglicherweise über- winden. Hochperformante, heterogene Vielkernarchitekturen die durch ein Netzwerk auf einem Chip verbunden sind, stellen einen vielversprechenden Ansatz in diesem Kontext dar. Diese Architekturen existieren jedoch in sehr unterschiedlichen Variationen, um den vielfältigen Anwendungsgebieten wie beispielsweise eingebettete Systeme, das Internet der Dinge sowie das Hoch- performanzrechnen gerecht zu werden. Dies wiederum erhöht die Komplexität im Entwurf und der Verifikation. Gleichzeitig überfordern die Designgröße, neuartige Verbindungsinfrastrukturen und die Integration heterogener Rech- enelemente zusätzlich die bestehenden Techniken und Methodiken für das Debugging, die Verifikation und die Validierung. Inspiriert durch diese Entwicklungen werden in der vorliegenden Arbeit neuar- tige Ansätze für das Design und das Prototyping von heterogenen Vielkernar- chitekturen vorgestellt. Der Fokus liegt hierbei auf drei Hauptaspekten, welche bisher im bestehenden Stand der Technik nicht ausreichend betrachtet worden sind. Diese Aspekte umfassen die frühzeitige Softwareentwicklung parallel zur Architekturentwicklung, die Hardwareverifikation und die Designautoma- tisierung. Jeder dieser Aspekte wird durch ein spezielles Szenario aus der Entwicklung einer Vielkernarchitektur motiviert. Insbesondere wird hier eine Erweiterung der Kommunikationsinfrastruktur hervorgehoben, welche eine Latenzreduzierung ermöglicht. Dieser neue Beitrag zur Leistungssteigerung von Vielkernarchitekturen zeigt ein deutliches Problem bestehender Entwurfs- und Verifikationstechniken: Die Skalierbarkeit für große Architekturen. Als zentrales Konzept werden in dieser Arbeit virtuelle Plattformen auf dem Elek- tronischen System Level (ESL) eingesetzt. Diese ermöglichen die frühzeitige iii Zusammenfassung Entwicklung und Verifikation von Software dank ihrer Binärkompatibilität mit der Zielarchitektur. Auf diese Weise kann selbst hardwarenahe Software, wie Treiber oder betriebssystemspezifische Funktionen, entwickelt werden während ein fertiges Hardwaredesign noch nicht existiert. In dieser Arbeit wird konkret eine Umgebung für virtuelle Plattformen speziell für die Modellierung von heterogenen Vielkernarchitekturen, eine abstrahierte Verbindungsstruktur sowie Kamera und Video Eingabe/Ausgabe erweitert. Virtuelle Plattformen spielen ebenso eine entscheidende Rolle als Teil der neuartigen hybriden Pro- totyping Methodik die eingeführt wird um eine skalierbare Lösung für die Hardwareverifikation zu liefern. Dieser Ansatz sieht vor, den Entwurfsprozess von einer virtuellen Plattform ausgehen zu lassen und Teile der Architektur auf einen FPGA zu verlagern. Die virtuelle Plattform wird über hochperfor- mantes PCIe angebunden um eine niedrige Latenz und hohen Durchsatz zu ermöglichen. Der hybride Ansatz reduziert die Synthesezeit und erlaubt die Erstellung von Prototypen für große Architekturen, welche ansonsten derzeit nicht auf reine FPGA-Lösungen passen würden. Als weiteres großes Thema in der vorliegenden Arbeit wird das Hardware/Software Codesign und die Designautomatisierung für heterogene Vielkernarchitekturen betrachtet. Ins- besondere wird ein Framework vorgestellt, welches den High-Level Synthese Entwurfsprozess verbessert. Dieser startet auf C Ebene mit OpenCL Quell- code und generiert automatisiert eine virtuelle Plattform als Zwischenschritt, im Gegensatz zur direkten Synthese auf Register Transfer (RT) Ebene bei bisherigen Ansätzen. Dies erspart kostbare Synthesezeit und ermöglicht es, Optimierungen in der gut verständlichen und übersichtlichen Zwischenebene vorzunehmen, anstatt des unleserlichen Codes der auf RT Ebene erzeugt wird. Das Framework wird zudem erweitert durch ein Feature zur automatisierten Konvertierung von reellen Zahlen. Dies ermöglicht die Evaluierung von Trade- offs für heterogene Beschleuniger im Sinne des approximativen Rechnens. Zusammengefasst beschleunigen die vorgestellten Beiträge den Designprozess signifikant und ermöglichen das skalierbare Prototyping von großen heteroge- nen Vielkernarchitekturen, was bisher nicht in dieser Form möglich war. iv Vorwort Die vorliegende Doktorarbeit ist in meiner Zeit am Institut für Technik der In- formationsverarbeitung (ITIV) des Karlsruher Instituts für Technologie (KIT) entstanden. An dieser Stelle möchte ich mich ganz herzlich bei all jenen bedanken, die mich in dieser Zeit auf meinem Weg begleitet und unterstützt haben. Mein ganz besonderer Dank gilt zunächst meinem Doktorvater Prof. Jürgen Becker für die Möglichkeit bei ihm am ITIV zu promovieren. Ich bin dankbar für die inhaltlichen Diskussionen, die Freiheit eigenen Ideen folgen zu können und alles was ich auf diesem Weg von ihm lernen durfte. Ebenfalls gilt mein besonderer Dank Prof. Andreas Herkersdorf für die Übernahme des Koreferats, den inhaltlichen Austausch und die gute Zusammenarbeit mit ihm und seinem Team über die Jahre. Nicht vergessen möchte ich auch meine Prüfungskommission, bestehend aus Prof. Ivan Peric, Prof. Laurent Schmalen und Prof. Ahmet Cagri Ulusoy, welchen ich für Ihre Zeit danken möchte. Mein weiterer Dank gilt insbesondere allen die mich auf meinem Weg be- gleitet haben. Dies sind zunächst einmal meine ehemaligen und aktuellen Kollegen vom
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