Identifying Performance Bottlenecks on Modern Microarchitectures Using an Adaptable Probe

Total Page:16

File Type:pdf, Size:1020Kb

Identifying Performance Bottlenecks on Modern Microarchitectures Using an Adaptable Probe Lawrence Berkeley National Laboratory Lawrence Berkeley National Laboratory Title Identifying performance bottlenecks on modern microarchitectures using an adaptable probe Permalink https://escholarship.org/uc/item/9203n4p5 Authors Griem, Gorden Oliker, Leonid Shalf, John et al. Publication Date 2004-01-20 eScholarship.org Powered by the California Digital Library University of California Identifying Performance Bottlenecks on Modern Microarchitectures using an Adaptable Probe Gorden Griem*, Leonid Oliker*, John Shalf*, and Katherine Yelick*+ *Lawrence Berkeley National Laboratory, 1 Cyclotron Road, Berkeley, CA, 94720 +Computer Science Division, University of California, 387 Soda Hall #1776, Berkeley, CA 94720 {ggriem, loliker, jshalf, kayelick}@lbl.gov Abstract Benchmarks, often present a narrow view of a broad, multi- The gap between peak and delivered performance for scien- dimensional parameter space of machine characteristics. We tific applications running on microprocessor-based systems therefore differentiate a “probe” from a “microbenchmark” or has grown considerably in recent years. The inability to synthetic benchmark on the basis that the latter typically offers achieve the desired performance even on a single processor is a single-valued result in order to rank processor performance often attributed to an inadequate memory system, but without consecutively – a few points of reference in a multidimen- identification or quantification of a specific bottleneck. In this sional space. A probe, by contrast, is used to explore a con- work, we use an adaptable synthetic benchmark to isolate ap- tinuous, multidimensional parameter space. The probe’s plication characteristics that cause a significant drop in per- parameterization helps the researcher uncover the peaks and formance, giving application programmers and architects valleys in a continuum of performance characteristics and ex- information about possible optimizations. Our adaptable plore the ambiguities of computer architectural comparisons probe, called sqmat, uses only four parameters to capture key that cannot be captured by a single-valued ranking. characteristics of scientific workloads: working-set size, com- In this paper, we introduce the sqmat probe [9], which at- putational intensity, indirection, and irregularity. This paper tempts to bridge the gap between these competing require- describes the implementation of sqmat and uses its tunable ments. It maintains the simplicity of a microbenchmark while parameters to evaluate four leading 64-bit microprocessors offering four distinct parameters to capture different types of that are popular building blocks for current high performance application workloads: working-set size (parameter “N”), systems: Intel Itanium2, AMD Opteron, IBM Power3, and computational intensity (parameter “M”), indirection (parame- IBM Power4. ter “I”), and irregularity (parameter “S”). By varying the parameters of sqmat, one can capture the 1. INTRODUCTION memory system behavior of a more diverse set of algorithms as shown in Table 1. With a high computational intensity (M), There is a growing gap between the peak speed of micro- the benchmark matches the characteristics of dense linear processor-based systems and the delivered performance for solvers that can be tiled into matrix-matrix operations (the so- scientific computing applications. This gap has raised the im- called “BLAS-3” operations). For example PARATEC [10] is portance of developing better benchmarking methods to im- a material science application that performs ab-initio quantum- prove performance understanding and prediction, while identi- mechanical total energy calculations using pseudopotentials fying hardware and application features that work well or and a plane wave basis set. This code relies on BLAS-3 librar- poorly together. Benchmarks are typically designed with two ies with direct memory addressing, thus having a high compu- competing interests in mind – capturing real application work- tational intensity, little indirection, and low irregularity. How- loads and identifying specific architectural bottlenecks that ever, not all dense linear algebra problems can be tiled in this inhibit the performance. Benchmarking suites like the NAS manner; instead they are organized as dense matrix-vector Parallel Benchmarks [7] and the Standard Performance (BLAS-2) or vector-vector (BLAS-1) operations, which re- Evaluation Corporation (SPEC) [1] emphasize the first goal of quire fewer operations on each element. This behavior is cap- representing real applications, but they are typically too large tured in sqmat by reducing the computational intensity, possi- to run on simulated architectures and are too complex to em- bly in combination with a reduced working set size (N). ploy for identification of specific architectural bottlenecks. Indirection, sometimes called scatter/gather style memory Likewise, the complexity of these benchmarks can often end access, occurs in sparse linear algebra, particle methods, and up measuring the quality of the compiler’s optimizations as grid-based applications with irregular domain boundaries. much as it does the underlying hardware architecture. At the Most are characterized by noncontiguous memory access; thus other extreme, microbenchmarks such as STREAM [6] are placing additional stress on memory systems that rely on large used to measure the performance of a specific feature of a cache lines to mask memory latency. The amount of irregular- given computer architecture. Such synthetic benchmarks are ity varies enormously in practice. For example, sparse matri- often easier to optimize so as to minimize the dependence on ces that arise in Finite Element applications often contain the maturity of the compiler technology. However, the sim- small dense sub-blocks, which cause a string of consecutive plicity and narrow focus of these codes often makes it quite indexes in an indirect access of a sparse matrix-vector product difficult to relate to real application codes. Indeed, it is rare (SPMV). Table 1 shows an example of SPMV where one-third that such probes offer any predictive value for the perform- of data are irregularly accessed; in general the irregularity (S) ance of full-fledged scientific application. would depend on the sparse matrix structure. Another example Floating-point M N CI S % 1 2 3 4 … 73 74 75 76 orig:sqmat irreg memory array DAXPY 1 1 0.5:0.5 - 0% Pointer memory 1 2 3 4 5 6 7 8 DGEMM 1 4 3.5:3.5 - 0% array MADCAP[12] 2 4 7.5:7.0 - 0% SPMV 1 4 3.5:3.5 3 33% Figure 1: Example of Sqmat indirection for S=4 Table 1: Mapping Sqmat parameters onto algorithms the results are written back to memory. We use a Java pro- gram to generate optimally hand-unrolled C-code [9], greatly of algorithmic irregularity can be found in GTC - a magnetic reducing the influence of the C-compiler’s code generation fusion code that solves the gyro-averaged Vlasov-Poisson and thereby making sure that the hardware architecture rather system of equations using the particle-in-cell (PIC) approach than the compiler is benchmarked. The innermost loop is un- [11]. PIC is a sparse method for calculating particle motion rolled enough to ensure that all available floating-point regis- and is characterized by relatively low computational intensity, ters are occupied by operands during each cycle of the loop. array indirection, and high irregularity. In both cases, the The unrolling is not so extreme as to cause processor stalls stream of memory accesses may contain sequences of con- either due to the increased number of instructions or additional tiguous memory accesses broken up by random-access jumps. branch-prediction penalties If enough registers are available In this paper, we describe the implementation of the sqmat . probe and focus on how its four parameters enable us to on the target machine, several matrices are squared at the same evaluate the behavior of four microprocessors that are popular time. Since squaring the matrix cannot be done in situ, an in- put and output matrix is needed for computation, thus a total building blocks for current high performance machines. The 2 processors are compared on a basis of the delivered percentage of 2⋅N registers are required per matrix. of peak performance rather than absolute performance so as to For direct access, each double-precision floating-point value limit the bias inherent in comparisons between different gen- has to be loaded and stored, creating 8 bytes memory-load and erations of microprocessor implementations. We evaluate 8 bytes memory-store traffic. For indirect access, the value these processors and isolate architectural features responsible and the pointer have to be loaded. As we always use 64-bit for performance bottlenecks, giving application developers pointers in 64-bit mode, each entry creates 16 bytes of mem- valuable hints on where to optimize their codes. Future work ory-load and 8 bytes of memory-store traffic. will focus on correlating sqmat parameters across a spectrum To allow a comparison between the different architectures, of scientific applications. we introduce the algorithmic peak performance (AP) metric. The AP is defined as the performance that could be achieved on the underlying hardware for a given algorithm if all the 2. SQMAT OVERVIEW floating-point units were optimally used. The AP is always The Sqmat benchmark is based on matrix multiplication and equal to or less than the machine peak performance (MP). For is therefore related to the Linpack benchmark
Recommended publications
  • Hardware Architecture
    Hardware Architecture Components Computing Infrastructure Components Servers Clients LAN & WLAN Internet Connectivity Computation Software Storage Backup Integration is the Key ! Security Data Network Management Computer Today’s Computer Computer Model: Von Neumann Architecture Computer Model Input: keyboard, mouse, scanner, punch cards Processing: CPU executes the computer program Output: monitor, printer, fax machine Storage: hard drive, optical media, diskettes, magnetic tape Von Neumann architecture - Wiki Article (15 min YouTube Video) Components Computer Components Components Computer Components CPU Memory Hard Disk Mother Board CD/DVD Drives Adaptors Power Supply Display Keyboard Mouse Network Interface I/O ports CPU CPU CPU – Central Processing Unit (Microprocessor) consists of three parts: Control Unit • Execute programs/instructions: the machine language • Move data from one memory location to another • Communicate between other parts of a PC Arithmetic Logic Unit • Arithmetic operations: add, subtract, multiply, divide • Logic operations: and, or, xor • Floating point operations: real number manipulation Registers CPU Processor Architecture See How the CPU Works In One Lesson (20 min YouTube Video) CPU CPU CPU speed is influenced by several factors: Chip Manufacturing Technology: nm (2002: 130 nm, 2004: 90nm, 2006: 65 nm, 2008: 45nm, 2010:32nm, Latest is 22nm) Clock speed: Gigahertz (Typical : 2 – 3 GHz, Maximum 5.5 GHz) Front Side Bus: MHz (Typical: 1333MHz , 1666MHz) Word size : 32-bit or 64-bit word sizes Cache: Level 1 (64 KB per core), Level 2 (256 KB per core) caches on die. Now Level 3 (2 MB to 8 MB shared) cache also on die Instruction set size: X86 (CISC), RISC Microarchitecture: CPU Internal Architecture (Ivy Bridge, Haswell) Single Core/Multi Core Multi Threading Hyper Threading vs.
    [Show full text]
  • Efficient Processing of Deep Neural Networks
    Efficient Processing of Deep Neural Networks Vivienne Sze, Yu-Hsin Chen, Tien-Ju Yang, Joel Emer Massachusetts Institute of Technology Reference: V. Sze, Y.-H.Chen, T.-J. Yang, J. S. Emer, ”Efficient Processing of Deep Neural Networks,” Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2020 For book updates, sign up for mailing list at http://mailman.mit.edu/mailman/listinfo/eems-news June 15, 2020 Abstract This book provides a structured treatment of the key principles and techniques for enabling efficient process- ing of deep neural networks (DNNs). DNNs are currently widely used for many artificial intelligence (AI) applications, including computer vision, speech recognition, and robotics. While DNNs deliver state-of-the- art accuracy on many AI tasks, it comes at the cost of high computational complexity. Therefore, techniques that enable efficient processing of deep neural networks to improve key metrics—such as energy-efficiency, throughput, and latency—without sacrificing accuracy or increasing hardware costs are critical to enabling the wide deployment of DNNs in AI systems. The book includes background on DNN processing; a description and taxonomy of hardware architectural approaches for designing DNN accelerators; key metrics for evaluating and comparing different designs; features of DNN processing that are amenable to hardware/algorithm co-design to improve energy efficiency and throughput; and opportunities for applying new technologies. Readers will find a structured introduction to the field as well as formalization and organization of key concepts from contemporary work that provide insights that may spark new ideas. 1 Contents Preface 9 I Understanding Deep Neural Networks 13 1 Introduction 14 1.1 Background on Deep Neural Networks .
    [Show full text]
  • Architectural Adaptation for Application-Specific Locality
    Architectural Adaptation for Application-Specific Locality Optimizations y z Xingbin Zhang Ali Dasdan Martin Schulz Rajesh K. Gupta Andrew A. Chien Department of Computer Science yInstitut f¨ur Informatik University of Illinois at Urbana-Champaign Technische Universit¨at M¨unchen g fzhang,dasdan,achien @cs.uiuc.edu [email protected] zInformation and Computer Science, University of California at Irvine [email protected] Abstract without repartitioning hardware and software functionality and reimplementing the co-processing hardware. This re- We propose a machine architecture that integrates pro- targetability problem is an obstacle toward exploiting pro- grammable logic into key components of the system with grammable logic for general purpose computing. the goal of customizing architectural mechanisms and poli- cies to match an application. This approach presents We propose a machine architecture that integrates pro- an improvement over traditional approach of exploiting grammable logic into key components of the system with programmable logic as a separate co-processor by pre- the goal of customizing architectural mechanisms and poli- serving machine usability through software and over tra- cies to match an application. We base our design on the ditional computer architecture by providing application- premise that communication is already critical and getting specific hardware assists. We present two case studies of increasingly so [17], and flexible interconnects can be used architectural customization to enhance latency tolerance to replace static wires at competitive performance [6, 9, 20]. and efficiently utilize network bisection on multiproces- Our approach presents an improvement over co-processing sors for sparse matrix computations. We demonstrate that by preserving machine usability through software and over application-specific hardware assists and policies can pro- traditional computer architecture by providing application- vide substantial improvements in performance on a per ap- specific hardware assists.
    [Show full text]
  • Development of a Predictable Hardware Architecture Template and Integration Into an Automated System Design Flow
    Development Secure of Reprogramming a Predictable Hardware of Architecturea Network Template Connected and Device Integration into an Automated System Design Flow Securing programmable logic controllers MARCUS MIKULCAK MUSSIE TESFAYE KTH Information and Communication Technology Masters’ Degree Project Second level, 30.0 HEC Stockholm, Sweden June 2013 TRITA-ICT-EX-2013:138Degree project in Communication Systems Second level, 30.0 HEC Stockholm, Sweden Secure Reprogramming of a Network Connected Device KTH ROYAL INSTITUTE OF TECHNOLOGY Securing programmable logic controllers SCHOOL OF INFORMATION AND COMMUNICATION TECHNOLOGY ELECTRONIC SYSTEMS MUSSIE TESFAYE Development of a Predictable Hardware Architecture TemplateKTH Information and Communication Technology and Integration into an Automated System Design Flow Master of Science Thesis in System-on-Chip Design Stockholm, June 2013 TRITA-ICT-EX-2013:138 Author: Examiner: Marcus Mikulcak Assoc. Prof. Ingo Sander Supervisor: Seyed Hosein Attarzadeh Niaki Degree project in Communication Systems Second level, 30.0 HEC Stockholm, Sweden Abstract The requirements of safety-critical real-time embedded systems pose unique challenges on their design process which cannot be fulfilled with traditional development methods. To ensure their correct timing and functionality, it has been suggested to move the design process to a higher abstraction level, which opens the possibility to utilize automated correct-by-design development flows from a functional specification of the system down to the level of Multiprocessor Systems-on-Chip. ForSyDe, an embedded system design methodology, presents a flow of this kind by basing system development on the theory of Models of Computation and side-effect-free processes, making it possible to separate the timing analysis of computation and communication of process networks.
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • Integrated Circuit Technology for Wireless Communications: an Overview Babak Daneshrad Integrated Circuits and Systems Laboratory UCLA Electrical Engineering Dept
    Integrated Circuit Technology for Wireless Communications: An Overview Babak Daneshrad Integrated Circuits and Systems Laboratory UCLA Electrical Engineering Dept. email: [email protected] http://www.ee.ucla.edu/~babak Abstract: Figure 1 shows a block diagram of a typical wireless com- This paper provides a brief overview of present trends in the develop- munication system. Moreover it shows the partitioning of the ment of integrated circuit technology for applications in the wireless receiver into RF, IF, baseband analog and digital components. communications industry. Through advanced circuit, architectural and In this paper we will focus on two main classes of integrated processing technologies, ICs have helped bring about the wireless revo- circuit technologies. The first is ICs for analog and more lution by enabling highly sophisticated, low cost and portable end user importantly RF communications. In general the technologist as terminals. In this paper two broad categories of circuits are highlighted. The first is RF integrated circuits and the second is digital baseband well as the circuit designer’s challenge here is to first, make the processing circuits. In both areas, the paper presents the circuit design transistors operate at higher carrier frequencies, and second, to challenges and options presented to the designer. It also highlights the integrate as many of the components required in the receiver manner in which these technologies have helped advance wireless com- onto the IC. The second class of circuits that we will focus on munications. are digital baseband circuits. Where increased density and I. Introduction reduced power consumption are the key factors for optimiza- tion.
    [Show full text]
  • Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES
    sensors Article Hybrid Pipeline Hardware Architecture Based on Error Detection and Correction for AES Ignacio Algredo-Badillo 1,† , Kelsey A. Ramírez-Gutiérrez 1,† , Luis Alberto Morales-Rosales 2,* , Daniel Pacheco Bautista 3,† and Claudia Feregrino-Uribe 4,† 1 CONACYT-Instituto Nacional de Astrofísica, Óptica y Electrónica, Puebla 72840, Mexico; [email protected] (I.A.-B.); [email protected] (K.A.R.-G.) 2 Faculty of Civil Engineering, CONACYT-Universidad Michoacana de San Nicolás de Hidalgo, Morelia 58000, Mexico 3 Departamento de Ingeniería en Computación, Universidad del Istmo, Campus Tehuantepec, Oaxaca 70760, Mexico; [email protected] 4 Instituto Nacional de Astrofísica, Óptica y Electrónica, Puebla 72840, Mexico; [email protected] * Correspondence: [email protected] † These authors contributed equally to this work. Abstract: Currently, cryptographic algorithms are widely applied to communications systems to guarantee data security. For instance, in an emerging automotive environment where connectivity is a core part of autonomous and connected cars, it is essential to guarantee secure communications both inside and outside the vehicle. The AES algorithm has been widely applied to protect communications in onboard networks and outside the vehicle. Hardware implementations use techniques such as iterative, parallel, unrolled, and pipeline architectures. Nevertheless, the use of AES does not Citation: Algredo-Badillo, I.; guarantee secure communication, because previous works have proved that implementations of secret Ramírez-Gutiérrez, K.A.; key cryptosystems, such as AES, in hardware are sensitive to differential fault analysis. Moreover, Morales-Rosales, L.A.; Pacheco it has been demonstrated that even a single fault during encryption or decryption could cause Bautista, D.; Feregrino-Uribe, C.
    [Show full text]
  • Extensible Hardware Architecture for Mobile Robots
    Extensible Hardware Architecture for Mobile Robots Eric Park∗, Linda Kobayashi, and Susan Y. Lee∗ Intelligent Robotics Group NASA Ames Research Center Moffett Field, CA 94035-1000, USA {epark, lkobayashi, sylee}@arc.nasa.gov Abstract— The Intelligent Robotics Group at NASA Ames Research Center has developed a new mobile robot hardware architecture designed for extensibility and reconfigurability. Currently implemented on the K9 rover, and soon to be integrated onto the K10 series of human-robot collaboration research robots, this achitecture allows for rapid changes in instrumentation configuration and provides a high degree of modularity through a synergistic mix of off-the-shelf and custom designed components, allowing eased transplantation into a wide variety of mobile robot platforms. A component level overview of this architecture is presented along with a description of the changes required for implementation on K10, followed by plans for future work. Index Terms— modular, extensible, hardware architecture, mobile robot, k9 INTRODUCTION Fig. 1. K9 rover Mobile robots used for research and development are in increasing demand as the application space for robotics K9 Overview widens. With this demand comes the need for a smarter way to produce reliable mobile robots with a proven set The K9 rover is a 6-wheel steer, 6-wheel drive rocker- of avionics. Time and money lost in developing custom bogey chassis outfitted with electronics and instruments architectures for each new robot makes it increasingly appropriate for supporting research relevant to remote important to develop extensible hardware architectures that exploration [2] [3] [4]. K9’s overall dimensions are 1.05m can expand and accommodate rapid changes in configu- long by 0.85m wide by 1.6m high, with a mass of ap- ration, including transfer to an entirely different mobile proximately 65 kg and a top speed of approximately 6 platform [1].
    [Show full text]
  • Ultra-Low-Power Design and Implementation of Application-Specific Instruction-Set Processors for Ubiquitous Sensing and Computing
    Ultra-low-power Design and Implementation of Application-specific Instruction-set Processors for Ubiquitous Sensing and Computing NING MA Doctoral Thesis in Electronic and Computer Systems Stockholm, Sweden 2015 TRITA-ICT 2015:11 KTH School of Information and ISSN 1653-6363 Communication Technology ISRN KTH/ICT-2015/11-SE SE-164 40 Kista, Stockholm ISBN 978-91-7595-692-3 SWEDEN Akademisk avhandling som med tillstånd av Kungl Tekniska högskolan framlägges till offentlig granskning för avläggande av teknologie doktorsexamen i Elektronik och Datorsystem onsdag den 4 november 2015 klockan 10.00 i Sal B, Electrum, Kungl Tekniska högskolan, Kista 164 40, Stockholm. © Ning Ma, September 2015 Tryck: Universitetsservice US AB iii Abstract The feature size of transistors keeps shrinking with the development of technology, which enables ubiquitous sensing and computing. However, with the break down of Dennard scaling caused by the difficulties for further lower- ing supply voltage, the power density increases significantly. The consequence is that, for a given power budget, the energy efficiency must be improved for hardware resources to maximize the performance. Application-specific inte- grated circuits (ASICs) obtain high energy efficiency at the cost of low flexi- bility for various applications, while general-purpose processors (GPPs) gain generality at the expense of efficiency. To provide both high energy efficiency and flexibility, this dissertation ex- plores the ultra-low-power design of application-specific instruction-set pro- cessors (ASIP) for ubiquitous sensing and computing. Two application sce- narios, i.e. high-throughput compute-intensive processing for multimedia and low-throughput low-cost processing for Internet of Things (IoT) are imple- mented in the proposed ASIPs.
    [Show full text]
  • Foundations for the Study of Software Architecture
    ACM SIGSOFT SOFTWARE ENGINEERING NOTES vol 17 no 4 Oct 1992 Page 40 Foundations for the Study of Software Architecture Alexander L. Wolf Dewayne E. Perry Department of Computer Science AT&T Bell Lab oratories University of Colorado 600 Mountain Avenue Boulder, Colorado 80309 Murray Hill, New Jersey 07974 [email protected] [email protected] c 1989,1991,1992 Dewayne E. Perry and Alexander L. Wolf ABSTRACT more toward integrating designs and the design pro cess into the broader context of the software pro cess and its management. One result of this integration was that The purp ose of this pap er is to build the foundation many of the notations and techniques develop ed for soft- for software architecture. We rst develop an intuition ware design have b een absorb ed by implementation lan- for software architecture by app ealing to several well- guages. Consider, for example, the concept of supp ort- established architectural disciplines. On the basis of ing \programmming-in-the-large". This integration has this intuition, we present a mo del of software architec- tended to blur, if not confuse, the distinction b etween ture that consists of three comp onents: elements, form, design and implementation. and rationale. Elements are either pro cessing, data, or The 1980s also saw great advances in our abilityto connecting elements. Form is de ned in terms of the describ e and analyze software systems. We refer here to prop erties of, and the relationships among, the elements | that is, the constraints on the elements. The ratio- such things as formal descriptive techniques and sophis- nale provides the underlying basis for the architecture in ticated notions of typing that enable us to reason more terms of the system constraints, which most often derive e ectively ab out software systems.
    [Show full text]
  • 1. SYSTEM ARCHITECTURE 1.1 System Hardware Architecture
    1. SYSTEM ARCHITECTURE 1.1 System Hardware Architecture This part represents a potential hardware architecture as a series view or deployment view. These are view base on the overall architectures of our hardware system and organization. Also, the system requirements are specified to hardware components. 1.1.1 List of Hardware components ● Ultrasonic sensor HC-SR04 ● Arduino Board MCU ESP8266 ● Monitor ● Keyboard/Mouse ● Wireless Router ● Computer CPU ● GPS/GPRS Module 1.1.2 Diagram showing the connectivity between the components We represent into the deployment view of the architecture. To showing the connectivity between the components. Describes the physical components (hardware), their distribution (e.g., a web server, database server) and how the different pieces are connected. So, we choose the deployment diagram to represent deployment view. The reason we choose this approach is the simplest model and suited for a proof of concept as shown in figure 1. Figure 1: Deployment Diagram Install the Ultrasonic sensor inside the waste container on its cover. The Ultrasonic sensor will measure the level of garbage inside the waste container and send the digital signal to centralized server by wireless cellular network. The centralized server will control all the process in a central location. System Administrator can manage all of it at the desktops at the waste station. Garbage truck driver can also check status of each waste container by their devices or Personal Computer at the waste station. 1.2 System Software Architecture This part represents a potential software architecture as a series views; use- case view. These are view based on the overall architecture of our software system and organization.
    [Show full text]
  • Method of Top-Level Design for Automated Test Systems
    Advances in Engineering Research, volume 127 3rd International Conference on Electrical, Automation and Mechanical Engineering (EAME 2018) Method of Top-level Design for Automated Test Systems Zhenjie Zeng1, Xiaofei Zhu1,*, Shiju Qi1, Kai Wu2 and Xiaowei Shen1 1Rocket Force University of Engineering, Xi’an, China 2Troops No. 96604, Beijing, China *Corresponding author Abstract—When designing an automatic test system, it is The top-level design of automatic test system integration is necessary to make each electronic test device conform to different based on sufficient requirements analysis, and comprehensively test requirements. The most important issue is the system top- considers the optimal matching of technical and economic level design. The article starts with the three steps of the top-level performances. It is advanced, practical, open, real-time, design: system requirements analysis, architecture selection and universal (compatibility), and reliability. , maintainability and analysis, and test equipment configuration. It describes in detail other aspects of a comprehensive analysis, determine the test how to develop the top-level system design efficiently and system architecture (including hardware platforms and software reasonably when developing automated test systems. The platforms), develop a corresponding test program. As shown in principles, available method techniques, and precautions have Figure 1, it is usually divided into three steps: requirements some guiding significance for the top-level design of automated analysis,
    [Show full text]