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NanGate
UCLA Electronic Theses and Dissertations
Predictive Aging of Reliability of Two Delay Pufs
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A Fine-Grained 3D IC Technology with NP-Dynamic Logic
Eg, Nangate 15 Nm Standard Cell Library
Timing Analysis of Integrated Circuits
Standard Cell Library Design and Optimization Methodology for ASAP7
Rapid Co-Optimization of Processing and Circuit Design to Overcome
Does Logic Locking Work with EDA Tools?
Exploring Voltage Scaling Techniques in Embedded Processors Hardware Monitors
Reliable Design of Three-Dimensional Integrated Circuits
Reliability-Aware Design to Suppress Aging
Area Complexity Estimation for Combinational Logic Using Fourier Transform on Boolean Cube
A Learning-Based Framework for Circuit Path Level NBTI Degradation Prediction
Compact Variation-Aware Standard Cell Models for Statistical Static Timing Analysis
Cell Libraries and Verification
Aging-Aware Standard Cell Library Design
Design Flows and Collateral for the ASAP 7Nm Finfet Predictive Process Design
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The Area-Latency Symbiosis: Towards Improved Serial Encryption Circuits
5Nm Finfet Standard Cell Library Optimization and Circuit Synthesis in Near- and Super-Threshold Voltage Regimes
1. Publishable Summary
Standard Cell Pin Access and Physical Design in Advanced Lithography
Mono3d: Open Source Cell Library for Monolithic 3-D Integrated Circuits
Aadam: a Fast, Accurate, and Versatile Aging-Aware Cell Library Delay Model Using Feed-Forward Neural Network
Discrete Circuit Optimization: Library Based Gate Sizing and Threshold Voltage Assignment Full Text Available At
Christian Pilato
Design of Coarse-Grained Power Gating for a Fine-Grained Many-Core Processor Array
DESIGN AUTOMATION and EVALUATION of EMERGING 3D – IC TECHNOLOGY USING STACKED HORIZONTAL NANOWIRES a THESIS in Electrical Engi