Aadam: A Fast, Accurate, and Versatile Aging-Aware Cell Library Delay Model using Feed-Forward Neural Network Seyed Milad Ebrahimipour1, Behnam Ghavami2, Hamid Mousavi1, Mohsen Raji3 Zhenman Fang2, Lesley Shannon2 1Shahid Bahonar University of Kerman, {miladebrahimi, hamidmousavi0}@eng.uk.ac.ir 2Simon Fraser University, {behnam_ghavami, zhenman, lesley_shannon}@sfu.ca 3Shiraz University, [email protected] ABSTRACT 1 INTRODUCTION With the CMOS technology scaling, transistor aging has become With the CMOS technology scaling, the reliability of circuits has one major issue affecting circuit reliability and lifetime. There are become one of the major issues affecting digital circuit designs1 [ , 7]. two major classes of existing studies that model the aging effects In addition to the correct functionality of the circuit, a longtime in the circuit delay. One is at transistor-level, which is highly ac- lifespan is also crucial in many application fields such as aerospace, curate but very slow. The other is at gate-level, which is faster but defense, and medical industries [5, 13]. Transistor aging is a key less accurate. Moreover, most prior studies only consider a limited source of failure that threatens the lifetime reliability of digital subset or limited value ranges of aging factors. circuits. It leads to a degradation of the electrical characteristics of In this paper, we propose Aadam, a fast, accurate, and versatile transistors and subsequently, a considerable increase of the device aging-aware delay model for generic cell libraries. In Aadam, we delay [19]. For example, the Negative Bias Temperature Instability first use transistor-level SPICE simulations to accurately charac- (NBTI) aging phenomenon, a major parametric reliability issue, terize the delay degradation of each library cell under a versatile may increase the circuit delay by up to 30% [14]. This impact may set of aging factors, including both physical parameters (i.e., initial eventually lead to violations of circuit timing constraints, reduction threshold voltage and transistor width/length ratio) and operat- of mean time to failure, and faster wear-out of the system. ing conditions (i.e., working temperature, signal probability, input To steer clear of the aging effects and guarantee the correct signal slew range, output load capacitance range, and projected functionality of the circuit for the projected lifetime (C), designers lifetime). For each library cell, we then train a feed-forward neu- have to include a safety timing margin called timing guard band in ral network (FFNN) to learn the relation between the input aging the design [6, 27]. This timing guard band may decrease the circuit factors and output cell delay degradation. Therefore, for a given frequency, as shown in Equation 1. input circuit and a given combination of aging factors, we can use 1 the trained FFNNs to quickly and accurately infer the delay degra- 5 A4@D4=2~ = ; 퐷 ¹Cº = 퐷 ¹0º ¸ 퐷 ¹Cº (1) 퐷 ¹Cº 퐺퐵 dation for each gate in the circuit. Finally, to effectively estimate the aging-aware lifetime delay of large-scale circuits, we also inte- where 5 A4@D4=2~ denotes the targeted frequency of the design and grate Aadam into a state-of-the-art static timing analysis tool called 퐷 ¹Cº represents the lifetime delay. 퐷 ¹0º and 퐷퐺퐵 ¹Cº respectively OpenTimer. Experimental results demonstrate that Aadam achieves denote the initial delay of the circuit and the delay of the tim- fast estimation of the aging-induced delay with high accuracy close ing guard band. To reduce the performance overhead imposed by to transistor-level simulation. 퐷퐺퐵 ¹Cº, it is essential to accurately estimate the aging-induced delay degradation of the circuit and apply a minimum 퐷퐺퐵 ¹Cº. KEYWORDS However, it is nontrivial to quickly and accurately estimate the Aging, Reliability, Delay Model, Machine Learning, Cell Library aging-induced delay degradation as there are many factors that affect the delay degradation. They include both physical parame- ACM Reference Format: ters (i.e., initial threshold voltage and transistor width/length ratio) Seyed Milad Ebrahimipour1, Behnam Ghavami2, Hamid Mousavi1, and operating conditions (i.e., working temperature, signal proba- Mohsen Raji3 and Zhenman Fang2, Lesley Shannon2. 2020. Aadam: A Fast, Accurate, and Versatile Aging-Aware Cell Library Delay Model using bility, input signal slew range, output load capacitance range, and Feed-Forward Neural Network. In IEEE/ACM International Conference on projected lifetime), which will be explained in detail in Section 2.1.2. Computer-Aided Design (ICCAD ’20), November 2–5, 2020, Virtual Event, USA. As will be detailed in Section 2.2, the prior studies that model ACM, New York, NY, USA, 9 pages. https://doi.org/10.1145/3400302.3415605 the aging effects in the circuit delay can be divided into thefol- lowing categories. The first category of work [34] uses full-circuit Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed transistor-level SPICE simulation to achieve high accuracy, but runs for profit or commercial advantage and that copies bear this notice and the full citation at very slow speed. The second category of work [2, 28–30, 37, 40] on the first page. Copyrights for components of this work owned by others than ACM uses lookup table (LUT) based gate-level models to achieve faster must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a speed at the expense of lower accuracy. The third category of work fee. Request permissions from [email protected]. [16, 26] only performs SPICE simulation for a set of critical paths, ICCAD ’20, November 2–5, 2020, Virtual Event, USA but is still slow for large-scale circuits. The last category of work © 2020 Association for Computing Machinery. ACM ISBN 978-1-4503-8026-3/20/11...$15.00 [20, 25, 38, 39] starts to use traditional machine learning techniques https://doi.org/10.1145/3400302.3415605 such as support vector machine (SVM) and non-linear regression ICCAD ’20, November 2–5, 2020, Virtual Event, USA Seyed Milad Ebrahimipour1, Behnam Ghavami2, Hamid Mousavi1, Mohsen Raji3 and Zhenman Fang2, Lesley Shannon2 model to predict the delay caused by the NBTI effect at gate-level or the channel and degrades the transistor’s mobility ¹`º. Second, critical path level. In fact, most prior studies only consider a limited because of the non-epitaxial structure of (8$2, the vertical electric subset of aging factors and/or limited value ranges of aging factors. field leads to defect generation in the interface of the transistor To address those issues in prior studies, in this paper, we propose and the formation of defects inside the (8$2. These defects cause Aadam, an accurate yet fast aging-aware delay model for generic accumulated charges around and within the gate dielectric, which cell libraries by considering a versatile set of aging factors that are ultimately increases the threshold voltage ¹+Cℎº of the transistor. summarized in Section 2.1.2. The major idea behind Aadam is to For a projected lifetime (C), the delay of a transistor ¹퐷¹Cºº is leverage 1) the high accuracy of transistor-level SPICE simulation inversely proportional to its drain current ¹퐼퐷 ¹Cºº, and 퐼퐷 ¹Cº is a to characterize the delay degradation of library cells only; 2) the function of the transistor’s mobility ¹`¹Cºº and threshold voltage learning power of feed-forward neural networks (FFNN) [18] to ¹+Cℎ ¹Cºº, as shown in Equation 2 (where +33 denotes the supply accurately and quickly predict the aging-induced delay at gate- voltage). As a result, with `¹Cº decreasing and +Cℎ ¹Cº increasing level under the versatile combinations of aging effects; and 3) the during the operation of the transistor, 퐼퐷 ¹Cº decreases and the fast aging-aware static timing analysis (STA) of large-scale circuits transistor delay ¹퐷¹Cºº increases. using the state-of-the-art STA tool called OpenTimer [21]. 1 `¹Cº Aadam provides a fully automated framework for aging-aware 퐷¹Cº / ; 퐼 ¹Cº ≈ ¹+ − + ¹Cºº2 (2) 퐼 ¹Cº 퐷 2 33 Cℎ STA of large-scale circuits. In Aadam, we first characterize the 퐷 delay degradation of each library cell under a versatile set of aging 2.1.2 Gate-Level. Each gate in the circuit is exposed to different factors as mentioned earlier, using the accurate transistor-level operating conditions that can lead to different aging-induced delay SPICE simulations. Based on these characterized data, we train an degradations over the projected lifetime (t). FFNN to learn the relation between the input aging factors and 1. The working temperature (T) has a great impact on the trap output delay degradation for each library cell. As a result, these generation of transistors in a gate. As ) increases, the rate of trained FFNNs can quickly and accurately predict the aging-induced interface and oxide trap generation increases [3, 4], i.e., +Cℎ ¹Cº delay at gate-level. Finally, we integrate these trained FFNN models increases faster and `¹Cº decreases faster. This includes both to a state-of-the-art STA tool called OpenTimer [21] to effectively Positive Bias Temperature Instability (PBTI) effect in NMOS estimate the aging-aware lifetime delay of large-scale circuits. We transistors and Negative Bias Temperature Instability (NBTI) plan to release our Aadam toolflow to the public in the near future. effect in PMOS transistors. In our experiments, we use the open-source Nangate 45nm 2. The signal probability (_) also has a great impact on the trap generic cell library [31], and a few circuits from the ISCAS’85 [10], generation.