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EMBEDDED PROGRAMMABLE LOGIC CORES By IMPLEMENTATION CONSIDERATIONS FOR “SOFT” EMBEDDED PROGRAMMABLE LOGIC CORES by James Cheng-Huan Wu B.A.Sc., University of British Columbia, 2002 A thesis submitted in partial fulfillment of the requirements for the degree of Master of Applied Science in The Faculty of Graduate Studies Department of Electrical and Computer Engineering We accept this thesis as conforming to the required standard: ___________________________ ___________________________ ___________________________ ___________________________ The University of British Columbia September 2004 © James C.H. Wu, 2004 ABSTRACT IMPLEMENTATION CONSIDERATIONS FOR “SOFT” EMBEDDED PROGRAMMABLE LOGIC CORES As integrated circuits become increasingly more complex and expensive, the ability to make post-fabrication changes will become much more attractive. This ability can be realized using programmable logic cores. Currently, such cores are available from vendors in the form of “hard” macro layouts. An alternative approach for fine-grain programmability is possible: vendors supply an RTL version of their programmable logic fabric that can be synthesized using standard cells. Although this technique may suffer in terms of speed, density, and power overhead, the task of integrating such cores is far easier than the task of integrating “hard” cores into an ASIC or SoC. When the required amount of programmable logic is small, this ease of use may be more important than the increased overhead. In this thesis, we identify potential implementation issues associated with such cores, and investigate in depth the area, speed and power overhead of using this approach. Based on this investigation, we attempt to improve the performance of programmable cores created in this manner. Using a test-chip implementation, we identify three main issues: core size selection, I/O connections, and clock-tree synthesis. Compared to a non-programmable design, the soft core approach exhibited an average area overhead of 200X, speed overhead of 10X, and power overhead of 150X. These numbers are high but expected, given that the approach is subject to limitations of the standard cell library elements of the ASIC flow, which are not optimized for use with programmable logic. ii TABLE OF CONTENTS ABSTRACT.................................................................................................................................. II TABLE OF CONTENTS ...........................................................................................................III LIST OF FIGURES ..................................................................................................................... V LIST OF TABLES .................................................................................................................... VII ACKNOWLEDGEMENTS ....................................................................................................VIII CHAPTER 1 INTRODUCTION.................................................................................................. 1 1.1 MOTIVATION ........................................................................................................................ 1 1.2 RESEARCH GOALS ................................................................................................................ 4 1.3 ORGANIZATION OF THE THESIS ........................................................................................... 5 CHAPTER 2 BACKGROUND AND RELEVANT WORK ..................................................... 7 2.1 EMBEDDED PROGRAMMABLE LOGIC CORES FOR SOCS .................................................... 7 2.1.1 Advantages and Design Approaches.............................................................................. 7 2.1.2 General IC Design Flow for SoC Designs................................................................... 10 2.1.3 Design Flow Employing Soft Programmable IPs........................................................ 14 2.2 OVERVIEW OF SYNTHESIZABLE GRADUAL ARCHITECTURE ............................................ 15 2.2.1 Logic Resources ...........................................................................................................16 2.2.2 Routing Fabric............................................................................................................. 17 2.3 CAD FOR SYNTHESIZABLE GRADUAL ARCHITECTURE.................................................... 19 2.3.1 Placement Algorithm.................................................................................................... 20 2.3.2 Routing Algorithm........................................................................................................ 24 2.4 SUMMARY ........................................................................................................................... 25 CHAPTER 3 DESIGN OF A PROOF-OF-CONCEPT PROGRAMMABLE MODULE.... 27 3.1 DESIGN ARCHITECTURE..................................................................................................... 27 3.1.1 Reference Version ........................................................................................................ 28 3.1.2 Programmable Version................................................................................................ 28 iii 3.2 TEST-CHIP IMPLEMENTATION FLOW................................................................................ 29 3.2.1 Modified ASIC IC Design Flow ................................................................................... 30 3.2.2 Front-end IC Design Flow........................................................................................... 31 3.2.3 Back-end IC Design Flow............................................................................................ 33 3.3 DESIGN AND IMPLEMENTATION ISSUES............................................................................. 34 3.3.1 Programmable Core Size Selection ............................................................................. 34 3.3.2 Connections between Programmable Core and Fixed Logic ...................................... 35 3.3.3 Routing the Programmable Clock Signals................................................................... 36 3.4 IMPLEMENTATION RESULTS .............................................................................................. 38 3.4.1 Area Overhead .............................................................................................................38 3.4.2 Speed Overhead ........................................................................................................... 41 3.4.3 Validation of Chip on Tester........................................................................................ 42 3.5 SUMMARY ........................................................................................................................... 43 CHAPTER 4 SPEED AND POWER CONSIDERATIONS FOR SOFT-PLC...................... 45 4.1 SPEED CONSIDERATIONS.................................................................................................... 45 4.1.1 Speed Measurement Methodology ............................................................................... 46 4.1.2 Soft-PLC vs. Equivalent ASIC Implementation ........................................................... 49 4.1.3 Speed Improvement Methodology................................................................................ 52 4.1.4 Experimental Results ................................................................................................... 57 4.2 POWER CONSIDERATIONS .................................................................................................. 63 4.2.1 Power Measurement Methodology .............................................................................. 63 4.2.2 Power Overhead vs. Equivalent ASIC Implementation ............................................... 64 4.3 SUMMARY ........................................................................................................................... 67 CHAPTER 5 CONCLUSIONS AND FUTURE WORK ......................................................... 69 5.1 SUMMARY ........................................................................................................................... 69 5.2 FUTURE WORK ................................................................................................................... 71 5.3 CONTRIBUTIONS ................................................................................................................. 72 REFERENCE.............................................................................................................................. 74 iv LIST OF FIGURES FIGURE 2.1 GENERAL IC DESIGN FLOW [18] ................................................................................. 10 FIGURE 2.2 FLOORPLANNING OF CHIP............................................................................................ 12 FIGURE 2.3 POWER PLANNING ....................................................................................................... 12 FIGURE 2.4 PLACEMENT, AND CLOCK-TREE SYNTHESIS ................................................................. 13 FIGURE 2.5 COMPARISON OF STANDARD FPGA AND SOFT PLC BLOCKS ....................................... 15 FIGURE 2.6 A GENERIC FPGA LOGIC BLOCK.................................................................................. 16 FIGURE 2.7 A LOGIC BLOCK FOR GRADUAL ARCHITECTURE.......................................................... 17 FIGURE 2.8 THE ISLAND-STYLED
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