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Advances in Debug Automation for a Modern Verification Environment

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Advances in Debug Automation for a Modern Verification Environment Advances in Debug Automation for a Modern Verification Environment by Brian Keng A thesis submitted in conformity with the requirements for the degree of Doctor of Philosophy Graduate Department of Electrical and Computer Engineering University of Toronto Copyright c 2013 by Brian Keng Abstract Advances in Debug Automation for a Modern Verification Environment Brian Keng Doctor of Philosophy Graduate Department of Electrical and Computer Engineering University of Toronto 2013 Over the past three decades, the growing list of requirements for integrated circuits has continually presented new challenges to the electronic design community. One of the biggest challenges in the design process is that of functional debugging, which aims to find the root- cause of a functional failure after it has been detected. In recent years, this key challenge has grown in size and scope as bugs commonly appear in both the design and verification environment. This increase in size and scope has made functional debugging one of the largest bottlenecks in the design cycle and points to an urgent need for more scalable and innovative debugging solutions. This dissertation presents multiple novel contributions that address the challenges of in- creased size and scope of modern functional debugging. In particular, these contributions address the scalability of existing automated design debugging techniques, as well as introduce novel automated tools specifically for debugging the verification environment. The first contribution introduces an unsatsifiable core-guided abstraction and refinement technique for design debugging that focuses on managing the design size aspect of debugging complexity. The second contribution introduces a path-directed abstraction and refinement technique that aims to manage the error trace length aspect of debugging complexity. The third contribution presents a novel method that utilizes unsatisfiable cores in design debugging to manage the multiple design errors aspect of debugging complexity. The fourth contribution presents an automated technique to aid debugging of errors found within formal properties themselves. The final contribution presents an automated technique to aid debugging of missing assumptions that are needed during verification methodologies that use formal methods. ii Acknowledgements First and foremost I would like to sincerely thank my Ph.D. supervisor Professor Andreas Veneris for being an excellent mentor, guide and teacher throughout my journey into research. You have been a constant source of motivation and guidance every step of the way. I would also like to thank my parents who are an infinite source of love and support. You have instilled in me the values and lessons that have guided me throughout my life. I am forever grateful. Many thanks to my brother and sister whose love and support always brings a smile to my face, and to my girlfriend Jane Wu for her never-ending encouragement in everything I do. Thank you to my colleagues at the University of Toronto and Vennsa Technologies for all your shared wisdom and constructive feedback. Special thanks are due to Duncan Exon Smith, Sean Safarpour, Hratch Mangassarian, Evean Qin, Alan Baker, Terry Yang, Bao Le, Dipanjan Sengupta and Zissis Poulos. I am also grateful to my Ph.D. committee members Professor Jason Anderson, Professor Vaughn Betz, Professor Stephen Brown, Professor Sharad Malik, Professor Konstantinos Pla- taniotis, and Professor Charles Rackoff for their excellent feedback and insightful suggestions for my dissertation. Finally, acknowledgments are due to the Natural Sciences and Engineering Research Council of Canada (NSERC), the Queen Elizabeth II Graduate Scholarship in Science and Technology, and the University of Toronto for their financial support. iii Contents List of Tables ix List of Figures xi List of Algorithms xiii 1 Introduction 1 1.1 Motivation ...................................... 1 1.1.1 Functional Verification and Debugging . ....... 4 1.1.2 CurrentStateofDebuggingTools . .... 6 1.1.3 DebugAutomation............................... 7 1.2 Contributions................................... ... 9 1.2.1 Core-Guided Abstraction and Refinement . ...... 10 1.2.2 Path Directed Abstraction and Refinement . ...... 11 1.2.3 Debugging of Multiple Errors Using UNSAT Cores . ....... 11 1.2.4 AutomatedDebuggingofAssertions . ..... 12 1.2.5 Automated Debugging of Missing Assumptions . ....... 12 1.3 ThesisOutline ................................... 13 2 Background 14 2.1 Introduction.................................... 14 2.2 FunctionalVerification . ...... 14 2.2.1 IterativeLogicArray. 17 iv 2.2.2 FormalVerification. 19 2.3 FunctionalDebugging ............................. 19 2.4 BooleanSatisfiability. ...... 21 2.4.1 CNFRepresentation . 22 2.4.2 Unsatisfiable Cores and Proofs of Unsatisfiability . ........... 23 2.5 SATSolvers...................................... 26 2.5.1 IncrementalSATandAssumptions . 32 2.6 SAT-basedAutomatedDesignDebugging . ....... 32 2.7 Formal Properties and SystemVerilog Assertions . ............ 36 2.8 Summary ........................................ 39 3 Core-Guided Abstraction and Refinement 40 3.1 Introduction.................................... 40 3.2 Preliminaries ................................... 42 3.2.1 ModuleNotation ................................ 42 3.2.2 Suspect-Guided Abstraction and Refinement . ....... 44 3.3 AbstractionandRefinement. ..... 45 3.3.1 AbstractionFormulation. 46 3.3.2 ModuleRefinement............................... 49 3.3.3 ExtensiontoBasicScheme . 52 3.3.4 OverallAlgorithm .............................. 52 3.4 Experiments..................................... 54 3.5 Summary ........................................ 59 4 Path Directed Abstraction and Refinement 61 4.1 Introduction.................................... 61 4.2 Preliminaries ................................... 63 4.2.1 TimeDiagnosisandTime-Windowing . 63 4.2.2 Counter-Example Guided Abstraction and Refinement . ......... 66 4.3 PathDirectedAbstractionandRefinement . ........ 66 v 4.3.1 Path-basedAbstraction . 69 4.3.2 PathDirectedRefinement . 73 4.3.3 OverallAlgorithm .............................. 77 4.4 ImprovedRefinement............................... 77 4.4.1 Finding Additional Conflicts using Necessary Assignments......... 78 4.4.2 Finding Additional Conflicts using Multiple State Cubes.......... 80 4.4.3 ImprovingtheInitialAbstraction . ....... 81 4.4.4 Leveraging the SAT-solver for Efficient Implementation .......... 83 4.5 FlexiblePathDirectedDebug . ...... 83 4.6 Experiments..................................... 85 4.6.1 RefinementImprovements . 86 4.6.2 WindowSize .................................. 88 4.6.3 FlexiblePathDirectedDebug. 90 4.6.4 TraceLength .................................. 92 4.7 Summary ........................................ 93 5 Debugging of Multiple Errors Using UNSAT Cores 97 5.1 Introduction.................................... 97 5.2 Preliminaries ................................... 98 5.2.1 Unsatisfiable Cores in Design Debugging . ....... 98 5.3 Efficient Debugging of Multiple Design Errors . ..........101 5.3.1 Reducing the Search Space of Multiple Design Errors . .........101 5.3.2 OverallAlgorithm .............................. 103 5.4 Experiments..................................... 104 5.5 Summary ........................................108 6 Automated Debugging of Assertions 109 6.1 Introduction.................................... 109 6.2 RelatedWork..................................... 111 6.3 AssertionDebuggingMethodology . .......111 vi 6.4 SystemVerilogAssertionMutation Model . .........113 6.5 Practical Considerations and Extensions . ...........118 6.6 Experiments..................................... 118 6.6.1 Localization.................................. 119 6.6.2 AssertionDebuggingMethodology . 120 6.7 Summary ........................................123 7 Automated Debugging of Missing Assumptions 127 7.1 Introduction.................................... 127 7.2 Preliminaries ................................... 129 7.2.1 Minimal Correction Sets and Unsatisfiable Cores . .........129 7.2.2 RelatedWork..................................130 7.3 AssumptionDebuggingFlow . 131 7.4 Generating Multiple Counter-examples . ..........132 7.4.1 Minimal Unsatisfiable Input Sets and Minimal Correction Input Sets . 133 7.4.2 Minimal Correction Input Subsets as Blocking Constraints . .135 7.4.3 APracticalAlgorithm . 137 7.4.4 Applications for Debugging Missing Input Assumptions ..........139 7.5 GeneratingAssumptions. 140 7.5.1 AssumptionModel ............................... 141 7.5.2 PruningCandidateAssumptions . 142 7.6 ExperimentalResults. 143 7.6.1 Generating Multiple Counter-Examples . .......143 7.6.2 AssumptionDebuggingMethodology . 145 7.6.3 Qualitative Analysis of Generated Assumptions . ..........148 7.7 Summary ........................................153 8 Conclusions and Future Work 154 8.1 Contributions................................... 154 8.2 FutureWork ...................................... 157 vii 8.2.1 ExtensionsofContributions . 158 8.2.2 FutureDirections.............................. 159 8.3 ClosingRemarks .................................. 161 Bibliography 162 viii List of Tables 1.1 TypesofErrors................................... 6 2.1 CNFforBasicLogicGates ........................... 23 2.2 Common SystemVerilog Assertion Operators . ......... 37 3.1 DesignStatistics ................................ 55 3.2 AbstractionandRefinementExperiments . ........ 60 4.1 DesignCharacteristics . ...... 87 4.2 RefinementImprovementExperiments
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