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Manoel Barros Marin BE-BI-BP ISOTDAQ 2019 @ Royal Holloway, University of London (UK) 09/04/2019

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Manoel Barros Marin BE-BI-BP ISOTDAQ 2019 @ Royal Holloway, University of London (UK) 09/04/2019 ISOTDAQ 2019 @ Royal Holloway, University of London (UK) 09/04/2019 Manoel Barros Marin BE-BI-BP ISOTDAQ 2019 @ Royal Holloway, University of London (UK) 09/04/2019 Outline: • … from the previous lesson • Key concepts about FPGA design • FPGA gateware design work flow • Summary Manoel Barros Marin BE-BI-BP ISOTDAQ 2019 @ Royal Holloway, University of London (UK) 09/04/2019 • … from the previous lesson Manoel Barros Marin BE-BI-BP … from the previous lesson What is an Field Programmable Gate Array (FPGA)? 4 … from the previous lesson What is an Field Programmable Gate Array (FPGA)? FPGA - Wikipedia https://en.wikipedia.org/wiki/Field-programmable_gate_array A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing – hence "field-programmable". 5 … from the previous lesson What is an Field Programmable Gate Array (FPGA)? FPGA - Wikipedia https://en.wikipedia.org/wiki/Field-programmable_gate_array A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing – hence "field-programmable". 6 … from the previous lesson • FPGA fabric (matrix like structure) made of: • I/O-cells to communicate with outside world • Logic cells o Look-Up-Table (LUT) to implement combinatorial logic o Flip-Flops (D) to implement sequential logic • Interconnect network between logic resources • Clock tree to distribute the clock signals 7 … from the previous lesson • But it also features Hard Blocks: Example of FPGA architecture 8 ISOTDAQ 2019 @ Royal Holloway, University of London (UK) 09/04/2019 •Key concepts about FPGA design Manoel Barros Marin BE-BI-BP Key concepts about FPGA design FPGA gateware design is NOT programming 10 Key concepts about FPGA design FPGA gateware design is NOT programming Sequential Parallel Processing Processing • Programming • Code is written and translated into instructions • Instructions are executed sequentially by the CPU(s) • Parallelism is achieved by running instructions on multiple threads/cores • Processing structures and instructions sets are fixed by the architecture of the system vs. • FPGA gateware design • No fixed architecture, the system is built according to the task • Building is done by describing/defining system elements and their relations • Intrinsically parallel, sequential behaviour is achieved by registers and Finite-State-Machines (FSMs) • Description done by schematics or a hardware description language (HDL) 11 Key concepts about FPGA design HDL are used for describing HARDWARE 12 Key concepts about FPGA design HDL are used for describing HARDWARE • Example of a WAIT statement (Programming Language VS. HDL) 13 Key concepts about FPGA design HDL are used for describing HARDWARE • Example of a WAIT statement (Programming Language VS. HDL) • In programming language (e.g. C) (Unix, #include <unistd.h>) sleep(5); // sleep 5 seconds 14 Key concepts about FPGA design HDL are used for describing HARDWARE • Example of a WAIT statement (Programming Language VS. HDL) • In programming language (e.g. C) (Unix, #include <unistd.h>) sleep(5); // sleep 5 seconds • In HDL (e.g. VHDL): o Not synthesizable (only for simulation test benches) 15 Key concepts about FPGA design HDL are used for describing HARDWARE • Example of a WAIT statement (Programming Language VS. HDL) • In programming language (e.g. C) (Unix, #include <unistd.h>) sleep(5); // sleep 5 seconds • In HDL (e.g. VHDL): o Not synthesizable (only for simulation test benches) o Synthesizable (for simulation and/or FPGA implementation) 16 Key concepts about FPGA design HDL are used for describing HARDWARE • Example of a WAIT statement (Programming Language VS. HDL) • In programming language (e.g. C) (Unix, #include <unistd.h>) sleep(5); // sleep 5 seconds • In HDL (e.g. VHDL): o Not synthesizable (only for simulation test benches) o Synthesizable (for simulation and/or FPGA implementation) Register Transfer Level (RTL) http://en.wikipedia.org/wiki/Register-transfer_level A design abstraction which models a synchronous digital circuit in terms of HDL to RTL the flow of digital signals (data) between registers and logical operations performed on those signals 17 Key concepts about FPGA design HDL are used for describing HARDWARE • Example of a WAIT statement (Programming Language VS. HDL) • In programming language (e.g. C) (Unix, #include <unistd.h>) sleep(5); // sleep 5 seconds • In HDL (e.g. VHDL): o Not synthesizable (only for simulation test benches) o Synthesizable (for simulation and/or FPGA implementation) Register Transfer Level (RTL) http://en.wikipedia.org/wiki/Register-transfer_level A design abstraction which models a synchronous digital circuit in terms of HDL to RTL the flow of digital signals (data) between registers and logical operations performed on those signals 18 Key concepts about FPGA design HDL are used for describing HARDWARE • Example of a WAIT statement (Programming Language VS. HDL) • In programming language (e.g. C) (Unix, #include <unistd.h>) sleep(5); // sleep 5 seconds • In HDL (e.g. VHDL): o Not synthesizable (only for simulation test benches) o Synthesizable (for simulation and/or FPGA implementation) Register Transfer Level (RTL) http://en.wikipedia.org/wiki/Register-transfer_level A design abstraction which models a synchronous digital circuit in terms of HDL to RTL the flow of digital signals (data) between registers and logical operations performed on those signals 19 Key concepts about FPGA design HDL are used for describing HARDWARE • Example of a WAIT statement (Programming Language VS. HDL) • In programming language (e.g. C) (Unix, #include <unistd.h>) sleep(5); // sleep 5 seconds • In HDL (e.g. VHDL): o Not synthesizable (only for simulation test benches) o Synthesizable (for simulation and/or FPGA implementation) Register Transfer Level (RTL) http://en.wikipedia.org/wiki/Register-transfer_level A design abstraction which models a synchronous digital circuit in terms of HDL to RTL the flow of digital signals (data) between registers and logical operations performed on those signals 20 Key concepts about FPGA design Timing in FPGA gateware design is critical 21 Key concepts about FPGA design Timing in FPGA gateware design is critical • Data propagates in the form of electrical signals through the FPGA x 22 Key concepts about FPGA design Timing in FPGA gateware design is critical • Data propagates in the form of electrical signals through the FPGA x Synthesized RTL (Netlist) is implemented into FPGA 23 Key concepts about FPGA design Timing in FPGA gateware design is critical • Data propagates in the form of electrical signals through the FPGA x Synthesized RTL (Netlist) is implemented into FPGA • If these signals do not arrive to their destination on time… The consequences may be catastrophic!!! 24 Key concepts about FPGA design When designing FPGA gateware you have to think HARD… 25 Key concepts about FPGA design When designing FPGA gateware you have to think HARDWARE… 26 ISOTDAQ 2019 @ Royal Holloway, University of London (UK) 09/04/2019 •FPGA gateware design work flow Manoel Barros Marin BE-BI-BP FPGA gateware design work flow Project Specification Design Entry Behavioural Simulation Synthesis Functional Simulations (Post-Synthesis or Constraints Implementation Post-Implementation) (Physical & Timing) Static Timing Analysis Timing Simulation Bitstream Generation In-System & FPGA Programming ` Debugging 28 FPGA gateware design work flow Project Specification The rest of the design process is based on it!!! 29 FPGA gateware design work flow Project Specification The rest of the design process is based on it!!! 30 FPGA gateware design work flow Project Specification • Gather requirements from the users The rest of the design process is based on it!!! 31 FPGA gateware design work flow Project Specification • Gather requirements from the users The rest of the design process is based on it!!! • Specify: • Target application (General purpose or Specific) Example of General Purpose Gateware 32 FPGA gateware design work flow Project Specification • Gather requirements from the users The rest of the design process is based on it!!! • Specify: • Target application (General purpose or Specific) Example of Application Specific Gateware LEGEND uTCA shelf GLIB CLK 40MHz FPGA TTC FMC CLK 160MHz Downstream Upstream CDR GBT Serializer TTC /4 Optical TTC GBT TX MGT TX Decoder transceiver 160Mbps source AMC GBT Deserializer Readout Processor SFP+ PCIe DMA Logic GBT RX MGT RX Transceiver GBTx AMC Connector AMC PLL Recovered 4.8Gbps CLK 33 FPGA gateware design work flow Project Specification • Gather requirements from the users The rest of the design process is based on it!!! • Specify: • Target application (General purpose or Specific) • Main features (e.g. System bus, SoC, Multi-gigabit transceivers, etc.) Example of FPGA Architecture` 34 FPGA gateware design work flow Project Specification • Gather requirements from the users The rest of the design process is based on it!!! • Specify: • Target application (General purpose or Specific) • Main features (e.g. System bus, SoC, Multi-gigabit transceivers, etc.) • FPGA vendor (e.g. Xilinx, IntelFPGA (Altera), Microsemi (Actel), Lattice, etc.) Small FPGA vendors may target specific markets (e.g. Microsemi offers high reliable FPGAs, etc..) 35 FPGA gateware design work flow Project Specification • Gather requirements from the users The rest of the design process is based on it!!! • Specify: Example of COTS board (Xilinx Devkit) • Target
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