DIRECT TORQUE CONTROL OF RESONANT
INVERTER DRIVEN PERMANENT MAGNET
SYNCHRONOUS MOTOR
by
TIMOTHY P. DEVER
Submitted in partial fulfillment of the requirements
for the degree of Doctor of Philosophy
Department of Electrical Engineering and Computer Science
CASE WESTERN RESERVE UNIVERSITY
May, 2020 CASE WESTERN RESERVE UNIVERSITY
SCHOOL OF GRADUATE STUDIES
We hereby approve the dissertation of Timothy P. Dever
candidate for the degree of Doctor of Philosophy*.
Committee Chair Dr. Kenneth Loparo
Committee Member Dr. Cenk Cavusoglu
Committee Member Dr. Vira Chankong
Committee Member Dr. Wei Lin
Date of Defense
March 20, 2020
*We also certify that written approval has been obtained
for any proprietary material contained therein. Contents
List of Tables viii
List of Figures x
Acknowledgments xviii
Nomenclature xx
Abstract xxiv
1 Introduction 1 1.1 Motivation ...... 1 1.2 Approach ...... 4 1.3 Motors ...... 6 1.3.1 DC Motor ...... 6 1.3.2 Permanent Magnet Synchronous Motor ...... 8 1.4 Inverters ...... 9 1.4.1 Hard Switching Inverter ...... 10 1.4.1.1 Six Switch Inverter ...... 10 1.4.1.2 Six-Step Operation ...... 10 1.4.1.3 Sinusoidal PWM ...... 12 1.4.2 Resonant Inverter ...... 14
i CONTENTS
1.5 Motor Control Algorithms ...... 15 1.5.1 DC Motor Control ...... 16 1.5.2 PMSM Motor Control ...... 19 1.5.2.1 Open Loop Control ...... 19 1.5.2.2 Field Oriented Control ...... 20 1.5.2.3 Direct Torque Control ...... 23 1.6 Literature Review ...... 24 1.7 Focus and Contributions of the Research ...... 28 1.8 Organization ...... 29
2 Model Development 32 2.1 Motor Model ...... 33 2.2 Inverter Models ...... 37 2.2.1 Hard Switching Inverter Models ...... 38 2.2.1.1 Ideal HSI Model ...... 38 2.2.1.2 Simple HSI Model ...... 39 2.2.1.3 High Fidelity HSI Model ...... 42 2.2.2 Resonant DC Link Inverter Model ...... 43 2.3 Inner Loop/Motor Control Models ...... 44 2.3.1 Open Loop Control Model ...... 45 2.3.2 Field Oriented Control Model ...... 46 2.3.2.1 FOC Theory ...... 46 2.3.2.2 FOC Variable Conversion ...... 47 2.3.2.3 FOC Control Implementation ...... 49 2.3.3 Direct Torque Control Model ...... 51 2.3.3.1 DTC Theory ...... 52 2.3.3.2 DTC Variable Conversion ...... 53 2.3.3.3 DTC Control Implementation ...... 55
ii CONTENTS
2.4 Outer Loop/Speed Control Model ...... 60 2.5 Load Model ...... 61
3 Simulation Results 63 3.1 Complete System Simulations ...... 63 3.1.1 Open Loop Control System Simulation ...... 64 3.1.2 Field Oriented Control System Simulation ...... 65 3.1.3 Direct Torque Control System Simulation ...... 68 3.2 Resonant Inverter Simulations ...... 72
4 Inverter Development 74 4.1 Hard Switching Inverter Implementation ...... 75 4.2 Resonant Link Inverter (ACRLI) Design and Development ...... 77 4.2.1 Resonant Inverter Requirements ...... 79 4.2.2 Resonant Inverter Topology Selection ...... 80 4.2.3 ACRLI Design ...... 82 4.2.3.1 Resonant Circuit Design ...... 85 4.2.3.2 Main Switch Control Circuit ...... 93 4.2.3.3 Clamp Switch Control Circuit ...... 99 4.2.3.4 ACRLI Latch Design ...... 104 4.2.3.5 Current Predict Circuit ...... 106 4.2.3.6 Dead Time Circuit ...... 112 4.2.4 ACRLI Testing ...... 114 4.2.4.1 ACRLI Subsystem Assembly ...... 114 4.2.4.2 Test Load Build ...... 115 4.2.4.3 ACRLI Testing into Test Load ...... 115 4.2.4.4 Clamp Capacitor Sizing ...... 116 4.2.4.5 Measurement of Resonant Board Switching Currents 119
iii CONTENTS
4.2.4.6 Stray Inductance Modeling ...... 121 4.2.5 ACRLI Control Circuit Printed Circuit Board Design . . . . . 122
5 Motor Lab and Equipment 127 5.1 Motor Controller ...... 128 5.2 Interface Computer ...... 128 5.3 Inverter Subsystem ...... 129 5.4 Motor Under Test ...... 129 5.5 Motor Test Load ...... 130 5.6 Voltage Measurement System ...... 131 5.7 Support Equipment ...... 132 5.8 Assembled Motor Lab ...... 132
6 Baseline and Research System Development 134 6.1 Motor Parameter Measurement ...... 135 6.1.1 PMSM Motor Parameter Measurement ...... 135 6.1.2 Load Motor Parameter Measurement ...... 137 6.2 Hardware Checkout and Open Loop Operation ...... 138 6.3 Filter Design ...... 141 6.3.1 Input Power Filter ...... 141 6.3.2 Signal Filter Design ...... 141 6.4 Controller Transfer to Hardware ...... 142 6.5 FOC-HSI Implementation ...... 142 6.5.1 Initial FOC Setup ...... 143 6.5.2 FOC Tuning ...... 144 6.5.3 Parameter Validation Under FOC ...... 145 6.6 DTC Implementation and Improvements ...... 147 6.6.1 Implementation Approach and Goals ...... 147
iv CONTENTS
6.6.2 DTC Initial Work ...... 147 6.6.3 Flux and Torque Estimation Improvements ...... 152 6.6.3.1 Flux Estimation using Low Pass Filter as Integrator 153 6.6.3.2 Flux Estimation using LPF with Automatic Magni- tude and Phase Compensation ...... 155 6.6.3.3 Flux Estimation using Extended Kalman Filter . . . 159 6.6.3.4 Flux Estimation using Current Based Model . . . . 167 6.6.3.5 Flux Estimation Improvement - Conclusion . . . . . 168 6.6.4 DTC-HSI Performance Improvements ...... 169 6.6.4.1 Verification of Controller Code Operation ...... 170 6.6.4.2 Comparator Improvements ...... 177 6.6.4.3 Improved Current Sensing and Filtering ...... 179 6.6.4.4 DTC-HSI Performance Improvements - Summary . . 181 6.7 DTC-ARCLI Implementation ...... 183 6.8 Efficiency Measurements ...... 184
7 Results 186 7.1 Inverter Parameter Studies ...... 186 7.1.1 Resonance Frequency Unclamped ...... 187 7.1.2 Clamping Factor ...... 188 7.1.3 Resonance Current ...... 189 7.1.4 Resonance Frequency Clamped ...... 190
7.1.4.1 fr as a function of k ...... 190
7.1.4.2 fr as a function of IR ...... 193
7.1.4.3 fr as a function of fo ...... 197 7.1.5 Main Switch Voltage On ...... 197 7.2 Controller Parameter Studies ...... 200 7.2.1 Comparator Configurations ...... 200
v CONTENTS
7.2.1.1 Flux Comparator Configuration ...... 200 7.2.1.2 Torque Comparator Configuration ...... 201 7.2.2 Comparator Switching Limits ...... 204 7.2.2.1 Flux Comparator Switching Limits ...... 204 7.2.2.2 Torque Comparator Switching Limits ...... 206 7.2.3 Offset Angle ...... 206 7.2.4 Controller Loop Frequency ...... 208 7.2.5 Outer Loop Tuning ...... 208 7.3 Parameter Study - Conclusion ...... 209 7.4 System Efficiency Measurements ...... 210 7.4.1 ZVS Verification ...... 210 7.4.1.1 Main Switch Inverter ZVS ...... 210 7.4.1.2 Clamp Switch ZVS ...... 211 7.4.1.3 Six Switch Inverter ZVS ...... 212 7.4.2 Efficiency Comparison vs. Baseline ...... 215 7.5 System Noise Measurements ...... 216 7.5.1 Input Current Noise vs. Baseline ...... 217 7.5.2 Motor Phase Current Noise vs. Baseline ...... 219 7.5.3 Motor Phase Voltage Noise vs. Baseline ...... 220 7.5.4 Noise Comparison Summary ...... 222
8 Conclusions 224 8.1 Contributions of This Work ...... 224 8.2 Future Work ...... 226
A Motor Parameters 228
B Resonant Circuit Design Code 229
vi CONTENTS
C Resonant Inverter Schematics 231
D Voltage Measurement Circuit 239
E Data Sheets 241
Bibliography 242
vii List of Tables
2.1 Allowable HSI switch configurations and resulting voltages (x VDC ) . 40 2.2 Inner loop variable summary ...... 45 2.3 Voltage Vector Selection ...... 60
4.1 General Inverter Requirements ...... 75 4.2 Resonant Inverter Requirements ...... 79 4.3 Resonant Inverter Parameters ...... 90 4.4 Loss table at resonant circuit design point ...... 91 4.5 Switch states and predicted six switch inverter input currents . . . . . 108 4.6 Dead Time Component Testing ...... 113 4.7 ACRLI PCB Control Board Connectors ...... 125
6.1 Model Validation Results ...... 146 6.2 DTC Voltage Vector Test ...... 149 6.3 Manual magnitude and phase correction test ...... 155 6.4 Flux Estimation Method Comparison ...... 168 6.5 Sector Definition ...... 171 6.6 Voltage Vector Selection ...... 174
7.1 ACRLI PCB Adjustment Resistors ...... 187 7.2 Unclamped Resonant Frequencies ...... 188 7.3 Noise Measurements Summary: FOC-HSI vs. DTC-ACRLI ...... 217
viii LIST OF TABLES
A.1 PMSM Motor Parameters ...... 228 A.2 Load Motor Parameters ...... 228
C.1 ACRLI Schematic List ...... 231
ix List of Figures
1.1 Electrified aircraft system configurations...... 3 1.2 Notional Hybrid Electric Aircraft System...... 4 1.3 Schematic of a DC machine...... 7 1.4 Schematic of a PMSM...... 8 1.5 Voltage Source Inverter...... 11 1.6 HSI inverter with wye-connected load...... 11 1.7 Switching of inverter under sinusoidal PWM control...... 13 1.8 Resonant link DC inverter...... 15 1.9 Actively clamped DC link inverter...... 16 1.10 Separately excited DC motor and field orientation...... 17 1.11 Schematic and field orientation of PMDC motor...... 18 1.12 Volts/Hz control of multiple synchronous motors...... 20 1.13 Induction motor FOC implementation and field orientation...... 23 1.14 Pole Commutated Inverter (PCI)...... 25 1.15 BRDCL (left) and PRDCL inverters...... 26 1.16 Quasi-resonant RDCL (QRDCL) inverter with active clamp...... 26
2.1 Schematic of system under test...... 32 2.2 System components to be modeled...... 33 2.3 Two Phase PMSM...... 34
x LIST OF FIGURES
2.4 Complete PMSM model...... 38 2.5 HSI inverter with wye-connected load...... 39 2.6 HSI inverter model...... 41 2.7 High fidelity HSI model...... 42 2.8 Resonant circuit model...... 43 2.9 Motor control (inner loop) components...... 44 2.10 Schematic of open loop (V/Hz) controller...... 45 2.11 FOC variable conversion block...... 47 2.12 Clarke transform...... 48 2.13 Park transform...... 49 2.14 FOC control block...... 50 2.15 DTC stator flux vector trajectory...... 53 2.16 DTC variable conversion block...... 54 2.17 DTC Control Block...... 56 2.18 DTC flux comparator function block...... 58 2.19 DTC torque comparator function block...... 58 2.20 Inverter voltage vectors and flux vector change when applied in time ∆t. 59 2.21 Outer (speed) loop model...... 60 2.22 Test load schematic...... 61
3.1 Open loop V/Hz block structure...... 64 3.2 Open loop simulation output...... 65 3.3 Idc and switch commands under FOC using simple HSI inverter model. 66 3.4 FOC System Simulation: line voltage with different inverter models. . 67 3.5 FOC System Simulation: phase current with different inverter models. 68 3.6 DTC system simulation analysis plot...... 69 3.7 Simulated stator flux linkage estimation plots...... 70 3.8 DTC simulated phase current comparison...... 71
xi LIST OF FIGURES
3.9 DTC estimated angle simulation using EKF...... 71 3.10 DTC system simulation phase current...... 72
4.1 Inverter Subsystem within Motor Lab...... 75 4.2 HSI High Level Schematic...... 76 4.3 Schematic of six switch inverter power stage...... 77 4.4 HSI subsystem...... 78 4.5 Voltage Sense Subsystem...... 79 4.6 Soft Switching Converter Topologies...... 81 4.7 ACRLI Schematic...... 83 4.8 ACRLI High Level Schematic...... 84 4.9 Resonant Circuit Board schematic...... 85 4.10 Ratio of clamped to unclamped frequency versus k...... 87
4.11 Loss plot as a function of Lr...... 90 4.12 Final resonant circuit design schematic...... 93 4.13 Main switch and resonant components...... 94 4.14 Main Switch Control power components simulation...... 95 4.15 Main Switch Control operation...... 95 4.16 Main Switch Control initial test setup...... 97 4.17 Main Switch Control initial testing...... 97 4.18 Main Switch Control high level schematic...... 98 4.19 Main Switch Control hardware test...... 98 4.20 Schematic of the resonant board, including the clamp switch and clamp capacitor...... 99 4.21 Clamp Switch Control power components closed loop simulation. . . . 100 4.22 Clamp Switch Control operation...... 101 4.23 Clamp Switch Control high level schematic...... 102 4.24 Clamp Switch and Main Switch Control Test Setup...... 102
xii LIST OF FIGURES
4.25 Clamp Switch Control hardware Test...... 103 4.26 Brass Board Resonant Circuit Board...... 103 4.27 Brass Board Main and Clamp Control circuits...... 103 4.28 High Level Schematic of ACRLI Latch...... 104 4.29 Schematic of single channel two stage ARCLI Latch design test circuit 105 4.30 Single channel two stage test circuit for ARCLI Latch design...... 105 4.31 Oscilloscope output, ACRLI Latch design test circuit, clocked at 1 kHz (left) and 200 kHz...... 106 4.32 Full Three-channel ACRLI Latch breadboard circuit...... 106 4.33 Example current prediction schematic...... 107 4.34 Current Predict High Level Schematic...... 108 4.35 PSIM model used for current predict testing...... 109 4.36 Current Predict simulation output...... 110 4.37 Breadboard Current Predict Circuit...... 111 4.38 Current Predict circuit test on motor...... 111 4.39 High level schematic, single channel of Dead Time Circuit ...... 112 4.40 Dead Time Circuit Test Timing...... 113 4.41 Assembled ACRLI prototype subsystems test configuration...... 115 4.42 Schematic of ACRLI test load...... 116 4.43 ACRLI test load...... 116 4.44 RDCL measured line voltages into test load...... 117 4.45 RDCL measured phase currents into test load...... 117 4.46 Simulation with constant I∗...... 118 4.47 Simulation of link current reversal...... 118
4.48 VLINK with different clamp capacitance...... 119 4.49 Simulated RDCL switch currents...... 120
4.50 Resonant board with SM (left) and SC current measurement loops added.121
xiii LIST OF FIGURES
4.51 Clamp switch current and link voltage...... 122
4.52 Main switch current at three levels of IR...... 123 4.53 Resonant circuit with labeled currents...... 124 4.54 Simulated (left) and measured source current...... 124 4.55 Simulated source current with added stray inductance...... 125 4.56 PCB ACRLI control circuit functional layout...... 125 4.57 PCB ACRLI control circuit...... 126
5.1 Schematic of motor lab...... 127 5.2 Motor Controller control panel GUI...... 129 5.3 Motor control and interface computers on work bench...... 130 5.4 Test load schematic...... 130 5.5 Voltage measurement system high level schematic...... 131 5.6 Photo of motor lab...... 133
6.1 PMSM back emf measurement...... 136 6.2 Plot of PMSM back emf vs. speed...... 136 6.3 Load motor back emf...... 137 6.4 Load motor blocked rotor test plot...... 138 6.5 Schematic of motor lab...... 138 6.6 Schematic of open loop (V/Hz) controller...... 139 6.7 Generated and measured angles open loop control...... 140 6.8 Diagram of combined motor controller...... 143 6.9 Outer loop tuning...... 144 6.10 Simulation and hardware line-line voltages at 1000 rpm...... 145 6.11 Simulation and hardware phase currents at 1000 rpm...... 146 6.12 DTC stator flux vector trajectory...... 148 6.13 Inverter voltage vectors and flux vector change when applied in time ∆t.149
xiv LIST OF FIGURES
6.14 Plot of commanded and actual speed, and torque command...... 150 6.15 Estimated stator flux linkage oscilloscope trace...... 151 6.16 Estimated stator flux linkage live on GUI screen...... 152 6.17 Low pass filter and integrator bode plots...... 154 6.18 Flux estimator LPF model...... 156 6.19 Magnitude and phase correction implementation...... 157
6.20 Magnitude and phase correction at selected fc ...... 158 6.21 EKF tuning simulation on FOC-HSI model...... 162 6.22 EKF simulation with incorrect tuning...... 164 6.23 EKF simulation after tuning...... 165 6.24 DTC control block diagram...... 171 6.25 DTC Controller electrical angle and calculated sector...... 172 6.26 DTC torque comparator function block...... 172 6.27 DTC torque comparator operation...... 173 6.28 DTC flux comparator function block...... 174 6.29 DTC flux comparator operation...... 175 6.30 DTC voltage vector selection test plot...... 176 6.31 DTC and post-processed torque estimate comparison...... 177 6.32 Takahashi (left) and quantized torque comparators...... 178 6.33 Torque estimate comparison with Takahashi and quantized comparators.179 6.34 Signal filter schematic...... 180 6.35 Installed current signal filter...... 180 6.36 DTC estimated and commanded torque before and after improvements. 182 6.37 DTC-HSI-PMSM phase currents before (left) and after improvements. 183 6.38 DTC-HSI-PMSM efficiency improvement summary...... 184 6.39 Inverter efficiency measurements...... 185
7.1 Clamp Switch Control high level schematic...... 188
xv LIST OF FIGURES
7.2 Main Switch Control high level schematic...... 189 7.3 Link voltages at varying clamping factors...... 191 7.4 Clamp switch currents at varying clamping factors...... 192 7.5 Link voltages at varying at constant clamp voltage...... 193
7.6 Clamped resonance frequency vs. k at varying IR...... 194
7.7 DC power vs. IR...... 194
7.8 Resonant link voltage with varying IR...... 195
7.9 Clamped resonance frequency vs. IR at 600 rpm...... 195
7.10 Clamp switch current with varying IR...... 196
7.11 System input power vs. IR...... 196
7.12 Clamped resonance frequency vs. k at varying fo...... 197
7.13 Main switch currents with varying V0ref ...... 199
7.14 Link voltage with varying V0ref ...... 199 7.15 DTC flux switch configuration - two-level hysteresis comparator. . . . 200 7.16 DTC torque switch configuration 1: Takahashi three-level hysteresis comparator...... 201 7.17 DTC torque switch configuration 2: two-level quantized comparator. . 202 7.18 Link power with different torque comparators...... 202 7.19 Clamp switch current with different torque comparators...... 203 7.20 Phase and commanded currents with different torque comparators. . . 203 7.21 Stator flux linkage estimate before improvements...... 205 7.22 Stator flux linkage estimates at varying flux comparator switch levels. 205 7.23 DC input power with varying torque comparator switch levels. . . . . 206 7.24 Phase voltage and current under FOC-HSI (left) and DTC-ACRLI MPTA control...... 207 7.25 Main switch current and voltage...... 211 7.26 Clamp switch current and voltage...... 212
xvi LIST OF FIGURES
7.27 Six switch inverter timing...... 213 7.28 Six switch inverter incorrect timing example...... 214 7.29 Efficiency comparison between baseline and test system...... 215 7.30 Input current comparison at 600 rpm...... 218 7.31 Input current spectra at 600 rpm...... 218 7.32 Phase current comparison at 600 rpm...... 219 7.33 Phase current comparison at 600 rpm...... 219 7.34 Phase current spectra at 600 rpm...... 220 7.35 Phase voltage comparison at 600 rpm...... 221 7.36 Phase voltage comparison at 600 rpm...... 221 7.37 Phase voltage spectra at 600 rpm...... 222
B.1 Resonant component design script...... 230
C.1 ACRLI interconnects...... 232 C.2 ACRLI Resonant circuit board...... 233 C.3 ACRLI main switch control circuit...... 234 C.4 ACRLI clamp switch control circuit...... 235 C.5 ACRLI current predict circuit...... 236 C.6 ACRLI latching circuit...... 237 C.7 ACRLI dead time circuit...... 238
D.1 ACRLI dead time circuit...... 240
xvii Acknowledgments
I would like to thank Professor Loparo for his guidance and support throughout this effort. He was helpful and supportive not only with the technical challenges, but also with the challenges facing a non-traditional student working from a remote location. I have also had great support from the NASA team. I am especially grateful for the contributions of the technical team, Dr. Peter Kascak and Ralph Jansen; their assistance has been crucial, from the initial selection of a relevant research topic through the final reviews of results. I would also like to thank the program leaders who supported this effort, including Dr. Rub´enDel Rosario, Amy Jankovsky, and again Ralph Jansen. My leadership team has also been very helpful. I would like to especially thank my immediate supervisor, John Thomas, for his guidance and advice from the very beginning of this effort, as well as the division leadership, notably Rob Button, Randy Furnas, Jim Soeder, and Kevin Carmichael. Additionally, I am grate- ful for the technical expertise of Keith Hunker, the assistance and equipment loans from Dave Sadey, Linda Taylor, and Mike Kussmaul, the electronics help from Dave Hausser, the excellent and timely PCB layout contributions of Susanah Kowalewski and Wes Miller, and the thorough proofreading of this document by Therese Griebel. Finally, without the power electronics mentoring provided by Art Birchenough this work would have suffered greatly; his advice was extremely helpful and is much ap- preciated. Lastly, I’d like to thank my wife Joyce, who has been very supportive, lending
xviii ACKNOWLEDGMENTS an ear and cheerfully and efficiently picking up extra tasks I’ve missed during the long hours required to complete this effort; and our children, who have been very helpful as well, their understanding and sense of humor always appreciated. And I would especially like to thank my parents for placing such a consistent and relentless emphasis on the importance of education from our earliest years; for enabling the educational goals of my siblings and me; and for keeping us all on track.
xix Nomenclature
Symbol Definition ACRLI active clamped resonant DC link inverter B motor friction BDC brushed DC motor BLDC brushless DC motor BRDCL basic resonant DC link
Cc clamp capacitance
Cr resonant capacitor DTC direct torque control EAP electrified aircraft propulsion EKF extended Kalman filter ESR equivalent series resistance
fc low pass filter corner frequency
fr clamped circuit resonance frequency
fo resonance frequency, ideal resonant circuit FOC field oriented control HSI hard switching inverter
Hψ limit of flux hysteresis comparator
HT limit of torque hysteresis comparator
Ia armature current
id rotor reference frame d axis current
xx CHAPTER 0. NOMENCLATURE
Symbol Definition
If field current
iq rotor reference frame q axis current
IR resonant current
iα orthogonal stationary reference frame current α
iβ orthogonal stationary reference frame current β
Ilink link current
ILr resonant inductor current
ISC clamp switch current
ISM main switch current
ISRC source current I∗ commanded current k clamping constant KPP key performance parameter
KV back emf constant
KT torque constant
i~s stator current space vector J combined moment of inertia of motor and load
SABC L1 command latched after receipt of new output signal
SABC L2 command latched after receipt of zero link voltage signal
Ld direct axis stator self inductance in rotor reference frame
Lq quadrature axis stator self inductance in rotor reference frame
Lr resonant inductor M mutual inductance between the q- and d- axis windings MPTA maximum torque per amp MUT motor under test d p differential operator dt
xxi CHAPTER 0. NOMENCLATURE
Symbol Definition P number of pole pairs PCI pole commutated inverter
Pcond−main main device conduction losses
Psw−main main device switching losses
Pcond−clamp clamp device conduction losses
Psw−clamp clamp device switching losses
Pesr resonant component equivalent series resistance (ESR) losses PRDCL parallel resonant DC link inverter PMSM permanent magnet synchronous motor PWM pulse width modulation QRDCL quasi-resonant DC link inverter RDCL resonant DC link inverter
Rs stator resistance
Sc clamp switch
Sm main switch SM synchronous machine
toff device turn off time
TL load torque T ∗ torque command Tˆ controller estimated torque real time ˆ Tpost post processed torque estimate
Vclamp clamping voltage value V/Hz Volts/Hz open loop control approach
Vlink link voltage
V0ref zero voltage link reference value
VLS−0 scaled link voltage measurement
xxii CHAPTER 0. NOMENCLATURE
Symbol Definition
VLS−k scaled link voltage for clamp circuit VR variable resistor adjustments in ACRLI (1-5)
vd rotor reference frame d-axis voltage
vq rotor reference frame q-axis voltage
VFW forward drop across main switches and diodes ~ Vs stator voltage space vector ~ Vn inverter voltage vectors (n = 0-7) VSI voltage source inverter ZVS zero voltage switching
∆Vcl voltage rise during clamping
ωe electrical speed ω mechanical speed
ψa armature flux
ψα quadrature stationary reference frame flux linkage α component
ψβ quadrature stationary reference frame flux linkage β component ~ ψs stator flux vector
ψF PMSM stator flux linkage due to permanent magnets
ψds stator d-axis stator flux linkage
ψqs stator q-axis stator flux linkage ψ∗ flux command ˆ ψpost post processed flux estimate ψˆ real time flux estimate θ rotor mechanical position
θe rotor position in electrical degrees
xxiii Direct Torque Control of Resonant Inverter Driven Permanent Magnet Synchronous Motor
Abstract by TIMOTHY P. DEVER
A motor drive system implementing direct torque control (DTC) and a resonant link inverter to drive a permanent magnet synchronous motor (PMSM) is designed, built, tested, and analyzed, and performance is compared to a standard drive system using field oriented control (FOC) and a hard switching inverter (HSI). Models and simula- tions of both systems are developed and presented. Simulations and design, build, and testing of the selected resonant inverter topology, the active clamped resonant link inverter (ACRLI), are discussed. A description of the specification and buildup of the motor lab for this effort, including the motor controller implementation, the motor under test, the test load, and support equipment is also provided. DTC performance improvement efforts are discussed, including the implementation of multiple flux and torque estimation schemes. Experimental results on the research system, the DTC- ACRLI, studying the effects of inverter and controller parameters on performance, are discussed. Comparisons of two key system performance metrics (system efficiency and noise) between the baseline FOC-HSI system and the research DTC-ACRLI sys- tem are presented. Conclusions, contributions of the work, and suggested areas for future work are also discussed.
xxiv Chapter 1
Introduction
This chapter first provides a discussion of the motivation for and approach taken for this research effort. Next, an overview of three key technology elements, motors, inverters, and motor control algorithms, is provided. Literature review results are then presented, along with the focus and contributions of the research. Finally, the organization of this document is presented.
1.1 Motivation
In response to expected increases in aviation traffic and environmental concerns, NASA is working to improve aircraft performance, and has identified specific goals targeting the reduction of aircraft fuel burn, emissions, and noise. These goals are quite aggressive, and meeting them will require a fundamental shift in approach to aircraft and engine design. One such approach is called Electrified Aircraft Propul- sion (EAP), which is the use of electric motors to drive the aircraft propellers or fans. This approach can be applied to multiple vehicle architectures, including conventional tube and wing aircraft as well as a blended wing-body aircraft. A number of possible advantages of the EAP approach have been identified. De- coupling of the power producing device from the propulsive device is the largest
1 CHAPTER 1. INTRODUCTION change from the current aircraft vehicle/engine architecture; under EAP turbine en- gine driven generators and the electric motor driven fans are able to be placed at optimum locations in the aircraft, maximizing vehicle performance. The increased effective engine bypass ratio (defined as the ratio of mass flow through all fans to the mass flow through the turbogenerators) provided by this approach will enable improved fuel efficiency. Also, this will enable larger fan area integration into the air- craft, as many smaller fans are easier to incorporate into an aircraft than fewer, large diameter fans of equal area. Additionally, this configuration allows the power turbine to be run independent of the fan shaft, allowing both to run at optimal speeds - direct coupling in the past has forced settling on a sub-optimal trade. Additional potential benefits of this approach include higher propulsive efficiency due to boundary layer ingestion (BLI) drag reduction by pulling lower velocity air near the airframe into the propulsors, minimal engine core jet noise, symmetric thrust capability in the event of a turbine engine or generator failure, asymmetric fan thrust for yaw control, the pos- sibility of larger, more efficient turbomachinery, very low community noise, increased safety, lower wing structure weight, low cabin noise, and easier maintenance access [1]. Implementation of the EAP approach will require a number of new components to be inserted into the aircraft propulsive drive train, including electric generators, rectifiers, distribution wiring, switch gear, inverters, and electric motors. Inclusion of these additional components will add weight to vehicle and require additional fuel burn, which would subtract from the desired benefits. Thus in order to result in a successful system, the electrical system cannot be too heavy or too inefficient. Al- though conventional solid-state switching power converters are acceptable for ground applications, improvement is required to achieve the efficiency and weight require- ments for an electrified aircraft propulsion system. A typical efficiency of a switching inverter is too low for this application; for example, a power loss of 5% would require
2 CHAPTER 1. INTRODUCTION the rejection of megawatts of heat in a large aircraft application, which would negate a large fraction of the expected fuel-saving benefit [2]. Many configurations EAP aircraft can be postulated, and thus a wide trade space for electric drive configurations exists. A few configurations are shown in Figure 1.1.
Figure 1.1: Electrified aircraft system configurations.
A specific electrified aircraft configuration has not been selected, however, a no- tional diagram of a system employing a combination of turbine driven generators and batteries for energy storage can be drawn (Figure 1.2). This diagram is intended to represent a generic electric aircraft system, including all relevant functions. In the electrified aircraft propulsion system the number of motor driven fans used could vary; some proposed configurations employ 10 or more motors. In order to compare system benefits and guide selections for the electrified aircraft development, two key performance parameters (KPPs) have been defined for the electrical system (dashed box, Figure 1.2). These two key parameters, crucial to optimizing system performance, are specific power and efficiency. Specific power is defined as the ratio of the rated power to the mass of the system, and efficiency is the ratio of the output power to the input power of the system [3]. The motors required for these proposed EAP aircraft are quite large, in the 1-
3 CHAPTER 1. INTRODUCTION
Figure 1.2: Notional Hybrid Electric Aircraft System.
10 MW range. The weight of the motor itself is an issue, as is the weight of the affiliated systems. Motor drive electronics are a significant portion of the system weight; any increase in power density and efficiency of the inverters will be helpful in reducing aircraft weight. As typical industrial motor drive systems do not have the demanding requirements needed for hybrid electric aircraft, this high efficiency drive approach has not been required or pursued for existing applications, leaving improvement opportunities. The purpose of this work is to research these potential improvements in the drives area; specifically, by investigating alternate configurations in the inverter system which drives the propulsor motors.
1.2 Approach
Past experience with NASA advanced motor drive applications has been using voltage fed, hard switching inverters, and field oriented control (FOC) [4] [5] [6]. This is a common approach, and is typical in many trade studies in the electrified aircraft propulsion area. The goal of this dissertation is to investigate improved drive efficiency and power density through changing both the inverter type and the control approach to a unique configuration: a resonant DC link inverter driven via direct torque control. A resonant link enables soft switching, an improvement over traditional hard
4 CHAPTER 1. INTRODUCTION switching inverters. Soft switching brings many benefits, and the selected config- uration works well with a DC input; a DC bus is typical of many electric aircraft ar- chitectures currently under study at NASA. The hard-switched mode in which most conventional motor drives operate increases losses, and also generates considerable device stresses, reducing reliability of both the inverter devices and the motor. Soft switching can reduce these stresses, and also enable higher switch frequencies, which can reduce electromagnetic interference (EMI) as well as harmonic distortion, and also significantly reduce the size and the weight of the magnetic and filter components [7]. However, one consequence of a resonant link is that in order to take advantage of the soft switching, the inverter can only switch states at discrete switch times deter- mined by the behavior of the resonant circuit. This means that the traditional PWM techniques, such as those used in FOC, cannot be used. In order to circumvent this, more complicated resonant inverter schemes, e.g. a quasi-resonant scheme, may be used; however, these schemes are more complicated than the resonant link, poten- tially increasing cost and decreasing reliability through the required additional parts and more complicated control apparatus [8]. Direct torque control (DTC) is a newer control scheme than FOC. It was selected for this study in the hopes that it will pair well with a resonant link, as the DTC scheme is inherently discrete, switching only at regular intervals. Additionally, DTC has a number of potential advantages over FOC, including faster dynamic response, reduced sensitivity to motor parameters, reduced requirement for sensors, and re- duced complexity, and thus potentially reduced loop time, through the elimination of coordinate transformations, the current loops, and the PWM scheme [9]. There are many additional potential benefits to the proposed configuration, which can be grouped into three major categories: increased efficiency and increased power density (both KPPs), and general performance improvement. Increased efficiency is driven by the lower switching losses provided by the resonant converter; increased
5 CHAPTER 1. INTRODUCTION power density (reduced weight) is achieved through reduced filter requirements, lower cooling requirements, and smaller switches; and general performance improvements include reduced switch stresses (enabling longer-life components and motor windings), improved EMI and harmonic distortion, increased flexibility/reduced programmatic risk (the final electric aircraft motor configuration is not yet known; this approach will work on a number of motor configurations including schemes with lower induc- tance), and improved speed/torque control performance. The proposed goal of the dissertation will be to research these potential benefits.
1.3 Motors
Two types of motor are used in this dissertation lab setup. They are a DC motor, and a permanent magnet synchronous motor. The following sections discuss the configuration of each of these motors, some relevant history, their operation, and merits relative to this work.
1.3.1 DC Motor
DC motors have been used in industry for over 100 years. They are versatile, able to work in a variety of desirable configurations, and are easily controlled [10]. Although the development of modern power electronic drive systems has enabled the replace- ment of them with AC machines, it is still worth discussing DC machines for several reasons. Firstly, the operation of the DC machine is helpful as a reference point in understanding AC machine control; and secondly, the DC machine does still have some applications - a DC machine is used as the load motor used to test the motor under test in this dissertation. A schematic of a DC motor is shown in Figure 1.3. The stationary portion, or stator, has field poles which are excited by direct current to generate the field along the
6 CHAPTER 1. INTRODUCTION direct axis. In permanent magnet (PM) DC machines, this field is supplied by PMs. The rotating portion of the motor, or rotor (the power conversion member, also called the armature) is wrapped in a winding through which current flows. The current to the armature winding is supplied via a switching action performed by brushes and the commutator. This switching is designed to keep the spatial orientation of the armature current in place, independent of the position or the speed of the armature [11]. This switching ensures that the armature magnetic field is aligned along the quadrature axis, 90 electrical degrees away from the direct axis; thus field orientation between rotor and stator in the DC motor is provided through mechanical means.
Figure 1.3: Schematic of a DC machine.
The DC motor has a number of advantages; however, the mechanical commuta- tor and brush assembly cause performance and maintenance issues. For example, sparking at the commutator causes wear which impedes performance, and thus the machines require maintenance, making them much more costly than their AC replace- ments over their life cycle.
7 CHAPTER 1. INTRODUCTION
1.3.2 Permanent Magnet Synchronous Motor
Synchronous machines (SMs) are AC machines whose steady state speed is propor- tional to the frequency of the armature current. There are a number of differences between SM and DC machines. The SM armature is typically located on the stator (opposed to the rotor, on the DC machine), and unlike the single phase DC machine, the SM armature has a three phase winding. The SM field is also reversed as opposed to the DC machine, located on the rotor. As with the DC machine, the field can be provided by a field current or by magnets; the latter version is called a permanent magnet synchronous machine, or PMSM. A schematic diagram of a PMSM is shown in Figure 1.4.
Figure 1.4: Schematic of a PMSM.
AC PM machines are often called brushless motors or brushless DC (BLDC)motors. This can cause some confusion, as the input to the motor must be AC in order for the motor to perform. There are several reasons for this nomenclature; when combined with a drive system, the performance of these motors is similar to that of DC motors; and, due to the reversed armature and field locations, these motors can be seen as inside-out DC motors, with the field rotating, and commutation provided via drive
8 CHAPTER 1. INTRODUCTION electronics to the stator [10]. Often in the literature PMSM refers to a machine with a sinusoidal back emf, whereas BLDC refers to a machine with a trapezoidal back emf. PM machines have advantages over their wound-field counterparts in that the electromagnetic field poles are no longer required for the PM machine, requiring less power and resulting in a smaller machine. And the AC version, the PMSM, does not require the brushes and commutator assembly of the DC machine, thereby eliminating the associated hardware and maintenance issues. Also, since the location of the armature on the stator enables superior performance, this configuration allows better cooling, and, because the additional space allows for extra insulation, higher applied voltages are possible [12]. Of course, in these machines stator and rotor field orientation is no longer ensured mechanically; commutation is now performed outside of the motor, in the motor control and drive electronics, and field alignment must be performed within the drive system. As discussed previously, the key performance parameters for the EAP application are efficiency and power density. PMSM machines promise both high efficiency and high power density, and were selected for study in this dissertation because of these advantages.
1.4 Inverters
Converters which change DC to AC are called inverters. The inverter performs the actions of the commutator in a DC motor, converting a DC voltage bus into a three- phase AC voltage at the motor terminals, while providing control of the supplied output voltage and frequency. Inverters are commonly used in variable speed AC motor drives, and also have many other applications in industry, for example renew- able energy, transportation, induction heating, and uninterruptable power supplies
9 CHAPTER 1. INTRODUCTION
[13]. Two types of inverter are discussed in this dissertation: the hard switching inverter and the resonant inverter; both are described below.
1.4.1 Hard Switching Inverter
The voltage source inverter (VSI) is commonly used in motor control systems. The VSI is a hard-switching inverter (HSI), that is, the non-ideal switching implementa- tion used in this inverter type results in power lost in the inverter switches. In this section, a typical inverter called the six-switch inverter is described, as are two com- mon strategies used for inverter control in motor drive applications: six-step operation and sinusoidal pulse width modulation (PWM).
1.4.1.1 Six Switch Inverter
A typical three phase HSI system is shown in Figure 1.5. It consists of six transistors T1-T6, along with six diodes, a DC supply, and an input capacitor. The switches used are power semiconductor devices, e.g. IGBTs or MOSFETs. The capacitor is used to ensure that the DC bus voltage remains constant, and the diodes are placed in antiparallel with each switch to allow current to flow in the negative direction across each switch, so that each output terminal is connected to an input terminal regardless of the current direction. With six switches, 64 switch configurations are possible; however, most configurations are unused. Typically the switches in each leg are operated in pairs, with one always on and the other always off; e.g. when the upper switch in leg a (T1) is on, the lower switch in that leg (T4) is off, and vice versa.
1.4.1.2 Six-Step Operation
Six-step operation is a relatively simple implementation of the HSI as a motor driver. A simplified version of the HSI schematic to be used in the six-step operation analysis,
10 CHAPTER 1. INTRODUCTION
Figure 1.5: Voltage Source Inverter. including a wye-connected load, is shown in Figure 1.6.
Figure 1.6: HSI inverter with wye-connected load.
In six-step operation, each switch in the inverter has a 50% duty cycle (is on half of the time), and the switching action occurs every 60 degrees, or every 1/6th of the output waveform period. As was mentioned above, the switches in each leg open and close opposite of each other, for good reason: if both switches in a leg are off at the same time, the corresponding motor terminal voltage is indeterminate; and if both switches in a leg are on at the same time, a short circuit is created across the DC bus
11 CHAPTER 1. INTRODUCTION
[14]. The switching scheme is named for the six steps in the generated line to neutral voltage output waveform. This control scheme has been successfully implemented in industrial motor drive systems; one of the earliest AC motor drives provided variable frequency control for an induction machine using a six-step HSI. However, development of improved switching transistors has allowed replacement of six-step HSI systems with PWM based inverter drives, allowing significant control improvement [11].
1.4.1.3 Sinusoidal PWM
The six-step inverter scheme has several advantages: the control method is simple, and since only six switchings are required per period of the fundamental frequency, the switching losses are very low. However, this scheme also has several disadvantages: while the six-step approach can successfully control the output frequency, the output voltage cannot be controlled without changing the DC bus voltage. Also, bulky low-pass filters need to be included in the system to diminish the lower harmonics generated by the six-step implementation [15]. Pulse width modulated (PWM) techniques provide an improvement over the six- step approach, enabling control of the output voltage amplitude as well as frequency, and reduced harmonics resulting in reduced filter requirements. The same three phase inverter used in the six-step discussion is used for sinusoidal PWM scheme. Referring to Figure 1.7, the switches in each leg are again controlled in pairs. Here each switch pair receives a reference wave, depicted by the three sinusoids in the top plot (red, green, blue); in order to generate balanced three phase output voltages, these reference waves are sinusoids set 120◦ apart. Switching timing is created by comparing these reference waves to a triangular carrier wave (black); in this example the carrier wave frequency is intentionally set low for illustration purposes. In each leg, the top switch is turned on (and the bottom switch is off) when its reference voltage waveform is
12 CHAPTER 1. INTRODUCTION
higher than the carrier, and its lower switch is on (and the top switch is off) when the reference is lower than the carrier [14].
Figure 1.7: Switching of inverter under sinusoidal PWM control.
The amplitude modulation ratio (Ma) is the ratio of the reference signal amplitude and the carrier signal amplitude:
Ma = Vreference amplitude/Vcarrier amplitude (1.1)
If Ma is less than or equal to 1.0, the amplitude of the output voltage fundamental is proportional to the DC bus supply voltage, allowing output voltage to be controlled.
The frequency modulation ratio (Mf ) is the ratio of the carrier frequency and the reference signal frequency:
Mf = Fcarrier/Freference = Ftriangle/Fsine (1.2)
Increasing the carrier frequency will increase Mf, which increase the frequencies of the generated harmonics.
13 CHAPTER 1. INTRODUCTION
1.4.2 Resonant Inverter
Ideally, a switch absorbs zero power: an ideal open switch carries no current, and an ideal closed switch has zero voltage drop; thus the power absorbed by the switch is zero. However, switching in a real device is imperfect; during a transition both voltage and current can be nonzero at the same time, resulting in power absorbed in the switching device. This imperfect switching is a significant source of power loss in converters, and these losses increase with switching frequency. Resonant converters minimize or prevent this overlap of voltage and current during the transitions by switching when voltage and/or current is zero, ideally eliminating switching losses. This is called soft switching, in contrast to the hard switching which is implemented in the HSI inverter [14]. Many different resonant inverter configurations are possible. These configurations can be divided into two categories, AC link and DC link types. AC link inverters of many classifications exist; however, they are not considered as the present project employs a DC link. DC links can also be divided into multiple categories, namely voltage fed resonant link DC, current fed resonant link DC, and resonant pole DC inverters [15]. The selected configuration for this application would ideally build upon our team‘s significant experience with the HSI inverter, require minimal additional parts over the HSI, and require a relatively simple control scheme. Based on these criteria, the selected configuration is the resonant link DC inverter, shown in Figure 1.8. Note that the selected configuration meets the above criteria. Its design is an add- on to a HSI, developed by placing an L-C resonant circuit between the DC bus and the inverter, thus capitalizing on the team HSI experience; a minimum of additional parts is required, as only three added components are employed beyond the standard
14 CHAPTER 1. INTRODUCTION
Figure 1.8: Resonant link DC inverter.
HSI circuit; the structure is simple, with only one resonant circuit per system; and the control is also relatively simple. The resonant link DC inverter (RDCL) concept is intended to force the bus to oscillate at a high frequency causing the bus voltage to go through periodic zero crossings. This sets up the opportunity for zero voltage switching conditions for any devices connected across the bus [16]. One drawback to this approach is that the resonant action of the LC elements can cause the link voltage to rise to more than double the DC bus voltage, imparting voltage stresses on the inverter components. One solution to this problem is to limit this voltage overshoot via the addition of a voltage clamp to the RDCL; this amounts to the addition of a switch and capacitor to the circuit, as seen in Figure 1.9. With this active voltage clamp, it is possible to reduce the device voltage stresses from approximately 2.5 times the DC bus voltage down to 120-140% DC bus voltage [17].
1.5 Motor Control Algorithms
Two separate motor types are employed in this effort: a brushed DC (BDC) motor, and a permanent magnet synchronous motor (PMSM). The PMSM is the motor under
15 CHAPTER 1. INTRODUCTION
Figure 1.9: Actively clamped DC link inverter. test; and the DC motor is used as the test load. Thus this section covers both DC and PMSM motor control.
1.5.1 DC Motor Control
Although the DC motor is not the item under test in this work, it is still worth discussing DC motor control theory. Understanding DC motor structure and con- trol is helpful for understanding the approach and motivation for the other control approaches used in this work, namely field oriented control and direct torque control. A schematic of a field wound separately excited DC motor, ignoring impedances, is shown in Figure 1.10. This DC motor is a single phase motor. The armature is fitted with brushes and commutator, and the input voltage is DC voltage. This motor generates two fluxes, the field (rotor) flux and the armature (stator) flux, called ψf and ψa respectively. These fluxes are orthogonal, and this orientation is maintained mechanically by the commutator. Ignoring second order effects, such as the armature effect and saturation,
16 CHAPTER 1. INTRODUCTION
Figure 1.10: Separately excited DC motor and field orientation. the expression for the electromagnetic torque generated may be written as
Te = Ktψaψf (1.3)
where Kt is the torque constant, a machine parameter. This DC motor is fed by two currents: the rotor current, called the armature current, Ia, and the stator current, called the field current If . Thus If is used to generate the field, and Ia is used to generate torque. This concept of two currents, one for field generation and one for torque production, is adapted to three phase syn- chronous motors in the development of field oriented control, which will be discussed in forthcoming sections. Ignoring saturation, these currents are proportional to the fluxes they generate, and thus the above equation can also be written as
0 Te = KtIaIf (1.4)
0 where Kt is a scaled version of the torque constant [18]. In the case of the PM DC motor, the field is generated by permanent magnets instead of by the field current If . A schematic of the PM DC motor is shown in
17 CHAPTER 1. INTRODUCTION
Figure 1.11.
Figure 1.11: Schematic and field orientation of PMDC motor.
In this machine the armature current generates the armature flux, and the torque expression [19] is
Te = KψF Ia (1.5)
Thus in the PM DC machine, ignoring second order effects the PM field can be treated as fixed, and torque production is a function of armature current. In fact, by linearizing the system, time domain block diagrams of the system can be developed, and fairly straightforward modeling and control of the PM DC motor is possible. As torque produced is a function of armature current, input current can be used as a control variable in a PI current loop to control motor torque. However, an outer speed loop (another PI loop wrapped around the inner, current loop), can be implemented if speed control is desired. This is another common approach, and is also extended commonly to synchronous motor control. Two important concepts from DC motor theory are helpful to bear in mind in the following sections. Firstly, two currents generate two orthogonal fluxes, one generat- ing field flux, and the other generating torque. The second is that these fluxes are kept perpendicular to each other, or field oriented, during machine operation - in the case of the DC machine this field orientation is done mechanically, within the motor,
18 CHAPTER 1. INTRODUCTION via the commutator action.
1.5.2 PMSM Motor Control
The permanent magnet synchronous motor (PMSM) is a three phase synchronous motor using permanent magnets, opposed to a wound rotor, to generate the field. The PMSM is used as the motor under test in this work. Three control approaches for the PMSM are described in this section: open loop control, field oriented control, and direct torque control.
1.5.2.1 Open Loop Control
Unlike induction machines, which run at non-synchronous speeds due to slip, syn- chronous machines (SMs) operate at synchronous speed, or not at all. The machine speed is directly correlated to the frequency supplied by the drive system. Control schemes used to drive synchronous motors can be broadly grouped into two categories: open loop control and closed loop control. Open Loop Control (also called Volts/Hz Control) is an example of a scalar (single variable) control method. While originally developed for speed control of induction machines, it can also be used for synchronous machines. While it has the advantage of being the simplest control method for a SM, it provides inferior performance compared to the more advanced control methods described in following sections. As the name implies, the concept behind Volts/Hz control is to scale the motor supply voltage with speed. Since the back emf and the motor impedance (neglecting resistance) scale with frequency, the goal is to maintain constant stator flux by main- taining phase voltages proportional to the desired operating frequency (at low speeds, where resistance dominates, a boost voltage is added to compensate). An example implementation is shown in Figure 1.12. This multiple machine implementation is used where close speed control over many
19 CHAPTER 1. INTRODUCTION
Figure 1.12: Volts/Hz control of multiple synchronous motors. machines is necessary, e.g. in fiber spinning mills. Note that all machines are tied to the same inverter, so they ideally move synchronously with the commanded speed ω∗. As mentioned above, the Volts/Hz method is straightforward, and it can be quite helpful. This approach was used in this work, enabling initial equipment and mo- tor testing as the vector control implementations were being developed. However, the method has multiple performance drawbacks. For example, speed change must be done fairly gradually; startup must be done slowly, and sudden changes in com- manded speed can cause the system to go unstable due to loss of synchronism. Also, dissimilarities in driven motor parameters or load torques can cause angular position variations between motors [15].
1.5.2.2 Field Oriented Control
Field orientation control (FOC) is an example of vector control, an advanced control algorithm so-called because it achieves control of both the amplitude and the phase of the output AC signal. This control of voltages and currents allows control of the spatial orientation of the motor electromagnetic fields, and thus has been termed field orientation [19]. Work in field orientation control was pioneered in the late
20 CHAPTER 1. INTRODUCTION
1960s and early 1970s by Hasse and Blaschke [20] [21]. Opposed to the previously described Volts/Hz method, field oriented control is a closed loop control scheme; higher performance is delivered, however, at the cost of a more complicated control scheme. FOC was developed in the 1980s to deal with problems with inverter fed induction and synchronous motor drives, namely oscillating flux and torque responses in these drives. This behavior led to undesirable motor performance, such as speed oscilla- tions, and to large current transients causing failure of inverters. The root cause was determined to be deviations in air gap flux linkages from their set values; deviations in both magnitude and phase. In contrast, the separately excited DC motor drives were very stable and robust [12]. Separately excited DC motor drives are simpler to control because they allow independent control of flux and torque; as mentioned in the previous section, this is enabled by the separate control of the currents in the field and the armature which create this flux and torque, enabling this simple control. The goal of FOC is to develop a control scheme wherein decoupled field and torque producing fluxes are similarly generated, controlled by independent field and torque producing currents. Under these conditions, FOC motor control makes the AC drives similar to DC drives in that they also provide independent flux and torque control, and superior to DC drives in performance [22]. As explained in Section 1.5.1, the torque equation for a separately exited DC motor is described as
0 Te = KtIaIf (1.6)
where the field and armature fluxes ψf and ψa are field oriented mechanically via the commutator, and are produced by the independent currents If and Ia. Extending this concept to a three phase machine is accomplished by first con-
21 CHAPTER 1. INTRODUCTION
sidering a synchronously rotating reference frame called the direct-quadrature (d-q) frame, where sinusoidal three phase currents appear as DC quantities in steady state. In practice, motor currents are first converted to orthogonal stationary frame (sinu- soidal) variables via the Clarke transform, and then to rotating reference frame d-q variables via the more computationally intensive Park transform, as discussed in Sec- tion 2.3.2.2. These currents are direct and quadrature axis components of the stator
current, where id is the field producing current, analogous to If , and iq is the torque production current, analogous to Ia. Thus the AC machine torque can be expressed as
0 Te = Ktidiq (1.7)
where the fluxes generated by id and iq are maintained perpendicular to each other, or field oriented, via the control algorithm, enabling DC machine-like performance [15]. Once transformed, the d-q currents are in the rotor reference frame, so they appear as DC values, and standard PI control can be used. Their outputs are then converted, via inverse Park and Clarke transformations, for implementation via the inverter. Note that the inverter control implementation in FOC typically employs some form of PWM, meaning that arbitrary changes to the voltage pulse width are necessary for implementation. A high level description of the control approach and the corresponding phasor diagram are shown in Figure 1.13.
As mentioned above, rotor reference frame variables id and iq are controlled via separate PI controllers in the FOC control algorithm. In the case of the PMSM machine, since the field is generated by the magnets, the id command is often set to zero, as no current needs to be spent generating field flux. Often in the control implementation, speed is a variable we are more interested in controlling; this is
22 CHAPTER 1. INTRODUCTION
Figure 1.13: Induction motor FOC implementation and field orientation. commonly implemented by controlling the variables that determine field and torque
(id and iq) in an inner loop, and implementing an outer PI loop to control speed, similar to the approach used in DC motor control.
1.5.2.3 Direct Torque Control
Direct Torque Control (DTC), also called direct torque and flux control and direct self control, is a newer control scheme than FOC. The techniques were developed in the mid 1980s independently by Takahashi and Noguchi in Japan [23] and Depenbrock in Germany [24]. The distinguishing feature of DTC is that torque and flux are directly controlled - as the name implies - opposed to FOC, wherein d- and q- axis currents are the controlled variables in the inner loop. In implementation of DTC of a PMSM using a HSI, stator flux linkage and the electromagnetic torque are controlled directly by applying the inverter optimum volt- age switching vectors. Torque and flux are estimated in the machine, and errors in these values are fed into hysteresis comparators; outputs of the comparators are input to look up tables defining optimum voltage switching selections [25]. If speed control is desired, an outer loop PI can be implemented, as in FOC, to feed the inner loop flux and torque inputs. The DTC system has a number of improvements over the FOC approach, including improved dynamic performance, and a potentially simpler control scheme. DTC does
23 CHAPTER 1. INTRODUCTION not require current loops or a modulation scheme, and since a stator reference model is employed, the computationally heavy coordinate transformations required in the FOC controller are not needed. Since DTC uses stator flux linkage control, dependence on multiple motor parameters is reduced. Additionally, sensorless control is easily achieved with DTC, allowing elimination of the position sensor, improving reliability and decreasing cost and required maintenance. [22]. As mentioned in Section 1.5.2.2, PWM schemes require the ability to arbitrarily change switching times. Since the switching instants available in a resonant inverter system are determined by the resonant circuit, and thus discrete, traditional PWM (and thus FOC) approach cannot be used. Thus one potential advantage of the DTC approach is that it inherently switches at discrete times, and thus does not require a PWM scheme. Since the goal of this work is to implement a resonant inverter, this is very attractive; the discrete output of the resonant inverter pairs well with the discrete switching voltages commanded by the DTC scheme.
1.6 Literature Review
A number of papers were located in the literature implementing direct torque control using resonant inverters to drive three phase motors; a review of the relevant research is provided in this section. These papers typically describe the type of resonant inverter implemented, along with the goal of the research - reduced switching losses are often a stated goal, although sometimes only implied, and further achievements are typically discussed. The papers also discuss implementation of key aspects of the system, such as modifications to the classical DTC scheme, and the flux estimation approach. For the purposes of this discussion, the references are divided into four groups based on the topology of resonant inverter that was implemented: the pole commutated inverter, the basic resonant DC link, the parallel resonant DC link, and
24 CHAPTER 1. INTRODUCTION the quasi-resonant DC link. Before summarizing the literature, it is helpful to review the topology categories (a more detailed topology discussion is included in Section 4.2.2). The DC link topology can be divided into two main categories: the pole com- mutated inverter (PCI), and the resonant DC link inverter (RDCL). PCIs have a resonant circuit on each pole, or leg, while the RDCL has only a single resonant cir- cuit. A high level schematic of one configuration of a basic PCI is shown in Figure 1.14.
Figure 1.14: Pole Commutated Inverter (PCI).
The RDCL topology can be further divided into two types: the basic RDCL (BRDCL, which is the topology employed in this work), and the parallel RDCL (PRDCL). Unlike the BRDCL, which is decoupled from the DC link voltage (hence the need for voltage clamping), the PRDCL is configured so that the resonant circuit is in parallel with the inverter and the DC link, and thus the inverter is tied to the DC bus during part of the cycle. A comparison of BRDCL and PRDCL is shown in Figure 1.15. The BRDCL can be further modified to enable the use of PWM schemes. This is done with a configuration called the quasi-resonant RDCL (QRDCL), so called because the resonance only occurs during switching transitions. The quasi-resonant control is achieved through the inclusion of auxiliary circuitry, shown generically in the figure as “AUX”. An example high level schematic of a QRDCL with an active
25 CHAPTER 1. INTRODUCTION
Figure 1.15: BRDCL (left) and PRDCL inverters. clamp is shown in Figure 1.16 [8].
Figure 1.16: Quasi-resonant RDCL (QRDCL) inverter with active clamp.
The first group of references, consisting of two papers, implemented a basic res- onant DC link (BRDCL) inverter with the DTC controller. The goal of the first paper was to provide a higher performance DTC drive which is economically com- petitive with a scalar Volts/Hz drive, potentially targeting traction drive applications [26]. Through an innovative current estimator, the line currents required for the flux estimation were approximated using a single DC current sensor coupled with knowl- edge of the inverter switch states. This reduction of required current measurements made the system sensor requirements identical to those in lower performance Volts/Hz drives. Similarly, the goals of the second paper were to eliminate sensors. In this case, the goal was to eliminate the speed sensor, targeting industrial applications where
26 CHAPTER 1. INTRODUCTION it is neither desirable nor possible to use mechanical sensors for speed or position [27]. Using available voltage, flux, and torque values along with the estimated stator resistance, motor synchronous speed and slip were estimated, and these were used to calculate shaft speed. The second group of references, consisting of three papers, implemented a quasi- resonant RDCL (QRDCL) inverter with a DTC controller. The QRDCL is a mod- ification which allows the BRDCL output to be PWM controlled, an improvement which is achieved at the cost of additional components and a more complex control scheme. The goals of the first paper were to reduce electrical stresses on components, reduce the switching losses, and improve system dynamic response [28]. The goals of the last two papers in this category, written by the same authors, are to provide a high performance, soft switching three phase induction motor drive. In addition to the fairly complicated resonant inverter control, the authors also developed and implemented a reduced order flux observer [29] [30]. The third group of references, also consisting of three papers, implemented a parallel resonant RDCL (PRDCL) inverter. The goals of the first paper were to improve DTC performance by reducing the hysteresis bands. Specifically the goal was to reduce torque ripple, thus improving speed performance, and flux ripple, reducing stator current ripple. This was to be accomplished by delivering higher frequency capability, made available through use of the resonant converter, and corresponding reduced losses. A modification was also made to the standard DTC scheme; two-level hysteresis bands were used (often the torque comparator uses three level hysteresis), and no zero vectors were used; this was done to improve low speed operation, enabled by the higher frequency operation [31]. The second paper hoped to improve speed regulation via increased switching speed, and improve losses via the resonant inverter. This paper presented results in simulation only [32]. The authors of the third paper in this group similarly hoped to improve performance, specifically by reducing pulse
27 CHAPTER 1. INTRODUCTION ripple, via higher switching enabled by use of a resonant topology. Their results are also simulation only [33]. The last reference was the only paper in the group that did not use an RDCL. Instead a PCI was used in combination with the DTC. This was again used to drive an induction machine. The control approach was described, and implemented in simulation and hardware [34].
1.7 Focus and Contributions of the Research
A number of references were identified in the literature which describe the combination of the use of direct torque control and a resonant inverter to drive three phase motors. These papers describe a number of intended goals, notably decreased switching loss based on resonant topology, improved performance based on the higher available switching frequency, decreased cost and increased reliability through reduction of required sensors, and reduction of voltage stresses on the components and motor itself. The papers described innovative (and sometimes very complex) resonant inverter topologies, the use of flux observers, and modifications to the DTC switching schemes. A number of topics relevant to the goals of this dissertation have not been covered in the literature. For example, all of the DTC and resonant inverter systems described in the literature review were used to drive induction motors. None of the papers focused on a synchronous motor of any type, while this paper will specifically employ a synchronous motor, the PMSM, with its additional issues stemming from the smaller inductance. Additionally, none of the papers make an attempt to benchmark the DTC resonant converter performance to that of the more standard high performance system - a field oriented control system combined with a HSI; this comparison is included in this work as well. Finally, there is no example in the literature of comparing system improvement in terms of energy efficiency or reduced filtering requirements; this work
28 CHAPTER 1. INTRODUCTION also includes such an analysis.
1.8 Organization
This work is organized as follows. Chapter 2 covers the development of component and controller software models. First, models for the three phase PMSM are developed from fundamental equations. Next, inverter models are presented for the hard switching inverter (three models of increasing fidelity are described) and resonant link DC inverter. Then the motor control models are presented; theory is discussed and the implementation approach is described for three schemes: the open loop, or V/Hz control model; the FOC control model; and the DTC control model. Finally, models for the outer loop controller and the load motor are presented. Chapter 3 includes results of system simulations, using the models presented in Chapter 2. These simulations cover two broad categories: complete system simula- tions (which include an entire motor drive system) and resonant inverter simulations. Complete system simulations are developed, and results presented, for three motor controller configurations: the open loop system, FOC system, and the DTC system; the FOC simulations include results using all three HSI (ideal, simple, and high fi- delity) inverter models. Finally, simulations of the resonant inverter power system components and controller functions, used in the inverter design, are discussed. Chapter 4 describes the inverter design and development for this effort. Two types of inverter are discussed: a hard switching inverter (HSI) and a resonant inverter (the active clamped resonant link inverter, or ACRLI). First, selection and implementation of the HSI is discussed. Then the design, build, testing, and implementation of the ACRLI is detailed. The resonant topology selection is discussed, and the design of key components (resonant circuit, main switch control, clamp switch control, latching,
29 CHAPTER 1. INTRODUCTION and current prediction) is detailed. Next, subassembly and testing is described, and finally, after the breadboard version of the ACRLI is checked out, the design and build of a printed circuit board version is discussed. Chapter 5 includes a description of the specification and buildup of the the motor lab for this effort. The selection, acquisition, and setup of the key subsystems are described. Topics covered include the motor controller implementation (the motor controller and the interface computer), the inverter subsystem, the motor under test (PMSM), and the motor test load. Support equipment is also described, including the voltage measurement system, the oscilloscopes, the sensors used, and the power supplies. Chapter 6 covers the hardware implementation of the controllers and motor drive systems, culminating in two operational systems ready for test and comparison: base- line system and the research system. First, motor parameter measurement is per- formed on both motors; the PMSM (MUT), and the load (BDC) motors. Next, hardware checkout of the motor lab is described using open loop operation, and the transfer of controllers to hardware is discussed. FOC-HSI implementation in the mo- tor lab is covered, and validation under FOC of measured parameters is discussed; then DTC implementation and improvement is discussed. Multiple approaches to flux and torque estimation improvements are presented; then other improvement efforts, such as controller code analysis, comparator improvements, and improved current sensing and filtering are discussed. Finally, the DTC-ACRLI implementation is de- tailed, and the development of a system efficiency measurement approach is described. Chapter 7 details the experimental results on the research system, the DTC- ACRLI-PMSM, studying the effects of inverter and controller parameters on perfor- mance, and discusses comparison of two relevant system performance metrics, system efficiency and noise, with the baseline FOC-HSI system. Topics covered include in- verter parameter studies, controller parameter studies, system efficiency compared
30 CHAPTER 1. INTRODUCTION to baseline, and system noise (at the input and output) compared to the baseline system. Chapter 8 presents conclusions, contributions of the work, and suggested areas for future work.
31 Chapter 2
Model Development
A representation of the system being tested in this work is shown in Figure 2.1. At a high level, the main components in the system are the control and drive, the motor under test, and the load.
Figure 2.1: Schematic of system under test.
For the purposes of discussing the modeling and simulation, it is helpful to present a more detailed view of the entire system, capturing the major subcomponents which are to be modeled. This schematic is presented in Figure 2.2. In this chapter, a model is developed of each of the boxes in Figure 2.2. The following topics are discussed in this section: the motor model, the inverter models, the inner loop/motor control models, the outer loop/speed control model,
32 CHAPTER 2. MODEL DEVELOPMENT
Figure 2.2: System components to be modeled. and the load model. A single model is presented for the motor, the load, and the outer loop; and multiple models will be presented for the inverter and the controller. The models were developed in Simulink and PSIM.
2.1 Motor Model
Development of a motor model for a three phase PMSM is done by first developing a model for a simpler case, a two phase motor, and then extending that model to three phases [12]. This two phase motor includes permanent magnets on the rotor and a set of windings that are 90 degrees apart from each other on the stator. The rotor spins in the counterclockwise direction, and the rotor PM location is defined at an angle θ from the winding located along the stator d-axis. The rotor magnets and stator windings, along with the correct senses of the winding voltages and currents, are shown in Figure 2.3. Using KVL, summing the resistive voltage drops and flux linkage derivatives, the equations for the stator voltages along the q and d axis are
d vqs = Rqsiqs + ψqs dt (2.1) d vds = Rdsids + dt ψds
where vqs and vds are the voltages across the q- and d-axis stator windings, iqs and ids
33 CHAPTER 2. MODEL DEVELOPMENT
Figure 2.3: Two Phase PMSM.
are the stator currents in the q- and d-axis windings, Rqs and Rds are q- and d-axis winding resistances, and ψqs and ψds are the stator q- and d-axis stator flux linkages. The stator winding flux linkages are the sum of flux linkages due to self excitation, and mutual flux linkages from elsewhere, namely currents in other windings and permanent magnets. They can be written as
ψqs = Lqqiqs + Mids + ψF sin(θ) (2.2) ψds = Miqs + Lddids + ψF cos(θ)
where Ldd and Lqq are the q- and d- axis winding the self inductances, M is the mutual inductance between the q- and d- axis windings, and θ is the rotor angle. Since the windings are balanced, the winding resistances are equal to each other, and will henceforth be called Rs. With this modification, equation 2.2 can be incor-
34 CHAPTER 2. MODEL DEVELOPMENT porated into equation 2.3 to give us
d d d d d vqs = Rsiqs + iqs Lqq + Lqq iqs + M ids + ids M + ψF sin(θ) dt dt dt dt dt (2.3) d d d d d vds = Rsids + iqs dt M + M dt iqs + Ldd dt ids + ids dt Ldd + ψF dt cos(θ)
The PMSM winding inductances vary with rotor angle. When θ is zero, the mag- net is aligned with the d axis, and the d-axis winding inductance is at a minimum, since the PM relative permeability is similar to the relative permeability of air, and thus the reluctance of the flux path for the d-axis winding is maximum at this po- sition. This minimum inductance is called Ld. When the rotor is rotated in the counterclockwise direction, more iron and less magnet is gradually introduced into the path, and so reluctance decreases and the inductance increases. The inductance of the d-axis winding reaches a maximum after rotation of 90 electrical degrees, when the PM is aligned with the q-axis, and this inductance maximum is called Lq. Because the PMSM is designed to provide sinusoidal MMF, the self inductances are modeled as sinusoidal functions of the maximum and minimum inductance values
Ld and Lq; note that the inductance varies at twice the electrical speed, because two cycles of maximum and minimum inductance are completed with a rotation of 360 electrical degrees. If we define the following inductance relationships
1 LM = (Lq + Ld) 2 (2.4) 1 Lm = 2 (Lq − Ld) the expression for the winding self-inductances can be written as
Lqq = LM + Lmcos(2θ) (2.5) Ldd = LM − Lmcos(2θ)
Again assuming a sinusoidal variation, the expression for mutual inductance be-
35 CHAPTER 2. MODEL DEVELOPMENT
tween the windings is
M = −Lmsin(2θ) (2.6)
By combining equations 2.5 and 2.6 into equation 2.3 we obtain the following set of machine equations in the stator reference frame:
vqs iqs LM + Lmcos(2θ) −Lmsin(2θ) d iqs = R + s dt vds ids −Lmsin(2θ) LM − Lmcos(2θ) ids (2.7) −sin(2θ) −cos(2θ) i cos(θ) qs +2ωLm + ψF ω −cos(2θ) sin(2θ) ids −sin(θ)
The above machine equations are highly dependent on rotor position. They can be greatly simplified by removing this dependency; this can be done by transforming the machine equations into the rotor reference frame. By revolving the reference frame at the same angular speed as the sinusoidal variable, system variables appear to be DC quantities rather than sinusoidal quantities, which makes the system inductance matrix independent of the angular position of the rotor. This is achieved using the Park transform. Applying the Park transform to equation 2.7 we have the PMSM model in the rotor reference frame [12]:
v R + L p ωL i ωψ q s q d q F = + (2.8) vd −ωLq Rs + Ldp id 0 where vq and vd are the voltages in the rotor reference frame, iq and id are the currents
d in the rotor reference frame, and p is the differential operator dt . Note that the angular position dependence has been removed from equation 2.8, and that this form of the machine equations is much simpler than those based in the stator reference frame. It is also worth noting that this system is not linear, as some of the elements in the
36 CHAPTER 2. MODEL DEVELOPMENT
impedance matrix depend on the speed of the rotor; the system only becomes linear at constant speed. The expressions for electromagnetic torque in the rotor reference frame and the motor electromechanical dynamic equation are given [12] by
3P T = [ψ i + (L − L )i i ] (2.9) e 2 F q d q q d and dω T = J + T + Bω (2.10) e dt L
where P is the number of pole pairs, ω is the mechanical rotor speed, J is the combined
moment of inertia of the motor and load, and B is the friction, and TL is the load torque. By rearrangement of equation 2.11, an expression for motor acceleration is obtained: dω 1 = T − T − Bω (2.11) dt J e L
The PMSM motor model is developed by incorporation of equations 2.8 - 2.11 into the simulation. The model is converted from the three phase motor system using the Clarke transform, then to the rotating reference frame using the Park transform. The complete PMSM motor model is presented in Figure 2.4.
2.2 Inverter Models
Two different types of inverter models are covered in this section: hard switching in- verters (HSI), and soft switching (resonant) inverters. Multiple models or subsystems of each inverter type are discussed, each with varying levels of fidelity, tailored for their intended application.
37 CHAPTER 2. MODEL DEVELOPMENT
Figure 2.4: Complete PMSM model.
2.2.1 Hard Switching Inverter Models
The Hard Switching Inverter (HSI) in this study is a six switch voltage source inverter. It is called a HSI to distinguish it from the soft switching resonant inverter also under study. Three different models are presented in this effort: the Ideal HSI Model, the Simple HSI Model, and the High Fidelity HSI Model. Each are discussed in the following sections.
2.2.1.1 Ideal HSI Model
The ideal HSI model simply assumes the voltages commanded at the controller output are generated at the motor input. No PWM, switching, or non-ideal device effects are captured. Although this model type does not present a high fidelity picture of behavior, it has the advantages of enabling quick simulation time and when applied correctly does capture first order behavior.
38 CHAPTER 2. MODEL DEVELOPMENT
2.2.1.2 Simple HSI Model
The Simple HSI Model captures some PWM and switching effects, but not the non- ideal switching device characteristics. Instead of being fed by the desired voltage command as in the Ideal HSI model, the Simple HSI Model is instead fed by PWM command, and its output presents the voltage across the motor leads according to this PWM and the circuit and inverter topologies. The Simple HSI Model was particularly helpful in the early DTC modeling effort. The first step in modeling the HSI is to identify the voltages that are applied to the motor windings under each of the possible voltage vectors (allowed switching states) of the inverter. This is manageable, as there are a finite number of allowed switching states. A schematic of a standard HSI inverter with a wye-connected balanced load is shown in Figure 2.5.
Figure 2.5: HSI inverter with wye-connected load.
6 The inverter switches S1 - S6 can be either on or off, which gives us 2 possible switching configurations. However, in practice, since having both switches in a leg
(e.g. leg A is switch pair S1 and S4) on at the same time results in a short circuit across the DC supply, and shutting both switches in a pair off results in an undefined state for the motor winding, there are only six allowed active configurations, wherein
39 CHAPTER 2. MODEL DEVELOPMENT one switch in each leg is always on, and the other is always off. If we define allowable switch states for each leg, SA, SB, and SC , wherein SX = 0 is the configuration with the lower switch on and the upper switch off within leg X, and SX = 1 is the configuration with the lower switch off and the upper is on for leg X, we can summarize the allowed voltage vectors (V0-V7) and their corresponding switch configurations in the left hand columns of Table 2.1.
Table 2.1: Allowable HSI switch configurations and resulting voltages (x VDC ) V Sa Sb Sc V ab V bc V ca V an V bn V cn V0 0 0 0 0 0 0 0.00 0.00 0.00 V1 1 0 0 1 0 -1 0.67 -0.33 -0.33 V2 1 1 0 0 1 -1 0.33 0.33 -0.67 V3 0 1 0 -1 1 0 -0.33 0.67 -0.33 V4 0 1 1 -1 0 1 -0.67 0.33 0.33 V5 0 0 1 0 -1 1 -0.33 -0.33 0.67 V6 1 0 1 1 -1 0 0.33 -0.67 0.33 V7 1 1 1 1 1 1 0.00 0.00 0.00
With the allowable switch stated defined, the next step is to determine the line- to-line voltages resulting from each switch state. This is quickly done by inspection.
For example, the case of voltage vector V1, the upper switch in leg A is on, and the lower switches are on for legs B and C; in this configuration point A is tied to the high rail while B and C are tied to the low rail. Thus voltage Vab is VDC , Vca is -VDC , and Vbc is 0. A similar analysis is performed for all of the voltage vectors, and the calculated line-to-line voltages are captured as multipliers of VDC in columns Vab - Vca of Table 2.1. Using the data in Table 2.1, the relationship between the switch states and the line-to-line voltages is found to be [35]:
Vab 1 −1 0 SA V = VDC 0 1 −1 S (2.12) bc B Vca −1 0 1 SC
The inverter model would ideally convert the commanded switch states of the HSI
40 CHAPTER 2. MODEL DEVELOPMENT
into applied motor line-to-neutral voltages, as this is how the model is implemented in the simulation. Using the following definitions
Vab = Van − Vbn
Vbc = Vbn − Vcn (2.13)
Vca = Vcn − Van along with the relationship arising from the balanced system
Van + Vbn + Vcn = 0 (2.14) combined with equation 2.12, the following relationship for motor line-to-neutral volt- ages as a function of switch states is generated:
Van 2 −1 −1 SA SA VDC V = −1 2 −1 S = V∆ S (2.15) bn 3 B B Vcn −1 −1 2 SC SC
Equation 2.15 is used to fill out the remaining columns of Table 2.1. The Simple HSI inverter model is implemented in code using the above relation- ~ ~ ship, converting the switch vector S into line to neutral voltage vector Vn as shown in Figure 2.6.
Figure 2.6: HSI inverter model.
41 CHAPTER 2. MODEL DEVELOPMENT
2.2.1.3 High Fidelity HSI Model
The High Fidelity HSI Model can capture PWM and switching effects as well as the effects of non-ideal switching device properties. This is achieved by using PSIM, which is a simulation and design tool for power electronics applications. The PSIM package was chosen because it will enable co-simulation with Simulink. Typically the power components are modeled in PSIM, and the controls elements in Simulink. A schematic of the high fidelity HSI model is shown in Figure 2.7.
Figure 2.7: High fidelity HSI model.
In Figure 2.7, the switches are modeled as they are in the hardware HSI (IGBTs and diodes). Also, the PWM circuit is built into the model; commanded voltages received from the Simulink model are modulated and used to drive the switches. Outputs feed to the Simulink PMSM model developed in Section 2.1.
42 CHAPTER 2. MODEL DEVELOPMENT
2.2.2 Resonant DC Link Inverter Model
The resonant inverter was modeled in stages, starting with basic modeling of the resonant circuit, and over time other circuit and control elements were added. The power and resonant circuits were modeled in PSIM, and the control portions were modeled in Simulink. Eventually a number of subsystems are modeled. This effort is discussed in detail in Chapter 4. A schematic of a PSIM model of the central portion of the Resonant DC Link Inverter - the resonant circuit, including all switches, resonant, and clamp elements - is shown in Figure 2.8.
Figure 2.8: Resonant circuit model.
The similarities between resonant board schematic shown in Figure 4.9 and the
schematic shown in Figure 2.8 are obvious. The main and clamp switches Sm and Sc are included in the model, as are resonant components Lr and Cr and clamp capacitor
Cc.
43 CHAPTER 2. MODEL DEVELOPMENT
2.3 Inner Loop/Motor Control Models
Two categories of motor control models were developed in this effort: the scalar control model and the vector control model. One scalar controller model is developed; the open loop, or V/Hz, controller. Models for two different motor control algorithms are developed in this section: a field oriented control (FOC) model, and a direct torque control (DTC) model. The Motor Control code is located in the “Inner Loop Control” block of Figure 2.2. In the case of the Open Loop controller, the figure becomes significantly simplified: there is no outer loop in this control architecture, and there are no feedback signals. The outer loop and feedback element, however, are in use in the vector controllers, the FOC and DTC models. For each these of motor control models, the “Inner Loop Control” block of Figure 2.2 can be divided into two subcomponents: variable conversion and control. The structure of these subcomponents is shown in Figure 2.9.
Figure 2.9: Motor control (inner loop) components.
The variable conversion function calculates inner loop variable values. Incoming signals are the sensor signals, namely the phase currents, the rotor position (θ), and in some implementations of DTC, the phase voltages; the output is the appropriate inner
44 CHAPTER 2. MODEL DEVELOPMENT loop estimates. The control function implements the motor control; the incoming signals are the inner loop variable command and estimated values and the rotor position, and the outputs are the voltage commands which are passed on to the inverter. The vector motor control algorithms use two different sets of inner loop variables, which will be discussed in the next sections. One inner loop command comes from the outer loop (speed) command, and the other is set internally. A summary of the details of the inner loop variables is included in Table 2.2.
Table 2.2: Inner loop variable summary V ariable FOC DTC Source 1 iq Test outer loop 2 id ψest set internally
2.3.1 Open Loop Control Model
Open loop control, also called the V/Hz control, is discussed in Section 1.5.2.1. The concept behind this open loop control is to scale motor voltage with speed. A schematic of the open loop controller is shown in Figure 2.10.
Figure 2.10: Schematic of open loop (V/Hz) controller.
In open loop control, an angle is calculated from the speed command, and used to generate three sinusoids spaced 120◦ apart. The amplitude of these sinusoids is set by the V/Hz block. This block contains a gain, to scale the voltage appropriately
45 CHAPTER 2. MODEL DEVELOPMENT
as a function of commanded speed, and also an offset to provide voltage at startup. Simulation of the open loop controller is discussed in Section 3.1.1, and implementa- tion in hardware in the motor lab as a part of system checkout is described in Section 6.2.
2.3.2 Field Oriented Control Model
The development of the FOC motor control model, which is the basis for the FOC motor control implementation, is discussed in this section. This discussion is divided into three topics: FOC theory, FOC variable conversion, and FOC control implemen- tation, which are discussed in the following sections.
2.3.2.1 FOC Theory
Vector control, also known as decoupling, orthogonal, or transvector control, is a motor control approach which enables the three phase motors to be controlled like much simpler DC machines, providing many performance benefits. Since this ap- proach controls both the amplitude and the phase of the output, it is referred to as vector control. The fact that the resulting control of the voltages and currents results in control of the machine spatial electromagnetic field orientation, this approach is also called field orientation, although this term often refers specifically to controllers wherein a 90◦ orientation between field components is maintained [19]. The goal of FOC is to properly orient the stator currents with respect to the rotor magnetic field to enable the desired control response. This is accomplished by performing a set of mathematical transformations, converting the motor three phase currents into two current variables, one controlling flux and the other independently controlling motor torque, in a reference frame that is synchronous with the rotor. In the rotating reference frame the control currents become DC values, enabling regu- lation via straightforward PI control techniques. The output of the PI controllers is
46 CHAPTER 2. MODEL DEVELOPMENT
then inverse transformed back to the stationary reference frame via inverse transfor- mations, modulated, and passed on to the inverter.
2.3.2.2 FOC Variable Conversion
Inputs to the FOC conversion block are the sensor outputs; namely the measured phase currents and the rotor position. Only two motor phase currents are measured,
ia and ib; in a balanced system, the third current is not independent, and is easily calculated from the other two. A schematic of the FOC conversion block is shown in Figure 2.11.
Figure 2.11: FOC variable conversion block.
The measured phase currents are transformed to a second reference frame, con- sisting of two orthogonal axes, the α axis and the β axis. This transformation is called the Clarke transform (also called the αβγ transform and the abc/αβ transform); the reference frames are depicted in Figure 2.12. In Figure 2.12, the axes corresponding to the physical location of the three phase currents are shown at 120◦ apart, labeled A, B, and C axis, and the orthogonal axes
are labeled the α and β axes. The stator current space vector is is shown in blue, projected onto the α and β axes.
47 CHAPTER 2. MODEL DEVELOPMENT
Figure 2.12: Clarke transform.
The Clarke transform is implemented in code using the relationship
ia −1 −1 iα 2 1 2 2 = √ √ ib (2.16) 3 3 − 3 iβ 0 2 2 ic
Next the resulting orthogonal currents, iα and iβ, are converted from the orthogo- nal stationary reference frame to an orthogonal rotating reference frame, the dq axis. This is achieved using the Park transform. Note that knowledge of the rotor position is required in order to complete this transformation; in the model, θ is provided as an input to the block, from the motor model. A graphical representation of this transformation is shown in Figure 2.13. In Figure 2.13, the q and d axes are shown, rotating with the current space vector; rotation is defined by electrical angle θe. The calculated currents id and iq, in green, are shown projected onto the rotating axis. The Park transformation is implemented in the model using the relationship
i cos(θ ) sin(θ ) i d e e α = (2.17) iq −sin(θe) cos(θe) iβ
The transformed stator currents id and iq are the outputs of the FOC Convert block;
48 CHAPTER 2. MODEL DEVELOPMENT
Figure 2.13: Park transform.
they are passed on to the FOC Control block.
2.3.2.3 FOC Control Implementation
The rotating components id and iq are in a reference frame that is synchronous with the rotor flux. In this rotating reference frame, the d-axis is defined to be aligned with the axis of the rotor magnetic field; thus id controls the flux, and iq is the torque productizing current. In the rotor reference frame these currents are DC values, and thus can be controlled in a straightforward manner; these inner loop variables are first compared to commanded values generated in the outer loop, and the error signals are input to the FOC Control block.
Currents id and iq are controlled using a synchronous frame current regulator [36]. This current regulator consists of two PI controllers; each of them control one axis of current. The synchronous frame current regulator outputs are voltage commands in the rotor reference frame, which are next converted via inverse Park and Clarke transforms to phase voltage commands in the stator reference frame. The inverse
Park transformation requires the position θe; it is implemented in software using the
49 CHAPTER 2. MODEL DEVELOPMENT relationship
i cos(θ ) −sin(θ ) i α e e d = (2.18) iβ sin(θe) cos(θe) iq
The inverse Clarke transform is implemented in code using the relationship
ia 1 0 √ iα i = −1 3 (2.19) b 2 2 √ iβ −1 − 3 ic 2 2 Once the voltage commands have been converted to the stator reference frame, they are processed through the modulation block; the PWM output is the output of the FOC Control block, the three phase voltages commands, which are passed on to the inverter. The FOC Control block is shown schematically in Figure 2.14.
Figure 2.14: FOC control block.
The expression for torque in the PMSM [12] is
3P T = [ψ i + (L − L )i i ] (2.20) e 2 F q d q q d where P is the number of pole pairs, ψF is the armature flux linkage due to the rotor magnets, and Ld and Lq are the direct and quadrature axis stator self-inductances in
50 CHAPTER 2. MODEL DEVELOPMENT
the rotor reference frame.
In certain motor types (induction motors for example) the value of id is varied as necessary to generate the flux required for motor operation. However, in the PMSM the flux is provided by the permanent magnets, so no field flux production is necessary; for the motor used in this study id is commanded to zero. Using this approach, the direct axis stator flux linkage is constant, entirely due to magnets in the rotor with no stator current contribution. And with the field component of current set to zero, the armature MMF and the field flux are orthogonal, and so the torque equation simplifies. Torque is produced by the interaction of the field flux and the q-axis current such that torque becomes directly proportional to current iq:
3P T = ψ i (2.21) e 2 F q
This relationship is similar to that of a separately excited DC motor with constant field winding current, wherein the torque is equal to the product of the armature current and the torque constant. Thus in the FOC control scheme the torque is
controlled by controlling id and iq, the rotor reference frame currents; and the inner
loop variables are set by the outer loop (iq) and set internally (to zero, id) as was described in Table 2.2.
2.3.3 Direct Torque Control Model
The development of the DTC motor control model, which is the basis for the DTC motor control implementation, is discussed in this section. This discussion is divided into three topics: DTC theory, DTC variable conversion, and DTC control imple- mentation, which are discussed in the following sections.
51 CHAPTER 2. MODEL DEVELOPMENT
2.3.3.1 DTC Theory
Direct Torque Control (DTC) is a newer motor control scheme than FOC, introduced in the late 1980s [23] [24]. Unlike FOC, wherein the motor torque and flux linkage are indirectly controlled via regulation of id and iq, in DTC the motor torque and flux are directly controlled. The inner loop variables are the motor torque and flux, thus estimates of these values are required. These are calculated in the DTC Vari- able Conversion block. Instead of PI controllers regulating id and iq, as in FOC, in DTC errors in flux and torque directly drive the inverter through a pair of hysteresis controllers, without the need for the synchronous frame controllers or the coordinate transformations required for FOC. If the stator resistance in the PMSM is ignored, we have the relationship
d V~ = ψ~ (2.22) s dt s
~ ~ where Vs is the stator voltage vector, and ψs is the stator flux vector. Rearranging the above gives us ~ ~ ∆ψs = Vs∆t (2.23) which shows that incremental changes in the stator flux vector can be made by apply- ~ ing Vs, the stator voltage vector, for the time step ∆t. Thus the voltage space vector at the inverter output directly controls the stator flux. By considering the torque de- mand, while keeping stator flux linkage magnitude within a selected hysteresis band, the correct voltage vector can be selected to move the stator flux linkage space vector to in the desired direction, thus directly controlling the torque. [25] The DTC algorithm is implemented as follows. Commands for torque and flux are calculated, and compared to calculated estimates of the motor torque and flux. The errors between the commanded and the estimated values are then applied to hysteresis band controllers. The outputs of the hysteresis controllers, along with the
52 CHAPTER 2. MODEL DEVELOPMENT present location of the flux vector, are fed into lookup tables, which are designed to select the correct switching states to apply to the inverter to generate the desired control voltage vector. The resultant stator flux vector has a circular path, and it follows the command flux, moving in a zigzag path, constrained within the circular hysteresis band as depicted in Figure 2.15 [15]. While accurate knowledge of the magnitude of the stator
Figure 2.15: DTC stator flux vector trajectory.
flux linkage space vector is required, exact knowledge of its instantaneous position is not needed. The controller requires only the approximate location of the flux vector; that is, in which of six sectors, which span 60 electrical degrees, the flux vector is located. Sectors S1 - S6 are also depicted in Figure 2.15.
2.3.3.2 DTC Variable Conversion
Inputs to the DTC Conversion Block are the sensor outputs; namely two measured motor line to neutral voltages, va and vb, two measured line currents, ia and ib. Outputs of the block are the inner loop variables, motor electromagnetic torque and
flux linkage estimates, Test and ψest. A schematic of the DTC Variable Conversion Block is shown in shown in Figure 2.16.
53 CHAPTER 2. MODEL DEVELOPMENT
Figure 2.16: DTC variable conversion block.
In the stationary reference frame, the stator voltage equation for the PMSM is
d ~v = R i~ + ψ~ (2.24) s s s dt s
~ where Rs is stator resistance, and ~vs, i~s and ψs are the stator voltage, stator current, and stator flux linkage space vectors. By rearranging the above equation, a relation- ship for the stator flux linkage space vector as a function of measured stator voltages and currents can be obtained [25]:
Z ~ ψs = (~vs − Rsi~s)dt (2.25)
Therefore expressions for quadrature stationary reference frame flux linkage compo- nents are Z ψα = (vα − Rsiα)dt (2.26)
and Z ψβ = (vβ − Rsiβ)dt (2.27)
As seen from the above expressions, one benefit of the DTC approach is that the only one machine parameter is required, namely stator resistance. To avoid initial value and drift problems with the integrator, integration is not typically implemented
54 CHAPTER 2. MODEL DEVELOPMENT
for the flux estimation; instead a low pass filter is used. The flux magnitude estimate is simply calculated using
q 2 2 ψs = ψα + ψβ (2.28)
Torque can be expressed as a function of estimated stator flux linkages [22] as
3P T = (ψ i − ψ i ) (2.29) e 2 α β β α
where iα and iβ are the measured motor currents expressed in the stator reference frame. Note that only the easily calculated Clarke transform is required to trans- form the currents into the αβ frame; the much more computationally intensive Park transform is not needed.
2.3.3.3 DTC Control Implementation
The inputs to the DTC Control Block are the torque command (the outer speed loop command variable), the flux and torque estimates, and the rotor angle θ. The output of the block is a set of switching commands which are sent to the inverter to generate voltage vectors. The model for the DTC Control Block is shown in shown in Figure 2.17. The operation of the internal blocks, i.e. the sector calculation, the flux command calcu- lation, the flux and torque comparators, and the switching lookup table, is described in the following sections.
Sector Calculation The sector is calculated within the Sector Calculation block, for use in the control implementation. As seen in Figure 2.15, there are six sectors total, spanning 360 electrical degrees. Calculation of sector α is completed as follows. First, the input
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Figure 2.17: DTC Control Block.
rotor position θ is converted to electrical degrees, θe. Then the electrical angle is quantized into the six sectors in the following manner:
◦ ◦ if (330 < θe ≤ 30 ) α = 1;
◦ ◦ if (30 < θe ≤ 90 ) α = 2; (2.30) ...
◦ ◦ if (240 < θe ≤ 330 ) α = 6.
Flux Command Calculation The two DTC inner loop commands are T ∗ and ψ∗. While the torque command T ∗ is calculated via the outer loop and passed into the DTC control block, ψ∗ is generated within the DTC Controller, calculated from the torque command within the Flux Command block. Derivation of this calculation is discussed below. The stator flux linkages in the rotor reference frame are
ψd = Ldid + ψF (2.31) ψq = Lqiq
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where ψF is the flux linkage due to the rotor magnets. Ideally, the employed switching strategy maximizes efficiency, that is, the desired torque is generated with minimum stator current (maximum torque per unit current, or MTPA, criteria); thus id is forced to zero. Using the above equations, the stator flux linkage space vector relationship for this case is q ~ 2 2 |ψs| = ψd + ψq (2.32) or q ~ 2 2 2 |ψs| = ψF + Lq iq . (2.33)
Additionally, the electromagnetic torque of the PMSM is
3P T = ψ i (2.34) e 2 F q and solving for the torque producing current we have
2Te is = (2.35) 3P ψF
Substitution of the above into equation 2.33 gives us the desired relationship for commanded flux as a function of commanded torque [25]:
s ∗ 2 ∗ 2 2 2Te ψ = ψF + Lq . (2.36) 3P ψF
The model of the flux command block is generated by implementation of equa- tion 2.36.
Flux and Torque Comparators The inputs to the comparator blocks are the error values between the flux and torque commands and estimates, called Terr and ψerr. Two different comparator types
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are used for the flux and torque comparator. The flux comparator is a standard two level comparator; note that this is the flux comparator used by Takahashi [23]. Plots of these flux comparator input and output
signals are presented in Figure 2.18. Given a hysteresis band of 2Hψ, the input error
Figure 2.18: DTC flux comparator function block.
signal ψerr results in a two level output Sψ. The torque comparator is a three level comparator; its function is shown in Figure 2.19. Note that this is structure of the torque comparator by Takahashi [23]. Given a
Figure 2.19: DTC torque comparator function block.
hysteresis band of 2HT , the input error signal Terr results in a three level output ST .
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Outputs of the comparator blocks, commands ST and Sψ, are passed on to the switching lookup table.
Switching Lookup Table The function of the DTC switching table is best explained by example. The ~ ~ available inverter voltage vectors, V1 - V6, are shown in Figure 2.20; also shown are ~ ~ the corresponding changes in the stator flux vectors, ∆ψ1 - ∆ψ6, when each of the voltage vectors are applied over time ∆t.
Figure 2.20: Inverter voltage vectors and flux vector change when applied in time ∆t.
For a motor operating at given speed and torque conditions, with counterclockwise rotor flux rotation, when the stator flux vector is located in Sector 1 as shown, ~ application of voltage vector V2 will cause an increase in both torque and flux; voltage ~ ~ vector V3 will cause an increase in torque and a decrease in flux; voltage vector V6 will ~ cause a decrease in torque and an increase in flux; and voltage vector V5 will cause a ~ ~ decrease in both torque and flux. Of course, the zero voltage vectors V0 and V7 have no effect. A similar set of vectors can be quickly generated for operation in all six sectors, and this set is used to generate the DTC switching tables. The resultant table, which is implemented in the DTC model, is summarized in Table 2.3.
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Table 2.3: Voltage Vector Selection
Sψ ST S1 S2 S3 S4 S5 S6 1 1 V2 V3 V4 V5 V6 V1 1 0 V7 V0 V7 V0 V7 V0 1 -1 V6 V1 V2 V3 V4 V5 -1 1 V3 V4 V5 V6 V1 V2 -1 0 V0 V7 V0 V7 V0 V7 -1 -1 V5 V6 V1 V2 V3 V4
2.4 Outer Loop/Speed Control Model
Although separate models are required for the two different inner loop motor con- trollers, the model for the outer loop controller remains essentially the same in both cases. Except for tuning and the generated output variable, the controller is identical. A speed loop is implemented in both cases, as shown in Figure 2.21.
Figure 2.21: Outer (speed) loop model.
As seen in Figure 2.21, the outer loop is implemented with a standard PI controller. A speed error - the difference between the commanded and measured speed - is generated, and passed in as the input of the PI. The output of the PI becomes the
∗ inner loop command variable; as discussed above, this is iq for the FOC controller, and T* for the DTC controller.
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2.5 Load Model
The Load Model is used to mimic the loads presented to the motor under test (MUT, the PMSM) on the hardware system. In the motor lab, the MUT drives a single phase brushed DC (BDC) motor, operating in generator mode. The terminals of the load motor are connected to a load resistor, a 5Ω 120W power resistor. A schematic of the test load is shown in Figure 2.22.
Figure 2.22: Test load schematic.
A model for this load is developed using the parameters for the BDC load motor; the measurements and calculations used to estimate these parameters are described in Section 6.1. The two parameters used are the back emf constant, KV , and the torque constant, KT .
The back emf constant, KV , is in units of V/rpm. It is used to convert rotor speed to BDC motor terminal voltage while in generator mode. The relationship is
VBDC = KV ωrpm (2.37)
Ignoring resistance in the BDC, the current generated in the load resistor from the BDC is then
VBDC ILOAD = (2.38) RLOAD
The torque constant, KT , is in units of Nm/A. It is used to calculate torque
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generated by the BDC based on the motor current. The relationship is
TLOAD = KT ILOAD (2.39)
Combining equations 2.37, 2.38, and 2.39 we get load torque as a function of motor parameters, load resistance, and motor speed:
KT KV ωrpm TLOAD = (2.40) RLOAD
The relationship in equation 2.40 was implemented in Simulink, and used as a load model for all motor simulations.
62 Chapter 3
Simulation Results
A significant number of simulations were performed as part of this work, using the models presented in Chapter 2. An exhaustive description of all simulations performed would be prohibitive. Instead, simulations of particular value are discussed. In some cases, the results are presented in this chapter; however, if the work was performed in later chapters as part of a design or analysis, it made more sense to include the results along with the activity. In those instances references to the simulation locations are provided. Multiple simulation configurations were implemented, depending on the goals. These configurations fall into two broad categories: Complete System Simulations and Resonant Inverter Simulations. Each simulation type is covered in separate sections in this chapter.
3.1 Complete System Simulations
System Simulations include an entire motor drive system; the main elements of inter- est are the models of the motor controller, the inverter, and the motor itself. In this section, simulations are assembled for multiple system configurations. In each system, the load model and the motor model were identical, as described in Chapter 2; and
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in the closed loop controllers (FOC and DTC) the form of the outer loop model was identical. Variations of interest were changes in the motor control and the inverter models. These system simulations can be divided into three categories: open loop control, the field oriented control, and the direct torque control system simulations. Each is described in the sections below. Note each of these control models were developed and tested in simulation. Once simulation performance was considered adequate, the controllers were directly trans- ferred to the hardware, and used as run code to drive the inverter and motor under test in the motor lab as is discussed in Chapter 6.
3.1.1 Open Loop Control System Simulation
The open loop control algorithm, also called Scalar Control and Volts/Hz Control, is described in Section 2.3.1. While the open loop model is much less complicated than that of the vector control models (FOC and DTC), development and testing in simulation was very helpful. The “V/Hz” block in the schematic of the open loop controller (Figure 2.10) contains a gain, as expected, as well as an offset value. The structure is shown in
Figure 3.1. In Figure 3.1, the VOL−G parameter serves as the V/Hz gain, increasing
Figure 3.1: Open loop V/Hz block structure.
the output voltage magnitude multiplier VS with increasing speed command. The
VOL−0 is an offset which provides voltage at startup. A simulation including the open loop motor controller and the ideal inverter was
64 CHAPTER 3. SIMULATION RESULTS built (for the fidelity required here, the ideal inverter fidelity was adequate). Simu- lation results are shown in Figure 3.2. In Figure 3.2, the top trace is the line voltage
Figure 3.2: Open loop simulation output. output in volts; the middle trace is the electrical angle in radians, and the bottom trace is the simulated motor speed in rpm. As desired, the line voltages are increased with the speed command. As is described in Section 6.2, this open loop controller was transferred directly into the motor lab and, after scaling the V/Hz gain and offset to the system, used for system checkout. The open loop controller enabled rapid development of the motor lab, and was used for the early checkout of many of the motor lab systems.
3.1.2 Field Oriented Control System Simulation
The FOC system simulations were performed using all three HSI models: the Ideal HSI Model, the Simple HSI Model, and the High Fidelity HSI Model. As is discussed in Section 2.2, the High Fidelity model is helpful in studying switching parameters;
65 CHAPTER 3. SIMULATION RESULTS
however the simulation time is very long, and it was only used when a high level of detail was required. The ideal inverter model was helpful for quick analyses, while the Simple model gave more realistic performance, as it includes switching effects. A pair of simulations were built using FOC, and including ideal and simple HSI models; results are shown in the following figures. In the ideal HSI inverter model, the commanded voltages are applied at the motor terminals without any PWM. The Simple HSI model is closer to reality, and includes switching features. One parameter which provides insight into the switching approach and its impact on system performance is the simulated DC current. Simulation results of the DC current and PWM switching under FOC using the Simple HSI model are seen in Figure 3.3. In the left hand plot of Figure 3.3, switch commands for switches
Figure 3.3: Idc and switch commands under FOC using simple HSI inverter model.
Sa (red), Sb (green), and Sc (blue) are shown from top to bottom, and DC current Idc (black) is shown in the bottom plot. The interactions are easier seen if the plots are laid on top of each other, as is done in the right hand plot, with Idc scaled for visibility. Here we see the switching implementation, taking place at the PWM frequency of 20 kHz; all switch commands are centered, with the highest duty cycle (switch C here) turning on first and off last. With each switch change, the DC current draw is different, as expected. One key result is that, although the PWM is happening
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at 20 kHz, change is made to the voltages and currents twice each switching cycle, explaining the 40 kHz seen in current and voltage spectra. Next, a comparison of the line voltages generated under the two different inverter models is presented in Figure 3.4. The left hand plot of Figure 3.4 shows line voltage
Figure 3.4: FOC System Simulation: line voltage with different inverter models.
VAB using the ideal HSI model (top, green) and the Simple HSI model (bottom, blue). Note that the simple model does provide a simulated voltage that is close to reality. The right hand traces are a close up of these simulated voltages near voltage crossover; note the differences in implementation. Also, consistent with the DC current discussion above, this switching is occurring twice per cycle. Finally, a comparison of the phase currents generated under the two different inverter models is presented in Figure 3.5. The top set of plots in Figure 3.5 use the ideal HSI model, and the bottom set uses the Simple HSI inverter model. The left hand plot shows a little more than one cycle of the simulated phase currents. The middle plot shows a close-up of phase C current, near the maximum value; at this range some switching effect is apparent in the Simple model current. The right hand plot is zoomed in again, and the current ripple due to switching is obvious in the bottom current (simple model). Note that, consistent with the DC current discussion above, this switching is occurring twice per cycle, and thus is at roughly 40 kHz.
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Figure 3.5: FOC System Simulation: phase current with different inverter models.
The FOC simulations were very helpful in enabling quick parameter and tuning studies for the FOC, and as is described in Chapter 6, once tested the simulated controller was directly transferred into the motor lab for motor drive. Additionally, the motor parameter validation was done using the FOC simulations, which was very helpful in the early tuning and setup work in DTC control.
3.1.3 Direct Torque Control System Simulation
The DTC system simulations were performed using the Ideal HSI Model and the Simple HSI Model. The author had no previous experience with DTC. It was clear from the research that implementing the hysteresis controllers and interpreting the outputs of look up tables in DTC would be very different from implementing the more familiar cur- rent loops and coordinate transformations of FOC. Thus simulation became very important. Validated motor parameters from the FOC studies (Section 6.5.3) were employed to attempt to provide realistic behavior. In order to assist with an under- standing of variables and parameters that were relevant in getting the DTC controller operational, a number of plots were developed which facilitated understanding of the controller operation, interpretation of relevant variables, and development of diagnos-
68 CHAPTER 3. SIMULATION RESULTS tics which useful in defining appropriate tuning. One such plot, based on a successful simulation of DTC driven PMSM under the simple HSI model, is shown in Figure 3.6. The sector (magenta) used in DTC
Figure 3.6: DTC system simulation analysis plot. control is plotted; note it is stepwise, integer values between 1 and 6, as expected. The simulated speeds (commanded, red and actual, green) in Figure 3.6 are in RPM, scaled by 1/10 to fit on the same plot as the other data. Note that the actual speed does not track perfectly. The torques are in Nm: commanded torque T ∗ is shown
∗ in blue, and load torque Tload is dashed black. T is the output of the outer loop controller; one key result of these simulations was the importance of its saturation level as a tuning parameter. Load torque is constant in this simulation. Note that,
∗ when the motor achieves the speed set point, T matches Tload as expected. These plots were used again in hardware implementation, as discussed in Section 6.6.2. Note the similarities in the commanded torque and speed behavior between Figure 3.6 and data collected in the motor lab of operating motor under DTC shown in Figure 6.14.
Two items of interest are Hψ, the limit of the flux hysteresis comparator, and the impact of delay in the system. Once the initial DTC system simulation was
69 CHAPTER 3. SIMULATION RESULTS
operating, sets of simulations were run to study these effects. The results are shown in the following figures. One metric which provides insight into system performance is the stator flux linkage estimate. Plots of the estimates are shown in Figure 3.7. Flux estimate for
Figure 3.7: Simulated stator flux linkage estimation plots. the baseline DTC system is shown on the leftmost plot of Figure 3.7; the middle plot is the result of a 5x increase in the value of Hψ, and the right hand plot uses the standard Hψ, but includes a delay in the simulated system. Note that the increase in
Hψ leads to a thicker estimated flux linkage plot (indicating the wider flux excursions expected with a larger switching gap), but the plot is still circular; the added delay features wider excursions in flux and also distortions in the circular plot. These effect of these changes is also visible in the phase currents, shown under the same simulation conditions in Figure 3.8. Again in Figure 3.8 the baseline system is on the left. An increase in Hψ leads to higher di/dts, as expected, and this shows in the middle plots. In the right hand plots, with the added delay, the higher di/dt is also visible, and distortion is visible in the current waveforms. Both of these effects, the increased di/dt and the distortions in the current and the estimated flux, are visible in the hardware system. As is discussed in 6.6.3.3, a number of alternate flux estimation schemes were studied during this effort; one such approach used an extended Kalman filter (EKF).
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Figure 3.8: DTC simulated phase current comparison.
The plot in Figure 3.9 is the result of one such study.
Figure 3.9: DTC estimated angle simulation using EKF.
One benefit of interest of the EKF was the potential to estimate rotor position, possibly eliminating the need for an encoder. In Figure 3.9 the rotor angle is in green, and the estimated angle from the EKF is in blue. As can be seen in this simulation, the EKF was soon able to match the rotor position from the motor model. One final item worth discussing in the DTC simulations is the switching speed under DTC. Figure 3.10 is a magnified view of one of the phase currents in the above baseline DTC simulation. As can be seen in the figure, the current changes direction regularly in this particular DTC implementation, and the switching timing is regular as expected. New voltage vectors are output from the DTC controller at
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Figure 3.10: DTC system simulation phase current. the PWM loop frequency, here 20 kHz, and the switching accordingly occurs regularly at 1/20kHz = 50 µs; this is in sharp contrast to the FOC switching under 20 kHz PWM control. The DTC modeling was very helpful in getting the motor running reliably un- der DTC in the motor lab. Once this was achieved, efforts to improve performance were shifted to diagnostics performed on measurements made on the hardware sys- tem. These studies and the corresponding changes in the controller, estimators, and support hardware which enabled performance improvement are detailed in Section 6.6.
3.2 Resonant Inverter Simulations
Simulation was key in the development of the resonant inverter. The resonant com- ponents were modeled in PSIM, and the control elements were modeled in Simulink. The two key inverter PSIM models are the resonant elements only model, shown in Figure 4.14, and the entire ACRLI, with clamp and resonant components, shown in Figure 4.21. Models were developed for the control of two key switches in the resonant inverter:
72 CHAPTER 3. SIMULATION RESULTS the main switch control, in Section 4.2.3.2, and the clamp switch control, in Section 4.2.3.3. These models provided insight into current shape, timing, logic required for these functions, and results were used in the hardware design of these two subsystems. Results were also helpful in diagnosis of hardware performance. During development and testing of the ACRLI hardware, loops were added to measure these current values; simulations were helpful in validating measurement, as discussed in Section 4.2.4.5. The resonant inverter simulations were also used in component sizing; notably in the clamp capacitor Cc sizing. Simulations performed in Section 4.2.4.4 helped describe behavior observed in the ACRLI in hardware, and to understand tradeoffs in the clamp capacitor size. The resonant inverter simulation was also helpful in interpreting non-ideal perfor- mance. For example, modeling of the stray inductance as done in Section 4.2.4.6 was able to adequately explain behavior of the source current, which varied considerably from the initial models.
73 Chapter 4
Inverter Development
This chapter covers the inverter design and development. Two types of inverter were studied: a hard switching inverter (HSI), and a resonant inverter; the selected resonant inverter configuration is the active clamped resonant link inverter (ACRLI). The HSI is used for the baseline system, under field oriented control (FOC), designated the FOC-HSI configuration. The ACRLI inverter is implemented in the research system, using direct torque control (DTC), called the DTC-ACRLI system. The development of both inverters is described. Each of these inverters are incorporated into the Motor Lab as shown in Figure 4.1. The inverter subsystem includes the inverter itself, along with the associated volt- age and current sensors. Note that the voltage sensors are used only in some configu- rations of the DTC-ACRLI system; they are not used at all on the FOC-HSI system. The other critical system components are the motor under test (MUT), encoder, and the controller. Inputs to the inverter subsystem are the commands (switch commands plus the New Command Available signal, used in the ACRLI configuration) and the DC power. Outputs of the inverter subsystem are the signal level (processed current and
74 CHAPTER 4. INVERTER DEVELOPMENT
Figure 4.1: Inverter Subsystem within Motor Lab. voltage sensor values) and the three phase motor drive. The inverter general requirements are summarized in Table 4.1.
Table 4.1: General Inverter Requirements Requirement Characteristic Level Units 1 Maximum DC Voltage 42 V DC 2 Output Current 5 A rms 3 Minimum Switch Frequency 20 kHz 4 Digital Interface Voltage 0 - 5 V DC
4.1 Hard Switching Inverter Implementation
The first of two inverters studied is the HSI, a voltage source inverter (VSI); the designation “hard switching” is used to distinguish it from the other inverter, the ACRLI, which is a resonant link (soft switching) inverter. A high level schematic of the HSI subsystem is shown in Figure 4.2. This constitutes the “Inverter” and “Current Sensor” blocks of the inverter subsystem in Figure 4.1. The HSI has 6 input commands, the top and bottom commands for each of the
75 CHAPTER 4. INVERTER DEVELOPMENT
Figure 4.2: HSI High Level Schematic. switches. The HSI implemented for this project was hardware of convenience: a subsystem that had been built for several projects, which provides a number of key functions, and facilitates straightforward incorporation into the larger motor drive system, all in one box. The six switch inverter at the heart of this subsystem is a PowerEx PM300CLA060, which is specified for 600V and 300A, easily meeting the requirements of the inverter. The unit employs six IGBTs with a maximum switching frequency of 20 kHz. Note that the HSI subsystem developed for this effort is directly incorporated into the resonant inverter, which is discussed in Section 4.2. The functions incorporated into the HSI subsystem include the buffer/driver, a pair of current sensors, a set of DC supplies, and appropriate connections. The buffer/driver circuits provide voltage level shifting and drive capabilities that allow command signals to be fed directly from the controller into the HSI subsystem from many controller types. The current sensors provide feedback for phase A and B output currents directly to the controller, at appropriate signal levels. The DC supplies provide power to the buffer/driver and the current sensors, enabling a single 120 VAC power requirement for the support functions. Connections include BNC connectors for command inputs and the current sense outputs, and screw-terminals for the motor
76 CHAPTER 4. INVERTER DEVELOPMENT connection. Note that the current sensor originally implemented in the system was sufficient for FOC-HSI implementation. However, during the course of performance testing, it was found to be insufficient for the DTC-ARCLI configuration, and was replaced. This is discussed in Section 6.6.4.3. A schematic of the power stage of the six switch inverter, including 6 pairs of IGBTs and free-wheel diodes, is shown in Figure 4.3, and a photo of the HSI subsystem is included in Figure 4.4.
Figure 4.3: Schematic of six switch inverter power stage.
The Voltage Sensing subsystem was not part of a standard combined HSI sub- system, as voltage sensing is only used in a subset of system configurations. Voltage sensing was developed separately for a different project, in its own packaging. A photo of the voltage sense subsystem is included in Figure 4.5.
4.2 Resonant Link Inverter (ACRLI) Design and
Development
Past implementations of advanced motor drives have utilized voltage fed, hard switch- ing inverters [4]. This is a common approach, and is typical in many trade studies
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Figure 4.4: HSI subsystem. in the turboelectric propulsion area. As discussed in Section 1.4.2, the soft switch- ing resonant inverter provides a possible improvement over traditional voltage fed, hard switching inverters, through lower switching losses, higher frequency operation, reduced cooling requirements, reduced EMI, and reduced filter size. The hope is that these will translate to improvements of Key Performance Parameters in an EAP system, specifically improved efficiency and specific power. In this chapter, first the functions of all of the subsystems of the inverter are described. Next, each of the subsystems is simulated where appropriate, then designed in hardware, then a breadboard version is built and tested in hardware. Next, all of the subsystems are interconnected and tested under a load circuit. Finally all of the prototype subsystem circuits are combined into a printed circuit board design. Five topics are discussed in this Section: resonant inverter requirements, the reso-
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Figure 4.5: Voltage Sense Subsystem. nant inverter topology selection, the ACRLI design, ACRLI testing, and the ACRLI control circuit printed circuit board design.
4.2.1 Resonant Inverter Requirements
The set of requirements used in defining the resonant inverter are summarized in Table 4.2.
Table 4.2: Resonant Inverter Requirements Requirement Characteristic Level Units 1 DC Clamp Voltage 50 V DC 2 DC Link Minimum 0 V DC 3 Output Current 5 A rms 4 Switch Frequency ≥20 kHz 5 Interface 0 - 5 V DC
The DC Clamp Voltage is specified at 50V, which is based on the voltage limits of the PMSM. The DC Link Minimum is set to zero volts, as this is the desired voltage
79 CHAPTER 4. INVERTER DEVELOPMENT to enable zero voltage switching. The Output Current is based on the PMSM input current limit value. The switch frequency limit is set to be greater than or equal to the HSI frequency limit. The Interface is set up to work well with the digital outputs of the controller.
4.2.2 Resonant Inverter Topology Selection
In addition to the requirements summarized in Table 4.2, additional goals were set for the resonant inverter: it was desired that a topology with a minimum parts count and a relatively simple control algorithm be selected. A large number of resonant switching topologies has been discussed in the liter- ature. In order to assist in selecting an appropriate topology for this research, an effort was undertaken to identify and classify available topologies; this classification was then used in selection of a topology which met the desired requirements. A diagram classifying published topologies according to mode of operation was presented in [8]. A version of this diagram, simplified for use in this discussion, is presented in Figure 4.6. AC-AC converter topologies, at the top of the diagram in Figure 4.6, can be divided into three broad categories: AC-link converters, direct AC-AC converters, and DC link converters. Examples of direct AC-AC converters include cycloconverters and matrix converters. AC-link converters employ a resonant circuit to link the power supply converter to a load converter. DC link converters can be hard switching or soft switching. As our work group’s traditional experience is with DC link inverters, the DC link topology is a natural choice for the research topic. This will also allow direct comparison to the baseline system, a DC-link HSI FOC system. The soft switching DC Link Inverters can be divided into two major types: pole commutated inverters (PCI) and resonant DC link inverters (RDCL). The RDCL topology was selected over the PCI topology because the PCI has multiple resonant
80 CHAPTER 4. INVERTER DEVELOPMENT
Figure 4.6: Soft Switching Converter Topologies. circuits, one on each pole, requiring a larger number of active and passive components than the RDCL, which has only a single resonant circuit. The next level of Figure 4.6, the RDCL inverters are subdivided into two groups: the basic RDCL (BRDCL) and the parallel resonant DC Link (PRDCL). The PRDCL includes a series switch in the DC link, which applies link voltage to the inverter when the switch is closed, and enables a resonant transition and zero voltage switching when the switch is opened. Since implementation of the BRDCL was possible with fewer devices, the BRDCL was selected. The last tier of Figure 4.6 shows three possible approaches: the quasi-resonant RDCL (q-BRDCL), and active clamping and passive clamping BRDCL.
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The q-BRDCL topology certainly has benefits - resonance only occurs during switching transitions, enabling use of PWM techniques - but this additional func- tionality is achieved through the inclusion of additional circuitry and more complex controls. These more complicated resonant inverter schemes can potentially increase cost and decrease the reliability of the system through the required additional parts and more complicated control apparatus. This additional complication would also not necessarily provide benefit in this study, as the goal of this work was to pair the discrete switching of the resonant inverter with the discrete switching of the DTC. Unfortunately, one potential issue exists with the selected topology: in the BRDCL, the line voltage generated can rise to more than twice the voltage of the DC link. Uncontrolled, this high link voltage could cause damage; thus a voltage clamping sys- tem is used. Active clamping was selected; this approach requires fewer parts (only two additional parts in the resonant circuit), and allows design and control flexibility that the passive scheme does not. Based on these considerations, the Active Clamped Resonant DC Link Inverter (ACRLI) topology was selected for use in this work because it provides a topology which meets the additional goals; e.g. a lower parts count and a simpler control scheme. A schematic of the ACRLI topology is shown in Figure 4.7. Note that there are five components required in addition to the six switch inverter: in the resonant
circuit, components Lr and Cr plus the main switch Sm; and in the clamp circuit the clamp capacitor Cc and clamp switch Sc.
4.2.3 ACRLI Design
The ACRLI inverter high level schematic is presented in Figure 4.8. A description of each of the ACRLI subsystems presented in the figure follows. The Resonant Circuit Board inputs DC and outputs a resonant link voltage, clamped to less than double the DC link voltage value, and resonating to zero each cycle to allow zero
82 CHAPTER 4. INVERTER DEVELOPMENT
Figure 4.7: ACRLI Schematic.
voltage switching at the 6 switch inverter circuit. The resonant board contains the
two switches (main switch and the clamp switch), the resonant components (Lr and
Cr), and the clamp capacitor Cc. Main Switch Control drives the main switch in the resonant board. The switch is on when two conditions are met: the voltage condition and the current condition. It is turned on when the link voltage has reached zero volts (the voltage condition), and left on until the resonant inductor Lr has been charged sufficiently to drive the motor in the following resonant cycle (the current condition). Measurements of the link voltage along with a signal from the current predict board are used in combination with a logic circuit to ensure that these conditions are met. Clamp Switch Control is used to limit the link voltage. Based on measurements of the link voltage, the clamp switch is turned on to route current to and from the clamp capacitor when the link has reached desired voltage. The ACRLI Latch is a two stage latch circuit, operating on the switch commands from the control computer. The commands are latched into the first stage when a signal is received from the control computer stating that a new output command
83 CHAPTER 4. INVERTER DEVELOPMENT
Figure 4.8: ACRLI High Level Schematic.
has been issued; this latched command, called SABC L1, is passed to the input of the
Current Predict circuit. SABC L1 is latched into the second stage, called SABC L2, when a signal indicating that the link voltage has reached zero volts is received from the Main Switch Control. SABC L2 is passed on to the Six Switch Inverter, to ensure zero voltage switching occurs. The Current Predict circuit provides a prediction of the current required at the resonant link output during the next control loop, based on the controller switch commands and the motor phase currents. The output predicted current is passed on to the Main Switch Control. The Dead Time circuit is used to prevent shoot-through, caused by accidental simultaneous turn on of a pair of switches in any leg of the Six Switch Inverter. Ideally enforcing ZVS switching in the Six Switch Inverter would prevent shoot through automatically; this circuit was included as a safety for initial testing, and remained in place as it had no deleterious impact on system performance. Six topics are discussed in this Section: the resonant inverter design, the main
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switch control circuit, the clamp switch control circuit, the ACRLI latch design, the current predict circuit, and the dead time circuit.
4.2.3.1 Resonant Circuit Design
In this section, the resonant components inductor Lr and capacitor Cr are specified.
Clamp capacitor (Cc) sizing is done separately in Section 4.2.4.4.
Introduction The DC bus (consisting of the DC supply plus the DC cap) provides the power input to the Resonant Circuit Board. The resonant board contains the two switches
(main switch Sm and the clamp switch Sc), the resonant components (Lr and Cr), and the clamp capacitor Cc. A schematic of the Resonant Circuit Board is provided in Figure 4.9.
Figure 4.9: Resonant Circuit Board schematic.
The purpose of the Resonant Circuit is to generate a resonant link voltage to
supply the six switch inverter power: Sm is turned on when the link voltage is zero,
allowing inductor Lr to charge; once it reaches sufficient current, Sm is opened allow- ing the bus voltage to resonate, rising then returning to zero. This zero voltage level enables zero voltage switching (ZVS), also called soft switching. This link voltage is
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to return to zero volts each cycle to allow ZVS in the Six Switch Inverter, and the link voltage is to be clamped to less than double the DC link voltage value to reduce voltage stresses in the system [7]. The resonant components are sized by first developing relationships for power
losses of Lr and Cr as a function of the passive and switch component parameters, along with the desired ACRLI operating conditions. Next, these relationships are
used to size Lr and Cr by identifying a minimum loss case for these components, within practical component values. The losses are broken into five categories, listed below, which will discussed in the following sections:
1. Main device conduction losses (Pcond−main)
2. Main device switching losses (Psw−main)
3. Clamp device conduction losses (Pcond−clamp)
4. Clamp device switching losses (Psw−clamp)
5. Resonant component equivalent series resistance (ESR) losses (Pesr)
A pair of references were used for insight and equations to describe the losses for soft switched inverters in the literature [38] and [39]. Three equations will be helpful in the following discussion. First, the resonance frequency of an ideal resonant circuit is the familiar
1 fo = √ (4.1) 2π LrCr
The second equation defines the clamping constant, k:
V k = link−pk (4.2) VDC
where Vlink−pk is the peak value that the link voltage is clamped to, and VDC is the DC supply voltage.
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The third relationship relates the resonance of the clamped circuit to the clamping constant[17],
1 fr = √ (4.3) k(2−k) √ 2[arccos(1 − k) + k−1 ] LrCr In hardware, the clamp value can range between about 1.2 and 2.3; however, values in the middle of this range are more desirable. A clamp value of 1.0 is not practical; in this case the link voltage would only ring to the DC bus value. At a value of 2.0 the link voltage rings to double the DC bus value, which is beyond the upper desired limit. Note that at values of k approaching 1.0, the relationship in brackets grows extremely large, implying a very low ringing frequency in this case (as is seen in hardware); and as k approaches 2.0, the relationship in square brackets in the denominator of equation 4.3 asymptotes to π, and thus theoretically fr reduces to the expression for an undamped resonant circuit (equation 4.1). A plot of the ratio of the clamped to unclamped frequency as a function of k is shown in Figure 4.10. Note that, as expected, the clamped frequency is very low as k approaches 1, and approaches unclamped frequency at k = 2.0.
Figure 4.10: Ratio of clamped to unclamped frequency versus k.
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Main Device Conduction Losses
The Main Device Conduction Losses, Pcond−main, are the conduction losses in the switches in the six switch inverter. These losses are dominated by the load current and the forward voltage drops. The load current is assumed to be a sinusoid of peak
value Io, and the forward drops across the main switches and diodes, assumed to be
equivalent, called VFW . Note that these losses are almost independent of Lr and Cr. For a six switch inverter these losses are
6I V P = o FW (4.4) cond−main π
Main Device Switching Losses The switches in the ACRLI are switching under zero voltage switching. Turn- on switching losses are assumed to be zero; however, under certain conditions, the voltage across the device begins to rise slightly before current drops to zero. This results in some switching power losses, but much lower than the switching losses in the traditional hard switching scheme. Based on these assumptions, the main device switching losses are
2 2 Io toff fr Psw−main = (4.5) 48Cr
where toff is the device turn off time.
Clamp Device Conduction Losses The current in the clamp switch can be modeled as a constant di/dt ramp, driven by the clamp voltage. Using this model along with the assumption that switch and diode losses are equal, the expression for clamp conduction losses is
V k(2 − k)V C f P = DC FW r r (4.6) cond−clamp k − 1
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Clamp Device Switching Losses In an analysis similar to that done for the main device switching losses, the clamp losses are calculated based on turn off losses, resulting in the following expression for clamp switching losses
2 2 VDC toff k(2 − k)fr Psw−clamp = (4.7) 24Lr
ESR Losses Both of the references assumed that the ESR of Cr was negligible, and the losses are dominated by the ESR of Lr. This loss is divided into two components: losses arising from the DC load current and from the AC circulating current. Based on worse case conditions and an assumption of modulation strategy, the expression for ESR losses is
1 Pesr = (4.8) 2p 2 p 2Q(Io Lr/Cr + VDC Cr/LR) where Q is the quality factor of the resonant tank.
Resonant Component Design Process
The first step of the design process is to define Lr and Cr, by finding a mini- mal power loss configuration. Next, actual inductor and capacitor components are designed and selected respectively, based on practical concerns. Minimal power loss resonant components were found by first assembling all of the equations developed in the previous sections into a Matlab script. Next, a set of parameters was developed, based on initial ACRLI performance requirements and component specifications, and collected in Table 4.3.
These parameters were selected as follows. Resonance frequency fr was selected to be 60 kHz; this is three times greater than the upper limit of the inverter when run
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Table 4.3: Resonant Inverter Parameters Requirement Characteristic Value Units 1 VDC 28.5 V 2 fr 60.0 kHz 3 Io 5.0 A 4 VFW 1.5 V 5 toff 2.5 us 6 k 1.4 V/V 7 Q 180.0
in HSI configuration, taking advantage of the ZVS, intended to provide the improved waveform shape, especially important due to the low inductance of the motor. The
VDC and k values were calculated to provide clamping, and a peak link voltage of 40V, typical for the MUT. Current outputs were based on motor specifications; and
a relatively high Q was assumed based on the references. Switch parameters toff and
VFW came from the HSI data sheet. With these parameters included, the script was run, plotting the various losses vs.
Lr (the script is included in Appendix B). The loss plot is shown in Figure 4.11.
Figure 4.11: Loss plot as a function of Lr.
From the plot, we see a minimum in the total losses at about 20 uH, and so this value was selected for Lr. Cr is then found using this inductance and equation 4.3,
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Table 4.4: Loss table at resonant circuit design point Component Loss [W] Pcond−main 14.3 Psw−main 1.0 Pcond−clamp 1.0 Psw−clamp 0.5
resulting in Cr = 0.19 uF. Based on these selections, a loss table was assembled at this design point in Table 4.4.
Note that at the selected Lr and Cr, the main switch losses dominate; this is expected as they carry the load current. Also note that the main switch conduction losses are 14 times larger than the switching losses, as expected due to the ZVS configuration.
Design of Resonant Inductor (Lr) The resonant inductor is required to carry inverter current and the resonant cur- rent. Resonant frequency in the initial design is specified at 60 kHz, however it is desired to leave the ability to increase this frequency during parameter studies, as discussed in Section 7.1. So in addition to the requirement of low hysteresis and eddy current losses, minimal impact on inductance value under operating frequencies in excess of 100 kHz is also desired. Based on this, the inductor core selected was a distributed gap toroidal core from Magnetics; this core is made from an alloy powder (81% nickel, 17% iron, and 2% molybdenum) [40]. The inductor design process, based on manufacturer recommendations, was as follows. First, based on the estimated current, and the desired inductance (here 20
uH, the Lr design) a range of acceptable cores can be selected. Next, a table was made of the acceptable cores, and in each case the number of turns needed for the desired inductance was calculated; then the bias in Amp-Turns was calculated for each core, and a correction applied to the turn count, if necessary, to account for bias effects. Finally, considering winding factor, and current, wire was selected.
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The core for the final design (Magnetics 55930) was selected for low frequency impact on permeability, about a 1% drop at 100 kHz, and low impact of temperature, less than 1% change at 100◦ C. Based on anticipated currents, with margin, 18 AWG magnet wire was specified for the inductor. Single layer winding approach was used; using this approach the number of turns is limited by the core size, but the advantages of interest included lower winding capacitance, more repeatable parasitics, and a good cooling configuration. If desired for testing purposes, the inductor could be adjusted by addition or removal of turns; one fewer turns would theoretically yield 16 uH, and one additional turn 23 uH. A set of inductors was wound, and tested on and inductance meter. The measured inductance was 20.5 uH, very close to the desired 20 uH target.
Selection of Resonant Capacitor (Cr)
Based on the design example, the resonance capacitor Cr was 0.19 uF. Two 0.1 uF low ESR film capacitors in parallel were selected for this application. The advantage of the two in parallel is that the resonance frequency could be modified fairly significantly and easily by the disconnection of one of the capacitors, halving the Cr value. This approach was used in the parameter studies (Section 7.1).
Selection of Clamp Capacitor (Cc)
The clamp circuit limits the link voltage, but since Cc charges during clamping, some voltage rise does occur. Specification of the desired link voltage rise during clamping can be used to specify Cc.
The voltage rise during clamping, ∆Vcl, can be found using the expression [39]
s 2 2 Lri1 ∆Vcl = [(k − 1)VDC ] + − (k − 1)VDC (4.9) Cc where i1 is the reversal current of the inverter bus. Assuming a desired clamp voltage
92 CHAPTER 4. INVERTER DEVELOPMENT rise limit of 2V and a typical current reversal of 2A, solving equation 4.9 sets the initial value for Cc at 1 µF.
Resonant Board Design A high level schematic of the final Resonant Circuit Design is shown in Figure 4.12.
Figure 4.12: Final resonant circuit design schematic.
Note that in addition to the resonant and clamp components and the switches, a current sensor is included for feedback of the Main Switch Control. The schematic for the Resonant Circuit is in Appendix C.
4.2.3.2 Main Switch Control Circuit
As the name implies, the Main Switch Control circuit drives the main switch on the resonant board. The main switch is turned on when two criteria are met: the zero link voltage condition and inductor current condition. A schematic of the main switch and resonant components (without the clamp), is shown in Figure 4.13. Main switch control operation is as follows. The main is turned on when the link voltage resonates to zero (zero link voltage condition), charging the resonant
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Figure 4.13: Main switch and resonant components. inductor. The resonant inductor is then charged until the desired current is reached - this current includes the inverter current required to drive the motor for the next control loop, called I* , and the current required to ensure any link losses are overcome
so that voltage across Cr will return to zero at the end of the resonant cycle, called
IRmin. In the ACRLI circuit the resonant current can be set arbitrarily, to IR. The
inductor current condition is met when ILr is greater than I* + IR, and at that point the main switch is turned off [16]. Measurements of the link voltage and a signal from the Current Predict board are used in combination with a logic circuit to ensure that these conditions are met.
Main Switch Control Simulation A main switch control simulation was built including both power electronics ele- ments and control elements. This was achieved via co-simulation of the power com- ponents in PSIM (a simulation and design tool for power electronics applications) and the control elements in Simulink. The Main Switch Control power components closed loop simulation is shown in Figure 4.14. Resonant L and C are included, along with the main switch. A small series resis-
tance is included to simulate losses. The link voltage, Vout, and the resonant inductor
current, IL, are passed onto the Simulink control code. The Main Switch Control sim- ulation is helpful in demonstrating the various voltages, currents, and logic signals
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Figure 4.14: Main Switch Control power components simulation.
required for main switch operation (note that this simulation was performed early in
the design phase - the design values of components, e.g. VDC , Cr, Lr, etc. are not those of the baseline design - however, the simulation is very helpful in understanding function). The output of the simulation shown in Figure 4.15.
Figure 4.15: Main Switch Control operation.
The top plot shows link voltage, and the second plot Lr current. The third plot
shows the switch conditions: solid line is when the current condition is met ILr is
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lower than I* + IR), and the dotted line shows then the zero link voltage condition is met. The logical AND of these two signals demonstrated main switch on-time, and the resultant main switch current is shown in the last plot. Note that the link voltage rings to zero, as intended, and Lr is charged appropriately. The bottom plot displays main switch current.
Main Switch Control Hardware Implementation The first step in the development of the resonant converter hardware implemen- tation was to perform simple testing on an open loop resonant circuit. The design value resonant components Lr and Cr were used, along with the main switch itself (the component selected for the main switch as well as the clamp switch was a FET, model IR17N20, with high switch speeds and more than sufficient current capability; the data sheet of the FET is found in Appendix E). For flexibility, a function gener- ator with sufficient output was used to drive the FET, and for this initial testing a resistive load was used. A photo of the main switch control initial test setup is shown in Figure 4.16. Note the spread-out configuration of this initial test - one lesson learned from this initial testing was that stray inductance is a problem; in order to alleviate this, the components were placed much closer together in the later version resonant circuit. Use of the function generator allowed considerable flexibility, allowing independent control of the frequency and duty cycle. Approximately correct control of the resonant link was achievable, as seen in Figure 4.17. With this initial configuration, the first resonance was achieved. The switch drive firing (a little late here) in yellow, we see the inductor current charging (purple) and the link voltage (green) is seen to reach zero. Next, a closed loop hardware circuit was designed. The logical conditions were defined using two comparator circuits. For the voltage condition, link voltage is measured and scaled (Vls−0), and compared to a scaled zero voltage level (V0ref ). For
96 CHAPTER 4. INVERTER DEVELOPMENT
Figure 4.16: Main Switch Control initial test setup.
Figure 4.17: Main Switch Control initial testing.
the inductor current condition, the desired current I* is added to IR, and the sum is
compared to the measured inductor current ILr using the second comparator. Then both signals are ANDed, and sent to a driver circuit. The functional schematic of the Main Switch Control is shown in Figure 4.18, and the schematic of the final design circuit is found in Appendix C. The Main Switch Control circuit was then built in breadboard, inserted in place of the function generator in the test setup, and tested. An oscilloscope trace of the output of this hardware design, the breadboard closed loop configuration, is shown in Figure 4.19.
97 CHAPTER 4. INVERTER DEVELOPMENT
Figure 4.18: Main Switch Control high level schematic.
Figure 4.19: Main Switch Control hardware test.
The two logical conditions (zero link voltage, orange, and Lr current, cyan) are shown alongside link voltage (green) and resonant current (blue). The main switch drive command is shown at the bottom (yellow). This figure demonstrates correct performance of the Main Switch Control circuit, using the correct resonant compo- nents and FET, in hardware. With this preliminary Main Switch Control circuit implemented and tested in hardware, work on the Clamp Switch Control circuit be- gan.
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4.2.3.3 Clamp Switch Control Circuit
Clamp Switch Control Operation In the RDCL inverter topology, the output is decoupled from the DC supply volt- age, so the resonance of the LC circuit can cause the link voltage to rise, potentially exceeding double the DC bus voltage, introducing undesired voltage stresses on the system. This problem is addressed by adding a voltage clamp to the circuit to limit the voltage overshoot. The Clamp Switch Control circuit drives the clamp switch, which is located on the resonant circuit board. Based on measurements of the link voltage, the clamp switch is turned on to route current to and from the clamp capacitor when the link has reached the desired voltage. A schematic of the resonant board, including the clamp switch and Cc, is shown in Figure 4.20.
Figure 4.20: Schematic of the resonant board, including the clamp switch and clamp capacitor.
Clamp switch control operation is as follows. The clamp switch is turned on when the link voltage reaches the desired clamping level, at which point current from Lr is shunted to the clamp capacitor Cc. The current in Cc then rings back, and once the link voltage drops below the desired clamp level, the clamp switch is turned off [17]. Measurement of the link voltage is used to determine the clamp switch condition.
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Clamp Switch Control Simulation Once again a simulation was built to test voltages, currents, switching, and signals for the clamp circuit. This simulation was closed loop, again done in PSIM co- simulated with Simulink, and included resonant components and the main switch. The power section of the simulation is shown in Figure 4.21.
Figure 4.21: Clamp Switch Control power components closed loop simulation.
The simulation includes the clamp switch and cap (Sc and Cc1 here, respectively) as well as the main switch and resonant components (called Sr, C, and L here). Note that, unlike in the Main Switch model, the resonant components and voltages here are set to those in the initial ACRLI design. Feedback signals passed on to the Simulink control program include Vlink and resonant current, IL. The output of the simulation shown in Figure 4.22.
The top plot of Figure 4.22 shows link voltage, and the second plot Lr current. The third plot shows the logic for the main switch (dashed blue) and the clamp switch (cyan). The resultant clamp switch current is shown in the last plot. Note that the link voltage again rings to zero, but is clamped to a much flatter level than if left to ring uncontrolled, as desired.
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Figure 4.22: Clamp Switch Control operation.
Clamp Switch Control Hardware Implementation Next, a hardware version of the Clamp Switch Control was designed. The same FET was used for the clamp switch as was used in the main switch; however, a different driver was required for the clamp, due to the placement of the switch. Unlike the main switch position, in which the source lead of the FET is tied to power ground, the source of the clamp FET is not; it is tied to Vlink. Thus an isolated gate drive, employing an internal opto-isolator, had to be used. Again a comparator was used
for the logic, comparing the scaled measured link voltage Vls−c to a reference voltage
Vclamp (set to a scaled kVDC , k being the clamp constant). A functional schematic of the Main Switch Control is shown in Figure 4.23; the schematic of the final design circuit is found in Appendix C. The Clamp Switch Control circuit was then built in breadboard, included with the closed loop main switch test breadboard, and tested. The test setup is shown in Figure 4.24; the Main Switch Control circuit is on the breadboard in the upper right,
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Figure 4.23: Clamp Switch Control high level schematic. and the clamp Control is the lower left breadboard.
Figure 4.24: Clamp Switch and Main Switch Control Test Setup.
An oscilloscope trace of the test results is presented in Figure 4.25. In Figure 4.25, the clamped link voltage is shown in green. Note that the top of the clamped voltage is not as flat as that in the simulation, due to stray inductance. This figure demonstrates correct performance of the Clamp Switch Control and the Main Switch Control circuits; however, due to the issues with stray inductance and potential noise due to the long lead lengths and the overall sprawl of the circuit, the decision was made to make brass board versions of the main and clamp circuits and the resonant board, with a tighter overall layout and improved grounding. After
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Figure 4.25: Clamp Switch Control hardware Test. updating the schematics and developing a bill of materials, technicians built these boards in accordance with the requirements. Due to schedule constraints these took some time to be built; in parallel design efforts continued on the next portions of the resonant inverter (ACRLI Latch, Current Predict, etc.), but the completed brass board versions are included here for continuity, in Figures 4.26 and 4.27.
Figure 4.26: Brass Board Resonant Circuit Board.
Figure 4.27: Brass Board Main and Clamp Control circuits.
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4.2.3.4 ACRLI Latch Design
The ACRLI only commands switching of the six switch inverter when the link voltage is zero. However, the link zero voltage timing is not synchronized with the output switching commands from the control computer. The purpose of the ACRLI latch is to act as interface, sending commands from the control computer to the six switch inverter at the proper time. A high level schematic of the ACRLI Latch is shown in Figure 4.28.
Figure 4.28: High Level Schematic of ACRLI Latch.
The ACRLI Latch is a two stage latch circuit. The commands for switching (SABC ) from the control computer are passed to the first latching circuit, and are clocked in when a change in the output command has been made. This is done via the New Command Available signal, implemented after a slight delay, which was included to ensure that the commands have settled, and to account for the dead time which is included on the switch signals in some controller configurations. The output of the
first latch, SABC L1, is passed to the input of the second latch, and also to the input of the Current Predict circuit. The second latch is clocked when the link voltage reaches zero, by the Vlink = 0 command from the Main Switch Control circuit. Output of the second latch is passed on to the six switch inverter via the deadtime circuit.
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ACRLI Latch Hardware Implementation A hardware implementation of the ACRLI Latch was designed using six D flip- flops, three for each stage. To ensure proper operation and sufficient speed, a test circuit was built, consisting of a pair of latches forming a single channel of the two stage latch circuit. The test circuit schematic is shown in Figure 4.29.
Figure 4.29: Schematic of single channel two stage ARCLI Latch design test circuit
The test circuit is driven by a signal generator. The D flip-flops only trigger on the positive-going transition of the clock pulse; therefore a clock pulse mid-cycle could be generated for the second latch with an inverter. By feeding the inverted output of the second latch into the input of the first, the outputs of the flip-flops toggle, testing circuit behavior without the need for additional circuitry. The breadboard for the test circuit is shown in Figure 4.30, and the oscilloscope output is in Figure 4.31.
Figure 4.30: Single channel two stage test circuit for ARCLI Latch design.
The top trace in Figure 4.31 is the clock; the second (orange) trace is the output
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Figure 4.31: Oscilloscope output, ACRLI Latch design test circuit, clocked at 1 kHz (left) and 200 kHz. of latch 1, and the third is the inverted output of latch 2. The left case is clocked at 1 kHz, the right is at 200 kHz, demonstrating that the latching works correctly at desired frequencies. This provided confidence in the design approach, and the full three channel ACRLI Latch circuit was built using this design. A breadboard of this three channel circuit is shown in Figure 4.32.
Figure 4.32: Full Three-channel ACRLI Latch breadboard circuit.
The schematic for the final ACRLI Latch circuit is included in Appendix C.
4.2.3.5 Current Predict Circuit
For correct operation, the ACRLI requires a prediction of the current that will be needed at the input of the six switch inverter during the next control loop. Providing this prediction is the function of the Current Predict circuit. The output predicted
106 CHAPTER 4. INVERTER DEVELOPMENT current is passed on to Main Switch Control. The prediction is made based on knowledge of the controller switch commands for the next loop, and the motor phase currents [41]. An example illustrates this approach, seen in Figure 4.33.
Figure 4.33: Example current prediction schematic.
In this example, the six switch inverter and motor are depicted. The top switch in leg A is on, as are the bottom switches of legs B and C; the opposite switches in the legs are off, in accordance to the switching rules. The predicted input current in this case is
∗ I = Ia (4.10)
Since the motor currents sum to zero, the following expression is also valid
∗ I = −Ib − Ic (4.11)
Examining all eight legal switch states provides us with the table of predicted six switch inverter input currents. These are summarized in Table 4.5 [41]. Switching rules require that one switch be on and the other off in each leg; notationally a 1 in
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Table 4.5: Switch states and predicted six switch inverter input currents ∗ Vector SA SB SC I 0 0 0 0 0 1 1 0 0 ia 2 1 1 0 ia + Ib = −ic 3 0 1 0 ib 4 0 1 1 ib + Ic = −ia 5 0 0 1 ic 6 1 0 1 ic + Ia = −ib 7 1 1 1 0 the Switch State column indicates the top switch in that leg is on (and the bottom is off), and a 0 indicates that the bottom switch in that leg is on (and the top is off). The current prediction is implemented in hardware as shown in the Current Pre- dict High Level Schematic shown in Figure 4.34.
Figure 4.34: Current Predict High Level Schematic.
Measured phase currents are input to an analog math circuit; this circuit consists of op amp summing circuits which generate the required current summations. These sums are passed on to an analog multiplexer, addressed via the switch commands to pass the correct current sum to the output; this is the I∗ command, which is then passed on to Main Switch Control.
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Current Predict Simulation The Current Predict algorithm shown in Figure 4.34 was simulated by addition of the algorithm to the PSIM/Simulink model for a FOC controller using the HSI inverter. Of course, this is not a practical configuration, as it used FOC instead of DTC; but it was convenient, and helpful for verification of the current prediction functionality. The PSIM power model is shown in Figure 4.35.
Figure 4.35: PSIM model used for current predict testing.
In the PSIM model a measurement was added on the input bus, called IDC ; this is analogous to the I∗ command in the ACRLI system. The current prediction code output was compared to the simulated IDC , shown in Figure 4.36. The top plot shows simulated phase currents, and the bottom plot shows the simulated input current (red) and the output of the simulated Current Predict circuit (green). Note the close agreement. Obviously in practice this will be implemented on DTC-ACRLI system, so it is expected that the predicted currents to have somewhat different shapes, but this simulation achieves the desired goal, demonstrating that
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Figure 4.36: Current Predict simulation output. the algorithm works well. A hardware design approach for the Current Predict circuit is provided in [42]. A quad op-amp is used to perform the summations of current signals, and an eight channel analog multiplexer circuit is employed to select the correct current sum. A breadboard version of the circuit was built and tested as described in the ref- erence. Early bench testing of the analog math circuit showed poor performance of the summation function, at desired frequencies and amplitudes, using the described op-amp (LM324). Therefore, a quad op-amp with significantly higher slew rate was selected, the LF347, and this new op-amp performed well. Input signals in excess of 100 kHz were checked; all eight addresses were checked, and all summations were completed correctly. The breadboard is shown in Figure 4.37. The final hardware test for the Current Predict subsystem was done by connecting the breadboard to the motor test rig. The resultant oscilloscope trace is shown in Figure 4.38. For this final Current Predict hardware test, the circuit was used off-line to predict input current to the HSI inverter driving the PMSM motor; the current measurement
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Figure 4.37: Breadboard Current Predict Circuit.
Figure 4.38: Current Predict circuit test on motor. and switch commands being used to drive the motor were also input to the Current Predict breadboard. Additionally a current probe was attached to the HSI DC input (link) current lead, and this measurement was compared to the Current Predict (I*) output. In Figure 4.38, the measured link current (pink) and the I* signal (cyan) are in very close agreement, verifying performance of the Current Predict breadboard circuit. The final design for the Current Predict circuit is shown in Appendix C.
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4.2.3.6 Dead Time Circuit
The output of the ACRLI Latch, SABC L2, is the controller switch commands syn- chronized to Vlink = 0. There are six commands in all - the top and bottom switch commands for each of the three legs of the inverter. The purpose of the Dead Time Circuit is to prevent shoot-through; that is, to ensure the top and bottom switches in the same inverter leg are not on at the same time. Since ZVS is implemented in the link voltage in this configuration, shoot-through prevention should be provided automatically; the dead time circuit was included as a safety precaution to prevent issues during initial testing, and was left in place as it did not impact performance. Dead Time Circuit is implemented with six AND gates; the high level schematic for one channel is included in Figure 4.39.
Figure 4.39: High level schematic, single channel of Dead Time Circuit .
The inputs of the Dead Time circuit, from the ACRLI Latch, are routed into a pair AND gates, each with an RC network on one input. Outputs go directly to the drivers of the Six Switch Inverter. Switching requirements state that one switch per inverter leg is on and the other is off; the RC-AND gate configuration ensures that an OFF command is implemented immediately, while and ON command is slightly delayed by the RC. Thus turn-off of either switch in each pair always precedes the turn-on of the other switch, preventing a shoot-through condition as desired.
Dead Time Circuit Hardware Implementation
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Table 4.6: Dead Time Component Testing T est R(kΩ) C(nF ) Delay(µs) τ = RC 1 10 0.23 2.0 2.3 2 5 0.23 1.1 1.2 3 5 0.32 1.5 1.6 4 10 0.32 2.6 3.2
The first step in hardware implementation was to select the R and C values for the circuit. The input voltage required to turn on the AND gate (given the selected Vdd) is available in the datasheet, and indicate that turn-on should occur at about one RC time constant. However, to be safe a circuit was set up to measure actual delay timing, to ensure other factors did not impact performance. A sample oscilloscope trace from the Dead Time Circuit test circuit is shown in Figure 4.40.
Figure 4.40: Dead Time Circuit Test Timing.
In the test circuit, the switching command output, SAO (green) is seen to turn off directly following the input command SAL2 (yellow); however, the turn-on is delayed, as desired. This test was performed for various R-C combinations, and the results of the test are summarized in Table 4.6. Note that the measured delay turned out to be very close to the predicted value of τ. R-C combination 2 was selected, providing approximately 1 µsec of delay,
113 CHAPTER 4. INVERTER DEVELOPMENT which was long enough to ensure shoot-through prevention, yet short enough to cause insignificant impact to system performance. The final design for the Dead Time circuit is shown in Appendix C.
4.2.4 ACRLI Testing
In this section, the ACRLI system is tested. First, the prototype ACRLI subsystems are assembled into a complete system. Next, the design and construction of a three phase test load for testing is completed. The load is implemented in ACRLI testing, and simulations and run data are used in sizing the clamp capacitor. A capability to measure switching currents in the resonance board is added, and results in hardware are compared to simulation. Simulation of stray inductance is performed, the results again compared to hardware measurements, and finally the design of the printed circuit board (PCB) ACRLI controller is discussed, including specifications and design requirements. Six topics are discussed in this Section: the ACRLI subsystem assembly, the test load build, the ACRLI testing into load, clamp capacitor sizing, measurement of resonant board switching currents, and stray inductance modeling.
4.2.4.1 ACRLI Subsystem Assembly
The first step of ACRLI testing was to assemble the prototype ACRLI subsystems into a complete system. The assembled ACRLI prototype subsystem test configuration is shown in Figure 4.41. The prototype subsystems are enclosed within the dashed line. At this stage of development the Resonant Circuit was on a single brass board, and the Main Switch Control and Clamp Switch Control circuits were combined onto a second brass board. The other subsystems - the ACRLI Latch, the Current Predict circuit, and the Dead Time circuits - were implemented on separate breadboards. In order to simplify initial
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Figure 4.41: Assembled ACRLI prototype subsystems test configuration. checkout of the prototype ACRLI, a test load was used in place of the motor.
4.2.4.2 Test Load Build
The three phase test load was used in the initial ACRLI testing. Each leg of the load included a resistor and inductor; both were sized based on measurements made on the operating motor driven by the FOC-HSI. A resistor of about 2 Ω was determined to be a good fit based on phase voltage and current measurements; fortunately, 2 Ω power resistors were readily available. Three 100 µH inductors were wound for the effort, enough to provide sufficient inductance to the load for testing purposes. A schematic of the test load is shown in Figure 4.42, and a photo of the test load is shown in Figure 4.43.
4.2.4.3 ACRLI Testing into Test Load
The ACRLI was successfully tested into the test load. An oscilloscope trace of the measured line voltages, VAB and VBC , are shown in Figure 4.44. Note the variation in peak voltage level. These peaks in the line voltages occur when the link current
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Figure 4.42: Schematic of ACRLI test load.
Figure 4.43: ACRLI test load. command changes direction, and are caused by insufficient clamping. This indicates a need to correctly size the clamp capacitor, which is discussed in the Section 4.2.4.4. An oscilloscope trace of the measured phase currents into the test load are shown in Figure 4.45. Initial testing of the assembled ACRLI was satisfactory. However, several items worthy of further study arose: clamp capacitor sizing, modification of the resonant board to enable switch current measurement, and analysis of ringing due to stray inductance. These topics are covered in the following subsections.
4.2.4.4 Clamp Capacitor Sizing
Using the data taken during the initial ACRLI testing, improved sizing of the clamp capacitor, Cc, was undertaken. First, a simulation of the resonant inverter was done to study the clamp capacitor impact. The model presented in Figure 4.21 was modified to generate a step in the link current command I∗, to simulate a link current direction reversal as seen in motor operation. For comparison, the output of this simulation with a constant I∗ command is shown in Figure 4.46. This plot shows the commanded current I∗ (red) and the resonant inductor cur-
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Figure 4.44: RDCL measured line voltages into test load.
Figure 4.45: RDCL measured phase currents into test load.
rent LR (green); the link voltage (blue) is scaled to similar size for ease of study. Additionally the switching states for the main switch are shown: the current condi- tion (magenta), link voltage condition (blue), and the main switch command (purple).
∗ Note that the addition of IR to I is noticeable, slightly impacting the main switch current condition timing, as is intended. The output with the addition of a step current command, simulating a negative current direction change, is shown in Figure 4.47.
When the clamp switch turns off at the end of a cycle, the clamp capacitor Cc is
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Figure 4.46: Simulation with constant I∗.
Figure 4.47: Simulation of link current reversal.
charged to the desired peak link voltage, kVDC . During the next cycle, when VLINK
rises to just above kVDC , the clamp switch turns on, and Cc charges, clamping the link voltage. As seen in Figure 4.47, in the case of a current reversal a negative current is
requested at the link output, ILr drops accordingly, and the current condition is met later than under constant current command; thus the link is clamped for a longer period. Note that, even in the case of a constant I∗ command, the clamped link
voltage is not completely flat; the VLINK rises slightly as Cc charges. However, in the case of a reversal, when the clamping continues for a longer time period, the clamped voltage continues rising. This voltage rise is a function of the size of Cc; given the same charge current, a smaller capacitor will charge to a higher voltage. The goal
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of the sizing is to limit this current reversal peak, to prevent voltage stresses on the system. The above behavior was observed during ACRLI testing. A comparison of link voltages under current reversal with two different clamp capacitors is included in Figure 4.48. Voltage peaking is obvious in both plots.
Figure 4.48: VLINK with different clamp capacitance.
As expected, increasing the value of Cc decreases the excess link voltage peaking: the value of Cc in the left hand plot is 2 µF, while the value in the right hand plot is 10 µF. Note that the peaking is decreased, as expected, and that the voltage rise during clamping is decreased, resulting in a flatter top to the link voltage, also as expected.
4.2.4.5 Measurement of Resonant Board Switching Currents
Simulations from the preceding section, using the PSIM model in Figure 4.21, gener- ated plots of simulated resonant circuit switching currents, shown in Figure 4.49.
In the plot, traces associated with main switch SM are displayed in red, and clamp switch SC in green. The solid lines show the switch currents, while the dashed lines, scaled and offset for visibility, display the switching commands. Note that in this ideal case the currents are ramps, typically starting negative and ending positive. When the Resonant Circuit brass board was laid out and built, emphasis was
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Figure 4.49: Simulated RDCL switch currents. made on keeping the line lengths as short as possible to avoid stray inductance issues; doing so left no opportunity to measure the switch currents in the operating resonant circuit. However, as testing on the ACRLI system progressed, it became obvious that direct measurement of these currents would be beneficial; without measurement performance of the switching circuits could not be properly baselined. Making these measurements required adding loops of wire in the switch circuits, to enable placement of current probes. These loops were kept as small as possible, just large enough to fit the current probe. Photos of the top and bottom of the modified resonant board, displaying the added measurement loops, are shown in Figure 4.50. Measurement of the clamp switch current is shown in the Figure 4.51. The link voltage is shown in blue, and the clamp switch current ISC is in gray. Although the general shape matches that seen in simulation, the current trace is not linear during charging; considerable ringing is visible in the current. Measurements of the main switch currents are shown in the Figure 4.52. This scope plot of ISM demonstrates the importance of the resonance current (IR) setting; if insufficient current is available, the main switch closes early, while link voltage has not yet reached zero volts, causing a positive spike in current. These switch current measurements were used to provide insight into setup of
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Figure 4.50: Resonant board with SM (left) and SC current measurement loops added.
ACRLI parameters. Study of the impact of variation of the parameters of interest is done in Section 7.1.
4.2.4.6 Stray Inductance Modeling
A schematic of the ACRLI resonant circuit with currents labeled in shown in Figure 4.53. When the clamp switch is off, the clamp is out of the circuit, and source current
ISRC closely matches the resonant inductor current, ILr, displaying resonant current behavior. When the clamp switch is on, ISRC tends to match the link current, Ilink. This behavior is seen in simulation, using a ramp I∗ command, as shown in the left hand plot of Figure 4.54. However, measured source currents show a different behavior: source current during motor operation, measured in the high speed scope and transferred to Matlab, is shown in the right hand plot of Figure 4.54. The resonant portion of the measured data looks as expected, however, when the clamp is on ISRC rings instead of displaying the ramp behavior of the output current. The assumption is that this ringing is due to stray inductance; accordingly, a small inductance was added in the clamp circuit of the simulation. The resulting current plot is shown in Figure 4.55. Note that the model with stray inductance now closely matches observed
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Figure 4.51: Clamp switch current and link voltage. behavior.
4.2.5 ACRLI Control Circuit Printed Circuit Board Design
The use of breadboard prototyping in the development of the ACRLI subsystem circuits was an effective approach, enabling quick replacement of parts and expansion flexibility during checkout as needed, and allowing easy access throughout the circuits for probing for diagnostic purposes. Once their function had been verified, a few of the subsystems (the resonant circuit and the main and clamp switch controls) were converted to brass board, enabling better grounding and tighter layout for those subsystems. And though the combination of breadboard and brass board subsystem circuits on the assembled ACRLI controller was sufficient to validate overall ACRLI performance, the assembled system was not satisfactory for further research; each individual circuit was well organized, but the integrated system was by nature spread over a large area, with long signal runs and large loops, resulting in substandard grounding and noise immunity. Issues arose with noise in the system, impacting performance, and so it was desirable to develop a printed circuit board (PCB) version of the ACRLI controller, with the goal of overcoming the shortcomings of the separate
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Figure 4.52: Main switch current at three levels of IR. subsystems. As was mentioned above, one goal was for the PCB circuit to have a smaller footprint; however, driving size to an absolute minimum, which may be necessary for a final product, was not a requirement here. Since this was still to be a research board, the goal was to enable testing and modifications if necessary. Thus DIP instead of surface mount components were selected for the ICs, all placed in sockets for ease of checkout and modification; large sized (1206) surface mount discrete parts were selected for ease of replacement if necessary; and more than 30 test points were added enabling easy scope probe access. Even with these concessions, the board was reduced considerably; down to 6”x9”, less than 25% of the area taken by the interconnected prototype subsystems. A six layer board was selected to enable separate planes for each supply voltage (+5V, +15V, -15V) as well as a separate a ground plane, and all traces were cleared in the area of the the clamp switch driver, which was by necessity an isolated circuit. The combined ACRLI Control PCB had numerous connections, listed in Table 4.7. BNC connectors were selected for the digital input and output connectors, allowing shielded coax cable use. Screw terminals with removable sockets were used for the
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Figure 4.53: Resonant circuit with labeled currents.
Figure 4.54: Simulated (left) and measured source current.
DC power, switch drive, and sense connectors, selected because they provided solid connection as well as ease of removal. To minimize noise/cross talk issues, the approach was to lay out the PCB as the schematic flows; the functional layout of the PCB is shown in Figure 4.56. A photo of the completed ACRLI control circuit PCB is shown in Figure 4.57. Once the completed PCB was received, it was checked out driving the test load. Next, the PCB ACRLI was integrated into the Motor Lab, as described in Chapter 5, and used to develop the research system, as discussed in Chapter 6.
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Figure 4.55: Simulated source current with added stray inductance.
Table 4.7: ACRLI PCB Control Board Connectors Type Count Digital Input 4 Digital Output 6 DC Power 2 Switch Drive 2 Sense 5
Figure 4.56: PCB ACRLI control circuit functional layout.
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Figure 4.57: PCB ACRLI control circuit.
126 Chapter 5
Motor Lab and Equipment
In order to facilitate this research project, a motor lab was specified and built. The key subsystems of the motor lab are the motor controller, the interface computer, the inverter subsystem, the motor under test (MUT), the test load, the voltage measure- ment system, and the support equipment (encoder, oscilloscopes, and DC supply). Each of these subsystems are discussed in this chapter. A schematic of the motor lab is shown in Figure 5.1.
Figure 5.1: Schematic of motor lab.
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5.1 Motor Controller
The motor controller is implemented on a dSPACE system, built upon the DS1006 Processor Board. The DS1006 is based on a quad-core AMD OpteronTM processor. The dSPACE system includes 48 channels of A/D, and 32 channels of D/A. The system also includes an incremental encoder interface board, to process the output of the encoder, and a digital waveform output board, used to generate PWM signals to drive the inverter. The dSPACE platform was selected because this system allows for rapid controller development, and results in control code that is portable. Control code can be written in Simulink, which is translated into C code via Mathworks Simulink CoderTM; this C code is then compiled, and loaded into the dSPACE hardware. This process enables hardware implementation of Simulink code in a manner this is basically transparent to the user. Also, the dSPACE system enables real time parameter adjustment and data acquisition; a graphical user interface (GUI) can be built to facilitate on-line tuning and data visualization, and acquired data can be stored and analyzed off-line. Inputs to the Motor Controller include the sensors (phase current, line voltage, and encoder), and outputs are the PWM command signals for the inverter subsystem. A photo of the control panel GUI for the Motor Controller is shown in Figure 5.2.
5.2 Interface Computer
The Interface Computer is implemented on a HP Z640 workstation. This machine interfaces with the Motor Controller (dSPACE machine) via an optical link. The Simulink motor control code is resident on this machine, and updates are compiled and downloaded to the Motor Controller. The GUI is also run on the Interface Computer, allowing real time tuning and data visualization. A photo of the motor control computer (rack mounted) and the interface computer
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Figure 5.2: Motor Controller control panel GUI. on the motor lab work bench is shown in Figure 5.3.
5.3 Inverter Subsystem
Two different inverter types are used in this research project: the hard switching inverter (HSI), and the resonant DC link (RDCL) inverter. Details about the design and implementation of both of these inverters are discussed in Chapter 4.
5.4 Motor Under Test
The motor under test (MUT) is a commercially available permanent magnet syn- chronous motor (PMSM), the Motorsolver BLDC5113. This is an eight pole motor (4 pole pairs), which is rated at 3000 RPM and 200W, and the motor parameters, from name plate data and from measurements taken in Section 6.1 , are summarized in Table A.1 in Appendix A.
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Figure 5.3: Motor control and interface computers on work bench.
5.5 Motor Test Load
The load used to test the performance of the MUT is comprised of the load motor and the load resistor. A schematic of the test load is shown in Figure 5.4.
Figure 5.4: Test load schematic.
The load motor is a two pole, 250W permanent magnet brush DC (BDC) motor, the Motorsolver MS3500. The resistor used for testing is a 5Ω 120W power resistor.
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5.6 Voltage Measurement System
The voltage measurement system required custom hardware development. This sys- tem was designed to enable measurement of the voltages of the motor phases. Motor voltage measurements are necessary for some implementations of flux estimation un- der DTC control; however, direct measurement of motor voltages is not achievable, as the voltage is too high for the controller A/Ds, and grounding would be prob- lematic because the shell of the A/D inputs is tied to earth ground. Therefore the requirements of this system included providing isolation between the motor leads and the analog input of the controller; an appropriate gain level to decrease high motor voltages into the range of the A/D inputs of the Motor Controller; large bandwidth with minimal phase delay; and low noise. These requirements were met in hardware via the voltage measurement system. A high level schematic is included in Figure 5.5.
Figure 5.5: Voltage measurement system high level schematic.
Three precision isolation amplifiers were used to provide isolation between the inputs (motor side) and the outputs (controller A/D side), and two pairs of DC-DC
131 CHAPTER 5. MOTOR LAB AND EQUIPMENT converters were used to provide isolated power to the input and output sides of the isolation amplifiers. A schematic of the voltage measurement system is in Appendix D.
5.7 Support Equipment
The support equipment for the motor lab includes the encoder, the oscilloscopes, and the DC supply, all of which are discussed in this section. The Encoder used was a Timken M15-1000-8 encoder, which is a high-resolution (less than 10 arc minutes) magnetic encoder. Multiple oscilloscopes were used in the motor lab; the ideal scope provides isolation, to enable placement of scope leads anywhere in the power circuit; and storage capability to enable post processing of measured data. The Yokogawa DL850 was used wherever possible, as this model met the above requirements. Additionally, an Agilent 54622A scope was used in X-Y mode to plot live stator flux linkage estimates during motor operation under DTC. The DC supply used was an Sorensen 50V, 8A regulated supply, capable of providing voltage and current required to drive the MUT.
5.8 Assembled Motor Lab
The motor lab was built specifically for this project. The dSPACE hardware was specified and purchased, and once received, unpacked, the processor and I/O boards were installed, and the system was assembled; then the I/O connector panels were mounted to the lab bench. Next Matlab/Simulink was installed onto the interface computer, and the dSPACE software was loaded onto the motor control and the inter- face computers, and the connection between them (optical link) was established. An initial control panel GUI was written on the interface computer, which allowed ini- tial system checkout, and the functionality to code, compile, and download Simulink
132 CHAPTER 5. MOTOR LAB AND EQUIPMENT code to the dSPACE hardware was verified. This initial code was also used to do preliminary tests to ensure the input and output boards were functioning. A photo of the assembled lab is shown in Figure 5.6.
Figure 5.6: Photo of motor lab.
133 Chapter 6
Baseline and Research System Development
This chapter describes steps taken to transfer the motor control models used in simu- lation into hardware, in complete motor drive systems in the motor lab. These motor drive systems can be divided into two categories: development systems, and systems under study. As the name implies, development systems are for use in development of aspects of the motor lab and control capability. Two development systems are discussed: the open loop system and the DTC-HSI system. The systems under study are used to develop the experimental results, as detailed in Chapter 7. Two systems under study were built: the baseline system, the FOC- DTC system, and the research system, the DTC-ACRLI system. Topics discussed in this section include motor parameter measurement, hardware checkout and open loop operation, filter design, controller transfer to hardware, FOC- HSI implementation, DTC-ACRLI implementation and improvements, DTC-ACRLI implementation, and efficiency measurements.
134 CHAPTER 6. BASELINE AND RESEARCH SYSTEM DEVELOPMENT
6.1 Motor Parameter Measurement
Motor parameter values of interest are estimated in this section. Measurements are done on both motors: the PMSM (MUT), and the load (BDC) motors. The processes used, measurements, and estimate calculations are discussed in the following sections. Note that the parameter estimates were verified via comparing simulations and hardware runs under FOC; these results are discussed in Section 6.5.3.
6.1.1 PMSM Motor Parameter Measurement
Several implementations of the DTC require knowledge of the stator resistance, Rs. This parameter can be determined by measuring the resistance across any two motor leads; in a wye-wound motor, Rs is simply half of this measured value. This measure- ment was done on the PMSM using an impedance measurement system, and found to be 90 mΩ. This is consistent with the measurement made with a lower resolu- tion hand-held impedance meter, which measured 100 mΩ. As this resistance varied
greatly from the Rs provided by the manufacturer, the measured resistance was used in the DTC controller development.
Another parameter of interest is ψF , the PMSM stator flux linkage due to the rotor
permanent magnets. ψF is used in the DTC controller to calculate the inner loop flux command, and in the PMSM model. To make this measurement, the PMSM was disconnected from the inverter and driven by the load motor at various speeds, while the peak to peak voltage across a pair of PMSM leads was measured. An oscilloscope trace of the PMSM motor back emf at 840 RPM is shown in Figure 6.1, and a plot of these measurements, back emf vs. motor speed, is shown in Figure 6.2. Note that the back emf is sinusoidal, as expected for this motor type; also note that the relationship between the back emf and speed is linear. The calculation of
ψF as a function of measured voltage and electrical frequency was calculated to be
135 CHAPTER 6. BASELINE AND RESEARCH SYSTEM DEVELOPMENT
Figure 6.1: PMSM back emf measurement.
Figure 6.2: Plot of PMSM back emf vs. speed.
0.015 V·s.
Other parameters of interest in the PMSM are Ld and Lq, the direct and quadra- ture axis stator self inductances in the rotor reference frame. Similar to ψF , these parameters are used in DTC modeling. Measurements were made, and estimated obtained, using the process described in [37].
The estimated values of the PMSM parameters, Rs, Ld, Lq, and ψF , are included in the PMSM Motor Parameters Table, Table A.1 in Appendix A.
136 CHAPTER 6. BASELINE AND RESEARCH SYSTEM DEVELOPMENT
6.1.2 Load Motor Parameter Measurement
The two parameters of interest for the load motor (BDC) are the torque constant,
KT , and the back emf constant, KV . These parameters are used in the load model, as discussed in Section 2.5. The procedures used to generate estimates of these parameters are discussed in this section.
The value of the load motor back emf constant (KV ) was determined by measure- ment. With the load resistor in place, the motor was driven at various speeds, and the back emf voltage (neglecting internal resistance) was measured. The results are displayed in Figure 6.3. Note that the data looks linear, as expected. The estimated
Figure 6.3: Load motor back emf.
value of KV = 0.0087 V/rpm is read directly from the linear fit.
In order to measure torque constant KT , a blocked rotor test was performed on the load motor. A C-clamp and a set of slats were used to block the rotor during the test, the load motor was driven with variable output DC supply, and a torque meter was used to measure generated torque at multiple input current levels. The results are shown in Figure 6.4. Again the data is linear; the estimated value of KT = 0.077 Nm/A is read directly from the linear fit. These parameters are included in the Load Motor Parameters Table, Table A.2 in Appendix A.
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Figure 6.4: Load motor blocked rotor test plot.
6.2 Hardware Checkout and Open Loop Operation
The interface computer and the motor control computers are discussed in Chapter 5. A schematic of the interconnected systems in the motor lab is shown in Figure 6.5. The controller GUI is operated from the interface computer, and the motor control
Figure 6.5: Schematic of motor lab. installation is done from this machine. Once checkout was complete, the goal was to transfer motor control models developed in Chapter 2 and simulated in Chapter 3 to the interface computer, then convert them for hardware operation. This is done via dSPACE-provided Simulink blocks, called Run-Time Interface (RTI) blocks, which allow Simulink models to be connected to dSPACE hardware I/O. The converted
138 CHAPTER 6. BASELINE AND RESEARCH SYSTEM DEVELOPMENT motor control models can then be transferred to the dSPACE hardware resident on the Motor Control computer. When the motor lab was built up, the motor control and interface computers were set up first; then the other associated hardware (inverter, PMSM motor, load, scopes, etc.) were installed. At that point a platform to test these entire systems was required. The open loop (V/Hz) controller was used to perform this function. A model for the open loop controller is described in Section 2.3.1, and a simulation of the system is described in Section 3.1.1. A schematic of the open loop controller is shown in Figure 6.6.
Figure 6.6: Schematic of open loop (V/Hz) controller.
The open loop controller was implemented in Simulink, using RTI blocks to pro- vide access to the dSPACE digital outputs, thus enabling the controller PWM com- mands to reach the inverter. The dSPACE GUI capability was used to develop a control panel, allowing command line inputs to controller setpoints and gains, and providing system diagnostics. The controller code was converted, complied on the Interface Computer, and downloaded to the Motor Controller (dSPACE) hardware. The open loop gain and offset were tuned manually. First, the DC supply voltage was increased with the speed command increase, and zero voltage and ramping voltage values that enabled open loop operation were found. These voltage values were then converted to open loop control parameters, considering the motor lab hardware: the desired DC supply voltage setting, and the PWM implementation. Once this was
139 CHAPTER 6. BASELINE AND RESEARCH SYSTEM DEVELOPMENT done, open loop motor control was achieved. This approach enabled first spinning of the PMSM, and verified operation of many components of the motor lab hardware and software. Successful output voltage generation served to demonstrate functionality of the dSPACE digital output PWM commands, the PMSM, the HSI inverter subsystem (drivers, current sensors, and the HSI itself), and the DC supply. By comparison with oscilloscope traces from voltage probes and current guns, the operation of and correct signs and scaling gains for the D/As and A/Ds were proven. Although the open loop controller does not utilize a feedback angle, this controller was nevertheless useful in testing the encoder for future use with the vector controllers. First, the output of the encoder, which is attached to the PMSM shaft, was fed into the motor controller, where the encoder signal was converted to an angle. Then the generated command angle was compared to this measured angle. The commanded and measured encoder angles lay on top of each other, with no phase or frequency errors. This constituted a successful test of the encoder input hardware, the angle generation software, and the encoder itself. The generated and measured angles from this test are plotted in Figure 6.7.
Figure 6.7: Generated and measured angles open loop control.
Once the initial system checkout was completed via the open loop controller,
140 CHAPTER 6. BASELINE AND RESEARCH SYSTEM DEVELOPMENT transfer of the closed loop (vector) motor controllers to hardware was possible.
6.3 Filter Design
Two filter types were used in the motor lab hardware implementation: the input filter, and the signal filter. The designs of both of these filters are discussed in this section. No output (AC power filter) was used in the lab, as is discussed in Section 7.5.
6.3.1 Input Power Filter
The DC input filter consisted of a bank of capacitors in series-parallel combination, with a total capacitance of 5000 µF . This filter was selected to keep the input voltage constant for both the baseline and the research motor drive systems, avoiding input voltage variation and enabling performance comparison of the two systems.
6.3.2 Signal Filter Design
There is considerable switching noise present in the motor drive system, particularly when the hard switching (HSI) inverter is used. The signal filters are used to attempt to prevent the noise from entering the system through the motor control A/Ds. They are also used to prevent aliasing. A single pole RC filter is used for this purpose, attached directly at the A/D input. In the initial motor lab configuration, the Nyquist frequency was 10 kHz, but noise issues drove the corner frequency lower, to about 1 kHz. Due to improvements in the hardware configuration, the signal filter corner frequency was able to be moved out considerably in the DTC implementation, as discussed in Section 6.6.4.3.
141 CHAPTER 6. BASELINE AND RESEARCH SYSTEM DEVELOPMENT
6.4 Controller Transfer to Hardware
As was discussed in 6.2, the system models developed in Chapters 2 and 3 were implemented in Simulink, which facilitated the desired simulation capability, and also greatly eased their conversion to motor controllers in hardware. The goal was to transfer these simulated controllers directly into hardware for use in the motor lab. Additionally, there was a desire for a single controller implementing all code of interest (open loop, FOC, and DTC) to aid testing. In addition to the actual motor controllers, the complete system models also include code which is not necessary in the hardware implementation, e.g. models of the inverter, the motor under test, and the load motor. To facilitate the desired single, combined motor control capability, the FOC and DTC motor control models were copied from their respective system models and added to the existing open loop (check-out) controller on the Interface Computer. Severed connections between the motor controllers and the eliminated system component models were reconnected to RTI hardware I/O connections in the open loop controller: A/D, D/A, and digital outputs to provide access to current, voltage, and speed sensor data. This updated controller is called the combined motor controller; in operation, the desired motor control scheme is selected via the Motor Control GUI. A high level diagram showing architecture of the combined motor controller is shown in Figure 6.8.
6.5 FOC-HSI Implementation
This section covers FOC-HSI implementation in the motor lab. Topics discussed include Initial FOC setup, FOC tuning, and parameter validation under FOC.
142 CHAPTER 6. BASELINE AND RESEARCH SYSTEM DEVELOPMENT
Figure 6.8: Diagram of combined motor controller.
6.5.1 Initial FOC Setup
The first step in FOC implementation was to get the motor spinning using only the inner loop controller. This approach would enable check out of many of the FOC controller functions, and also provide an initial set of inner loop controller gains. This was achieved by first severing the outer loop connection to the FOC controller,
∗ and instead providing a manual command for the inner loop control variable iq (the
∗ other FOC inner loop variable id is set to zero under FOC). Next, the MUT is spun up to 500 rpm under open loop control, and the current controllers are tuned so that the open loop (driving) and FOC (off line at this point)
∗ output command voltages match each other - this is done by varying command iq and the current loop proportional gains; at this point the integrators are set to zero. Once output voltages match, the control is transitioned to FOC mode. This constitutes
∗ closed loop control, although the setup is unusual - the input command is iq, instead of speed.
143 CHAPTER 6. BASELINE AND RESEARCH SYSTEM DEVELOPMENT
6.5.2 FOC Tuning
The controllers were tuned by first optimizing the inner loop. With the MUT running under FOC, the controller was temporarily modified to generate step commands to
∗ the input command iq, and the commanded and measured iq were output for viewing on an oscilloscope. Next the amplitude and frequency of the step commands were adjusted to desired levels, the proportional gains were set for an underdamped re- sponse, and the integral gains were set to eliminate error. The controller was then modified to add the outer loop, and the process was repeated, verifying speed tracking to commands. Since no dynamic testing was planned for this effort, the goal was for stable operation; the controller only needed to hold speed. A photo of an oscilloscope trace during outer loop tuning is shown in Figure 6.9.
∗ The commanded current iq (pink) and measured speed (cyan) are shown.
Figure 6.9: Outer loop tuning.
144 CHAPTER 6. BASELINE AND RESEARCH SYSTEM DEVELOPMENT
6.5.3 Parameter Validation Under FOC
Simulation was key to understanding of the operation of the DTC controller. Thus accurate motor parameters for the PMSM and the load motor were desired to ensure validity of the DTC simulations. Therefore an effort was made to validate the motor parameters measured in Section 6.1. This validation was done by running the motor lab under the FOC-HSI system, driving the PMSM into the load motor, and capturing measurements of line voltages, phase currents, estimated torque, and speed. This data was then transferred to Mat- lab for processing and plotting. Next, a simulation of the FOC system was built in Simulink, including the FOC inner and outer loop controller, the ideal inverter, the PMSM, and the load motor and resistor, incorporating all measured motor parame- ters. The motor in the lab was run and data captured at 500, 1000, and 1500 rpm; matching simulations were performed; and the results were compared. The line voltages for the 1000 rpm runs are plotted in Figure 6.10. The left hand
Figure 6.10: Simulation and hardware line-line voltages at 1000 rpm. plot shows the simulated results for line voltage, in volts. Since the ideal inverter was used in this simulation, there is no switching noise present; this has no impact on the results, and is actually helpful for the magnitude comparison, as no filtering is needed. The right hand plot shows two phases of line voltage measured in the motor lab, one
145 CHAPTER 6. BASELINE AND RESEARCH SYSTEM DEVELOPMENT phase with some filtering at the scope input, and the other filtered in post processing to remove switching noise. Since the PWM frequency (20 kHz) is so much higher than the fundamental (67 Hz), there is no appreciable impact on magnitude. Note that the measured and simulated voltage levels are in good agreement, as desired. The phase currents for the 1000 rpm runs are plotted in Figure 6.11. The left
Figure 6.11: Simulation and hardware phase currents at 1000 rpm. hand plot shows the simulated results for phase current, in amps. The right hand plot shows the phase currents measured in the motor lab. Note that the measured and simulated current magnitudes are in good agreement, as desired. A table summarizing the model validation results is included in Table 6.1. At 500,
Table 6.1: Model Validation Results rpm VLN Sim VLN VLN % IpeakSim Ipeak Ipeak% TestSim Test Test% 500 5.6 5.8 3.6 1.8 1.9 6.7 0.176 0.17 -3.5 1000 11.4 11.6 1.5 3.1 3.0 -4.4 0.27 0.27 0.0 1500 17.3 17.3 0.0 4.0 4.0 0.0 0.366 0.36 -1.7
1000, and 1500 rpm, comparisons are made between line to neutral voltage (Volts), phase current (Amps), and estimated torque (Nm) generated by simulation and mea- sured in the lab. Note the excellent agreement; all measured performance matches the simulation to well within 10%. This close agreement constituted validation of motor parameter estimates to the levels needed for the DTC simulation efforts.
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6.6 DTC Implementation and Improvements
While Chapter 4 covered the ACRLI design and development, this chapter focuses on controller improvements. Topics covered in this section are the implementation approach and goals, DTC initial work, flux and torque estimation improvements, and DTC-HSI performance improvements.
6.6.1 Implementation Approach and Goals
Although the author had some previous experience with implementing FOC on a HSI implementation, he had no previous experience implementing direct torque control. Thus it was decided to develop the initial hardware DTC motor drive implementation using a HSI, and avoiding the complications of implementing an unknown inverter (ACRLI) and an unknown controller simultaneously. Once the initial DTC-HSI- PMSM system was operating, the goal was to optimize the DTC-HSI performance, then transfer best practices when developing the DTC-ACRLI system. The hope was that any benefits found in the DTC-HSI implementation would also benefit the DTC-ACRLI implementation; given the nature of the improvements, this turned out to be the case. Since improved efficiency was a key goal of this effort, efficiency was used as the metric for performance. The approach was to improve efficiency on the DTC- HSI system, discussed in this Section, then convert to the DTC-ACRLI as covered in Section 6.7, and to study the performance of the research DTC-ACRLI system, covered in Chapter 7.
6.6.2 DTC Initial Work
As was described in Section 6.4, the DTC controller model was transferred directly into the Motor Lab control computer, external connections were replaced with Real
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Time Interface blocks, and the model was compiled and loaded into the dSPACE controller. The first step in implementation of the DTC model to hardware was to verify the correct performance of several key DTC controller components, specifically the sector calculation and the voltage vector table. This was achieved via a simple checkout test. DTC utilizes six sectors for control, each spanning 60 electrical degrees, as de- scribed in Section 2.3.3.3, repeated for convenience here in Figure 6.12. To verify
Figure 6.12: DTC stator flux vector trajectory. that the hardware DTC controller provides correct sector calculation and orientation (i.e. sector 1 is centered at zero electrical degrees, etc.), the shaft was hand spun through 360 electrical degree (90 mechanical degrees for the 4 pole PMSM), while the the angle generated from the encoder was displayed on the controller GUI. The shaft location was compared to the measured sector, and correct correspondence was verified. The next step was to verify that the generated voltage vectors had the correct sense and location. There are six non-zero voltage vectors available to the DTC controller, described in Section 2.3.3.3 and repeated here for convenience, in Figure
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Table 6.2: DTC Voltage Vector Test T rial V ector SA SB SC SectorRange F inalAngle 1 1 1 0 0 330-30 353 2 2 1 1 0 30-90 50 3 3 0 1 0 90-150 101 4 4 0 1 1 150-210 171 5 5 0 0 1 210-270 225 6 6 1 0 1 270-330 289 7 5 0 0 1 210-270 246 8 4 0 1 1 150-210 187 9 3 0 1 0 90-150 132 10 2 1 1 0 30-90 68 11 1 1 0 0 330-30 12
6.13.
Figure 6.13: Inverter voltage vectors and flux vector change when applied in time ∆t.
To verify voltage vector mechanical orientation, the DTC portion of the combined motor controller was modified to enable manual selection of the voltage vector output command. Then each voltage vector was applied, from V 1 to V 6 and back again. This was achieved simply by first turning off DC voltage, then selecting the voltage vector output to the HSI, then slowly increasing the DC voltage until sufficient current was present to move the PMSM rotor. The rotor final location in each case was noted, as detailed in Table 6.2.
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Note that, upon application of each voltage vector, the rotor moved to the correct angular position (approaching the center of the sector angle range), and thus the correct mechanical orientation was verified. With verification of the sector calculation and the voltage vector generation, the next step was to attempt first spin using the DTC. Initial debugging began with the parameters developed during the DTC simulation effort. The diagnostic techniques developed in simulation in Section 3.1.3, plots to enable interpretation of relevant variables, were adapted for hardware implementation efforts. Measurements were downloaded into Matlab files, for off-line interpretation. Previous DTC simulation and diagnostic efforts allowed interpretation of relevant variables. They were useful in defining appropriate setup to allow the simulation code to operate correctly, and proved very helpful during the hardware implementation. One example of a parameter that was studied is the saturation level of the outer loop command, T ∗. As was the case in the simulation effort, adjustment of this saturation level turned out to be important in hardware. The measured parameter and its associated off line plot is shown in Figure 6.14. Commanded speed in RPM
Figure 6.14: Plot of commanded and actual speed, and torque command. is shown in red, measured speed in green, and T ∗ is in blue. This plot assisted in
150 CHAPTER 6. BASELINE AND RESEARCH SYSTEM DEVELOPMENT developing appropriate saturation limits to enable operation; note the similarity to the simulated DTC system output, shown in Figure 3.6. Once initial spinning was achieved, these diagnostics were implemented in the GUI screen. Sector, voltage vector, motor voltages and currents, and measured angle were plotted, as were estimated torque and flux errors versus allowed limits. Flux linkage estimation is a crucial function of the DTC system. Therefore es- timated stator flux linkage components ψα and ψβ are displayed live in two places during motor operation: in polar plots on the Agilent oscilloscope, and on the GUI. A photo of the estimated stator flux linkage oscilloscope plot is shown in Figure 6.15, and a photo of a portion of the GUI screen, showing the estimated stator flux linkages along with the hysteresis limits, is shown in Figure 6.16.
Figure 6.15: Estimated stator flux linkage oscilloscope trace.
In the GUI photo (Figure 6.16), estimated flux is in red, and the outer and inner limits of the hysteresis bands are in yellow and cyan respectively. Note that the diameter of the estimated flux linkage polar plot does not change with speed; this is expected as the stator flux linkage is dominated by the motor permanent magnets in a PMSM.
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Figure 6.16: Estimated stator flux linkage live on GUI screen.
After initial spinning was achieved, live tuning commenced; the inner loop com-
parator limits Hψ and HT were adjusted, and in the outer loop the PI controller gains
kp and ki were tuned. With this tuning effort repeatable motor spin was achieved under DTC at low speeds. However, performance was poor; the rotation was choppy, and there was a high current draw from the DC supply. It was assumed that the problem was with the flux estimation; accordingly improvements were sought, as is discussed in the next section.
6.6.3 Flux and Torque Estimation Improvements
In DTC, flux and torque estimates are used as the inner loop variables. Improved estimates of these variables are found to improve performance; notably system effi- ciency. Topics covered in this section include flux estimation using: the low pass filter (LPF) as an integrator; an LPF with automatic magnitude and phase compensation; an Extended Kalman Filter (EKF); and the current based model.
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6.6.3.1 Flux Estimation using Low Pass Filter as Integrator
As described in Section 2.3.3, the DTC controller flux estimation is performed by the integration of voltage and current values. The expressions for quadrature stationary reference frame flux linkage components are repeated here for convenience:
Z ψα = (vα − Rsiα)dt (6.1) and Z ψβ = (vβ − Rsiβ)dt (6.2)
The estimated flux magnitude and electrical torque estimates are calculated from these values. This approach to flux linkage estimation is attractive because it relies on knowl- edge of only a single parameter, the stator resistance Rs, and is not computationally intensive, an attractive feature as this is intended to be implemented in real time control. However, the use of integration will cause problems; since the DC gain of a pure integrator is infinite, even small offsets in the measured voltage will quickly saturate the output. Therefore in practice a low pass filter is used in place of a pure integrator. However, selection of the LPF corner frequency fc is problematic. Selec- tion of a low fc results in a LPF that looks more like an integrator; however, the DC offset problem is still an issue. Selection of a higher corner frequency will solve this problem, but causes significant errors in the magnitude and phase, especially at lower frequencies where a high fc LPF looks less like an ideal integrator. A quick visual expression of this trade off is shown in Figure 6.17. The figure shows bode plots of a pure integrator, in green, and LPFs of three different corner frequencies, 0.1, 1.0, and 10 Hz. The LPF behavior approaches that of the pure integrator at high frequencies, but has significant magnitude errors below fc. At low speed operation, say 100 RPM, the electrical frequency for the MUT is
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Figure 6.17: Low pass filter and integrator bode plots. about 7 Hz. With the lowest corner frequency, we see that the gain and phase are very close to that of the pure integrator at 7 Hz, however, the DC gain is very high for this LPF. At the higher corner, the gain is close at 7 Hz, but the phase is off by more that 45 degrees; however, the DC gain is much lower, preventing saturation issues.
In the hardware implementation, a higher fc LPF was required, because the offset issues made the lower fc LPF unworkable. An acceptable corner frequency was found experimentally by running the LPF estimator in parallel with the operating FOC, and adjusting the corner until good agreement was reached between the two algorithms.
Using this approach, fc = 15 Hz electrical had been selected to enable initial spinning; this corresponds to 225 RPM. To attempt to improve the poor initial DTC performance, several modifications were made to the controller to enable tunable corrections: live adjustment of torque
154 CHAPTER 6. BASELINE AND RESEARCH SYSTEM DEVELOPMENT and flux estimate magnitudes and an offset angle were added. Starting at a low speed, these parameters were hand-tuned for improved controller performance; once good performance was achieved, the speed was increased, and the process repeated. Using this approach, higher speeds could be attained under DTC. A summary of the manual correction test results is shown in Table 6.3.
Table 6.3: Manual magnitude and phase correction test Speed rpm Flux adjust T adjust Theta offset 400 1.150 1.32 30 500 1.100 1.20 30 600 1.070 1.14 29 700 1.050 1.10 27 800 1.040 1.08 24 900 1.030 1.06 21 1000 1.025 1.05 25 1100 1.020 1.04 15 1200 1.017 1.04 9 1300 1.015 1.03 9 1400 1.010 1.03 7
As seen in the summary above, the amount of correction required to achieve good performance decreased with speed. By 1400 RPM the required magnitude correction approached 1.0 (no correction); and phase angle correction approached zero degrees. This behavior makes intuitive sense; at higher frequencies the LPF looks more like an ideal integrator. These test results point to the need for magnitude and phase angle correction to improve performance; thus a magnitude and phase (MP) correction was developed.
6.6.3.2 Flux Estimation using LPF with Automatic Magnitude and Phase Compensation
The use of a LPF only in flux estimation required manual adjustment of controller parameters with speed to correct for estimation errors; these adjustments were needed to prevent the controller from crashing. With stable operation achieved manually,
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the next goal was to automatically correct for the magnitude and phase errors. This approach is possible because both the transfer function of the LPF and the electrical frequency of the operating motor are known. Until the electrical speed is fast enough to overcome the non-ideal integrator properties of the LPF, the magnitude of the LPF output is less than that of a pure integrator, and the phase lag will be less than the -90◦ of the pure integrator. Thus this magnitude and phase compensation become a gain adjustment, and a phase delay addition. The flux estimator LPF is shown in Figure 6.18. This form was selected because
Figure 6.18: Flux estimator LPF model.
at high frequencies, the LPF behavior approximates that of an integrator, 1/s. The transfer function of this LPF is
1 H(s) = (6.3) s + 2πfc
and the magnitude of this function, operating at the electrical frequency fe (in Hz), is
1 |H(f)| = (6.4) p 2 2 (2πfe) + (2πfc) )
The magnitude correction as a function of fe, given LPF corner frequency fc, can be derived from Equation 6.4 and the integrator transfer function of 1/s:
s 2 2 fe + fc Cmag = 2 (6.5) fe
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The phase angle correction, β, is found by first finding the phase impact of the LPF at the electrical frequency, φ. From Equation 6.4, this phase impact is
f φ = atan e (6.6) fc
Since the pure integrator phase shift is -90 electrical degrees, the phase angle correc- tion is β = φ − 90◦ (6.7)
Using the above equations to calculate Cmag and β, the automatic magnitude and phase compensation is implemented in code as shown in Figure 6.19.
Figure 6.19: Magnitude and phase correction implementation.
To make implementation of the compensation straightforward, a phasor approach was used. The inputs to the compensator are the phase voltages and currents, which are converted to phasor form, wherein the compensation correction is easily per- formed, based on the operating speed. Next, the corrected voltages and currents are converted to stator reference frame alpha-beta and passed on to the LPF flux estimator. These flux estimates are then used for flux and torque in the controller. In operation, it was helpful to remove any offsets in the voltage measurement.
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This was accomplished via a setup procedure. First the compensation is disabled, and the LPF flux estimator corner frequency was set very low, to allow DC components to pass. Then the motor was spun up on FOC, and the voltage input offsets are zeroed out using a straightforward visual correction: the stator flux estimation circle is centered on the oscilloscope. Once the voltage offsets were corrected, the controller was set to DTC, the LPF corner frequency was set to a higher corner for faster convergence, and the automatic compensation was enabled. Through experimentation, 16 Hz was found to be a good corner frequency for the speed range of interest. The correction factors at his corner frequency, calculated as a function of speed in RPM, are shown in Figure 6.20.
Figure 6.20: Magnitude and phase correction at selected fc
The automatic magnitude and phase worked as intended, providing automatic correction of the magnitude and phase issues caused by use of the LPF filter in the flux linkage estimation. With the compensation in place, the DTC drive performance increased considerably, enabling spin up and speed changes without issues. However, further improvements were still desired. This approach was computa- tionally intensive; although a low enough loop time was achievable to enable real time operation, more reduction would be needed to increase loop speed, which was
158 CHAPTER 6. BASELINE AND RESEARCH SYSTEM DEVELOPMENT desired once the DTC-ACRLI system was complete. Additionally, voltage drift was still a potential issue; this could be manually overcome using the setup procedure to zero out voltage offsets, but automatic correction was also desired. Based on these goals, the extended Kalman filter approach was developed, and is discussed in the next section.
6.6.3.3 Flux Estimation using Extended Kalman Filter
In an effort to improve upon the automatic magnitude and phase compensated LPF approach, specifically to eliminate voltage offset and drift issues, the Extended Kalman Filter (EKF) was considered as an alternate approach to flux estimation. This approach was additionally attractive because it featured the potential to gen- erate position and speed estimates as well, which might be used to eliminate the encoder. This discussion is divided into three topics: EKF Introduction and Formu- lation, EKF Simulation, and EKF Hardware Implementation and Results.
EKF Introduction and Formulation Kalman filtering is an optimal state estimation process, applied to a dynamic system in the presence of noise. The Kalman filter is a recursive algorithm, and has been widely applied in real-time applications. It was designed to estimate the state vector of a linear model. In the case of a nonlinear system (the PMSM is a nonlinear system), a linearization procedure is performed, adapting the Kalman filter to apply to nonlinear systems; this is called the Extended Kalman Filter (EKF) [43]. The EKF is a two stage process, employing a prediction stage and a correction stage. First, states are predicted using a mathematical model, along with the previ- ous estimated state values; then corrected using a feedback correction scheme, using measured values. Measurement noise and disturbance noise are assumed to be un- correlated [25]. The first step in implementing the EKF is to select the time domain machine
159 CHAPTER 6. BASELINE AND RESEARCH SYSTEM DEVELOPMENT model. The equations are in the form
d x = Ax + Bu dt (6.8) y = Cx where x is the state vector, defined as
T x = [iα iβ ω θ] (6.9) u is the input vector, the voltages,
T u = [vα vβ] (6.10) and y is the output vector, the currents,
T y = [iα iβ] (6.11) and A, B, and C are the state, input, and transformation matrices, respectively. The stator reference frame equations for the PMSM, assuming a non-salient motor, are [12]
d d vα = Rsiα + L iα + ψF cos(θ) dt dt (6.12) d d vβ = Rsiβ + L dt iβ + ψF dt sin(θ) Solving for the current derivatives, and performing the derivatives of θ and substitut-
d ing the dt θ with ω, we have the first two equations for the model:
d Rs ψF vα iα = − iα + ω sin(θ) + dt L L L (6.13) d Rs ψF vβ dt iβ = − L iβ − L ω cos(θ) + L For the third relationship we begin by solving the electromechanical equation, 2.10,
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d for dt ω: d T T Bω ω = e − L − (6.14) dt J J J
Next we substitute the relationship for Te in the stator frame, which is [12]:
3 T = P ψ (−i sin(θ) + i cos(θ)) (6.15) e 2 F α β resulting in the third equation for the time domain model:
d 3 ψ P Bω T ω = F (−i sin(θ) + i cos(θ)) − − L (6.16) dt 2 J α β J J
Recognizing that the derivative of position is speed provides the fourth equation; combining this with 6.13 and 6.16 we have the time domain machine model:
d Rs ψF vα dt iα = − L iα + L ω sin(θ) + L
d Rs ψF vβ iβ = − iβ − ω cos(θ) + dt L L L (6.17) d 3 ψF P Bω TL dt ω = 2 J (−iαsin(θ) + iβcos(θ)) − J − J d dt θ = ω Next, the partial derivative matrix required to implement the EKF is generated, taking the partial derivative of the equations with respect to each of the state variables in turn, The resultant derivative matrix is
−Rs 0 ψF sin(θ) ψF ωcos(θ) L L L ψ ψ 0 −Rs − F cos(θ) F ωsin(θ) 0 L L L f = − 3 ψF P sin(θ) − 3 ψF P cos(θ) − B 3 ψF P (i cos(θ) − i sin(θ)) 2 J 2 J J 2 J α β 0 0 1 0 (6.18) The next step was determining the values for the covariance matrices, Q, R, and
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P. System noise covariance Q accounts for inaccuracy in the model and system disturbances, and noise covariance R accounts for quantization and measurement noise; P is the state covariance matrix. Here P and Q are 4 x 4 matrices, and R is 2 x 2. However, the noise signals are assumed to be uncorrelated, thus only diagonal elements must be specified; furthermore, since the voltages and currents have similar properties, first two elements of P are equal, as are the first two elements of Q, and both nonzero elements of R, reducing the covariance matrix specification to only seven terms [25].
EKF Simulation Using equations 6.17 and 6.18, the EKF was implemented in standard form [43]. The implementation was done in Simulink, to enable simulation, tuning, and eventual incorporation into the controller in hardware. To facilitate testing and tuning, the EKF was incorporated into to a closed loop motor control system simulation, start- ing with the FOC-HSI-PMSM model. The EKF testing and tuning configuration is shown in Figure 6.21. The EKF was run open loop in parallel with the closed loop
Figure 6.21: EKF tuning simulation on FOC-HSI model.
simulation. Inputs to the EKF came from the motor system simulation: input values
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T T (y = [vα vβ] ) and measured values (u = [iα iβ] ). Within the EKF code noise (a Gaussian distributed random signal) was added to the simulated measurements, the model motor currents. To facilitate tuning, the values from the simulated motor system (state parameters and estimated flux: iα foc, iβ foc, ωfoc, θfoc, and ψfoc) were compared to those calculated by the EKF (iα ekf , iβ ekf , ωekf , θekf , and ψekf ). As EKF tuning was an unknown process, the simplest system was selected for the first tuning effort. Thus the FOC-HSI model was used initially - based on pre- vious experience, the FOC is easier to manage; the currents are smoother, providing smoother flux estimates. Once the EKF tuning was acceptable on the FOC system, the simulation was moved to the DTC-HSI simulation, and again successfully tuned. Next, the model was simplified, in an effort to speed calculation loop time. By as- suming that the acceleration during a loop is negligible, the system equations become simplified. The system equations assuming zero acceleration are
d Rs ψF vα dt iα = − L iα + L ω sin(θ) + L
d Rs ψF vβ iβ = − iβ − ω cos(θ) + dt L L L (6.19) d dt ω = 0 d dt θ = ω and the corresponding derivative matrix is simplified considerably:
−Rs 0 ψF sin(θ) ψF ωcos(θ) L L L ψ ψ 0 −Rs − F cos(θ) F ωsin(θ) 0 L L L f = (6.20) 0 0 0 0 0 0 1 0
Tuning proceeded as follows. Diagonal covariance matrices were assumed, and initial values of the matrix values were made based on EKF implementation on motor state estimation in the literature [44]. These values were then tuned using trial and
163 CHAPTER 6. BASELINE AND RESEARCH SYSTEM DEVELOPMENT error, watching for improvement, then convergence of the EKF estimates with the motor simulation in the presence of the added noise. Example tuning outputs are provided in the figures below.
Figure 6.22: EKF simulation with incorrect tuning.
An early, unsuccessful tuning attempt is shown in Figure 6.22. The top two plots are the simulated currents; note that the added noise in the EKF portion is obvious in the EKF-generated currents. In this simulation the EKF output did not converge; about halfway through the simulation the EKF currents, speed (third plot from top), and angle (bottom plot) all diverge from the closed loop simulation. A later, successful tuning under more challenging conditions is included in Figure 6.23. In this case, the inherently noisier DTC-HSI system is used in the tuning; additionally the noise to the EKF currents has been increased tenfold, and the reduced system described in 6.19 and 6.20 was used. Note that, despite these challenges, the states (currents, angle, and speed) all converge. Note that a fifth graph, the estimated
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Figure 6.23: EKF simulation after tuning.
flux, was added on the bottom of this set of plots; the flux estimates converge was well. Once successful tuning was made on the simplified DTC-HSI system, the EKF was moved to hardware implementation, as discussed in the next section.
EKF Hardware Implementation and Results Transition of the EKF to hardware began with copying the latest EKF implemen- tation to the control computer. Next, the latest covariance matrix tuning parameters were added to the setup file, controls for their live tuning were added to the GUI, and the noise that had been generated on the currents for testing purposes was elim- inated. As was done in the simulation, the EKF was set up to run out of the closed loop in parallel with the DTC controller using the LPF automatic compensation scheme. Starting with the final tuning parameters from the simulation, tuning then
165 CHAPTER 6. BASELINE AND RESEARCH SYSTEM DEVELOPMENT progressed as it had been done in simulation: pairs of variables (the state variables iα, iβ, ω, and θ, as well as the estimated flux ψ) from the controller and the EKF the were plotted to the GUI on the same graph, this time live, and compared. Live tuning of the covariance matrix components then proceeded until the EKF-generated variables matched those from the live motor control. Next the EKF was switched into the loop, replacing the LPF automatic compensa- tion scheme, and the controller was run on the EKF-based flux and torque estimation. Further, the estimated angle from the EKF was used in place of that generated by the encoder; it was sufficiently stable to enable operation of the motor off of the EKF angle estimate, a step toward elimination of the encoder. Finally, the EKF input vector was changed: instead of inputting measured volt- ages from the voltage sensor circuit, the applied voltage was estimated using the commanded voltages from the DTC controller as inputs to the EKF. This approach worked; the system ran well, opening the possibility of eliminating not only the volt- age offset problem, but the requirement for a voltage sensor system entirely.
EKF Flux Estimation: Conclusion Flux estimation via the use of an EKF proved successful, in that the EKF system solved problems of the earlier approaches; the voltage offset problem was eliminated, along with the voltage sensors themselves. Additionally, results were promising for use of estimated position and speed, potentially enabling elimination of the encoder. However, the EKF, even in the reduced state, was still very computationally intensive, limiting the loop speed. The search for a flux estimate that would bring the relevant benefits of the EKF with a faster loop speed led to investigation of the current based model, which is discussed in the next section.
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6.6.3.4 Flux Estimation using Current Based Model
The EKF approach to flux estimation showed promise. Elimination of the voltage sensing is attractive, not only eliminating hardware but, due to the required filtering on the voltage sense measurement, also possibly eliminating phase lag issues. However, as was mentioned previously, the EKF was too computationally intensive to run at the desired speeds. In addition, there is another potential issue: link voltage shape. Voltage sensing elimination was accomplished in the EKF by simply estimating applied voltage by using the commanded voltage, instead of the voltage read through the voltage sensors. This approach worked well with the DTC-HSI configuration, because under DTC the voltage applied across the motor terminals is static; held constant throughout the entire loop - however, with the impending application of resonant link inverter, that will no longer be the case. A loop time required to resolve the dynamic, ringing link voltage provided by the resonant inverter, given potential resonance frequencies in excess of 100 kHz, will not be achieved. Avoiding this potential problem, in addition to the goal of reduced computational complexity, was another reason an alternate flux estimation scheme was pursued - a flux estimation approach which was not at all reliant on voltage measurement or estimation. This new approach is the current based model. Estimates for the stator flux linkages in the PMSM are made by using the following relationships, simplified by assuming no saliency in the rotor [12]
ˆ ψα = Lsiα + ψF cos(θ) (6.21) ˆ ψβ = Lsiβ + ψF sin(θ)
The magnitude of the stator flux linkage estimate is calculated using
q ˆ ˆ 2 ˆ 2 ψs = ψα + ψβ (6.22)
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Table 6.4: Flux Estimation Method Comparison Automatic Flux LPF only Magnitude and Phase EKF Current Based Estimation Method Compensation LPF Automatic with - Yes Yes Yes speed Eliminates - - Yes Yes offset issues Eliminates - - Yes Yes Voltage sensor Enable faster - - - Yes loop
and the torque estimate is found using
3P Tˆ = (ψˆ i − ψˆ i ) (6.23) e 2 α β β α
Note that, as desired, neither measured nor estimated voltage is required for this estimation scheme. There was some concern about the simplification inherent in this approach (assumed non-saliency), and also about potential increased computation requirements over the simple LPF approach, however this system worked very well. The current based estimation was coded in Simulink and simulated using the DTC- HSI-PMSM code, and worked well; then it was input into the dSPACE controller, also performing well. As is discussed in the following section, the current based estimation scheme became the choice for research system.
6.6.3.5 Flux Estimation Improvement - Conclusion
A table summarizing the performance of each of the flux estimation techniques is provided in Table 6.4. The current based model provided an improvement over all previous models. This approach does not have to be corrected with speed - it is automatic, like the Automatic Phase Compensation approach. And it has the benefits of the EKF; no requirement
168 CHAPTER 6. BASELINE AND RESEARCH SYSTEM DEVELOPMENT to correct for offset and no need for the voltage sensor hardware. Additionally, it is an improvement over the EKF because of the reduced computational requirements, enabling loop speed increases. Thus the current based model for flux estimation was selected as the standard for the research system. Unfortunately, the system efficiency of the DTC-HSI is still considerably worse than that of the baseline system, the FOC-HSI. Therefore steps were taken to develop diagnostic tools to understand the efficiency issues, and provide improvements. This effort is described in the next section.
6.6.4 DTC-HSI Performance Improvements
Once a flux and torque estimation scheme meeting all requirements was developed and implemented, the efficiency of the DTC-HSI development system was still con- siderably worse than that of the baseline system, the FOC-HSI. One of the two key performance parameters of interest in this study is efficiency; obviously poor effi- ciency was an important issue. Therefore a set of tools to diagnose the cause of the inefficiency of the DTC-HSI system was developed. As the same inverter was used in both of the compared systems (the HSI), the study instead focused on the DTC controller. This section discusses the next steps: to develop tools to analyze the perfor- mance of the DTC-HSI-PMSM system in hardware, with a goal of understanding the efficiency issues; then to systematically add improvements to improve the effi- ciency. Topics covered include verification of controller code operation, comparator improvements, improved current sensing and filtering, and a summary of DTC-HSI performance improvement.
169 CHAPTER 6. BASELINE AND RESEARCH SYSTEM DEVELOPMENT
6.6.4.1 Verification of Controller Code Operation
The goal of the analysis performed in this section was to verify that the DTC con- troller was operating as intended, in hardware. The approach was to gather data during motor operation on a high speed digital oscilloscope (16 channels, isolated inputs, 10 MHz). Data gathered included measurements of voltages and currents (motor line voltages and phase currents, and DC input voltage and current). Addi- tionally, since operation of the DTC controller was under study, a number of internal parameters were scaled and output via spare controller D/A channels, and captured simultaneously on the scopes. Captured controller signals included calculated angle and speed, estimated and commanded flux and torque, torque and flux comparator outputs, selected voltage vector, and calculated sector. The data capture and transfer to Matlab for analysis was formalized, using unique variable naming on all captured signals to enable comparison across runs on multiple days. Post processing was then performed on this data in Matlab, and plots were generated of variables of interest. These plots are discussed in this section. Five areas are covered in this section: sector to encoder mapping, torque compara- tor operation, flux comparator operation, voltage vector selection, and post processed torque and flux estimates.
Sector to Encoder Mapping For reference, the DTC control block diagram is included in Figure 6.24. The first test of interest was to verify that the sector is being correctly determined by the DTC controller. The sector is calculated in the controller based on input from the encoder, connected to the motor shaft. Obviously this mapping must be done correctly, as the sector is used to determine output voltage vector position. The table defining the sectors as a function of electrical angle in degrees is shown in Table 6.5.
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Figure 6.24: DTC control block diagram.
Table 6.5: Sector Definition Sector SectorAngles 1 330-30 2 30-90 3 90-150 4 150-210 5 210-270 6 270-330
During motor operation, the sector output and encoder outputs were captured on the scope; a plot is shown below. The top plot in Figure 6.25 is the electrical angle calculated by the controller, and the bottom plot is the calculated sector. Compar- ison to the sector definitions presented in Table 6.5 shows that the sector is being calculated correctly by the controller.
Torque Comparator Operation The torque comparator operation was the next function to be verified. The input to the torque comparator is the torque error signal, calculated by the difference be- tween commanded torque T ∗ (from the outer speed loop output), and the estimated torque Test. For this test, both of these signals were output to D/As and captured by
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Figure 6.25: DTC Controller electrical angle and calculated sector.
the scope, along with the output of the torque comparator ST . The torque comparator function is shown in Figure 6.26; note that this is structure of the torque comparator by Takahashi [23]. Plots of these torque comparator input and output signals are presented in Figure 6.27.
Figure 6.26: DTC torque comparator function block.
The top plot in Figure 6.27 shows the estimated torque in blue, the commanded torque in green, and the hysteresis bands, referenced to the commanded signal, are
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Figure 6.27: DTC torque comparator operation. in magenta. The bottom plot shows the output of the torque comparator block. Note that the torque comparator has three levels, and that the output follows the comparator function block correctly. Note also that the hysteresis limits are small compared to the swing in commanded torque; hysteresis band sizing is discussed in Section 6.6.4.2. .
Flux Comparator Operation Next the flux comparator operation was verified. The input to the flux comparator is the flux error signal, calculated by the difference between commanded and the
∗ estimated flux signals, ψ and ψest. Both of these signals were output to D/As and captured by the scope, along with the output of the flux comparator Sψ. The flux comparator function is shown in Figure 6.28; note that this is the flux comparator used by Takahashi [23]. Plots of these flux comparator input and output signals are presented in Figure 6.29.
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Figure 6.28: DTC flux comparator function block.
The top plot in Figure 6.29 shows the estimated flux in blue, the commanded flux in green, and the hysteresis bands, referenced to the commanded signal, are in magenta. The bottom plot shows the output of the flux comparator block. Note that hysteresis is demonstrated, and that the output follows the comparator function block correctly.
Voltage Vector Selection Correct selection of the voltage vector, which is the output command of the DTC controller, was verified next. The voltage vector is selected using the signals verified in the previous sections: the torque and flux comparator outputs, and the present sector (location of the shaft). Voltage vector selection is performed according to Table 6.6.
Table 6.6: Voltage Vector Selection
Sψ ST S1 S2 S3 S4 S5 S6 1 1 V2 V3 V4 V5 V6 V1 1 0 V7 V0 V7 V0 V7 V0 1 -1 V6 V1 V2 V3 V4 V5 -1 1 V3 V4 V5 V6 V1 V2 -1 0 V0 V7 V0 V7 V0 V7 -1 -1 V5 V6 V1 V2 V3 V4
The voltage vector selection works as follows. All possible flux comparator outputs
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Figure 6.29: DTC flux comparator operation.
(Sψ) are listed in column one, and all possible torque comparator outputs (ST ) are listed in column two. With Sψ and ST defined, the present rotor location, defined by the sector, is used to select the commanded voltage vector output; all sector possibilities are listed S1 to S6 along the tops of the right hand columns. The voltage vector (V0 - V7) selection, based on the three described inputs, is listed in the column identifying the present sector. An example plot showing the selection process from data gathered during motor operation is shown in Figure 6.30.
The top plot in Figure 6.30 displays the flux comparator output (red), Hψ, while the second plot displays the torque comparator output, HT (green). Plot three shows the sector; the motor rotor is in sector 6 during the presented sample period. The bottom plot shows the selected voltage vector (black). Using Table 6.6 and the data from the top three plots, we see that the voltage selection function is working properly.
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Figure 6.30: DTC voltage vector selection test plot.
Post Processed Torque and Flux Estimates With the completion of the analysis in the previous sections, correct action of all areas of interest in the DTC controller was verified: sector calculation, torque and flux comparator operation, and voltage vector selection (Figure 6.24). The next area to explore was the inputs to the DTC: the flux and torque estimates themselves. The approach used was to compare the flux and torque estimated by the DTC, ˆ ˆ ˆ ˆ ψ and T , with “real-time” estimates, ψpost and Tpost. These post processed estimates were calculated using algorithms identical to those employed by the controller, using currents measured with current guns and captured (with negligible delay) simultane- ously with the controller outputs via the high speed scope. Next these post processed estimated were compared to those used in the DTC controller. Even under the best conditions it can be assumed that some mismatch between the estimates would exist, at the very least due to the quantization and the input filtering, causing the estimated
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flux and torque to look different than those that are post processed without delays. A comparison of DTC-estimated and post-processed torque is shown in Figure 6.31.
Figure 6.31: DTC and post-processed torque estimate comparison.
In 6.31, the DTC torque estimate Tˆ is shown in blue, while the post processed ˆ estimate Tpost is magenta. Immediately a problem becomes obvious: the controller ˆ ˆ estimated torque T is so far behind the post processed estimate Tpost that the con- troller is clearly acting on old data. Torque is one of the inner loop variables; based on the post processed estimates, the controller is driving very wide swings, and causing negative and positive torque excursions, extending the range to three times the mean value. As mentioned above, some delay is expected, but this is rather drastic. This points to the next level of investigation, which is implementing a series of efforts to eliminate this delay.
6.6.4.2 Comparator Improvements
Unlike the PWM scheme, in which voltages are applied across the motor leads for a fraction of the loop time, DTC control applies the selected voltage across the mo- tor leads for the entire control loop. This combined with the PMSM being a low
177 CHAPTER 6. BASELINE AND RESEARCH SYSTEM DEVELOPMENT inductance machine means current changes during a loop can be much larger under DTC control. Since both the torque and flux estimates rely heavily on the current measurements, large di/dts will translate to large changes in the flux and torque estimates. It is obvious from Figure 6.27 that, as the controller is configured, the torque hysteresis bands are too narrow; guaranteeing that the torque estimates continuously exceed the limits of the hysteresis bands, and ensuring constant switching. The proposed approach to remedy this is to change the configuration to enable better torque control; that is, make improvements such that the controller is capable of limiting the estimated torque within the hysteresis bands. This is accomplished by changing the comparator type, and widening the hysteresis bands. The hysteresis comparator initially implemented in the DTC controller was the one used by Takahashi, which was employed to drive an induction machine. An alternative approach, considered because it will enable reduced switching given the same width hysteresis bands, is the use of a simple quantized comparator in place of the hysteresis comparator. A comparison of the two comparators is shown in Figure 6.32.
Figure 6.32: Takahashi (left) and quantized torque comparators.
The quantized comparator was implemented and the hysteresis bands were widened, and data was captured on the operating motor. A comparison of the torque estimates
178 CHAPTER 6. BASELINE AND RESEARCH SYSTEM DEVELOPMENT before and after the change is shown in Figure 6.33.
Figure 6.33: Torque estimate comparison with Takahashi and quantized comparators.
Note that the new comparator demonstrates improved switching control, driving smaller torque excursions. The torque was more closely held within bands as desired, resulting in a considerable improvement in system efficiency.
6.6.4.3 Improved Current Sensing and Filtering
An obvious approach to controller performance improvement was to reduce the lag due to signal filtering. Signal filters are employed on the current measurements; placed at the A/D inputs to the controller to limit noise, inevitable with inverter switching, and also to prevent the aliasing of higher frequency noise into the controller input signals, which will cause control problems. Single pole RC filters were used for this task; a schematic of the current input signal filter design is shown in Figure 6.34. The signal filter is installed in a metal box, with BNC connectors to enable coax cable input, and output directly into the controller A/D input. A photo of the signal filter connected to the controller input is shown in Figure 6.35. In the DTC controller, the goal was to set the corner frequency of the signal filter as high as possible, without incurring either noise or aliasing issues. With the original current sensor, noise was found to be the dominant problem. Setting the corner frequency was
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Figure 6.34: Signal filter schematic.
Figure 6.35: Installed current signal filter. achieved experimentally by running the motor system in open loop, plotting input current signals live on the GUI, and selecting a filter which would eliminate the noise. This frequency was about 1 kHz, well under the Nyquist frequency. One opportunity to increase the signal filter bandwidth was to implement a current sensor configuration which was more immune to noise, and so be able to increase the corner frequency. The output signal of the current sensors originally employed in this effort was a voltage at a signal level of 0 - 5 V, which meant the scaled current range (due to limits at the rail) was about ±2 V for the entire current range of interest. Since the current sensors are located at the inverter output, the signal output lines travel some distance to reach the controller input. Despite grounding and shielding efforts, this voltage-based signal was very susceptible to noise. An alternate current sensor was identified which output a current signal instead
180 CHAPTER 6. BASELINE AND RESEARCH SYSTEM DEVELOPMENT of a voltage signal, to be terminated at a burden resistor located at the signal filter input, very close to the controller input. This new current sensor provided several benefits. First was the signal scale improvement; the new sensor burden resistor can be sized to generate a scaled current signal of at least ±10 V, a signal 5x larger than that of the previous design. Also, the current-based output signal in the new sensor is less susceptible to noise than was the voltage output signal of the previous design. The new current sensors were installed in the system, and a repeat of the setup procedure on the GUI live screen demonstrated that noise was no longer the dominant issue. The corner frequency of the current signal filter could be moved out as far as necessary with this current sensor configuration, limited only by antialiasing concerns. With the new switching configuration incorporated in the previous section, it was noted that considerably less switching was required to control the motor. This enabled an increase in the HSI switching frequency, which had been held to the switching loss limited upper bound of 20 kHz, up to 30 kHz, the controller loop frequency limit. With the new current sensor and the higher frequency controller output, the signal filter corner frequency could be moved: from just under 1000 Hz out to 15 kHz, the Nyquist frequency for the 30 kHz control loop, resulting in additional efficiency benefits.
6.6.4.4 DTC-HSI Performance Improvements - Summary
Work done in this section, verification of key controller operations, improvements in the torque comparator, and replacement of the current sensors with improved, lower noise sensors enabling higher corner frequency signal filters, resulted in significant efficiency improvements. One measure of improvement is the change in estimated torque behavior. A comparison of system performance before and after the improvements is shown in Figure 6.36.
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Figure 6.36: DTC estimated and commanded torque before and after improvements.
The left plot of Figure 6.36 once again, shows the DTC-estimated torque (blue) and post-processed torque (magenta) before any improvements, and the right hand plot shows performance with all improvements in place. Note that the two estimates are much closer in value with the improvements in place, and torque is held to a much tighter range. Another metric of improvement is the shape of the produced current. Ideally the phase current output from the inverter would be a sinusoid at the electrical frequency. A comparison of phase A current from the DTC-HSI-PMSM system running at 600 rpm (40 Hz electrical) before and after the system improvements is shown in Figure 6.37. In Figure 6.37, the phase current before improvement is shown on the left (green), and the after improvements, on the right (blue). Note that the noise in the current has been greatly reduced after the improvements, which is consistent with the measured efficiency improvements. A chart summarizing the impact on the DTC-HSI-PMSM system electrical effi- ciency is captured in Figure 6.38. The efficiency, measured by comparing DC input power of improved configurations normalized to that of the initial system (that is, the system before the improvements
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Figure 6.37: DTC-HSI-PMSM phase currents before (left) and after improvements. described in this section) is shown in Figure 6.38. The efficiency improvement put performance of the DTC-HSI system very close to that of the baseline. With this goal achieved, the next step was conversion to the DTC-ACRLI system.
6.7 DTC-ARCLI Implementation
Studies performed on the DTC-HSI system generated much benefit, providing the op- portunity to verify the internal portions of the DTC were working properly, providing updates to the switching approach, and a chance to greatly reduce the noise and lag in the system and thus improve the flux and torque estimates. Next the system was converted from the hard switching inverter, and all of these improvements were in- corporated into the DTC-ACRLI system. With these improvements, the motor ran well enough to begin performance studies, as discussed in Chapter 7.
183 CHAPTER 6. BASELINE AND RESEARCH SYSTEM DEVELOPMENT
Figure 6.38: DTC-HSI-PMSM efficiency improvement summary.
6.8 Efficiency Measurements
The system efficiency numbers reported previously in this work were made using measurements of DC input power, calculated using measurements from voltage and current meters located at the DC power supply. This approach was valid, consider- ing that the output power was the same in each test configuration (the MUT was driving the same load PM motor/resistor combination), thus ratios of input power were reflective of system configuration relative efficiency. And this level of fidelity was sufficient, given that initial efficiency was so poor, as seen in Figure 6.38. However, with the improvements from this chapter in place, the research DTC-ACRLI system efficiencies approached that of the baseline FOC-HSI system, and more fidelity was required in the power measurements. Thus the goal became to measure input and output power of the inverter more accurately. The setup used to measure inverter efficiency is shown in Figure 6.39. The efficiencies were first calculated by using direct measurement; use of a com- mercial watt meter was initially considered as an approach to make the power mea- surements, but during testing it was determined that the watt meter biased the
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Figure 6.39: Inverter efficiency measurements.
measurements, and so that approach was abandoned. Instead high speed digital os-
cilloscopes and current guns were used to measure VDC and IDC at the input of the inverter, and line voltages and phase currents at the inverter output. In post process- ing, instantaneous powers were calculated and integrated to provide measurements
for the power at the input of the inverter (PDC ) and the inverter output (PM ). The ratio of these input and output powers used to calculate inverter efficiency, using the equation
PM ηINV = (6.24) PDC
This efficiency measurement approach is used in conjunction with the parameter adjustment studies in the DTC-ACRLI system, as discussed in Section 7.1.
185 Chapter 7
Results
Chapter 4 covered the ACRLI inverter design and development, culminating in an operating DTC-ACRLI system successfully driving a test load. Chapter 6 discusses implementation of the simulation motor control models into hardware, emphasizing controller improvements, resulting in an operating research DTC-ACRLI system driv- ing the PMSM motor. This chapter covers experimental studies performed on the research system, the DTC-ACRLI-PMSM, studying the effects of inverter and con- troller parameters on performance, and discusses comparison of two relevant system performance metrics, system efficiency and noise, with the baseline FOC-HSI-PMSM system. Topics covered include inverter parameter studies, controller parameter stud- ies, system efficiency compared to baseline, and system noise compared to baseline.
7.1 Inverter Parameter Studies
In this section, the effects of inverter parameters of interest on the DTC-ACRLI- PMSM system are studied, with a goal of finding optimum settings to improve system performance. Parameters discussed include resonance frequency unclamped, clamp factor, resonance current, resonance frequency clamped, and main switch voltage on. Some of the inverter parameters are adjusted using adjustment variable resistors;
186 CHAPTER 7. RESULTS
there are five on the PCB, designated VR 1-5. They are listed in Table 7.1, and the function of each is discussed in this section.
Table 7.1: ACRLI PCB Adjustment Resistors Adjustment Function VR1 VLS−k VR2 Vclamp VR3 IR VR4 VLS−0 VR5 V0ref
7.1.1 Resonance Frequency Unclamped
The unclamped resonance frequency, called fo, is the natural resonance frequency of the tank circuit in the absence of the clamping circuit. It is defined in equation 4.1, and is repeated here for convenience:
1 fo = √ (7.1) 2π LrCr
As seen in equation 7.1, fo is a function of the resonance circuit components, Lr and
Cr, and so changing the value of fo in the system requires a hardware change.
For this study, changing Lr would have been very time consuming, requiring disassembly of the system to gain access to the resonant board, then removal and
replacement of the inductor before reassembly. Fortunately, Cr was much easier to change; since it was built as two 0.1 µF capacitors in parallel, decreasing Cr simply required snipping the leads of one of the caps to halve Cr; due to square root in denominator, this resulted in approximately a 40% increase in fo. This process was used during testing. A summary of the two unclamped resonant frequencies employed in testing is captured in Table 7.2.
Note that fo is set independently of the other inverter parameters.
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Table 7.2: Unclamped Resonant Frequencies
configuration Lr(µH) Cr(µF ) fo(kHz) 1 20 0.2 80 2 20 0.1 113
7.1.2 Clamping Factor
The clamping factor, k, relates the link voltage at which the clamp switch turns on to the DC bus supply [17]. In theory k has an upper limit of 2.0, and the DC link stays clamped at the defined level, but in practice the output voltage continues rising as the clamp capacitor charges. Since the practical application of this parameter is to describe the peak voltage the link actually achieves, in this report the clamp factor is defined as
V k = link−pk (7.2) VDC where Vlink−pk is the peak value that the clamped link voltage finally reaches, and
VDC is the DC supply voltage. Using this definition, k can exceed 2.0 in practice. The clamp switch control, as described in Section 4.2.3.3, is shown in Figure 7.1:
Figure 7.1: Clamp Switch Control high level schematic.
The clamp switch is turned on when the link voltage reaches the desired clamping level, at which point current from Lr is shunted to the clamp capacitor Cc. At this point the link voltage rises very slowly as the larger clamp capacitor charges. When the Cc current rings back, the link begins to slowly drop, and once the link voltage drops again below the desired clamp level, the clamp switch is turned off. Clamp switch operation is controlled by two of the adjustment resistors, VR1 and
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VR2, which set the voltage input levels to the Clamp Control circuit in (Figure 7.1):
VLS−k is the scaled link voltage for the clamp circuit, and Vclamp sets the clamping voltage value. The clamping factor k is set using both of these adjustment resistors.
Typically VLS−k is set first; using VR1, the link voltage is scaled to provide a good full scale value of link voltage that is still within the rail limits of the comparator.
Next, VR2 is used to set Vclamp to turn the clamp switch on at the desired voltage level. The clamp factor measured in this study is varied from about 1.2 - 2.3. Note that k is set independently of the other inverter parameters.
7.1.3 Resonance Current
The minimum resonance current, called IRmin, is the current required to ensure any link losses are overcome so that voltage across Cr will return to zero at the end of the resonant cycle. Operation of the ACRLI will continue if the value of resonance current requested each cycle is larger than this minimum IRmin; this variable resonance current, called IR, is settable via resistor VR3. IR is used in the Main Switch Control circuit as discussed in Section 4.2.3.2; details are reproduced below for reference. As
Figure 7.2: Main Switch Control high level schematic. seen in Figure 7.2, the current condition of main switch operation is implemented
∗ using resonance current IR added to the command current I , and compared to
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resonant inductor current ILr. In this effort the value of IR is varied from 0.2-2.2A.
Note that IR is set independently of the other inverter parameters.
7.1.4 Resonance Frequency Clamped
As discussed in equation 4.3, repeated below for convenience, the clamping circuit heavily impacts the resonance frequency. The relationship between clamping factor
k and clamped resonance frequency fr is
1 fr = √ (7.3) k(2−k) √ 2[arccos(1 − k) + k−1 ] LrCr
According to equation 7.3, as k approaches 2.0, fr approaches fo; in practice, the peak value of the link voltage can exceed double the DC supply voltage, and so k can exceed 2.0.
Thus fr is a function of the resonant components, Lr and Cr, as well k. However, relationship in equation 7.3 assumes lossless components; that is, IRmin = 0, and thus
resonance current is zero[17]. But in the actual circuit IR is not zero, and in practice
also has a significant impact on fr. During the course of this effort fr ranged from
16 kHz up to 105 kHz, and never reached fo. In the following sections we will discuss
fr as a function of k, of IR, and of fo.
7.1.4.1 fr as a function of k
First we will look at fr as a function of k. In these studies, the resonance current IR is kept constant, and the ACRLI is run unloaded, so that I∗ is also constant at zero.
The first measurements were made by keeping the source voltage VDC constant
at about 15V. The scaled link voltage in the clamp circuit VLS−k (Figure 7.1) was
held constant at an appropriate level, and clamp voltage level Vclamp was adjusted to trigger the clamp switch at varying levels, resulting in different peak link voltages.
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The plots are shown Figure 7.3. In Figure 7.3, the clamping factor k was set at 4
Figure 7.3: Link voltages at varying clamping factors.
levels: k = 2.3 (red), 1.8 (green), 1.33 (blue), and 1.25 (magenta). Note that different values of k have a dramatic impact on link voltage.
Vlink begins to rise when the main switch turns off, which is done once ILr has
∗ ∗ fully charged to IR + I , with IR = 2.2A and I = 0A in this case. Current from Lr
first flows to Cr, then once Vclamp is reached, begins to flow to clamp capacitor Cc.
When Vclamp is set high, much of the current in ILr goes to charging Cr, allowing
link voltage to rise; and when Vclamp is set to a lower value, current transfers to Cc earlier, preventing this voltage rise as intended. However, the relative size of these
capacitors impacts timing: Cc is much larger than Cr, and thus charges more slowly,
resulting in a longer cycle for Vlink when clamping is higher, and directly impacting fr. As discussed in Section 4.2.4.4, longer clamping times also result in higher voltage rises. In the cases above with the higher clamping (k = 1.25 and 1.33), we see that the peaking of the link voltage is much more pronounced than that in the cases with
191 CHAPTER 7. RESULTS lighter clamping. The clamp switch currents under the same conditions are shown Figure 7.4. Note that these currents are all centered around zero; they have been offset, stacked ver- tically to enable easy comparison. This plot shows the current charging (negative)
Figure 7.4: Clamp switch currents at varying clamping factors.
and discharging Cc, and demonstrates that increasing energy is stored in Cc per cycle with increased clamping. Another approach to studying clamping is to change the input DC voltage while keeping the clamping voltage the same. That was done in this next set of plots, again
∗ taken with IR constant and I = 0. The resonant current was set lower than in the
∗ previous test, with IR = 1.3A, and again I = 0A. The results are shown in Figure 7.5.
For the link voltage plots in Figure 7.5, VDC was varied from 16V up to over 28V, and the clamping factor ranged from 1.24-2.2. Note that the peak link voltage was kept about the same, but fr varied considerably. Note also the peak voltage rise in the case of the highest clamping.
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Figure 7.5: Link voltages at varying at constant clamp voltage.
7.1.4.2 fr as a function of IR
The measurements presented in Figure 7.3 and in Figure 7.5 were taken at constant
IR; however, the IR setting between the two tests was different. This provides an opportunity to look at the impact of IR on fr. Clamped resonance frequency is plotted vs. clamping value for the two sets of tests, in Figure 7.6. This test was done at the lower resonance frequency configuration (fo = 80kHz); note that the clamped resonance frequency fr increases with decreasing resonance current. Perhaps the most important impact resonance current has on the DTC-ACRLI system is its effect on consumed power. In the unloaded case (I∗ = 0), input power was measured at several levels of IR; the results are in Figure 7.7. As is seen in Figure
7.7, higher levels of IR result in higher power consumption, obviously an important factor as improved efficiency is a goal of this study. Some insight into the cause of this increased power consumption can be seen by looking at the link voltage as a function of IR; an example is plotted in Figure 7.8. In Figure 7.8, the value of IR was
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Figure 7.6: Clamped resonance frequency vs. k at varying IR.
Figure 7.7: DC power vs. IR. increased from 0.95A (blue) to 1.6A (green). We see that the frequency has dropped with increased IR as expected, and that the more time was spent under clamping, since the additional current was routed to the clamp circuit. Thus a potential cause for the extra power drawn with increased IR is due to losses in the clamp circuit. Although ZVS is employed in the clamp switch, there are still conduction losses to be considered in the switch, and ESR losses in the clamp capacitor. The previous examples were performed on the unloaded ACRLI. Now the DTC- ACRLI driving the PMSM is studied, to verify that the behaviors translate to the
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Figure 7.8: Resonant link voltage with varying IR. system while driving a motor. Under light clamping (k = 2.3), the motor was run to
600 rpm, and measurements were taken as IR was varied. The results are shown in
Figure 7.9. As seen in Figure 7.9, the impact of fr is the same in the loaded case as
Figure 7.9: Clamped resonance frequency vs. IR at 600 rpm. in the unloaded case, that is, increased resonance current leads to decreased clamped resonance frequency. Additionally, the clamp currents for these cases are plotted in Figure 7.10. The currents in Figure 7.10 are all centered around zero; they are offset,
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Figure 7.10: Clamp switch current with varying IR. stacked vertically for easy comparison. The clamp switch current corresponding to the highest IR is the top plot (red); the IR decreases from top to bottom. In the case of the inverter under load, the lower IR values also correspond to less clamping; when the motor is operating this shows up as sparser clamp currents, rather than currents of decreased width, as in the unloaded case. The input power for this test is plotted versus IR in Figure 7.11. As can be seen in Figure 7.11, as in the unloaded
Figure 7.11: System input power vs. IR.
case, increasing IR increases power drawn in the DTC-ACRLI system during motor
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operation.
In conclusion, changes in IR while driving the motor have the same effect as in
the unloaded case, and therefore the impact IR has on system efficiency is certainly a concern.
7.1.4.3 fr as a function of fo
Finally, the impact of the unclamped resonance frequency fo on fr is discussed in this
section. fo is set by the resonant components Cr and Lr. Two different values of Cr were used in this study (Table 7.2). The study of link voltages at varying clamping
∗ factors (Figure 7.3) was repeated, again with IR = 2.2A and I = 0A, with the smaller
Cr (higher fo), and the results are shown in Figure 7.12. Note that the increase in fo
Figure 7.12: Clamped resonance frequency vs. k at varying fo.
corresponds to an increase in fr, but, as expected, even at light clamping the clamped frequency never reaches fo.
7.1.5 Main Switch Voltage On
The main switch is turned on when two conditions are met: the current condition, met when ILr is charging and has not yet reached its charge set point; and the voltage
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condition, met when link voltage Vlink has dropped to zero volts. Control is performed by the Main Switch Control circuit; a schematic is shown in Figure 7.2. The topmost comparator handles the voltage condition, which is met when the scaled link voltage measurement (VLS−0) drops below the zero voltage set point (V0ref ). VLS−0 and V0ref are set using the remaining two adjustment variable resistors, VR4 and VR5 (Table
7.1). Typically VLS−0 is set first; using VR4, the link voltage is scaled to provide a good full scale value of link voltage that is still within the rail limits of the comparator.
Next, VR5 is used to set V0ref , ideally to turn the main switch on when link voltage reaches zero. Under proper operation, when the main switch turns on the switch current is negative; flowing through the diode portion of the switch which has turned on under
ZVS conditions. Then as ILr charges the current goes positive, and is turned off when
ILr is fully charged and the current condition is no longer met. However, if the switch is turned on early, before the link voltage drops to zero, resonance capacitor Cr is discharged through the main switch and current flows in the positive direction first. This is undesirable operation, and lossy, as ZVS is no longer achieved in the main switch. Since zero voltage set point V0ref is adjustable, this condition can be studied.
The ACRLI was run in the unloaded case under varying settings for V0ref , and data was captured. During the test, V0ref was deliberately set too high, causing early switching. The first plot is shown in shown in Figure 7.13. In Figure 7.13, the main switch currents are shown for four different settings of V0ref . The left hand plot, currents are all centered at zero, but are stacked vertically for visibility; the V0ref setting is increased from the bottom to the top plot. The right hand plot shows the currents on top of each other. Note that the first two sets of current behave correctly, but as V0ref increases we see the effects of early main switch turn-on: the current swings positive first, getting more dramatic with earlier turn-on, demonstrating the effects of incorrect timing.
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Figure 7.13: Main switch currents with varying V0ref .
This effect can also be seen in the link voltage, shown in Figure 7.14. In Figure
Figure 7.14: Link voltage with varying V0ref .
7.14 the link voltages are shown in full in the left hand plot, and zoomed in on the plot on the right. The colors of the traces are kept consistent with those in Figure 7.13; thus the earliest main switch turn-on corresponds to the red trace. Note that the link voltage is also impacted by the early turn-on of the main switch; voltage drops to zero early, and rings more. The early switching also affects power consumed; the early turn-on run consumed
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7% more power than did the run measured under correct timing.
7.2 Controller Parameter Studies
In this section, the effects of controller parameters of interest on the DTC-ACRLI- PMSM system are studied, with a goal of finding optimum settings to improve system performance. Parameters discussed include comparator configurations, comparator switching limits, offset angle, and controller loop frequency; outer loop tuning is also discussed.
7.2.1 Comparator Configurations
In this section, switching comparator types are discussed. The DTC system employs two comparators: the flux comparator and the torque comparator, both of which are discussed here.
7.2.1.1 Flux Comparator Configuration
The flux switch configuration is a two-level hysteresis comparator, discussed in Section 6.6.4.1. A schematic of the flux comparator is shown in Figure 7.15. This flux
Figure 7.15: DTC flux switch configuration - two-level hysteresis comparator. comparator type was used throughout the testing.
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7.2.1.2 Torque Comparator Configuration
Two different torque comparator configurations were employed in this study, as dis- cussed in Section 6.6.4.2. The DTC controller and GUI were configured to enable rapid change out of these comparators, to facilitate study under both switching schemes. The first torque switch was a thee-level hysteresis comparator, utilized in Taka- hashi’s initial paper [23] . The configuration is shown in Figure 7.16. The second
Figure 7.16: DTC torque switch configuration 1: Takahashi three-level hysteresis comparator.
torque switch was a two-level quantized comparator. The configuration is shown in Figure 7.17. One difference in performance of the comparators can be seen by study- ing the link power; that is, the power at the ACRLI output. This is displayed in Figure 7.18. In Figure 7.18, link power using the Takahashi comparator is on the left, and the quantized comparator is on the right. With the switching imposed by Takahashi, more regeneration is seen; this leads to busier switching, current reversals in I∗, and more frequent and longer on-time clamp switching. In this case, driving identical loads the Takahashi system required 10% more input power than did the system using the quantized comparator.
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Figure 7.17: DTC torque switch configuration 2: two-level quantized comparator.
Figure 7.18: Link power with different torque comparators.
Study of clamp switch current provides additional insight. The currents in the clamp switches under the same conditions as above is shown in Figure 7.19. Both sets of clamp switch currents are centered at zero, and are offset, stacked vertically for comparison. The clamp stitching under Takahashi (blue) is the bottom trace, and under quantized comparator is in green. Note that the clamp switch currents have increased with the Takahashi comparator. Another insight into the different behaviors of the two torque comparators can be seen by looking at plots of the phase currents and the commanded current I∗. These
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Figure 7.19: Clamp switch current with different torque comparators. are included in Figure 7.20.
Figure 7.20: Phase and commanded currents with different torque comparators.
In Figure 7.20, the left hand plot shows the Takahashi comparator results while the behavior under the quantized comparator is shown on the right. In both cases the motor is running at 600 rpm. Phase currents for phase A, B, and C are in red, green, and blue, respectively, and the commanded current I∗ is in black. With the Takahashi comparator, a current reversal is occurring at about 1/4 of the way through the plot; current swings from 3.5A to -2.5A. This can be understood by observing the
203 CHAPTER 7. RESULTS commanded voltage vectors: in the first portion of the plot, before the reversal, the commanded vector is V 4, corresponding to −iA (per Table 6.6), which agrees with the plot. Next V 2 is commanded, corresponding to −iC . Both of these changes are
∗ consistent with commanded current I displayed in the plot. Because iA was negative at the time of the change and iC was positive, this results in a direction change for I∗. Note that switching in the quantized comparator case does not cause the current reversals, avoiding the associated additional current flow and losses. As was discussed in Section 6.6.4.2, operating under the Takahashi comparator requires more power than does operating under the quantized comparator. Since improved efficiency is a goal of this effort, the quantized torque comparator was selected for use.
7.2.2 Comparator Switching Limits
In this section, the varying of the switching limits on the comparators in the DTC controller is discussed. The DTC controller and GUI were configured to enable live changes to the switching limits, to facilitate study of the switch level impact on performance. This section is divided into two topics; flux comparator switching limits, and torque comparator switching limits.
7.2.2.1 Flux Comparator Switching Limits
During motor control, stator flux linkage estimates were plotted live on an oscillo- scope, and were also calculated in post processing using data captured during the runs. As was discussed in Section 6.6.3, much progress was made during this effort in improving the stator flux linkage estimation. A post-processed flux plot from an early run, before the improvements, is shown in Figure 7.21. A set of estimates from the improved system is shown in Figure 7.22. Note that all of these stator reference
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Figure 7.21: Stator flux linkage estimate before improvements.
Figure 7.22: Stator flux linkage estimates at varying flux comparator switch levels.
frame flux linkage estimates form a circle of a radius equal to ψF , the flux linkage due to the rotor permanent magnets, which has a value of 0.015 V·s; this is as expected because the permanent magnet flux dominates the stator flux linkage. Note also that the spread is much tighter on the improved system, indicating greater control of this inner loop variable. In Figure 7.22, the value of the flux hysteresis limit, Hψ, has been adjusted from 0.4 mV·s (left) to 0.8 mV·s. Note that the thickness of the flux circles is somewhat larger with the larger Hψ command. No change in performance was observed over this Hψ variation range, and no efficiency improvement was observed through its adjustment.
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7.2.2.2 Torque Comparator Switching Limits
As was mentioned in Section 7.2.1, the type of torque comparator employed does have a significant impact on efficiency. Additionally, an efficiency impact was observed with
the adjustment of the torque comparator switching limit value, HT . While driving
the PMSM at 600 rpm, the HT limits on the DTC-ACRLI system were adjusted, and the input power was observed. The results are shown in Figure 7.23. In Figure 7.23,
Figure 7.23: DC input power with varying torque comparator switch levels.
the DC power consumed by the system decreases significantly with the increase of
HT . The benefit plateaus out, and this assisted in selection of the parameter value during operation.
7.2.3 Offset Angle
The encoder on the motor rig is directly attached to the motor shaft. However, the encoder zero count is lost each time the controller is turned off, and so the angle zero is lost. To account for this, during testing the motor shaft was first manually set to approximately the zero point before the system was turned on, then the zero angle was adjusted during operation. Both the FOC and the DTC controllers have built-in offset angles for this purpose. Since the systems were being compared, the desire was to pick identical modes of operation; the choice was to set the offset angle in each
206 CHAPTER 7. RESULTS case to achieve maximum torque per amp (MTPA) operation. Since the load on the MUT was the same in all all cases (BDC motor and resistor) and the speed was the same since both controllers were run in speed control mode, the output power was the same in both cases; thus to achieve MTPA the offset angle was fine-tuned while observing input power to the system, and selecting the point where input power was minimum. One interesting measurement is to compare the power factor angle of the motors under this condition. Although arrived at through very different control algorithms, regardless of the motor control algorithm the offset angle between phase current and phase voltage would theoretically be the same if MTPA were achieved. This comparison was done by capturing motor voltages and currents, and post processing them to enable the fundamental frequencies to be viewed using a LPF with a corner at the electrical frequency. The phase currents and voltages were then plotted to be compared; these plots for the MUT run under FOC-HSI and DTC-ACRLI at 600 rpm are shown in Figure 7.24.
Figure 7.24: Phase voltage and current under FOC-HSI (left) and DTC-ACRLI MPTA control.
In Figure 7.24, the phase A voltages are in blue, and the currents are in green; the FOC-HSI test case is on the left, and DTC-ACRLI test is on the right. Of
207 CHAPTER 7. RESULTS course the LPF will affect the phase of the voltage and current measurements, but it should affect the phases of the fundamentals equally, and so relative angle can still be determined. We do not expect the angle to be exactly zero, due the the PMSM saliency and other factors, but we see that in both cases the voltage and current are nearly in phase. Note that although control was achieved via two very different motor control strategies and different inverters, the phase angle under MTPA operation was essentially the same.
7.2.4 Controller Loop Frequency
As was discussed in 6.6.4, an increase in controller loop frequency improved system efficiency. This is not unexpected, given the DTC switching implementation. The DTC system does not allow for pulse width modulation, so the voltage vectors are applied for the entire loop; this switching approach combined with the low inductance of the motor causes large variations in phase currents over the loop time, negatively impacting controller performance. Faster loop time should allow current control with more fidelity, resulting in improved performance.
7.2.5 Outer Loop Tuning
Since dynamic testing was not in the scope of this study, optimized tuning of the outer (speed) loop was not a priority. The goal was for both systems to hold speed during study. A PI controller is used as the outer loop controller for both the FOC and DTC system. In order to facilitate performance comparisons, the same tuning process was used for both controllers. The tuning was done manually; speed steps were commanded while the speed was plotted on a scope, and live tuning of the speed loop Kp and Ki was done. Kp was set to an underdamped response, and then Ki was increased until error was eliminated. This tuning allowed both systems to hold speed
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while parameters of interest were measured.
7.3 Parameter Study - Conclusion
This summary is intended to capture the best practices from the discussions of the inverter parameter studies (Section 7.1) and controller parameter studies (Section 7.2). Given the characteristics of the PMSM (low inductance) and the switching scheme employed, increased loop frequency drives improvements in performance, as was dis-
cussed in 7.2.4. Accordingly, higher fo and fr would be desired for improved perfor- mance. The choice of switching approach employed in the DTC controller impacts effi- ciency. Selection of the correct torque comparator (the quantized version) and selec-
tion of wider torque switch limits (HT ) both improved efficiency. A decrease in clamping correlated with reduced losses. In the selected inverter configuration, lighter clamping (larger k) translated to higher efficiency, and minimiz- ing the resonant current (which also decreases clamping) also had a positive impact on efficiency. One goal for future work would be to seek ways to limit losses in the clamp circuit. For example, the new switching scheme would likely require a smaller clamp capacitor than the one originally specified; also lower ESR components and improved conduction loss clamp switch could be pursued.
Additionally, continuing best practices, such as setting main switch timing (V0ref ) to ensure ZVS is achieved and setting of the offset angle to ensure max torque per amp (MTPA), is desired for best efficiency.
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7.4 System Efficiency Measurements
A key goal of this effort was to improve motor drive efficiency by employing zero voltage switching (ZVS) in the inverter switches. This section discusses the results. First, the voltages and currents in the switches are studied to verify that ZVS is in fact occurring. Next, comparisons are made between the efficiency of the baseline system, the FOC-HSI, and the research system, the DTC-ACRLI.
7.4.1 ZVS Verification
The goal of ZVS is to control switching such that switches only change state when the voltage across them is zero, thus limiting switching losses incurred when voltage is present across a switch while current is flowing through it. There are three categories of switches in the ACRLI to be considered: the main switch, the clamp switch, and the switches in the six-switch inverter. Each is discussed in the following sections.
7.4.1.1 Main Switch Inverter ZVS
The main switch (SM ) is located in the resonant circuit. As discussed in 4.2.3.2, the Main Switch Control circuit turns SM on when link voltage is zero, and when resonant inductor Lr reaches its charge set point, SM is turned off. Link voltage appears across this switch, and while it is on, the current flowing through it charges Lr. Main switch currents and voltages measured while the DTC- ACRLI was driving the PMSM at 600 rpm are included in Figure 7.25. In Figure 7.25, the top plot shows main switch current, while the lower plot shows voltage across the switch, which is also link voltage. Note that current is flowing while the voltage across the link is zero, showing that ZVS was in fact demonstrated in the main switch.
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Figure 7.25: Main switch current and voltage.
7.4.1.2 Clamp Switch ZVS
The clamp switch (SC ) is located in the clamp circuit, on the resonant board. As discussed in 4.2.3.3, the Clamp Switch Control circuit turns the clamp switch on when the link voltage reaches the desired clamping level, at which point current through
SC charges then discharges the clamp capacitor Cc; and turns it back off again once the link voltage drops below the desired clamp level. The voltage appearing across this switch is the voltage difference between the link and the clamp capacitor; and while SC is on, the current flowing through it charges clamp capacitor Cc. Clamp switch currents and voltages measured while the DTC- ACRLI was driving the PMSM at 600 rpm are included in Figure 7.26. In Figure 7.26, the top plot shows clamp switch current, while the lower plot shows voltage across the switch. Note that current is flowing while the voltage across the link is zero, showing that ZVS was in fact demonstrated in the clamp switch.
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Figure 7.26: Clamp switch current and voltage.
7.4.1.3 Six Switch Inverter ZVS
The six switch inverter carries the motor drive current. Ideally, verification of ZVS operation would be done by observing currents and voltages in individual switches in the six switch inverter, as was done in the previous sections for the main and clamp switches. Unfortunately, this is not possible; due to the construction of the six switch inverter, currents flowing through individual legs cannot be accessed. Instead, a different approach was used to verify ZVS operation. Voltage probes were inserted across the top and bottom switches of phase A of the six switch inverter. As the motor was driven under DTC-ACRLI at 600 rpm, the switch voltages along with the switching commands were captured on a digital oscilloscope; a plot of this measurement is shown in Figure 7.27. In Figure 7.27, the top plot shows the output command for phase A from the control computer: an ON signal commands the top switch in leg A on, and the bottom switch off; and OFF does the opposite, commanding the top switch in leg A off, and the bottom switch on.
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Figure 7.27: Six switch inverter timing.
The second plot (magenta) shows the New Command Available signal, from the control computer, slightly delayed to allow for settling, signifying that a change has been made in the output command voltage vector. This signal clocks the new voltage command into the first set of ACRLI latches as described in 4.2.3.4. But because ZVS operation is desired, the inverter switching state is not changed until the link voltage reaches zero. When this occurs the Main Switch Control circuit sends the Vlink = 0 signal, which clocks the second latch, the output of which is passed on to the six switch inverter via the deadtime circuit. The third plot shows the commands from the output of the deadtime circuit, top switch command (solid blue) and bottom switch command (dashed blue); and the bottom plot shows voltages across the phase A switches, top switch voltage (red) and bottom switch voltage (green). As described in 4.2.3.6, the purpose of the Dead Time Circuit is to prevent shoot- through; to ensure that the top and bottom switches in the same inverter leg are
213 CHAPTER 7. RESULTS not on at the same time. As can be in the third plot, the dead time is operating correctly; the OFF command is issued first, followed by the ON command, regardless of whether the top or the bottom switch of the phase A leg is being turned on. As can be seen in the last two plots, the timing of the switching is being done correctly. After receipt of a New Command Available signal, switching occurs as soon as the link voltage reaches zero. This can be seen by observing the switch voltages: when either switch in ON, the voltage across it is near zero (except for conduction drop), and when it is off, the link voltage is present across it. For ZVS to occur in the six switch inverter the switching commands from the deadtime circuit need to appear while the link voltage is zero; in this case, the link voltage appears across one switch before the change, and the other switch after, indicating a hand-off of the switch current between switches at zero voltage. As this is the case, we see that ZVS has been successfully implemented in the six switch inverter. For comparison, an example from early testing of mistiming of the switching in the six switch inverter is shown in Figure 7.28. Here we see that the voltage transition
Figure 7.28: Six switch inverter incorrect timing example. was late, after the ZVS condition no longer exists. As mentioned in 4.2.3.6, shoot-through prevention is provided automatically under
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ZVS. The dead time circuit was included as a safety precaution to prevent issues during initial testing, and was left in place as it did not impact performance.
7.4.2 Efficiency Comparison vs. Baseline
Although ZVS was successfully demonstrated in all of the system switches in Section 7.4.1, presumably minimizing switching losses, the ACRLI configuration added com- ponents to the power system (the inductor, capacitors, and switches in the Resonant Circuit) which will add losses. The hope is that the switching loss reduction will overcome losses added in the resonant system. In order to quantify potential efficiency improvements, efficiency of the research system (DTC-ACRLI) was compared to that of the baseline system (FOC-HSI), under identical conditions, i.e. both drove the PMSM into identical loads at the same speed (600 rpm). The results are shown in Figure 7.29. In Figure 7.29 the baseline system
Figure 7.29: Efficiency comparison between baseline and test system. relative efficiency is shown at the far left. The first comparison was to the research system implementing a small subset of the improvements described in Chapter 6. Not
215 CHAPTER 7. RESULTS surprisingly, the baseline system performed much more efficiently than this first test system. Next, the improved torque comparator changes were implemented in the DTC controller (quantized comparator, larger HT ), resulting in a system that was a few percent improved over the baseline. Next, the increased resonance frequency was implemented, showing more improvement. Finally, the last improvement was made; the resonance current was reduced - and under these comparison conditions (into the standard motor load at 600 rpm), this final version of the DTC-ACRLI system showed almost an 8% efficiency improvement over the baseline FOC-HSI system.
7.5 System Noise Measurements
A second key performance variable (KPV) of interest is specific power. Input and output filters can constitute a sizable portion of the mass and volume of an inverter system, and thus reduction in the filter size and mass could enable a significant improvement in system specific power. Two types of filter are considered in this study: the inverter input filter, and inverter output filter. The input filter employed in the motor lab was a DC capacitor sized to be large enough to hold the input voltage constant on both systems under study. This was done to eliminate any voltage variation in the input as a variable when comparing systems. No output filtering was used in the motor lab: the inverter output was connected directly to the PMSM. This was done to enable unbiased comparison between systems, by preventing output filtering from impacting noise measurements. Measurements of interest for comparison between systems are thus the inverter input currents, and the motor phase voltages and currents at the output of the in- verter (since input voltage was deliberately held constant for both systems, it is not
216 CHAPTER 7. RESULTS worth studying here). A comparison of these variables plotted versus time is used to understand the differences in the signals under different controller and inverter schemes; and the frequency spectra is presented to quantify the scale of the noise, and to test for improvement provided by the research DTC-ACRLI system over the baseline FOC-HSI system. Thus there were three pairs of variables measured during the tests of the two systems, and time and frequency plots were prepared for each, resulting in six sets of side-by-side plots to discuss. Measurements in all tests were taken while driving the PMSM into the standard load, at 600 rpm. A summary of the test plots is tabulated in Table 7.3.
Table 7.3: Noise Measurements Summary: FOC-HSI vs. DTC-ACRLI P lot V ariable Baseline Research 1 IDC time time 2 IDC frequency frequency 3 IA time time 4 IA frequency frequency 5 VAN time time 6 VAN frequency frequency
These plots are presented and results are discussed in the following sections: input current noise versus baseline; motor phase current noise versus baseline; motor phase voltage noise versus baseline; and noise comparison summary.
7.5.1 Input Current Noise vs. Baseline
Plot 1, the comparison of input currents (IDC ) plotted versus time, is shown in Figure 7.30. In Figure 7.30, three PWM switching cycles of the FOC-HSI system are shown (the PWM switch frequency is 20 kHz). The left hand plot is the FOC-HSI system: due to the nature of the PWM scheme - the switching pulses are centered for all three phases, so sets of input current pulses are generated twice during each cycle - dominant switching noise is be expected to be at twice the PWM frequency (see
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Figure 7.30: Input current comparison at 600 rpm.
Figure 3.3). For the DTC-ACRLI system (right, plotted over the same time span) the controller loop frequency is faster than the FOC-HIS PWM, at 30 kHz, and the clamped resonance resonance frequency is in this case is about 68 kHz. Plot 2 of Table 7.3, the frequency spectra comparison for these measurements, is shown in Figure 7.31.
Figure 7.31: Input current spectra at 600 rpm.
In Figure 7.31, the FOC-HSI system (left) displays a noise spike at the PWM frequency of 20 kHz and its harmonics, with the dominant noise seen at twice the PWM frequency and its harmonics, as expected. In the DTC-ACRLI plot (right), spikes can be seen at the controller loop frequency of 30 kHz and its harmonics, and a broader noise feature is centered near the clamped resonance frequency, about 68 kHz. Based on this data, the DTC-ARCLI system is shown to generate less high fre-
218 CHAPTER 7. RESULTS quency noise on the input current than does the FOC-HSI system.
7.5.2 Motor Phase Current Noise vs. Baseline
Motor phase current comparison, Plot 3 of Table 7.3, is shown in Figure 7.32.
Figure 7.32: Phase current comparison at 600 rpm.
In Figure 7.32, motor phase currents for both systems (FOC-HSI on the left) are plotted showing two electrical cycles. The electrical synchronous for the four pole machine is 40 Hz, and it is obvious and dominant for both machines, and both plots show noise in addition to the synchronous current. Before looking at the frequency spectra, it is helpful to zoom in on the time plot for more insight. This is done on Figure 7.33.
Figure 7.33: Phase current comparison at 600 rpm.
In Figure 7.33, a time period encompassing ten cycles of the FOC-HSI PWM (switching at 20 kHz) is displayed on both plots; and plots for both systems are
219 CHAPTER 7. RESULTS zoomed in on areas of positive peak synchronous current. In the FOC-HSI system (left), repeatable spikes are present at 40 kHz, so again noise is expected at the switch frequency and its harmonics, and dominant at 40 kHz and its harmonics. The DTC- ACRLI phase currents (right) features peaks that are less repeatable, so a broader, flatter spectrum would be expected. The motor phase current frequency spectra for this test configuration, Plot 4 of Table 7.3, is shown in Figure 7.34.
Figure 7.34: Phase current spectra at 600 rpm.
As expected, in Figure 7.34 the spectra for the baseline FOC-HSI system (left) shows peaks at PWM frequency of 20 kHz and its harmonics, and dominant peak is 40 kHz and its harmonics. The research DTC-ACRLI system (right) shows broad, flat noise; notable features include a small peak at the control loop frequency (30 kHz) and a small flat feature at the clamped resonance frequency (68 kHz). Based on these measurements, the DTC-ARCLI system is shown to generate less high frequency noise on the phase current than does the FOC-HSI system.
7.5.3 Motor Phase Voltage Noise vs. Baseline
Motor phase voltage comparison, Plot 5 of Table 7.3, is shown in Figure 7.35. In Fig- ure 7.35, phase A voltage is plotted for 2 electrical cycles. The shape of synchronous waveform is visible in both plots, however, although these output commands repre- sent generation of the same voltage magnitude in both systems, much more noise is
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Figure 7.35: Phase voltage comparison at 600 rpm. visible in the plot of the FOC-HSI system (left) than in the DTC-ACRLI plot. For insight into the nature of the noise a close-up plot is produced, shown in Figure 7.36.
Figure 7.36: Phase voltage comparison at 600 rpm.
In Figure 7.36, a time period encompassing four cycles of the FOC-HSI PWM (switching at 20 kHz) is displayed on both plots; and plots for both systems focus on areas where the inverters output voltages are near a zero crossing. In the FOC-HSI system (left), the noise in the switching is evident; this is due to the hard switching output across the low inductance motor load. High peaks are evident, as is significant ringing. The DTC-ACRLI output (right) displays the resonant peaks of the link voltage applied across the motor phase, with no visible noise. Thus reduced switching noise is expected in the DTC-ACRLI spectrum. The motor phase voltage frequency spectra for this test configuration, Plot 6 of
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Table 7.3, is shown in Figure 7.37.
Figure 7.37: Phase voltage spectra at 600 rpm.
As expected, in Figure 7.37 the spectrum for the baseline FOC-HSI system (left) shows peaks at the PWM frequency of 20 kHz and its harmonics, and the dominant peak is 40 kHz and its harmonics. Once again the research DTC-ACRLI system (right) shows broad, flat noise; notable areas include a small peak at the control loop frequency (30 kHz) and its harmonics, and a small flat feature at the clamped resonance frequency (68 kHz). Based on these measurements, the DTC-ARCLI system is shown to generate less high frequency noise on the phase voltage than does the FOC-HSI system.
7.5.4 Noise Comparison Summary
In this section, the electrical noise present at the input and the output of the inverters while driving the PMSM MUT into the standard test load at 600 rpm was compared for the two systems of interest: the baseline FOC-HSI system, and the research DTC-ARCLI system. Input current and output (motor) phase voltages and currents were studied. In all cases, the research system generated less noise than the baseline system. The greatest noise reduction impact was observed in the phase voltage. This noise decrease would translate to lower filtering requirements for the DTC- ACRLI system, and since filtering is such a large fraction of total inverter weight and
222 CHAPTER 7. RESULTS volume, increases in system power density.
223 Chapter 8
Conclusions
This Chapter is divided into two sections: Contributions of This Work, and Future Work.
8.1 Contributions of This Work
In this dissertation, a novel motor drive system was designed, built and tested: a resonant inverter was used to drive a permanent magnet synchronous motor (PMSM) under direct torque control (DTC). A number of references were identified in the lit- erature which describe the combination of DTC and a resonant inverter to drive three phase motors; however, all of the systems were used to drive induction motors. None focused on a synchronous motor of any type, while this effort employs a synchronous motor: the potentially higher power density PMSM. Additionally, none of the references make an attempt to benchmark the DTC res- onant converter performance to that of the more standard high performance system - a field oriented control (FOC) system combined with a traditional, hard switching in- verter (HSI). This comparison, quantifying system improvement in terms of improved energy efficiency and reduced noise generation (potentially reducing the volume and mass of required filtering) is included in this work as well.
224 CHAPTER 8. CONCLUSIONS
Chapter 2 covers the development of component and controller software models. A motor model for the three phase PMSM; inverter models for the hard switching inverter (three levels of fidelity) and resonant link DC inverter; control models for FOC, DTC, and open loop motor control; and finally, models for the outer loop controller and the load motor are developed and discussed. Chapter 3 includes results of system simulations covering two broad categories: complete system simulations, which include an entire motor drive system; and res- onant inverter simulations. Complete system simulations are developed, and results are presented, for three motor controller configurations: the open loop system, the FOC system, and the DTC system. Finally, simulations of the resonant inverter control and power system components are discussed. Chapter 4 describes the design, build, testing, and implementation of the resonant inverter for this effort. The selection of the resonant topology (the active clamped resonant link inverter, or ACRLI) is discussed, and the design of key components (resonant circuit, main switch control, clamp switch control, latching, and current prediction) is detailed. Next, breadboard and brass board versions of subassemblies are built and tested, and finally assembled; and after checkout, the design and build of a printed circuit board version is described. Chapter 5 includes a description of the specification and buildup of the motor lab for this effort. The selection, acquisition, and setup of the motor controller, the interface computer, the inverter subsystem, the motor under test, the test load, and the support equipment (voltage measurement system, the oscilloscopes, the sensors used, and the power supplies) is described. Chapter 6 covers the hardware implementation of the controllers, motor drives, and motors, resulting in the two systems which were used for the performance com- parison: the FOC-HSI (baseline) system, and the DTC-ACRLI (research) system. To assist in the modelling effort, motor parameters are measured, and the measurements
225 CHAPTER 8. CONCLUSIONS are validated, for both the PMSM the load motors. Next, checkout of the motor lab hardware is described using open loop operation, and the transfer of the simulation controller models to hardware is discussed. DTC implementation and improvement are discussed - multiple approaches to flux and torque estimation improvements are presented, as are various software and hardware improvements. Finally, the DTC- ACRLI (research system) implementation is detailed, and the development of a system efficiency measurement approach is described. Chapter 7 details the experimental results. First, the effects of varying inverter and controller parameters on performance on the research system are discussed, with a conclusion of settings and parameters for best performance. Next, results of the comparison of the research and baseline systems are presented: system efficiency and system electrical noise, at the input and output, are compared. Improved efficiency and reduced generated noise are both reported in the research system, both desirable results for positively impacting key performance parameters (system efficiency and power density) in an aircraft application.
8.2 Future Work
There are a number of potential future work areas, building on lessons learned during this effort. These ideas are discussed in the following paragraphs. Reduced electrical noise, at the input and output, was observed in the research system. Given the large volume and mass of electrical input and output filters, it would be worth extending these results - studying the impact of the reduction in noise considering practical filter designs and EMI specifications; getting a sense of the achievable reduction in filter size this system would provide, and quantifying the possible power density improvement. Investigating the reduction of losses in the clamp circuit might provide significant
226 CHAPTER 8. CONCLUSIONS gains. The new switching scheme would likely require a smaller clamp capacitor than the one originally specified. Also, a lower ESR clamp capacitor and a clamp switch with reduced conduction loss could be pursued. Increasing both the resonant frequency and the control loop frequency would be beneficial, given the low inductance of the PMSM. Motor control code simplification to enable loop time reduction and resonant component resizing might bring additional gains. Many assumptions were made in the resonant component sizing based on the best guesses available at the time: anticipated modulation scheme, voltages and currents in components under operation, switch specifications (forward drops on transistors and diodes), etc. With an operating system, many of those initial assumptions could be validated with measurement. Using these new parameters, the resonant component design could be redone, providing possible gains. For ease, an encoder was employed in the research effort. Evaluation of sensorless operation in the DTC-ACRLI system would be worthwhile, to determine the ease with which the encoder could be eliminated. Increasing the study space by repeating the baseline and research system compar- isons at multiple speeds and power levels might prove interesting. Also, performing dynamic testing comparisons would be worth considering, to see if the research system provides the dynamic improvements DTC is intended to bring over FOC systems.
227 Appendix A
Motor Parameters
The parameters for the motor under test (PMSM) and the load motor (BDC) are presented in Tables A.1 and A.2.
Table A.1: PMSM Motor Parameters P arameter V alue Units Power 200 W Speed 3000 RPM Ld 620 µH Lq 710 µH Rs 0.090 ohms ψF 0.015 V·s J 0.0001 kg·m2 P 4 pole pairs
Table A.2: Load Motor Parameters P arameter V alue Units Power 250 W Voltage 42 V DC Speed 4000 RPM Kt 0.077 Nm/A Kv 0.0087 V/rpm Rs 3.9 ohms J 0.0007 kg.m2
228 Appendix B
Resonant Circuit Design Code
The Matlab script used for calculating the resonant components Lr and Cr is included below.
229 APPENDIX B. RESONANT CIRCUIT DESIGN CODE
Figure B.1: Resonant component design script.
230 Appendix C
Resonant Inverter Schematics
The schematics for the ACRLI resonant inverter are included in this Appendix. A list of the included schematics is included in Table C.1.
Table C.1: ACRLI Schematic List P age Schematic 1 ACRLI Interconnects Resonant Circuit 2 Board 3 Main Switch Control 4 Clamp Switch Control 5 Current Predict 6 Latching 7 Dead Time Circuit
231 APPENDIX C. RESONANT INVERTER SCHEMATICS C.1: ACRLI interconnects. Figure
232 APPENDIX C. RESONANT INVERTER SCHEMATICS C.2: ACRLI Resonant circuit board. Figure
233 APPENDIX C. RESONANT INVERTER SCHEMATICS C.3: ACRLI main switch control circuit. Figure
234 APPENDIX C. RESONANT INVERTER SCHEMATICS C.4: ACRLI clamp switch control circuit. Figure
235 APPENDIX C. RESONANT INVERTER SCHEMATICS C.5: ACRLI current predict circuit. Figure
236 APPENDIX C. RESONANT INVERTER SCHEMATICS C.6: ACRLI latching circuit. Figure
237 APPENDIX C. RESONANT INVERTER SCHEMATICS C.7: ACRLI dead time circuit. Figure
238 Appendix D
Voltage Measurement Circuit
The schematic for the voltage measurement circuit employed during early testing is included below, in Figure D.1.
239 APPENDIX D. VOLTAGE MEASUREMENT CIRCUIT D.1: ACRLI dead time circuit. Figure
240 Appendix E
Data Sheets
Links for the data sheets for the inverter components are included below.
HSI inverter model and data sheet: PowerEx PM300CLA060 https://www.mitsubishielectric-mesh.com/products/pdf/PM300CLA060 e.pdf
Switch model and data sheet: IRFB17N20D http://www.irf.com/product-info/datasheets/data/irfb17n20d.pdf
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