Non-Ideal Behavior of Circuit Components 5.0 Introduction

Total Page:16

File Type:pdf, Size:1020Kb

Non-Ideal Behavior of Circuit Components 5.0 Introduction Module 5: Non-Ideal Behavior of Circuit Components 5.0 Introduction Most engineers are introduced to common circuit elements such as resistors, capacitors, and inductors through a course in basic circuit analysis. In this context, these common devices are often presented in the ideal sense, i.e. as being purely resistive, capacitive, or inductive, respectively. The effects due to wires, leads, and connectors are also usually neglected in circuit analysis. While this approach is clearly necessary to impart the fundamental concepts of circuit behavior, this ideal presentation often leads to misconceptions about how actual devices function. In reality, each type of circuit element exhibits some combination of resistive, capacitive, and inductive behaviors when operated at any frequency other than zero. The types of materials and construction techniques employed may also affect the performance of circuit elements. These factors can cause the impedance, capacitance, or inductance of these devices to differ greatly from the expected ideal values. As was demonstrated in previous chapters, even simple devices and circuits may require relatively complex models in order to correctly predict behavior over a wide frequency range. Through the application of certain approximations, these complex models may be simplified somewhat, while still providing the needed physical insight into device behavior. In this chapter, equivalent circuit models of basic circuit elements will be developed and analyzed. The response of these circuit elements to a broad range of operational inputs will be discussed and related to the topics presented in the earlier sections. From this it will become clear that what is usually referred to as "non-ideal" behavior of a circuit element is, in actuality, perfectly natural behavior in a regime that lies outside the range of validity of commonly accepted approximations. 5.1 Internal Impedance of Electric Circuit Elements circular wires Effects due to wires are often overlooked when considering the behavior of electric circuits. For most low-frequency applications, wires are modeled as having no effect on circuit performance. However, the impedance of wires can become significant under certain conditions. In this section a general expression for the internal impedance of a long cylindrical conductor (i.e., a wire) will be developed. Consider an infinitely-long, thin conductor, with cylindrical cross-section of radius a, having £ ¡ permittivity , permeability µ, and conductivity ¢ . It will be assumed that a current with density J £ £ flows through the conductor, supported by electric and magnetic fields E and H. Because the conductor is infinite in length, and has rotational symmetry, longitudinal and axial invariance will be assumed, therefore £ £ ¤ ¤ ¥ E ¥ H ¤ ¤ 0 z z and 5-1 z z^ r ¦ E ^ ¦ H p(r, ,z) r^ E z zo y ¦ J 2a x Figure 1. Infinitely-long cylindrical conductor. £ £ ¤ ¤ ¥ E ¥ H ¤¨§ ¤¨§ 0 . It will also be assumed that only an axially directed electric field exists within the conductor £ ¥ E zˆEz(r) which corresponds to the current density within the conductor. Also let the electric field maintained at the conductor surface by the external sources which excite the system be represented by ¥ ¥ Ezo Ez (r a) . A system of time-harmonic Maxwell's equations appropriately specialized for this structure is £ © ¥ E ¥ 0 ¡ £ £ © ¥ ×E j B 5-2 £ £ © ¡ ¥ ×B µ ( ¢ j )E £ © B ¥ 0 . Expanding the curl equations yields ¤ § § E ¥ ˆ z ˆ ¤ j (rˆB B zˆB ) r r z and B z 1 ˆ zˆ (rB ) µ ( j )zˆE . r r r z = = From these it is apparent that Br Bz 0 with Ez j B r and 1 (rB ) µ( j )E . (*) r r z Substitution of the expression 1 Ez B j r into (*) yields 1 r Ez µ ( j )Ez . r r j r which may be rewritten 5-3 2E E z 1 z 2 k E 0 z (**) 2r r r where 2 2 k µ 1 j . Equation (**) is known as Bessel's equation of order zero, with parameter k. This second order partial differential equation has solution Ez(r) AJo (kr) BNo (kr) where Jo (kr) is a Bessel function of the first kind of order zero, and No (kr) is a Bessel function of the second kind of order zero. A review of Bessel functions appears at the end of this chapter. The region under consideration is that lying inside the conductor. This region contains the point r =0, therefore the behavior of the Bessel functions for small arguments must be examined. As r approaches zero, the Bessel function of the second kind becomes infinitely large. In order for Ez to remain finite, the constant B must be equal to zero. The general expression for the electric field at any point inside the conductor is thus Ez (r) AJo (kr) . The unknown constant A is determined through application of boundary conditions. At the surface of the cylindrical conductor Ez(r a) Ezo A Jo(ka) thus Ezo A . Jo (ka) Substitution into the general expression for electric field within the conductor yields the electric field distribution over the cross-section of the wire. Jo(kr) E z(r) Ezo . Jo(ka) 5-4 Application of Ohm's law gives the distribution of current density in the cross-section of the conductor Jo(kr) Jz(r) Ezo . Jo(ka) The total axial current is found by integration of the current density over the cross-section of the conductor a a 2#$ Ezo " # I ! J (r)ds J (r)2 rdr rJ (kr)dr . z z z J (ka) o c.s. 0 o 0 A change of variables is now made by letting kr x. Then when r 0, x 0, and when r a, x ka, and dr 1 kdx. This results in ka 2#$ Ezo 1 I xJ (x)dx . z J (ka) 2 o o 0 k Application of a look-up integration formula for Bessel functions (see the Bessel function review section) leads to x & ka 2#$ Ezo 1 % I x J (x) z 2 1 Jo(ka) k x & 0 or 2# a Ezo J1(ka) Iz . k Jo(ka) From this expression for the total axial current, the internal impedance per unit length of a cylindrical conductor is determined E J (ka) ' k z i zo o . * I 2) a J (ka) z ( 1 This general expression is valid for all frequencies. Approximations to this general formula can 5-5 be made to obtain expressions which are valid in the limit that the frequency of operation is either very low, or very high. - internal impedance in the low frequency limit The frequency dependence of the impedance expression above occurs through the wavenumber term 2 2 * - k µ , 1 j . , (+ + From this, it can be seen that the wavenumber k approaches zero as approaches zero in the low frequency limit. This would suggest performing a power series + expansion to investigate the behavior of the Bessel function terms for small arguments. The Bessel function of the first kind may be expressed as a power series 3 .0/ m n 2m ( 2 1) z Jn(z) . n 3 2m 1 m 0 4 ( 2 m! (m n)! For small values of z z 2 z 2 2 4 6 2 J (z) 5 1 ... 1 o 4 4 and z z 3 z z 2 2 4 6 2 J (z) 5 ... 1 . 1 2 16 2 8 Substitution of these approximations into the general impedance expression results in 2 2 2 2 2 2 i k 1 2 k a /4 1 k a k a 6 2 4 z 6 1 1 2 2 2 7 8 7 8 2 a ka/2(1 2 k a /8) a 4 8 or 5-6 2 i 1 k 6 z 2 2 7$8 8 7 a 8 but 2 2 8 : 2 6!2 9 8 k 59 µ 1 j j µ 9: 9: because 8 ( ) » 1 at low frequencies. Substitution leads to the expression for the impedance per unit length of a cylindrical conductor in the low frequency limit i i i i i 1 µ 4 4 5 4 9 5 9 z 5 r jx r j l j 2 7 8 7 a 8 where i 1 r 5 2 8 7 a is the low frequency (dc) internal resistance per unit length, and i µ l 5 87 is the low frequency (dc) internal inductance per unit length. - internal impedance in the high frequency limit Once again, we begin with an examination of the wavenumber term 2 ;< 2 > ? k µ = 1 j . < = < For a good conductor, conductivity = is large, therefore it is assumed that / » 1. It is ? ? apparent that k approaches infinity as the frequency < approaches infinity, thus in the high frequency limit 5-7 < 2 @ k > j µ . ? or 1 A j A j ; < < ; < k ; j j µ j µ e 2 2 je 4 µ ? ? ? < 2 B j 2 > B < ; ; ; µ 1 j > B ? j µ ( 1 j) C 2 ? 2 where CED 2 ; 1 < µ F fµ ? ? is the skin depth or the depth that fields penetrate into a conductor, as discussed in Chapter 2. In this case, the behavior of the Bessel function terms for large arguments must be investigated. The asymptotic formula for large arguments for the Bessel function of the first kind is K K 2 K n L L lim J (x) J cos x . n K x GIH x 2 4 The internal impedance per unit length of the cylindrical conductor can now be expressed as K J (ka) cos ka L 1/4 i k o k z J K K K N M 2 a M J (ka) 2 a 1 cos ka L 3/4 or P Q S jO (ka 1/4) j (ka 1/4) R i k e e R z J .
Recommended publications
  • PDF Package Information
    This version: Apr. 2001 Previous version: Jun. 1997 PACKAGE INFORMATION 1. PACKAGE CLASSIFICATIONS This document is Chapter 1 of the package information document consisting of 8 chapters in total. PACKAGE INFORMATION 1. PACKAGE CLASSIFICATIONS 1. PACKAGE CLASSIFICATIONS 1.1 Packaging Trends In recent years, marked advances have been made in the electronics field. One such advance has been the progression from vacuum tubes to transistors and finally, to ICs. ICs themselves have been more highly integrated into LSIs, VLSIs, and now, ULSIs. With increased functions and pin counts, IC packages have had to change significantly in the last few years in order to keep-up with the advancement in semiconductor development. Functions required for conventional IC packages are as follows: 1) To protect IC chips from the external environment 2) To facilitate the packaging and handling of IC chips 3) To dissipate heat generated by IC chips 4) To protect the electrical characteristics of the IC Standard dual-in-line packages (DIP), which fulfill these basic requirements, have enjoyed wide usage in the electronics industry for a number of years. With increasing integration and higher speed ICs, and with the miniaturization of electronic equipment, newer packages have been requested by the industry which incorporate the functions listed below: 1) Multi-pin I/O 2) Ultra-miniature packages 3) Packages suited to high density ICs 4) Improved heat resistance for use with reflow soldering techniques 5) High throughput speed 6) Improved heat dissipation 7) Lower cost per pin In response to these requests, OKI has developed a diversified family of packages to meet the myriad requirements of today’s burgeoning electronics industry.
    [Show full text]
  • Parasitic Oscillation and Ringing of Power Mosfets Application Note
    Parasitic Oscillation and Ringing of Power MOSFETs Application Note Parasitic Oscillation and Ringing of Power MOSFETs Description This document describes the causes of and solutions for parasitic oscillation and ringing of power MOSFETs. © 2017 - 2018 1 2018-07-26 Toshiba Electronic Devices & Storage Corporation Parasitic Oscillation and Ringing of Power MOSFETs Application Note Table of Contents Description ............................................................................................................................................ 1 Table of Contents ................................................................................................................................. 2 1. Parasitic oscillation and ringing of a standalone MOSFET .......................................................... 3 2. Forming of an oscillation network ....................................................................................................... 3 2.1. Oscillation phenomenon ..................................................................................................................... 3 2.1.1. Feedback circuit (positive and negative feedback) ......................................................................... 4 2.1.2. Conditions for oscillation ...................................................................................................................... 5 2.2. MOSFET oscillation .............................................................................................................................. 5 2.2.1.
    [Show full text]
  • Packaging Product Specification
    Packaging Product Specification PS007225-0607 Copyright ©2007 by ZiLOG, Inc. All rights reserved. www.zilog.com DO NOT USE IN LIFE SUPPORT Warning: LIFE SUPPORT POLICY ZiLOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF ZiLOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer ©2007 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered trademarks of ZiLOG, Inc.
    [Show full text]
  • Surface Mount • Chips, Melfs & Sots Introduction
    ® Association Connecting Electronics Industries DRM-18H (G) Global License This PDF document is licensed for simultaneous usage on every computer throughout all company facilities and locations. Global License files may be opened, copied or downloaded onto individual computers, or over computer networks, intranets, internet or web. Appropriate security measures and policies must be in place to prevent access to this PDF version of the IPC-DRM-18H by anyone from outside the licensed company. DEMO ONLY Version This is a promotional sample of the IPC Training and Reference Guide — DRM-18H / PDF Version. Please do not use this SAMPLE for training or reference purposes. IPC is a not-for-profit association for the electronics industry. Please respect our copyright. You may order printed or PDF versions of DRM-18H from IPC at: www.ipctraining.org, [email protected], or call (847) 597-2862. Table of Contents Terminology Surface Mount • CHIPs, MELFs & SOTs Introduction ......................... 2 Chip Components ....................... 39 Through Hole vs. Surface Mount ....... 3 Chip Components/Resistor .............. 40 Through Hole Leads ................ 3, 4 Chip Components/Capacitor ............. 41 Surface Mount Leadless .............. 4 Tantalum Capacitor ..................... 42 Surface Mount Leaded ............... 5 MELF ................................. 43 Component Packaging ................ 6 SOT/SOD .............................. 44 Identifying Components ............... 7 DPAK.................................. 45 Lead-Free Components
    [Show full text]
  • Aluminum Electrolytic Capacitors
    ALUMINUM ELECTROLYTIC CAPACITORS Snap-in Terminal Type, Withstanding Overvoltage series AD series Withstanding 3000 hours application of ripple current at 105°C. Suited for 100V/200V switch-over use in switching power supplies. Withstanding overvoltage and suited for IEC-60950 application. Withstandard AD overvoltage GU Specifications a Item Performance Characteristics Category Temperature Range – 40 ~ +105°C Rated Voltage Range 250V Rated Capacitance Range 82 ~ 1200µF Capacitance Tolerance ± 20% at 120Hz, 20°C Leakage Current I 3 CV (µA) (After 5 minutes' application of rated voltage) [C:Rated Capacitance (µF), V:Voltage (V)] Rated voltage(V) 250 Measurement frequency:120Hz, Temperature:20°C tan δ tan δ (MAX.) 0.15 Rated voltage(V) 250 Measurement frequency:120Hz Stability at Low Temperature Z—25°C/Z+20°C 3 Impedance ratio ZT/Z20 (MAX.) Z—40°C/Z+20°C 12 After an application of DC voltage (in the range of rated DC voltage Capacitance change Within ±20% of intial value even after over-lapping the specified ripple current)for 3000 hours Endurance tan δ 200% or less of intial spesified value at 105°C, capacitors meet the characteristic requirements listed at Leakage current Initial specified value or less right. Capacitance change Within ±15% of intial value After leaving capacitors under no load at 105°C for 1000 hours, they Shelf Life tan δ 150% or less of intial spesified value meet the requirements listed at right. Leakage current Initial specified value or less Withstand excess voltage Not defective after 7 hours continuous charges of 360VDC at 70°C atmosphere. Marking Printed with white color letter on black sleeve.
    [Show full text]
  • Resistors, Capacitors and Inductors Are Not As They Appear
    Paper ID #21050 Resistors, Capacitors and Inductors Are Not as They Appear Dr. Paul Benjamin Crilly, U.S. Coast Guard Academy Paul Crilly is a Professor of Electrical Engineering at the United States Coast Guard Academy. He re- ceived his Ph.D. from New Mexico State University, his M. S. and B.S. degrees at Rensselaer Polytechnic Institute, all in Electrical Engineering. He was previously an Associate Professor of Electrical and Com- puter Engineering at the University of Tennessee and was a Development Engineer at the Hewlett Packard Company. His areas of interest include laboratory development, antennas, wireless communications, sig- nal processing, and instrumentation. Dr. Tooran Emami, U.S. Coast Guard Academy Tooran Emami is an associate professor of Electrical Engineering at the U. S. Coast Guard Academy. She received M.S. and Ph.D. degrees in Electrical Engineering from Wichita State University in 2006 and 2009, respectively. Dr. Emami was an adjunct faculty member of the Department of Electrical Engineering and Computer Science at Wichita State University for three semesters. Her research interests are Proportional Integral Derivative (PID) controllers, robust control, time delay, compensator design, and filter design applications, for continuous-time and discrete-time systems. c American Society for Engineering Education, 2018 Abstract This paper presents an analysis of the basic elements of an electrical circuit in order that undergraduate engineering students will experience, and thereby understand the non-ideal nature of electrical components. It is motivated by the fact that many electrical engineering students, after they have completed their first circuits course believe that the assigned or measured values of a given resistor (R), inductor (L) or capacitor (C) are within the manufacturer’s stated tolerances and are in fact pure Rs, Ls and Cs.
    [Show full text]
  • Lead Type Disc Ceramic Capacitors (Safety Standard Certified)
    C85E.pdf Feb. 1,2021 Lead Type Disc Ceramic Capacitors (Safety Standard Certifi ed) Resin Molding SMD Type Ceramic Capacitors (Safety Standard Certifi ed) !Note • Please read rating and !CAUTION (for storage, operating, rating, soldering, mounting and handling) in this catalog to prevent smoking and/or burning, etc. C85E.pdf • This catalog has only typical specifications. Therefore, please approve our product specifications or transact the approval sheet for product specifications before ordering. Feb. 1,2021 EU RoHS Compliant • All the products in this catalog comply with EU RoHS. • EU RoHS is "the European Directive 2011/65/EU on the Restriction of the Use of Certain Hazardous Substances in Electrical and Electronic Equipment." • For more details, please refer to our web page, "Murata's Approach for EU RoHS" (https://www.murata.com/en-eu/support/ compliance/rohs). !Note • Please read rating and !CAUTION (for storage, operating, rating, soldering, mounting and handling) in this catalog to prevent smoking and/or burning, etc. C85E.pdf • This catalog has only typical specifications. Therefore, please approve our product specifications or transact the approval sheet for product specifications before ordering. Feb. 1,2021 1 Contents Product specifications are as of January 2021. Part Numbering p2 2 Safety Standard Certified Resin Molding SMD Type Ceramic Capacitors for General Purpose 1 Type EA (Reinforced Insulation) -Class X1, Y1- (Recommend) p5 Type EA Specifications and Test Methods p7 Type EA Complemant of Test Methods p9 3 Type EA Packing
    [Show full text]
  • Dual In-Line Package
    DUAL IN-LINE PACKAGE In microelectronics, a dual in-line package (DIP), sometimes called a DIL package, is an electronic device package with a rectangular housing and two parallel rows of electrical connecting pins. The pins are all parallel, point downward, and extend past the bottom plane of the package at least enough to be through-hole mounted to a printed circuit board (PCB), i.e. to pass through holes on the PCB and be soldered on the other side. DIP is also sometimes considered to stand for dual in-line pin, in which case the phrase "DIP package" is non-redundant. Generally, a DIP is relatively broadly defined as any rectangular package with two uniformly spaced parallel rows of pins pointing downward, whether it contains an IC chip or some other device(s), and whether the pins emerge from the sides of the package and bend downwards or emerge directly from the bottom of the package and are completely straight. In more specific usage, the term refers only an IC package of the former description (with bent leads at the sides.) A DIP is usually referred to as a DIPn, where n is the total number of pins. For example, a microcircuit package with two rows of seven vertical leads would be a DIP14. The photograph at the upper right shows three DIP14 ICs. DIPs may be used for semiconductor integrated circuits (ICs, "chips"), like logic gates, analog circuits, and microprocessors, which is by far their most common use. They may also be used for other types of devices including arrays of discrete components such as resistors (often called resistor packs), arrays of miniature rocker or slide switches known as DIP switches, various LED arrays including segmented and bargraph displays and light bars, miniature rotary encoder switches, and electromechanical relays.
    [Show full text]
  • Aluminum Electrolytic Capacitors Radial Lead Type
    Aluminum Electrolytic Capacitors Radial Lead Type FR-A series Features Country of origin ● Endurance : 105 ℃ 5000 h to 10000 h ● Malaysia ● Low ESR (Same as FM Series) ● RoHS compliant Specifications Category temp. range –40 ℃ to +105 ℃ Rated voltage range 6.3 V to 100 V Capacitance range 4.7 μF to 8200 μF Capacitance tolerance ±20 % (120 Hz / +20℃) Leakage current I ≦ 0.01 CV (μA) After 2 minutes Rated voltage(V) 6.3 10 16 25 35 50 63 100 (120 Hz /+20℃) Dissipation factor(tan δ) Dissipation factor(tan δ) 0.22 0.19 0.16 0.14 0.12 0.10 0.09 0.08 For capacitance value ≧ 1000 μF, add 0.02 per every 1000 μF. After following life test with DC voltage and +105 ℃±2 ℃ ripple current value applied (The sum of DC and ripple peak voltage shall not exceed the rated working voltage) when the capacitors are restored to 20 ℃, the capacitors shall meet the limits specified bellow. Duration ø5×11, ø6.3×11.2 : 5000 h Endurance ø8×11.5, ø10×12.5 : 6000 h (✽ Only EEUFR1V331U (ø10×12.5) 5000 h) ø8×15, ø10×16 : 8000 h, ø8×20 : 9000 h ø10×20 to ø10×25, ø12.5×20 to ø12.5×35, ø16×20 to ø16×25 : 10000 h Capacitance change Within ±25 % of the initial value (6.3 V to 10 V : ±30 %) Dissipation factor(tan δ) ≦ 200 % of the initial limit DC leakage current Within the initial limit After storage for 1000 h at +105 ℃±2 ℃ with no voltage applied and then being Shelf life stabilized at +20 °C, capacitors shall meet the limits specified in endurance.
    [Show full text]
  • Inductance Bridge
    OPERATING INSTRUCTIONS TYPE 667-A INDUCTANCE BRIDGE Serio I No. L.l \ i GENERAL RADIO COMPANY 410-I OPERATING INSTRUCTIONS TYPE 667-A INDUCTANCE BRIDGE Form 410-1 March, 1959 G E .N E R A L R A D I 0 C 0 M P A N Y WEST CONCORD, MASSACHUSETTS, USA SPECIFICATIONS INDUCTANCE RANGE: 0. 1 ,uh to 1 h; can be extended by Type 1482 Standard Inductors used as external standards. With internal standard, the bridge wi II balance for storage factors from 0.06 to infinity at 1 kc. ACCURACY: Inductance, ±(0.2% + 0.1 ,uh). Capacitance across UN­ KNOWN terminals is about 60 ,u,uf. Specific value is given for each bridge. This capacitance will increQse the measured value of large inductors fractionally by 2 w LC. At 1 kc and 1 h the increase is about 0.24%. By direct substitution, two nearly equal external inductors can be compared to ±0.02%. FREQUENCY RANGE: All calibration adjustments are made at 1 kc. The bridge can be used from 60 cps to 10 kc, but errors resulting from stray capacitance increase with frequency. When large inductances are measured with external standards~ the frequency should be lowered to avoid resonance ef· fects. STANDARDS: The standard inductor is a 1-mh toroid wound on a ce­ ramic form. Resistance bal once is made by resistors having small residual inductances. MOUNTING: Shielded walnut cabinet. ·ACCESSORIES REQUIRED: Oscillator, amplifier, and earphones or vi sua I null de­ tector. Refer to paragraph 1. 3. ACCESSORIES SUPPLIED: Two Type 274-NC<;l Shielded Connectors.
    [Show full text]
  • HI-8020 Rev. G
    HI-8020, HI-8120 CMOS High Voltage November 2007 Display Driver GENERAL DESCRIPTION PIN CONFIGURATION (Top View) The HI-8020 & HI-8120 high voltage display drivers are functional replacements for the AMI S5420 and Micrel MIC8013/8014 series. These CMOS prod- S26 S25 S24 S23 S22 S21 S20 DOUT 32 BP S19 ucts are designed to drive liquid crystal displays by S18 converting 5 volt serial data to parallel segment and 6 5 4 3 2 1 44 43 42 41 40 backplane waveforms with amplitudes up to 30 volts. S27 7 39 S17 The HI-8020 & HI-8120 differ from the HI-8010 by S28 8 38 S16 only the shift register clock and chip select gating S29 9 HI-8020J-85 37 S15 S30 10 36 VEE logic. The HI-8020 has TTL logic inputs whereas the & S31 11 HI-8120J-85 35 S14 HI-8120 has CMOS logic inputs. S32 12 34 S13 N/C 13 33 S12 44 - PIN VSS 14 32 S11 Both devices can drive up to 38 segments and have 3 PLASTIC CS 15 31 S10 possible shift register data taps to provide options to PLCC CL 16 30 S9 cascade devices for larger displays. Data is clocked LD 17 29 S8 into a 38 stage shift register and parallel latched 18 19 20 21 22 23 24 25 26 27 28 before the output translators by a Load input. DD S1 S2 S3 S4 S5 S6 S7 DIN V The HI-8020 & HI-8120 are available in ceramic LCDØ leadless chip carriers and plastic PLCC packages.
    [Show full text]
  • Packing Datasheet
    Corporate names revised in the documents On March 1st 2015, system LSI businesses of Fujitsu Limited and Panasonic Corporation have been consolidated and transferred to Socionext Inc. The corporate names “Fujitsu Semiconductor Limited” and “Panasonic” all in this document have been revised to the “Socionext”. Thank you for your cooperation and understanding of this notice. March 2, 2015 Socionext Inc. http://www.socionext.com/en/ Package Lineup/ Forms/ Structures 1. Package Lineup 2. Package Forms 3. Package Structures DB81-10002-2E 1 Package Lineup/ Forms/ Structures 1. Package Lineup PACKAGE 1. Package Lineup The packages are classified as follows, according to form, material, and the mounting methods for which they are suited. Packages Lead inserted type Matrix type Standard PGA Surface mounted type Flat type Dual lead SOP TSOP I TSOP II LSSOP TSSOP Quad lead QFP LQFP TQFP UQFP HQFP Leadless chip carrier Quad lead QFN Matrix type BGA FBGA SPGA Tape carrier Dual lead DTP Quad lead QTP 2 DB81-10002-2E Package Lineup/ Forms/ Structures PACKAGE 1. Package Lineup Name of Description Lead pitch (mm) package PGA Pin Grid Array Package 1.27/2.54 SOP Small Outline Package (straight lead) 1.27 Small Outline L-Leaded Package SSOP Shrink Small Outline L-Leaded Package 0.65/0.80/1.00 TSOP (1) Thin Small Outline L-Leaded Package (1) 0.50/0.55/0.60 TSOP (2) Thin Small Outline L-Leaded Package (2) 0.50/0.80/1.00/1.27 SON Small Outline Non-Leaded Package 0.50/1.00 QFP Quad Flat Package (straight lead) 0.40/0.50/0.65/0.80/1.00 Quad Flat L-Leaded Package LQFP* Low-Profile Quad Flat L-Leaded Package 0.40/0.50/0.65/0.80 TQFP Thin Quad Flat L-Leaded Package 0.40/0.50 HQFP QFP with Heat Sink 0.40/0.50/0.65 LCC* Leadless Chip Carrier 1.016/1.27 QFN Quad Flat Non-Leaded Package BGA Ball Grid Array 1.27/1.0 FBGA Fine pitch Ball Grid Array 0.8/0.75/0.65/0.5 DTP Dual Tape Carrier Package ⎯ QTP Quad Tape Carrier Package ⎯ *: Package name used by Fujitsu Microelectronics Limited DB81-10002-2E 3 Package Lineup/ Forms/ Structures 2.
    [Show full text]