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AN-1205 Electrical Performance of Packages (Rev. A)

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AN-1205 Electrical Performance of Packages (Rev. A) Application Report SNOA405A–May 2004–Revised May 2004 AN-1205 Electrical Performance of Packages ABSTRACT This note is a snapshot of electrical performance of National's IC packages. It is provided to help designers get an idea about electrical parasitics associated with the package, and help them compare the electrical performance of different packages. The electrical performance of a package is usually expressed in terms of resistance (R), inductance (L), and capacitance (C). Example R-L-C data is provided for National's package types. Contents 1 Introduction .................................................................................................................. 2 1.1 RESISTANCE ...................................................................................................... 2 1.2 INDUCTANCE ...................................................................................................... 2 1.3 CAPACITANCE .................................................................................................... 2 1.4 FREQUENCY LIMITATIONS OF R-L-C PARAMETERS ..................................................... 3 2 Circuit Model of a Package Lead ......................................................................................... 3 3 Example R-L-C Values for Packages .................................................................................... 3 3.1 LAMINATE BASED CSP (CHIP-SCALE PACKAGE) ......................................................... 4 3.2 BGA PACKAGES .................................................................................................. 5 4 Wirebonds .................................................................................................................... 7 List of Figures 1 Inductance of a Signal Loop............................................................................................... 2 2 Equivalent of three package leads........................................................................................ 3 3 Laminate CSP packages (not to scale) .................................................................................. 5 4 Ball Grid Array packages .................................................................................................. 6 List of Tables 1 Frequency limitations of RLC parameters ............................................................................... 3 2 Example RLC values for lead-frame based packages and micro SMD ............................................. 4 3 Example RLC data for CSP packages ................................................................................... 5 4 Example RLC Characteristics of BGAs (without planes) .............................................................. 6 5 AC Inductance - EBGA packages ........................................................................................ 6 6 Resistance and Capacitance - EBGA packages........................................................................ 7 7 Wirebond inductance ....................................................................................................... 7 All trademarks are the property of their respective owners. SNOA405A–May 2004–Revised May 2004 AN-1205 Electrical Performance of Packages 1 Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Introduction www.ti.com 1 Introduction This note is a snapshot of electrical performance of National's IC packages. It is provided to help designers get an idea about electrical parasitics associated with the package, and help them compare the electrical performance of different packages. The electrical performance of a package is usually expressed in terms of resistance (R), inductance (L), and capacitance (C). Example R-L-C data is provided for National's package types. 1.1 RESISTANCE Resistance is the cause of IR drops in the package. DC resistance is the resistance of a conductor when the entire cross section of the conductor is carrying current. At higher frequencies, the current is concentrated along the surface of the conductor, due to skin effect. AC resistance increases with frequency, because as the frequency increases, skin depth decreases, and the available cross section for the current flow decreases. AC resistance varies linearly with length of the conductor, but not with respect to cross sectional area. 1.2 INDUCTANCE Inductance (L) is defined as the relationship between the following for a closed current path: • flux linkage (λ) and current flow (i): λ = L × i or • time varying voltage (v) and current (i): v = L × di /dt On an IC package, signals propagate in and out through the signal leads and return through the power leads. The closed current path (or loop) is thus formed by signal leads together with power or ground leads. It is also possible to calculate inductance for an open circuit path, or a section of a closed loop (e.g., just a single lead). This is called partial inductance. Using this concept, the inductance contributions of different elements in the loop (and their interactions) can be separated into different inductance elements. This allows the designer to determine return paths and noise by simulation. It is possible to determine the total loop inductance of an IO signal (returning through the power lead) or a differential pair using partial self and mutual inductance. (See Figure 1). DC and AC Inductance: DC Inductance is calculated assuming that the current flows through the entire cross section of the conductor. AC inductance is calculated assuming that the skin depth is small compared to the cross section of the conductor, and current flows only on the surface of the conductors. Both DC and AC Inductance can be provided for packages. To determine which inductance is appropriate for your application, please see the section "Frequency limitations of R-L-C parameters". Figure 1. Inductance of a Signal Loop 1.3 CAPACITANCE Self capacitance is the capacitance of any element to "ground". In package electrical models, the plane on the PC board is assumed to be an ideal ground. Thus, self capacitance of any package element is the capacitance of that element to the board plane. Mutual capacitance is the capacitance between any two elements. For example, in a lumped model of ball grid array package, capacitance from a package trace to the package VSS plane is mutual capacitance. 2 AN-1205 Electrical Performance of Packages SNOA405A–May 2004–Revised May 2004 Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated www.ti.com Circuit Model of a Package Lead 1.4 FREQUENCY LIMITATIONS OF R-L-C PARAMETERS As long as the conductor lengths are small compared to the maximum sinusoidal frequency of the signal, the lumped R-L-C approximation of the element is appropriate. For digital ICs, a lumped model is appropriate for a maximum lead length of 60 × tr (tr is rise time in nanoseconds and length is in millimeters). When using lumped elements, it is important to know which parameters (DC or AC) should be used. Table 1 gives this information. Transmission line models or distributed models should be used for high frequencies. To determine if your product requires this analysis, contact your local National Semiconductor technical representative. Table 1. Frequency limitations of RLC parameters Parameter Valid Frequency Range DC Resistance Leadframe packages: DC to 500 kHz Substrate packages: DC to 5 MHz AC Resistance Leadframe packages: 500 kHz to any freq. Substrate packages: 5 MHz to any freq. DC Inductance Leadframe packages: DC to 10 MHz Substrate packages: DC to 100 MHz Leadframe packages: 10 MHz to any frequency provided lumped model is adequate. AC Inductance Substrate packages: 10 MHz to any frequency provided lumped model is adequate. Capacitance From DC to any frequency, as long as dielectric loss can be neglected. 2 Circuit Model of a Package Lead National Semiconductor defines package models in terms of their T-equivalent circuits. Each lead has two terminals - a "source" and a "sink" - representing its two ends. In a T-equivalent circuit, the lead inductance and resistance are divided in two parts, and placed on either sides of the lead capacitance. Figure 2 shows a T-equivalent model of three leads. The leads are labeled "Lead 1", "Lead 2" and "Return". Signal current flows in or out of "Lead 1" and return current flows on the "Return" lead. Mutual inductance between signal and return lead significantly affects the performance of the signal loop. Therefore, mutual inductance of all leads to the ground lead must be included in detailed simulations. Similarly for calculating package cross-talk, mutual inductance between two signal leads should be taken into account. Package circuit models can be provided in SPICE format. For package SPICE models contact your local National Semiconductor technical representative. Figure 2. Equivalent of three package leads 3 Example R-L-C Values for Packages This section provides RLC values for National's packages. The following is true for the data presented in this note: 1. Example R-L-C data is provided for typical leads only. For detailed analysis, accurate package models SNOA405A–May 2004–Revised May 2004 AN-1205 Electrical Performance of Packages 3 Submit Documentation Feedback Copyright © 2004, Texas Instruments Incorporated Example R-L-C Values for Packages www.ti.com should be obtained. 2. The PC board plane is assumed 20 mils (0.5 mm) below the seating plane of the package. 3. Wirebond parasitics are not included in this section; they are separately
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