Ethernet Datasheet Ethernet XAUI Physical Coding Sublayer (PCS) IP
Overview
Cadence IP Factory delivers custom, synthesizable Application Processor IP to support specific design requirements. Host XGMII Interface CPU 1 CPU 2 or
The Cadence Ethernet XAUI PCS IP provides C (XGM) GMII XAUI Config 4x
the logic required to integrate a XAUI PCS with a UI PCS Interface SerDes 10G Ethernet MAC (XGM) into any system on chip XA MDIO (SoC). 10/40G MA PMA/PMD
Compliant with IEEE Standard 802.3 and 802.3az, SoC the Cadence Ethernet XAUI PCS IP has many configurable features and input parameters to Figure 1: Example System Level Block Diagram customize the XAUI PCS for the specific needs of any application. The Cadence Ethernet XAUI PCS IP also supports Clause 36 of IEEE Standard 802.3 for applications requiring up to four Gigabit Ethernet ports.
The Cadence Ethernet XAUI PCS IP is architected to quickly and easily integrate into any SoC, and to connect seamlessly to a Cadence, or third-party, SerDes through a XAUI (4x10-bit) interface. Access from the MAC to the XAUI PCS is through a demultiplexed 64-bit XGMII interface, or a 4-port GMII interface.
Cadence IP Factory offers a comprehensive IP solution that is in volume production, and has been successfully implemented in more than 400 applications.
Key Features
• 64-bit demuxed XGMII works with Cadence XGM 10G • Optional 1Gb/s mode with 4x GMII channels Ethernet MAC
• Standard 10-bit data path • Operates at 312.5MHz
• Built-in Idle conversion • Lane synchronization and lane-to-lane alignment
• Optional MDIO interface for PHY management • Support for IEEE 802.3az Energy-Efficient Ethernet
• 8b/10b encoding/decoding for each lane • TX buffer option for phase compensation Product Details 8b RX Lane-to-Lane 8b Data[63:0] 8b 8b 10b 10b Deskew 10b/8b Comma The Cadence Ethernet XAUI PCS IP provides the functionality 8b CTC
XGMII and Ctrl[7:0] Decoder Alignment Idle Replacement 8b of a physical coding sublayer (PCS) to facilitate full-duplex 10G, 8b 8b 10b 10b 10b/8b Comma CTC or optional 4x1G, Ethernet communication with a compliant MAC 8b Decoder Alignment Port A 8b to GMII 8b 8b 10b 10b 10b/8b Comma and XAUI-based SerDes. 8b CTC Port B 8b to GMII Decoder Alignment 8b 8b 8b 10b 10b
GMII 10b/8b Comma Port C 8b to GMII CTC Decoder Alignment Receive Path 8b Port D 8b to GMII XA
For each lane, the receive path realigns unaligned data from the UI Interface xgmii_sel SerDes to the correct 10b boundary (comma alignment) before XAUI passing data to the 10b/8b decoder. 32b 8b TX Idle Conversion Data[63:0] 8b and 8b 10b 4b 8b 8b/10b
XGMII Code Group In the case of 10G operation, decoded data is sent to the CTC Ctrl[7:0] Encoder Insertion 8b 8b 10b FIFO for over/underrun detection. Data from the four receive lanes 8b/10b 8b Encoder is then passed to additional logic for lane-to-lane deskewing and Port A GMII to 8b 8b 10b 8b 8b/10b Port B GMII to 8b Encoder idle replacement (realignment) prior to transmission to the MAC. TX Buffer (optional) 8b 8b 10b
GMII 8b/10b Port C GMII to 8b Encoder In the case of 1G operation, each lane operates as an independent 8b Port D GMII to 8b 1G channel and does not require deskewing. Therefore, decoded data is sent directly from the 10b/8b decoder to an 8b-to-GMII converter for transmission to the MAC. Figure 2: IP Level Block Diagram An optional transmit buffer is available to decouple the XAUI PCS Transmit Path from the MAC for simpler clock tree insertion. For each lane, in the case of 10G operation the transmit path performs idle conversion and code group generation before Cadence IP Factory passing data to the 8b/10b encoder. The 8b/10b encoder then Cadence IP Factory can deliver various configurations of Ethernet sends encoded data to the SerDes. PCS to meet your design requirements.
In the case of 1G operation, each lane operates as an independent For more information, visit www.cadence.com/ip 1G channel and does not require idle conversion. Therefore, GMII traffic is sent to a GMII-to-8b converter for code group conversion before passing data to the 8b/10b encoder. The 8b/10b encoder then sends encoded data to the SerDes.
Benefits Deliverables • Low Risk solutions – Silicon proven design • Verilog HDL • Ease of Use – Customizable with easy integration • Cadence® Encounter® RTL Compiler synthesis scripts • Designed by an industry leader – Cadence is an active • User guide with full programming interface, parameterization contributor to 802.3 standards working groups instructions, and synthesis instructions • Verilog testbench Related Products • Cadence® Verification IP for Ethernet Available Products • 10/40G Ethernet MAC (XGM) IP • Ethernet XAUI PCS IP • 10GBASE-R Ethernet PCS (PCSR) IP • Ethernet XAUI20 PCS IP • 10/40G Ethernet PHY IP
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