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Siu System Interface Unit Reference Manual Freescale Semiconductor, Inc. SIU SYSTEM INTERFACE UNIT REFERENCE MANUAL . c This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without notice. Information in this n document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied copyright licenses granted hereunder I to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this document. , r o t c u PowerPC microcontrollers embody the intellectual property of IBM and of Motorola. However, neither party assumes any responsibility or liability as to any aspects of the per- formance, operation, or other attributes of the microprocessor as marketed by the other party. Neither party is to be considered an agent or representative of the other party, d and neither has granted any right or authority to the other to assume or create any express or implied obligations on its behalf. Information such as data sheets, as well as sales n terms and conditions such as prices, schedules, and support, for the microprocessor may vary as between IBM and Motorola. Accordingly, customers wishing to learn more o information about the products as marketed by a given party should contact that party. c i Motorola reserves the right to modify this manual and/or any of the products as described herein without further notice. Nothing in this manual, nor in any of the errata sheets, data sheets, and other supporting documentation, shall be interpreted as conveying an express or implied warranty, representation, or guarantee regarding the suitability of the m products for any particular purpose. The parties do not assume any liability or obligation for damages of any kind arising out of the application or use of these materials. Any e warranty or other obligations as to the products described herein shall be undertaken solely by the marketing party to the customer, under a separate sale agreement between S the marketing party and the customer. In the absence of such an agreement, no liability is assumed by the marketing party for any damages, actual or otherwise. e “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals”, must be validated for each customer application by customer's l technical experts. Neither IBM nor Motorola convey any license under their respective intellectual property rights nor the rights of others. The products described in this manual a are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, c or for any other application in which the failure of the product could create a situation where personal injury or death may occur.Should customer purchase or use the products s for any such unintended or unauthorized application, customer shall indemnify and hold IBM and Motorola and their respective officers, employees, subsidiaries, affiliates, and e distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death e associated with such unintended or unauthorized use, even if such claim alleges that Motorola or IBM was negligent regarding the design or manufacture of the part. r F MOTOROLA and the Motorola logo are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. PowerPC, PowerPC Architecture, and POWER are trademarks of IBM Corp. used by Motorola under license from IBM Corp. © MOTOROLA, INC. 1994, 1996 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... Freescale Semiconductor,Inc. F o r M o r G e o I n t f o o : r w m w a t w i o . f n r e O e n s c T a h l i e s . c P o r o m d u c t , Freescale TABLE Semiconductor, OF CONTENTS Inc. Paragraph Title Page PREFACE Audience ....................................................................................................xiii Additional Reading .....................................................................................xiii Conventions ...............................................................................................xiii Nomenclature .............................................................................................xiv SECTION 1OVERVIEW . 1.1 SIU Overview ............................................................................................1-2 . 1.2 SIU Block Diagram ....................................................................................1-3 c 1.3 SIU Address Map ......................................................................................1-3 n I 1.4 Peripheral Control Unit Overview ..............................................................1-5 , 1.5 PCU Block Diagram ..................................................................................1-5 r 1.6 PCU Address Map .....................................................................................1-6 o t c SECTION 2 SIGNAL DESCRIPTIONS u d n 2.1 Pin Characteristics ....................................................................................2-1 o 2.2 Signal Descriptions ....................................................................................2-2 c 2.2.1 Bus Arbitration and Reservation Support Signals .............................2-2 i 2.2.1.1 Bus Request (BR) ........................................................................2-2 m 2.2.1.2 Bus Grant (BG) ............................................................................2-3 e 2.2.1.3 Bus Busy (BB) ..............................................................................2-4 S 2.2.1.4 Cancel Reservation (CR) .............................................................2-4 e l 2.2.2 Address Phase Signals .....................................................................2-4 a 2.2.2.1 Address Bus (ADDR[0:29]) ..........................................................2-5 c 2.2.2.2 Write/Read (WR) ..........................................................................2-5 s 2.2.2.3 Burst Indicator (BURST) ..............................................................2-5 e 2.2.2.4 Byte Enables (BE[0:3]) .................................................................2-6 e r 2.2.2.5 Transfer Start (TS) .......................................................................2-6 F 2.2.2.6 Address Acknowledge (AACK) ....................................................2-6 2.2.2.7 Burst Inhibit (BI) ...........................................................................2-7 2.2.2.8 Address Retry (ARETRY) ............................................................2-8 2.2.2.9 Address Type (AT[0:1]) ................................................................2-8 2.2.2.10 Cycle Types (CT[0:3]) ..................................................................2-9 2.2.3 Data Phase Signals ...........................................................................2-9 2.2.3.1 Data Bus (DATA[0:31]) ................................................................2-9 2.2.3.2 Burst Data in Progress (BDIP) ...................................................2-10 2.2.3.3 Transfer Acknowledge (TA) .......................................................2-10 2.2.3.4 Transfer Error Acknowledge (TEA) ............................................2-11 2.2.3.5 Data Strobe (DS) .......................................................................2-11 2.2.4 Development Support Signals .........................................................2-11 SIU MOTOROLA REFERENCE MANUAL For More Information On This Product, iii Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Paragraph Title Page 2.2.4.1 Development Port Serial Data Out (DSDO) .............................. 2-11 2.2.4.2 Development Port Serial Data In (DSDI) ................................... 2-12 2.2.4.3 Development Port Serial Clock Input (DSCK) ........................... 2-12 2.2.4.4 Instruction Fetch Visibility Signals (VF[0:2]) .............................. 2-12 2.2.4.5 Instruction Flush Count (VFLS[0:1]) .......................................... 2-13 2.2.4.6 Watchpoints (WP[0:5]) ............................................................... 2-13 2.2.5 Chip-Select Signals ......................................................................... 2-13 2.2.5.1 Chip Select for System Boot Memory (CSBOOT) ..................... 2-13 2.2.5.2 Chip Selects for External Memory (CS[0:11]) ............................ 2-14 2.2.6 Clock Signals .................................................................................. 2-14 2.2.6.1 Clock Output (CLKOUT) ............................................................ 2-14 . 2.2.6.2 Engineering Clock Output (ECROUT) ....................................... 2-14 c 2.2.6.3 Crystal Oscillator Connections (EXTAL, XTAL) ......................... 2-14 n 2.2.6.4 External Filter Capacitor Pins (XFCP, XFCN) ........................... 2-15 I 2.2.6.5 Clock Mode (MODCLK) ............................................................. 2-15 , r 2.2.6.6 Phase-Locked Loop Lock Signal (PLLL) ................................... 2-15 o 2.2.6.7 Power-Down Wake-Up (PDWU) ................................................ 2-15 t c 2.2.7 Reset Signals .................................................................................. 2-15 u 2.2.7.1 Reset
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