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An Introduction to Openvg™ FTF-AUT-F0465

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An Introduction to Openvg™ FTF-AUT-F0465 An Introduction to OpenVG™ FTF-AUT-F0465 Oliver Tian | Auto FAE M A Y . 2 0 1 4 TM External Use Agenda • Trend of Graphics in Vehicle • Roadmap of Cluster • Introduction of Rainbow/Vybrid • OpenVG Scenario • Development Ecosystem • Conclusion TM External Use 1 Trend of Graphics in Vehicle TM External Use 2 The Connected Vehicle Infotainment + Communication + Security • Consumer electronics trends are dictating features in the car • Always connected, applications driven, advanced graphics • Infotainment systems becoming battleground for Auto differentiation • As more connected systems get introduced into the vehicle, the need for security is critical − Increasing external communication features (Bluetooth, TPMS, Ethernet, Wi-Fi, etc). − Future interface for vehicle-to-vehicle and vehicle-to-infrastructure. TM External Use 3 Mobility for Everyone Affordable Solutions for Emerging Markets • 100M vehicles annually forecasted before 2020, on top of motorcycle & e-bike growth • 80% of quantity growth after 2015 happening in emerging markets • Safety and emissions reduction are key for a sustainable development Source: IHS Automotive, February 2014 TM External Use 4 More, More, More for Less, Less, Less More performance, more embedded memory, more safety for less cost, less power and less development effort More • Electronic complexity • ECUs per car (50+) • MCUs per car (100+) • In-car Wi-Fi ® (7.2Mbps and 3.7Bpcs by 2017) iSuppli Less Reuse • Other markets have less critical applications • Some automotive specific challenges TM External Use 5 Today’s Car • Complex computerized control − Millions of lines of code, from multiple vendors − Dozens of distinct ECUs, from multiple vendors • Shared internal networking (e.g., CAN, FlexRay) − Increasing external communications features . Telematics, Bluetooth, TPMS, RDS, XM radio, GPS, keyless start/entry, USB ports, Wi-Fi, etc. TM External Use 6 Tomorrow’s car -> much more of everything • The Infrastructure − The Intelligent Transportation System (ITS) . V2V/ACAS, V2I, traffic control, autonomous driving, real-time data fusion, pervasive sensing TM External Use 7 Driver Information Systems Roadmap Applications st Q3 15 I.MX 8 SOLO 1 Si Jan12 I.MX 6 DUAL ARM Cortex-Dual A7/M4, High-end VSPA, 2D-ACE, GC355 Q1 15 I.MX 6 SLX +VPU I.MX 6 DUALLITE Proposal Best Graphics, ARM Cortex-Dual A7/M4, May12 VSPA, 2D-ACE, GC355 Q1 ‘14 Performance & I.MX 6 SLX I.MX 6 SOLO Planning Integration I.MX53 Execution Jun 14 MACHxx (Halo) ARM Cortex-A5/M4/M0+, 2D- Mid-range ACE, 2D-GPU, GC355 Production Jan 13 SVF5/3R Pin Compatible (Faraday/Vybrid) QFP/BGA’s Optimized ARM Cortex-Dual A5/M4, S08 Core MPC5645S 2D-ACE, GC355 Graphics, High (Rainbow) MACCxx S12 Core Integration Q2 15 (Corona) S12z Core (MagniV) ARM Cortex-/M4/M0+, 2D-ACE, Power Architecture 2D-GPU, GC255 MPC5606S Pin Compatible Cost Effective ARM Cortex Performance (Spectrum) Color Graphics QFP’s Security Aug 12 S12ZVH (Lumen-4WL) Q1’16 Low-end S12XHY LumenNG512 (Sea Wasp) ARM CortexM0+, 2xCANPhy, MagniV S12HY Nov 12 (Lumen-2W) Lowest System S12ZVHY Cost, High (Jellyfish) Integration S08LG32 2011 2012 2013 2014 2015 2016 2017 TM External Use 8 r6 11-Feb-14 MPC5645S: Rainbow 2M General Characteritics: System Debug Crossbar Masters • PPC e200z4d Dual Issue core, 5 stage pipeline, 4k I-Cache Integration • 16 entry Memory Management Unit TCON JTAG Z160 • 2M FLASH with ECC PPCTM RSDS DCU • 64k SRAM with ECC VReg Nexus e200z4d 2D VIU DCU Lite • 16 channel DMA Class 3+ Core Oscillator GFX • Memory Protection Unit (16 regions) (4k I-cache) • QuadSPI Serial Flash Interface FMPLLx2 • Voltage Regulator with external ballast transistor RTC/32Kosc MMU • Real Time Counter + 32kHz crystal oscillator 16ch • Watchdog, Periodic Interrupt Timer, System Timer Interrupt DMA • 4-16MHz XOSC Controller • Frequency Modulated PLL (x2) • Nexus 3+ / JTAG CROSSBAR SWITCH Graphics Features: Memory Protection Unit (MPU) • 2D Graphics Accelerator: AMD z160 OpenVG • 1M Graphics SRAM • Display Control Unit: 4 planes / 16 layers PIT • Display Conrol Unit –Lite: 2 planes / 4 layers WDOG • DDR DRAM interface (324BGA only) Sys Timer 64k 1M I/O RLE DDR-2 2M Quad • Video input Unit (VIU) SRAM Graphics Bridge Decode DRAM Flash SPI2 • RLE Decoder Boot SRAM Interface Assist EEE Crossbar General Characteristics: Module • Up to 120MHz operation (BAM) Slaves • Low power modes • -40 to +105C, 3.0V to 5.5V • 176LQFP, 208LQFP, 324BGA package options Communications I/O System Peripherals and Communications: • 6 Stepper Motor Drivers with Stall Detection 20 ch SSD eMIOS0 eMIOS1 3 4 3 4 • Sound Generator Module SGM ATD 6 16ch 16ch FlexCAN LINFlex DSPI I2C • 3xCAN, 3xDSPI, 4xI2C, 4xLIN 10bit SMD • 32 channel eMIOS (PWM+Timer) • 20 channel, 10bit ADC TM External Use 9 Vybrid F Series System Key Functional Characteristics: • Cortex-A5 “value“ processor for best MIPs/mW • On-chip SRAM, 2D-ACE, Quad-SPI and RTOS result NEON optimized HMI Tools Royalty-free CODECS/Libraries Comm Stacks RTOS in low system cost (no DRAM) • Flexible memory solution configurable based on application needs (1.5MB SRAM or 1MB SRAM + 512K Power Multimedia Cortex-A5 L2) Management Up to 400MHz Connectivity - single 3.3V supply NEON/FPU USB OTG + Phy • DDR3 and OpenVG support for performance critical - low voltage reset 32KB/32KB L1 applications USB OTG + Phy • Synchronous Audio Interface (SAI) supporting 1.5MB SRAM System eMMC/SD independent I2S, TDM, AC97 and Codec/DSP Connectivity x2 System and interfaces CAN General Purpose x2 Audio I/O • Enhanced Serial Audio Interface (ESAI) with I2S and I2C DMA SAI x4 (i2s x4) x4 ESAI x1 (i2s x6) AC97 modes HAB 4.1 Security UART/LIN Tamper Detect SP/DIF x6 Receiver/Transmitter Key Electrical Characteristics: SPI Watchdog Timer Sample Rate x3 Other Timers (x8) Convertor • A5 at up to 400MHz, and DDR3-800 Media Local Bus Real Time Clock AudioReciever Multiplexer • -40 to +85C (ambient) 3-wire 10/100 Ethernet Pulse Width • 3.0V to 3.6V supply (3.3V nominal) Modulator Display I/O Package: GPIO 2D-ACE x2 External Memory Animation &Comp Engine • 144/176 LQFP; 364MAPBGA 2x 12-bit SAR ADC DRAM (16-bit) with Touchscreen OpenVG GPU LPDDR2, DDR3 (GC355) Initial Samples: Dual Quad-SPI 2x 12-bit DAC Segment Display Flash (SDR and DDR) With Tone Generation Controller (4x40) • Ready Internal Temperature NAND/NOR Flash Monitor Camera Input, 18-bit + 8/16b Composite (4 to 1)) Enablement • Production Software including CODECs, Stacks, RTOS • UI development Tools for 2D-ACE • Radio Reference Design – HW and SW TM External Use 10 • ARM Core Architecture: - Cortex M4 vehicle processor - Cortex A5 application processor MACHxx Block Diagram - Cortex M0+ I/O processor • 4MByte ECC flash • 2x 512KB ECC SRAM Power Management Cortex-A5 Cortex-M4 • 1.3MB non-ECC SRAM Single 3.3V supply Up to 320MHz Up to 160MHz Low Voltage Detection NEON / FPU/ MMU FPU • Supports 2 x WVGA displays: Low Power Control 32K / 32K L1 cache 16K / 16K L1 cache - OpenVG 1.1 GPU - 2 x 2D-ACE display interfaces 64 KB TCM System and General Purpose - DigitalRGB, RSDS, LVDS i/f - Hardware HUD warping engine Memory Protection DMA I/O Processor - Digital camera input Security-CSE2 Autonomous RTC Cortex – M0+ Up to 80MHz • Extensive connectivity : Peripherals - Ethernet AVB, MLB50, CAN-FD 32K ECC SRAM CAN(FD) x3 I2C x2 Internal Memory • I/O Processor (Cortex M0+) UART/LIN x3 Watchdog Timers - Supports autonomous operation 4MB ECC Flash SPI x5 IC/OC Timers / PWM Stepper Motor Drivers - Peripheral control and Low power MLB 3-wire SMD / SSD x6 1.3MB Non ECC SRAM operation 12-bit SAR ADC 10/100 Ethernet + AVB 2 x 512KB ECC SRAM • Security (CSE2) Audio / GFx / Video / Display - Meets SHE specification External Memory - Meets GM’s Global B Cybersecurity SGM (includes I2S) 2D-ACE + inline HUD requirements DDR QuadSPI Flash x2 Warping Digital Video In • Functional Safety 16/32-bit DDR2 2D - ACE - Built in support for ASIL-B GC355 OpenVG GPU Open LDI & RSDS 16-bit SDR • Software Support - AutoSAR - GC355 - I/OP Stepper motor driver • BGA and QFP package options: - 176/208LQFP + 516MAPBGA TM -40 to +105C TA External Use 11 MPC56xxS vs MACHxx vs Vybrid Feature MPC56xxS MACHxx Vybrid Spectrum - 1 x WQVGA MACCxx– 1 x WVGA Target Use-Case Up to 2 x WVGA Rainbow – 2 x WQVGA MACHxx- 2 x WVGA Spectrum - e200z0h Corona - ARM CM4 Core(s) ARM CM4/CA5 Rainbow - e200z4d Halo - ARM CM4/CA5 Security Censorship only CSE2 (encrypted protection) CAAM Safety Limited features ASIL-B Limited Features Flash Spectrum-1M, Rainbow-2M Corona-1-2M, Halo-2-4M None – supports XIP QuadSPI Flash Corona-256kB Up to 1.5MB on-chip SRAM in total Graphics SRAM Spectum-160kB, Rainbow-1MB Halo-1.3MB (+1MB ECC RAM) (1MB no ECC, 512k ECC) Stepper Motors SMD/Stall Detect ‘Intelligent’ SMD/SSD None Head-Up Display None Hardware warping engine on Halo GC355 can support warping Spectrum - None Corona/Halo - 2D-GPU GPU GC355 OpenVG Rainbow - Z160-OpenVG Halo - GC355 OpenVG High Speed Serial None MLB50, ENET-AVB, CAN-FD MLB50, ENETx2, USB-HS x2 GRAM Spectrum – None Corona – SDR LPDDR2 / DDR3 Expandability Rainbow – SDR/DDR2 Halo – (SDR)/DDR2 EVB, Basic Compiler tools, “Lab EVBs, Complete High-Performance EVBs, Complete High-Performance Enablement Bench” Demos Demos, Optimized Graphics Tools Demos, Optimized Graphics Tools TM External Use 12 r0: 23-Sep-13 MPC5645S working scenario LEDs 3x CAN eMIOS 6 Stepper Motor Drivers PWMs with patented stall detection 4x LIN Video Vreg MPC5645S Input Unit 64K SRAM 4x16k 1MB RTC EEPROM Graphics 125MHz RAM sound Power 2MB eMIOS Display TFT DISPLAY PWMs E200z4d core FLASH Control DCU on MPC5645S can drive up to QuadSPI Unit 800x480 24-bit LCD DRAM Serial Flash DCU Lite OpenVG • Optional 2nd Display (DCU-lite) interface Controller GPU OpenVG1.1 GPU (Z160) natively renders Low-cost • Lines, curves, polygons, textures,etc.
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