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HCS12 Reference Manual

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HCS12 Reference Manual S12CPUV2 Reference Manual HCS12 Microcontrollers S12CPUV2 Rev. 4.0 03/2006 freescale.com S12CPUV2 Reference Manual To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com The following revision history table summarizes changes contained in this document. Revision History Revision Date Summary of Changes Number 3.0 April, 2002 Incorporated information covering HCS12 Family of 16-bit MCUs throughout the book. 4.0 March, 2006 Reformatted to Freescale publication standards. Corrected mistake in ANDCC/TAP descriptions (Instruction Glossary). Corrected mistake in MEM description (Instruction Glossary). Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2005. All rights reserved. S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor 3 S12CPUV2 Reference Manual, Rev. 4.0 4 Freescale Semiconductor Reference Manual — S12CPUV2 List of Sections Table of Contents . .7 Section 1. Introduction . .15 Section 2. Overview . .21 Section 3. Addressing Modes . .29 Section 4. Instruction Queue . .47 Section 5. Instruction Set Overview . .55 Section 6. Instruction Glossary . .87 Section 7. Exception Processing. .311 Section 8. Instruction Queue . .323 Section 9. Fuzzy Logic Support. .337 Appendix A. Instruction Reference . .375 Appendix B. M68HC11 to CPU12 Upgrade Path. .403 Appendix C. High-Level Language Support . .425 Index . .433 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor 5 S12CPUV2 Reference Manual, Rev. 4.0 6 Freescale Semiconductor Reference Manual — S12CPUV2 Table of Contents Section 1. Introduction 1.1 Introduction . .15 1.2 Features . .15 1.3 Symbols and Notation. .16 1.3.1 Abbreviations for System Resources . .16 1.3.2 Memory and Addressing. .17 1.3.3 Operators . .18 1.3.4 Definitions. .19 Section 2. Overview 2.1 Introduction . .21 2.2 Programming Model . .21 2.2.1 Accumulators . .22 2.2.2 Index Registers. .22 2.2.3 Stack Pointer . .22 2.2.4 Program Counter . .23 2.2.5 Condition Code Register . .23 2.2.5.1 S Control Bit . .24 2.2.5.2 X Mask Bit . .25 2.2.5.3 H Status Bit . .25 2.2.5.4 I Mask Bit . .25 2.2.5.5 N Status Bit . .26 2.2.5.6 Z Status Bit. .26 2.2.5.7 V Status Bit. .26 2.2.5.8 C Status Bit . .26 2.3 Data Types . .27 2.4 Memory Organization . .27 2.5 Instruction Queue . .28 S12CPUV2 Reference Manual, Rev. 4.0 Freescale Semiconductor 7 Section 3. Addressing Modes 3.1 Introduction . .29 3.2 Mode Summary. .29 3.3 Effective Address . .29 3.4 Inherent Addressing Mode . .31 3.5 Immediate Addressing Mode . .31 3.6 Direct Addressing Mode . .32 3.7 Extended Addressing Mode . .33 3.8 Relative Addressing Mode . .33 3.9 Indexed Addressing Modes . .34 3.9.1 5-Bit Constant Offset Indexed Addressing . .37 3.9.2 9-Bit Constant Offset Indexed Addressing . .37 3.9.3 16-Bit Constant Offset Indexed Addressing . .38 3.9.4 16-Bit Constant Indirect Indexed Addressing . .38 3.9.5 Auto Pre/Post Decrement/Increment Indexed Addressing . .39 3.9.6 Accumulator Offset Indexed Addressing . .40 3.9.7 Accumulator D Indirect Indexed Addressing . .41 3.10 Instructions Using Multiple Modes . .41 3.10.1 Move Instructions . .41 3.10.2 Bit Manipulation Instructions. .43 3.11 Addressing More than 64 Kbytes . .44 Section 4. Instruction Queue 4.1 Introduction . .47 4.2 Queue Description . .47 4.2.1 Original M68HC12 Queue Implementation. .48 4.2.2 HCS12 Queue Implementation. .48 4.3 Data Movement in the Queue. .48 4.3.1 No Movement . .49 4.3.2 Latch Data from Bus (Applies Only to the M68HC12 Queue) . .49 4.3.3 Advance and Load from Data Bus . .49 4.3.4 Advance and Load from Buffer (Applies Only to M68HC12 Queue) . .49 4.4 Changes in Execution Flow . .49 4.4.1 Exceptions . .50 4.4.2 Subroutines . .50 4.4.3 Branches . .51 S12CPUV2 Reference Manual, Rev. 4.0 8 Freescale Semiconductor 4.4.3.1 Short Branches. .52 4.4.3.2 Long Branches . .52 4.4.3.3 Bit Condition Branches. .53 4.4.3.4 Loop Primitives. .53 4.4.4 Jumps . .53 Section 5. Instruction Set Overview 5.1 Introduction . .55 5.2 Instruction Set Description . .55 5.3 Load and Store Instructions . .56 5.4 Transfer and Exchange Instructions . .57 5.5 Move Instructions . .58 5.6 Addition and Subtraction Instructions . .59 5.7 Binary-Coded Decimal Instructions. .60 5.8 Decrement and Increment Instructions. .61 5.9 Compare and Test Instructions. .62 5.10 Boolean Logic Instructions . ..
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