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HCS12 V1.5 Core User Guide Version not are currently here Freescale Semiconductor, I..nc. Family indicated Product negligent regardingthedesign ormanufactureofthepart. personal injury or deathagainst associated all claims, with costs, such damages,application, and unintended Buyer expenses, shall or and indemnify reasonable and unauthorized hold attorney use,personal Motorola fees and injury arising even its or out officers, if of, death employees, subsidiaries, such directly maysupport affiliates, or occur. claim and or indirectly, distributors Should alleges any sustain harmless Buyer claim that life, purchase of or Motorola or or authorized use was for for Motorola any products use otherneither for as does application any components it in such convey in unintended which any systemsdesign. or license the intended unauthorized Motorola under failure for does its of patent surgical not the rightsMotorola implant assume nor Motorola reserves into any the product the liability the rights could of body, arising right create others. or out to Motorola a other of products make situation the applications are where changes not application intended designed, without or to intended, use further of notice any to product any or products circuit described herein herein; to improve reliability, function or numbers part DragonBall and Family, lines Product product i.MX Freescale Semiconductor,Inc. Original ReleaseDate:12May2000 For More Information OnThis Product, HCS12 V1.5 Core 2010: BGA-packaged Revised: 17August2000 Go to:www.freescale.com Version 1.2 User Guide September to Motorola, Inc Commission, prior Trade States United the International in sale States or United import the for DOCUMENT NUMBER from order Freescale S12CPU15UG/D an from of Because available 1 not are currently here Freescale Semiconductor, I..nc. Family indicated Revision History Revision Product 2 1.2—Version 2000 17August Revision History Release Number Date numbers part DragonBall 1.0 1.1 1.2 1.2 and Family, lines 13 October2000 17 August 2000 17 August Product product 12 May 2000 12 May 21 July 2000 21 July i.MX Freescale Semiconductor,Inc. For More Information OnThis Product, 2010: BGA-packaged Go to:www.freescale.com Author September to Commission, prior Trade States outputs andperi_clk2, peri_clk4, inputs. andram_fmts core_per_t2 Security addcore_exp_t2, enhancements, Correct access detail for LSLinstruction inappendixB Correct accessdetailfor Original onlywithinMotorola Distributed draft. Update allocatedRAMspacetable. United the International in Summary ofChanges sale States or United import the for from HCS12 V1.5Core order Freescale an MOTOROLA from of Because available not are currently here Freescale Semiconductor, I..nc. Family indicated Product 3.23.1.5 Core RegisterMap . .58 3.1.4 ConditionCode Register(CCR). .56 3.1.3 ProgramCounter (PC) ..56 3.1.2 StackPointer (SP) . .55 3.1.1 IndexRegisters (XandY) . ..54 3.1 Accumulators . .53 ProgrammingModel ..53Section 3CoreRegisters 2.42.3 Terminology . .51 2.2 Symbology . .51 2.1 UnitsandMeasures . ..51 References . .51Section 2Nomenclature 1.8.71.8.6 ConditionCodeStateNotation. ..49 1.8.5 AccessDetailNotation ..47 1.8.4 MachineCodeNotation ..46 1.8.3 AddressModeNotation ..45 1.8.2 OperationNotation . ..45 1.8.1 SourceFormNotation . ..43 1.8 RegisterandMemoryNotation . .43 1.7 InstructionSetOverview. ..29 1.6.2 Addressingmodes . .28 1.6.1 MemoryOrganization. ..28 1.6 DataTypes. 1.5 DataFormatSummary ..27 1.4 ProgrammingModel . ..26 1.3 ArchitecturalSummary ..26 1.2 BlockDiagram . 1.1 Features . .23 CoreOverview . Section 1Introduction Table ofContents numbers part DragonBall and Family, lines Product product i.MX Freescale Semiconductor,Inc. For More Information OnThis Product, 2010: BGA-packaged Go to:www.freescale.com September to Commission, prior Trade States United the International in Core UserGuide—S12CPU15UGV1.2 sale States or United import the for from order Freescale an from of Because available .27 .25 .23 3 not are currently here Freescale Semiconductor, I..nc. Family indicated Product 4.3.24 STOPandWAIInstructions4.3.23 . .91 Condition Code Instructions4.3.22 . ..90 LoadEffective AddressInstructions.4.3.21 . .90 StackingInstructions4.3.20 . ..89 IndexManipulation Instructions . .884.3.19 InterruptInstructions4.3.18 ..87 Jumpand Subroutine Instructions . .864.3.17 BranchInstructions4.3.16 . .84 TableInterpolationInstructions4.3.15 ..83 MultiplyandAccumulateInstruction. ..834.3.14 MaximumandMinimumInstructions ..814.3.13 FuzzyLogicInstructions. ..814.3.12 ShiftandRotateInstructions4.3.11 ..80 BitTestandManipulationInstructions4.3.10 ..79 MultiplyandDivideInstructions . ..794.3.94.3.8 Clear,Complement,andNegateInstructions ..78 4.3.7 BooleanLogicInstructions . ..78 4.3.6 CompareandTestInstructions . ..77 4.3.5 DecrementandIncrementInstructions ..76 4.3.4 BinaryCodedDecimalInstructions ..76 4.3.3 AddandSubtractInstructions . ..75 4.3.2 MoveInstructions . ..74 4.3.1 TransferandExchangeInstructions ..74 4.3 LoadandStoreInstructions ..73 4.2.8 InstructionDescriptions . ..73 4.2.7 InstructionsUsingMultipleModes ..71 4.2.6 IndexedAddressingModes ..66 4.2.5 RelativeAddressingMode . .66 4.2.4 ExtendedAddressingMode ..65 4.2.3 DirectAddressingMode. ..65 4.2.2 ImmediateAddressingMode ..64 4.2.1 InherentAddressingMode ..64 4.2 EffectiveAddress ..64 4.1 AddressingModes . .63 InstructionTypes . Section 4Instructions Core UserGuide—S12CPU15UGV1.2 4 numbers part DragonBall and Family, lines Product product i.MX Freescale Semiconductor,Inc. For More Information OnThis Product, 2010: BGA-packaged Go to:www.freescale.com September to Commission, prior Trade States United the International in sale States or United import the for from order Freescale an from of Because available .63 not are currently here Freescale Semiconductor, I..nc. Family indicated Product 5.5.15.5 InstructionQueueStatus Signals. .126 5.4.7 ExternalVisibilityOfInstruction Queue ..126 5.4.6 ConditionCode StateNotation. .126 5.4.5 AccessDetail Notation . ..123 5.4.4 MachineCode Notation . .123 5.4.3 AddressMode Notation . .122 5.4.2 OperationNotation . ..122 5.4.1 SourceForm Notation . ..121 5.4 RegisterandMemoryNotation . .120 5.3.4 InstructionTiming ..106 5.3.3 Jumps. .106 5.3.2 Branches . ..104 5.3.1 Subroutines . ..104 5.3 Exceptions ..104 5.2.2 ChangesofFlow. .104 5.2.1 AdvanceandLoadfromDataBus ..103 5.2 NoMovement. ..103 5.1 ExecutionSequence. ..103 NormalInstructionExecution . ..103 Section 5InstructionExecution 4.84.7 IndexedAddressingPostbyte(xb)Encoding . ..101 4.6 LoopPrimitivePostbyte(lb)Encoding ..100 4.5 TransferandExchangePostbyteEncoding . ..99 4.4.9 OpcodeMap. 4.4.8 InstructionSetOrthogonality ..95 4.4.7 FunctionCalls ..95 4.4.6 Pointers . ..95 4.4.5 CaseandSwitchStatements ..95 4.4.4 ConditionalIfConstructs ..94 4.4.3 HigherMathFunctions ..94 4.4.2 IncrementandDecrementOperators. ..94 4.4.1 ParametersandVariables ..92 4.4 DataTypes. 4.3.25 High-LevelLanguageSupport . .92 BackgroundModeandNullOperationInstructions ..91 numbers part DragonBall and Family, lines Product product i.MX Freescale Semiconductor,Inc. For More Information OnThis Product, 2010: BGA-packaged Go to:www.freescale.com September to Commission, prior Trade States United the International in Core UserGuide—S12CPU15UGV1.2 sale States or United import the for from order Freescale an from of Because available .97 .92 5 not are currently here Freescale Semiconductor, I..nc. Family indicated Product 8.1 ClockingOverview ..163 Section 8CoreClockandResetConnections 7.3.57.3.4 DetectingAccess TypefromExternalSignals ..162 7.3.3 GeneralInternal ReadVisibilityTiming . ..161 7.3.2 Multiplexed ExternalBusInterface. .158 7.3.1 WriteOperations ..155 7.3 ReadOperations . ..152 7.2.8 InterfaceOperation. ..152 7.2.7 ScanControlInterfaceSignals. ..152 7.2.6 MemoryConfigurationSignals . ..152 7.2.5 BackgroundDebugMode(BDM)InterfaceSignals ..151 7.2.4 StopandWaitModeControl/StatusSignals . ..151 7.2.3 VectorRequest/AcknowledgeSignals ..151 7.2.2 ClockandResetSignals ..150 7.2.1 ExternalBusInterfaceSignals . ..148 7.2 InternalBusInterfaceSignals ..145 7.1.1 SignalDescriptions. ..145 7.1 SignalSummary. ..142 CoreInterfaceOverview. ..141 Section 7CoreInterface 6.3.26.3.1 Interrupts . .137 6.3 Resets . .136 6.2 ExceptionTypes. ..136 6.1.2 ExceptionVectors. ..135 6.1.1 InterruptProcessing ..133 6.1 ResetProcessing ..133 ExceptionProcessingOverview. ..131 Section 6ExceptionProcessing 5.5.65.5.5 SOD—StartOddInstruction(1:1) ..129 5.5.4 SEV—StartEvenInstruction(1:0) ..128 5.5.3 INT—StartInterrupt(0:1) ..128 5.5.2 ALD—AdvanceandLoadfromDataBus(1:0) . ..128 NoMovement(0:0) ..128 Core UserGuide—S12CPU15UGV1.2 6 numbers part DragonBall and Family, lines Product product i.MX Freescale Semiconductor,Inc. For More Information OnThis Product, 2010: BGA-packaged Go to:www.freescale.com September to Commission, prior Trade States United the International in sale States or United import the for from order Freescale an from of Because available not are currently here Freescale Semiconductor, I..nc. Family indicated Product Section 11Module MappingControl(MMC) 10.7 MotorolaInternalInformation . .177 10.6.3 StopMode10.6.2 . .177 WaitMode10.6.1 . ..177 RunMode. .17710.6 Low-PowerOptions ..177 10.5.3 Emulation Modes10.5.2 . .177 SpecialOperation. .17710.5.1 NormalOperation.10.5 ..177 ModesofOperation ..177 10.4.3 ExceptionPriority10.4.2 . ..176 ResetExceptionRequests.10.4.1 ..176 InterruptExceptionRequests.10.4 ..175 Operation . ..175 10.3.3 HighestPriorityIInterrupt(Optional) ..17510.3.2 InterruptTestRegisters ..17410.3.1 InterruptTestControlRegister.10.3
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