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Powerpc User Instruction Set Architecture Book I Version 2.01

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Powerpc User Instruction Set Architecture Book I Version 2.01 PowerPC User Instruction Set Architecture Book I Version 2.01 September 2003 Manager: Joe Wetzel/Poughkeepsie/IBM Technical Content: Ed Silha/Austin/IBM Cathy May/Watson/IBM Brad Frey/Austin/IBM The following paragraph does not apply to the United Kingdom or any country or state where such provisions are inconsistent with local law. The specifications in this manual are subject to change without notice. This manual is provided “AS IS”. Interna- tional Business Machines Corp. makes no warranty of any kind, either expressed or implied, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. International Business Machines Corp. does not warrant that the contents of this publication or the accompanying source code examples, whether individually or as one or more groups, will meet your requirements or that the publication or the accompanying source code examples are error-free. This publication could include technical inaccuracies or typographical errors. Changes are periodically made to the information herein; these changes will be incorporated in new editions of the publication. Address comments to IBM Corporation, Internal Zip 9630, 11400 Burnett Road, Austin, Texas 78758-3493. IBM may use or distribute whatever information you supply in any way it believes appropriate without incurring any obligation to you. The following terms are trademarks of the International Business Machines Corporation in the United States and/or other countries: IBM PowerPC RISC/System 6000 POWER POWER2 POWER4 POWER4+ IBM System/370 Notice to U.S. Government Users—Documentation Related to Restricted Rights—Use, duplication or disclosure is subject to restrictions set fourth in GSA ADP Schedule Contract with IBM Corporation. Copyright International Business Machines Corporation, 1994, 2003. All rights reserved. ii PowerPC User Instruction Set Architecture Version 2.01 Preface This document defines the PowerPC User Instruction Operating Environment Architecture defines the Set Architecture. It covers the base instruction set system (privileged) instructions and related facilities. and related facilities available to the application pro- Book IV, PowerPC Implementation Features defines grammer. the implementation-dependent aspects of a particular implementation. Other related documents define the PowerPC Virtual Environment Architecture, the PowerPC Operating As used in this document, the term “PowerPC Archi- Environment Architecture, and PowerPC Implementa- tecture” refers to the instructions and facilities tion Features. Book II, PowerPC Virtual Environment described in Books I, II, and III. The description of the Architecture defines the storage model and related instantiation of the PowerPC Architecture in a given instructions and facilities available to the application implementation includes also the material in Book IV programmer, and the time-keeping facilities available for that implementation. to the application programmer. Book III, PowerPC Preface iii Version 2.01 iv PowerPC User Instruction Set Architecture Version 2.01 Table of Contents Chapter 1. Introduction ......... 1 2.1 Branch Processor Overview .... 17 1.1 Overview ................ 1 2.2 Instruction Execution Order .... 17 1.2 Computation Modes ......... 1 2.3 Branch Processor Registers .... 18 1.3 Instruction Mnemonics and 2.3.1 Condition Register ......... 18 Operands ................. 1 2.3.2 Link Register ............ 19 1.4 Compatibility with the POWER 2.3.3 Count Register ........... 19 Architecture ................ 2 2.4 Branch Processor Instructions ... 20 1.5 Document Conventions ....... 2 2.4.1 Branch Instructions ........ 20 1.5.1 Definitions and Notation ..... 2 2.4.2 System Call Instruction ...... 25 1.5.2 Reserved Fields .......... 3 2.4.3 Condition Register Logical 1.5.3 Description of Instruction Operation 4 Instructions ................ 26 1.6 Processor Overview ......... 6 2.4.4 Condition Register Field 1.7 Instruction Formats ......... 7 Instruction ................. 28 1.7.1 I-Form ................ 8 1.7.2 B-Form ................ 8 Chapter 3. Fixed-Point Processor .. 29 1.7.3 SC-Form ............... 8 3.1 Fixed-Point Processor Overview .. 29 1.7.4 D-Form ................ 8 3.2 Fixed-Point Processor Registers .. 29 1.7.5 DS-Form ............... 8 3.2.1 General Purpose Registers .... 29 1.7.6 X-Form ................ 9 3.2.2 Fixed-Point Exception Register . 30 1.7.7 XL-Form ............... 9 3.3 Fixed-Point Processor Instructions 31 1.7.8 XFX-Form .............. 9 3.3.1 Fixed-Point Storage Access 1.7.9 XFL-Form .............. 9 Instructions ................ 31 1.7.10 XS-Form .............. 9 3.3.2 Fixed-Point Load Instructions .. 31 1.7.11 XO-Form .............. 9 3.3.3 Fixed-Point Store Instructions .. 38 1.7.12 A-Form ............... 10 3.3.4 Fixed-Point Load and Store with 1.7.13 M-Form ............... 10 Byte Reversal Instructions ....... 42 1.7.14 MD-Form .............. 10 3.3.5 Fixed-Point Load and Store 1.7.15 MDS-Form ............. 10 Multiple Instructions ........... 44 1.7.16 Instruction Fields ......... 10 3.3.6 Fixed-Point Move Assist 1.8 Classes of Instructions ....... 12 Instructions ................ 45 1.8.1 Defined Instruction Class ..... 12 3.3.7 Other Fixed-Point Instructions .. 48 1.8.2 Illegal Instruction Class ...... 12 3.3.8 Fixed-Point Arithmetic Instructions 49 1.8.3 Reserved Instruction Class .... 12 3.3.9 Fixed-Point Compare Instructions 58 1.9 Forms of Defined Instructions ... 13 3.3.10 Fixed-Point Trap Instructions .. 60 1.9.1 Preferred Instruction Forms ... 13 3.3.11 Fixed-Point Logical Instructions 62 1.9.2 Invalid Instruction Forms ..... 13 3.3.12 Fixed-Point Rotate and Shift 1.10 Optionality .............. 13 Instructions ................ 68 1.11 Exceptions .............. 13 3.3.13 Move To/From System Register 1.12 Storage Addressing ........ 14 Instructions ................ 78 1.12.1 Storage Operands ........ 14 1.12.2 Effective Address Calculation .. 14 Chapter 4. Floating-Point Processor 81 4.1 Floating-Point Processor Overview 81 Chapter 2. Branch Processor ..... 17 4.2 Floating-Point Processor Registers 82 4.2.1 Floating-Point Registers ...... 82 Table of Contents v Version 2.01 4.2.2 Floating-Point Status and Control 5.3.6 PowerPC Cache Management Register .................. 83 Instructions in Little-Endian Mode . 127 4.3 Floating-Point Data .......... 85 5.3.7 PowerPC I/O in Little-Endian 4.3.1 Data Format ............. 85 Mode ................... 128 4.3.2 Value Representation ....... 86 5.3.8 Origin of Endian ......... 128 4.3.3 Sign of Result ............ 87 4.3.4 Normalization and Chapter 6. Optional Facilities and Denormalization ............. 87 Instructions that are being Phased 4.3.5 Data Handling and Precision ... 88 Out of the Architecture ........ 131 4.3.6 Rounding .............. 89 6.1 Move To Condition Register from 4.4 Floating-Point Exceptions ...... 89 XER .................... 131 4.4.1 Invalid Operation Exception ... 91 4.4.2 Zero Divide Exception ....... 92 Appendix A. Suggested 4.4.3 Overflow Exception ........ 93 4.4.4 Underflow Exception ........ 93 Floating-Point Models ......... 133 4.4.5 Inexact Exception ......... 94 A.1 Floating-Point Round to 4.5 Floating-Point Execution Models .. 94 Single-Precision Model ........ 133 4.5.1 Execution Model for IEEE A.2 Floating-Point Convert to Integer Operations ................ 95 Model .................. 138 4.5.2 Execution Model for Multiply-Add A.3 Floating-Point Convert from Type Instructions ............. 96 Integer Model .............. 141 4.6 Floating-Point Processor Instructions ................ 97 Appendix B. Assembler Extended 4.6.1 Floating-Point Storage Access Mnemonics ................. 143 Instructions ................ 97 B.1 Symbols ............... 143 4.6.2 Floating-Point Load Instructions . 97 B.2 Branch Mnemonics ........ 144 4.6.3 Floating-Point Store Instructions 100 B.2.1 BO and BI Fields ......... 144 4.6.4 Floating-Point Move Instructions 104 B.2.2 Simple Branch Mnemonics .. 144 4.6.5 Floating-Point Arithmetic B.2.3 Branch Mnemonics Instructions ............... 105 Incorporating Conditions ....... 145 4.6.6 Floating-Point Rounding and B.2.4 Branch Prediction ........ 146 Conversion Instructions ........ 109 B.3 Condition Register Logical 4.6.7 Floating-Point Compare Mnemonics ............... 147 Instructions ............... 113 B.4 Subtract Mnemonics ....... 147 4.6.8 Floating-Point Status and Control B.4.1 Subtract Immediate ....... 147 Register Instructions ......... 114 B.4.2 Subtract .............. 148 B.5 Compare Mnemonics ....... 148 Chapter 5. Optional Facilities and B.5.1 Doubleword Comparisons ... 149 Instructions ................. 117 B.5.2 Word Comparisons ....... 149 5.1 Fixed-Point Processor Instructions 118 B.6 Trap Mnemonics .......... 150 5.1.1 Move To/From System Register B.7 Rotate and Shift Mnemonics ... 151 Instructions ............... 118 B.7.1 Operations on Doublewords .. 151 5.2 Floating-Point Processor B.7.2 Operations on Words ...... 152 Instructions ............... 119 B.8 Move To/From Special Purpose 5.2.1 Floating-Point Arithmetic Register Mnemonics ......... 153 Instructions ............... 120 B.9 Miscellaneous Mnemonics .... 153 5.2.2 Floating-Point Select Instruction 121 5.3 Little-Endian ............. 122 Appendix C. Programming 5.3.1 Byte Ordering ........... 122 Examples .................. 155 5.3.2 Structure Mapping Examples . 122 C.1 Multiple-Precision Shifts ..... 155 5.3.3 PowerPC Byte Ordering ..... 123 C.2 Floating-Point Conversions .... 158
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