Programmable Logic Device (PLD) Preface

• Introduction. • Types of PLD. • Applications. • Advantages and Disadvantages. Introduction.

• Why PLD? Idea Behind: Use Memory as Programmable logic

• PLD is an IC that contains large no of gates, flip-, etc. that can be configured by the user to perform different functions. • The internal logic gates and/or connections of PLDs can be changed/configured by a programming process. Cont. • One of the simplest programming technologies is to use fuses. In the original state of the device, all the fuses are intact. • Programming the device involves blowing those fuses along the paths that must be removed in order to obtain the particular configuration of the desired logic function. • In order to show the internal logic diagram in a concise form, it is necessary to employ a special gate symbology applicable to array logic. Types of PLD. • Fundamental Types PLDs. (Combinational PLDs) . The PROM (Programmable Read Only Memory) has a fixed AND array (constructed as a decoder) and programmable connections for the output OR gates array. The PROM implements Boolean functions in sum-of-minterms form. . The PAL () device has a programmable AND array and fixed connections for the OR array. . The PLA () has programmable connections for both AND and OR arrays. So it is the most flexible type of PLD. • Advanced Types PLDs.(Sequential PLDs) . A CPLD (Complex Programmable Logic Devices)contains a bunch of PLD blocks whose inputs and outputs are connected together by a global interconnection matrix. Thus a CPLD has two levels of programmability: each PLD block can be programmed, and then the interconnections between the PLDs can be programmed. . FPGAs (Field Programmable Gate Arrays )consists of a 2-dimensional array of configurable logic blocks (CLBs). Each CLB can be configured (programmed) to implement any Boolean function of its input variables. Functions of larger number of variables are implemented using more than one CLB. PROM (Programmable Read Only Memory) • Fixed AND array constructed as a decoder (hard-wired ) and programmable OR array. • 2n minterms for n-input AND gates & these minterms are shared by the outputs. Cont.

Drawback: • Requires large area because of 2n AND Gates PLA (Programmable Logic Array) • In PLAs, instead of using a decoder as in PROMs, a number (k) of AND gates is used where k < 2n, (n is the number of inputs). • Each of the AND gates can be programmed to generate a product term of the input variables and does not generate all the minterms as in the ROM. Cont. • The AND and OR gates inside the PLA are initially fabricated with the links (fuses) among them. • The specific Boolean functions are implemented in sum of products form by opening appropriate links and leaving the desired connections. • A block diagram of the PLA is shown in the figure. It consists of n inputs, m outputs, and k product terms. The product terms constitute a group of k AND gates each of 2n inputs Cont.

Drawback: Through very flexible but more complicated programming. Cont. Example: Implement the combinational circuit having the shown truth table, using PLA. Cont. PAL (Programmable Array Logic) • The PAL device is a PLD with a fixed OR array and a programmable AND array. • As only AND gates are programmable, the PAL device is easier to program but it is not as flexible as the PLA. Cont. Cont. • Example: Implement the following Boolean functions using the PAL device as shown above: W(A, B, C, D) = ∑m(2, 12, 13) X(A, B, C, D) = ∑m(7, 8, 9, 10, 11, 12, 13, 14, 15) Y(A, B, C, D) = ∑m(0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15) Z(A, B, C, D) = ∑m(1, 2, 8, 12, 13) Cont. FPGA (Field Programmable Grid Array) • FPGA is a VLSI circuit that can be programmed in the user’s location. • A typical FPGA consists of look-up tables, , gates, and flip-flops. • Look-up table is a truth table stored in a SRAM and provides the combinational circuit functions for the logic block. • The advantage of using RAM instead of ROM to store the truth table is that the table can be programmed by writing into memory. • The disadvantage is that the memory is volatile and presents the need for the look-up table content to be reloaded in the event that power is disrupted. • Basically, the FPGA (field-programmable ) differs in architecture, does not use PAL/PLA type arrays, and has much greater densities than CPLDs. • A typical FPGA has many times more equivalent gates than a typical CPLD. The logic-producing elements in FPGAs are generally much smaller than in CPLDs, and there are many more of them. • Also, the programmable interconnections are generally organized in a row and column arrangement in FPGAs. • Cont. • The configurable logic blocks (CLBs) in an FPGA are not as complex as the LABs or function blocks (FBs) in a CPLD, but generally there are many more of them. • The distributed matrix of programmable interconnections provide for interconnection of the CLBs and connection to inputs and outputs. • FPGAs are reprogrammable and use SRAM or anti-fuse process technology for the programmable links.

• Based on the complexities of CLBs there are two types of FPGAs: 1. Fine Grained FPGA (i.e. Simple CLBs [Configurable Logic Blocks]). 2. Coarse Grained FPGA (i.e. Larger and Complex CLBs [Configurable Logic Blocks]).

• The FPGA consists of 3 main structures: 1. Programmable logic structure (i.e. CLBs [Configurable Logic Blocks]). 2. Programmable routing structure (i.e. Horizontal and Vertical routing channels, Connection boxes and Switch boxes). 3. Programmable Input/output (I/O).

Programmable logic structure • The programmable logic structure FPGA consists of a 2-dimensional array of configurable logic blocks (CLBs). • Figure here shows the fundamental configurable logic blocks (CLBs) within the global row/column programmable interconnects that are used to connect logic blocks. • Each CLB (also known as logic array block, LAB) is made up of multiple smaller logic modules and a local programmable interconnect that is used to connect logic modules within the CLB. • Large designs are partitioned and mapped to a number of CLBs with each CLB configured (programmed) to perform a particular function. • These CLBs are then connected together to fully implement the target design. Connecting the CLBs is done using the FPGA programmable routing structure. Cont. • A logic module in an FPGA logic block can be configured for combinational logic, registered logic, or a combination of both. • A flip-flop is part of the associated logic and is used for registered logic. • As you know, an LUT (look-up table) is a type of memory that is programmable and used to generate SOP combinational logic functions. • The LUT essentially does the same job as the PAL or PLA does. Cont. • Generally, the organization of an LUT consists of a number of memory cells equal to 2n , where n is the no. of input variables. • For example, three inputs can select up to eight memory cells, so an LUT with three input variables can produce an SOP expression with up to eight product terms. • A pattern of 1s and 0s can be programmed into the LUT memory cells. • Each 1 means the associated product term appears in the SOP output, and each 0 means that the associated product term does not appear in the SOP output. • The resulting SOP output expression is

Ā2Ā1Ā0 + Ā2A1A0 + A2Ā1A0 + + A2A1A0 Cont.

• Typically, a logic module (LM) can be programmed for the following modes of operation: ▪ Normal mode ▪ Extended LUT mode ▪ Arithmetic mode ▪ Shared arithmetic mode • In addition to these four modes, a logic module can be utilized as a register chain to create counters and shift registers. • The normal mode is used primarily for generating combinational logic functions. • The extended LUT mode allows expansion to input variable function. SRAM-Based FPGAs

• FPGAs are either nonvolatile because they are based on anti-fuse technology or they are volatile because they are based on SRAM technology. • Therefore, SRAM-based FPGAs include either a nonvolatile configuration memory embedded on the chip to store the program data and reconfigure the device each time power is turned back on or they use an external memory with data transfer controlled by a host .