I C D nertdCir Integrated Content W PLAs Storage T Pass Standar using Design System Paths Euler and Design Cell Abstraction and Rules Design Layout T of Overview Intr drV ider oduction asso Cir ransistor iew utDesign cuit echnologies nertdCrutDesign Circuit Integrated cuits osi Maharatna Koushik anMcNally Iain Cells d lectur lectur es es anMcNally Iain nertdCir Integrated History Gor ipelgcfntosfr functions logic Simple akKly T Kilby Jack oetNye Fair Noyce Robert onBar John Geof oe Resour Notes Books Assessment Moor is Commer First is nertdCir Integrated First is lnrItgae Cir Integrated Planar First is T First nertdCir Integrated http users ecs soton ac uk bim notes icd ACir Design VLSI CMOS of Principles Circuits Integrated Digital o Moor don fr yDme RylRdrEtbihet Establishment Radar Royal Dummer ey ut n ytm Perspective Systems and cuits Law e s en W deen ransistor Examination Coursework Informal xsInstr exas Fair e Addison W W Neil Pr Rabaey Jan utDesign cuit le rtan n W and Brattain alter entice Hall ilICs cial ut Pr cuits hl child hl osre h tr the observes child mns uments se DvdHarris David este ces mT n Fair and TI om cuit Co inventor se esley oposed Co inventor cuit LEi aeLayout Gate L Edit limSoke Bl Labs Bell Shockley illiam child nsi integration in ends pr ttp failed ototype History History Pr 1,000,000,000 100,000,000 dcsepnnilgr exponential edicts 10,000,000 1,000,000 ne a one yGor by founded was Intel obe vr ersne n pr and since year every doubled Gor In te er befor years other pr he In ef Gr Moor In Moor thr 100,000 10,000 cetpcigo components of packing cient 1,000 whwudnwdpn nyo pr on only depend now would owth uht to ough 048080 4004 9018 902000 1990 1980 1970 ecie i nta gr initial his describes e obigEeyY Every Doubling obigEeyT Every Doubling 8008 o Moor don er dce httegr the that edicted vsdgr evised 8086 whi h ubro opnnsprchip per components of number the in owth o Moor don Moor bevdta h ubro opnnsprci had chip per components of number the that observed e lwn u opyia limits physical to due slowing e 286 whpr owth Moor whpr owth n oetNyefr Noyce Robert and e a tIntel at Law e s whwudcniu ttesm aefran for rate same the at continue would owth dcin oduln vr w years two every doubling to edictions 386 oY wo ear Law e s dcin s iiuosypr ridiculously as edictions cs impr ocess dce httetr the that edicted 486 DX ears Pentium mFair om vmnsrte hno mor on than rather ovements child Pentium II Itantium n ol continue would end Itantium 2 Pentium III Pentium 4 Dual Core Itantium 2 ecise 2010 e History Faster Slower Moor the uses industry whole The rteIntels the or oto aia qimn obidIsdulsappr years doubles ICs build ery to equipment capital of Cost Joneses the with up keep Must o costly too atdinvestment wasted Moor Law e s a uv opa e arcto facilities fabrication new plan to curve Law e s efflligPr Self ful lling a ophesy xmtl ev oximately 1947 Point Contact transistor 1961 Fairchild Bipolar RTL RS Flip-Flop (4 Transistors)
1965 Moore’s Law (Mk I) Number of transistor has doubled every year and will continue to do so until 1975
1975 Moore’s Law (Mk II) Number of transistors will double every two years Dual Core Itantium 2 1,000,000,000 Itantium 2 Itantium 100,000,000 Pentium 4 Pentium III 10,000,000 Pentium II Self-fulfilling Pentium 1,000,000 Prophecy 486 DX 286 386 100,000 8086
10,000 4004 8080 8008 1,000 1970 1980 1990 2000 2010
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ABZ
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A B Z AB Z GND! GND! GND! GND!
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Transmission Gate Multiplexor EN EN S OUT Tri-state gates are used for Multiplexing IN1 IN1 Distributed Multiplexing OUT S OUT using transmission gates IN0 IN0 IN1 IN0
S S S S *note distictive polysilicon crossover using tri-state inverters
Tri-state Inverter
using tri-state buffers
IN OUT IN OUT EN EN
Bi-directional I/O EN IN OUT Tri-state Buffer
IN OUT IN OUT
EN EN *this is another form of multiplexing
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D D 1 1 Q Q 0 0 D Q D Q
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LD LD CLK CLK CLK CLK
D D 1 1 Q Q 0 0 D Q D Q
CLOCK CLOCK
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LD LD CLK CLK CLK CLK *muliplexor based latches and flip-flops include distictive polysilicon crossover
Edge Triggered D-Type Flip-Flop
D
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CLK 26 Transistors
CLK D Q Euler path analysis is applied creatively to these multi-gate cells - gates are often linked via the common gnd/pwr node Final layouts will be more complex where clock buffers, reset circuitry and metal 2 i/o are included
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BIT BIT
WORD select
AND Plane OR Plane
ROM is PLA with fixed AND (decoder) plane programmable OR (data) plane Cells are designed to butt together in two dimensions leading to efficient layout PLA layout efficiency will depend on the actual function implemented (e.g. number of common product terms)
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Skill Required Little Lots
Time to Market Quick Slow One-off Cheap Manufacturing Cost Expensive Unit Cost Cheap In Production Expensive
Speed Fast Slow
Area Small Big
Power Low High
All design styles need full custom designers A large ASIC (especially SoC) may mix Semi-Custom and Full Custom