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Section 5 ASIC Cost Effectiveness 5 ASIC COST EFFECTIVENESS INTRODUCTION When making most decisions, there are numerous pros and cons that must be weighed in order to make an intelligent choice. This is especially true when an IC user considers the advantages and disadvantages of ASIC devices (Figure 5-1). STANDARD ICs Pros Cons •Low cost •Not optimized for each system •Off-the-shelf availability •More difficult system product differentiation •Proven reliability (fully tested) •Inefficient use of board space •Multiple sources (usually) ASICs Pros Cons •Efficiency of the ASIC for optimizing system •High unit cost of IC performance •IC user pays for IC design •Efficient use of board space •Potential for design failure •Performance (speed) enhanced (usually by •Most vendors single-source ASICs replacing numerous standard ICs with a •System house needs internal IC design and single ASIC) test expertise •Long leadtimes (not including PLDs/FPGAs) Source: ICE, "ASIC 1997" 17660 Figure 5-1. Pros and Cons of Standard ICs and ASICs In comparison to ASICs, the advantages of standard devices can be summed up in one phrase –– ease-of-use. For standard ICs the cost structures are easily identified and the IC manufacturer can supply the standard IC user with fairly specific availability and reliability information. Moreover, in most cases, if the standard IC user does not like the way a vendor is treating him, it takes little effort to patronize other companies that make identical parts and that will better serve the user’s needs. The major problem with standard ICs that helped begin the move to using ASIC devices was that stan- dard parts were not optimized for each individual system’s specifications. The most important “pro” for ASIC devices has always been the “efficiency of the ASIC for optimizing system performance.” INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-1 ASIC Cost Effectiveness The major negatives of using ASICs have almost always dealt with cost. The obvious costs are the typically higher ASIC unit costs and NREs (non-recurring engineering costs). But there are other “costs” involved with using ASICs that are not so readily apparent to the potential ASIC user. By definition, the decision to use ASICs instead of standard ICs will carry increased risks. These risks can lead to high costs incurred by the ASIC user. For example, if the ASIC design fails to work properly in the system, a new design (and possibly another NRE charge) will have to be cre- ated. Besides a cash outlay, the ASIC user will need to devote expensive in-house engineering and management resources to fix the problem. Testing can also create some significant costs to the ASIC user. In some cases NRE charges do not include test program development. Moreover, with advanced ASICs averaging 95 percent to 99 percent fault coverage, problem-susceptible ASICs that make it into systems may increase field service and warranty costs. Problems occurring at the vendor’s manufacturing facility could lead to long delays for a user to receive its ASICs, and thus lead to delays in shipping the system itself. The costs to a small com- pany of not shipping its systems on-time could be catastrophic. For the most part, IC vendors and users have worked hard to minimize the total “costs” of using ASICs. The growth of the ASIC industry is one indication that for most IC users the risks and associated costs of using ASICs are well worth the effort. While it is true that each IC customer will have its own specific system requirements, some basic criteria can and should be explored by the ASIC user. This section will analyze the significant trade-offs and essential considerations necessary in choosing from among PLD, gate array, and standard cell approaches. THE DESIGN CYCLE As was previously mentioned, one of the primary distinguishing attributes of a gate array or stan- dard cell approach is the cooperation that must exist between the vendor and user. In every cell- based design there are three major steps: design (including designing for test), layout and verifi- cation, and manufacturing. As shown in Figure 5-2, the user typically handles most of the design work, while the layout and verification responsibilities are usually shared. Actual manufacturing of the device is, of course, handled entirely by the vendor (except in the case of PLDs where the user will sometimes pro- gram the devices). 5-2 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Cost Effectiveness MAJOR ACTIVITY WITHIN DIVISION OF PHASES EACH PHASE RESPONSIBILITIES Design Pre-design start Vendor/Customer Design review Cell selection Customer Schematic Customer capture Simulation Customer (functional) Layout and Simulation (timing) Vendor/Customer verification Pre-layout design Vendor/Customer review Test vector Vendor/Customer generation Auto-layout Vendor Post-layout Vendor/Customer simulation Prototype Post-layout Vendor/Customer manufacturing approval Mask generation Vendor Wafer fab Vendor Assembly/test Vendor Prototype Customer approval Source: Intel/ICE, "ASIC 1997" 14033 Figure 5-2. Typical Design Cycle It should be noted that the above description assumes that the user has at least a medium level of ASIC sophistication. Typically a user with little design experience will require more “hand hold- ing” by the vendor or may choose to use a third-party design house (a list of third-party design houses is given in the Appendix). Figure 5-3 shows a typical ASIC schedule when using a third- party design house and foundry. Both of these approaches are effective but result in a more costly ASIC device. It behooves a large system house (or heavy user of ASICs) to perform internally as much of the design work as possible. Not only are systems companies performing more of the design work of ASICs in-house, they are also becoming much more productive. Figures 5-4 and 5-5 show Silicon Graphics’ increasing pro- ductivity from using advanced CAD tools and the increasing ASIC design productivity as mea- sured in gates designed over a period (day or month) of time. As will be discussed further in Section 6, much of this increase is due to better CAD tools. However, it should be noted that some of the productivity gain is attributed to the increasing experience of ASIC designers within the system company. INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-3 ASIC Cost Effectiveness Week 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Technology Assessment Process, Device, Design Rules Simulation Develop Porting Methods Define Porting Algorithms Negotiate Rule Deviations Write Post Processing DRC, ERC, Verification Files Verification Prototyping Identify Prototype Design Post Process, Ship E-Tape Sign Off Maskmaking/Silicon Test/Assembly/Char'N E-Test/Sort Evaluation Assembly/Final Test Design House Foundry Source: Integrated System Design/ICE, "ASIC 1997" 20100 Figure 5-3. Typical Design House/Foundry ASIC Schedule NUMBER TOTAL PRODUCTIVITY OF CHIPS GATE COUNT PROJECT A 56 - 66 3 18,000 Gates per person/day PROJECT B 75 1 30,000 Gates per person/day PROJECT C 26 1 2,000 Gates per person/day SCHEMATIC ENTRY PROJECT A 130 - 170 2 120,000 Gates per person/day PROJECT B 110 - 180 2 105,000 Gates per person/day SYNTHESIS PROJECT C 68 - 120 5 305,000 Gates per person/day Source: Silicon Graphics/ICE, "ASIC 1997" 17661 Figure 5-4. Increasing ASIC Design Productivity With Design Synthesis Although great strides have been made in ASIC software design tools, the improvements have not been able to keep pace with the increases in gate density (Figure 5-6). Figure 5-7 shows how far design productivity has lagged IC density increases since 1981. As will be discussed in Section 6, CAD tools are going to be a key issue in producing high-density sub-0.35µm ASICs. 5-4 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Cost Effectiveness 3,000 3,000 2,500 2,000 1,500 1,500 Gates/Person/Month 1,000 750 500 500 150 0 Early 1980's Mid 1980'sLate 1980's Early 1990's Mid 1990's Source: ICE, "ASIC 1997" 17667B Figure 5-5. Increasing Design Productivity 10M Memory Density MPU Density (Bits) (Transistors) 1M ASIC Density (Usable Gates) 100K 10K 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 Year Source: ICE, "ASIC 1997" 21019 Figure 5-6. IC Density Increases INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-5 ASIC Cost Effectiveness Memory Density (Bits) 250x ASICs (Usable Gates) 100x MPUs (Transistors) 75x Design Productivity* 20x *(Gates/Person/Month) Source: ICE, "ASIC 1997" 21020 Figure 5-7. 1981-1996 IC Industry Improvements Among the most critical areas for the ultimate success of an ASIC program are the simulation and verification steps. As was shown in Figure 5-2, most of the steps are a combined effort of the ASIC manufacturer and customer. As CAD tools become more sophisticated, some ASIC vendors are allowing the user to do all of the simulation and design-rule verification, when using the ASIC vendors’ software programs. NRE COST TRENDS The costs that are passed on to the user by the vendor (or third-party design house) are known as NREs or non-recurring engineering expenses. NREs usually cover everything from circuit design through prototype approval. The other major cost passed on to the user is the component charge, which is the cost of manufacturing the gate array or standard cell device. Since the early 1980’s, the ASIC vendor’s revenue split between component charges and NREs has dramatically shifted. Revenue data from LSI Logic (the leading U.S.-based ASIC house) shows how rapidly the NRE portion has shrunk (Figure 5-8). The increasing capability of the system companies’ in-house design resources as well as the increasing number of ASIC designs moving into volume production are driving this evolution.
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