Section 5 ASIC Cost Effectiveness

5 ASIC COST EFFECTIVENESS

INTRODUCTION

When making most decisions, there are numerous pros and cons that must be weighed in order to make an intelligent choice. This is especially true when an IC user considers the advantages and disadvantages of ASIC devices (Figure 5-1).

STANDARD ICs Pros Cons •Low cost •Not optimized for each system •Off-the-shelf availability •More difficult system product differentiation •Proven reliability (fully tested) •Inefficient use of board space •Multiple sources (usually) ASICs Pros Cons •Efficiency of the ASIC for optimizing system •High unit cost of IC performance •IC user pays for IC design •Efficient use of board space •Potential for design failure •Performance (speed) enhanced (usually by •Most vendors single-source ASICs replacing numerous standard ICs with a •System house needs internal IC design and single ASIC) test expertise •Long leadtimes (not including PLDs/FPGAs)

Source: ICE, "ASIC 1997" 17660

Figure 5-1. Pros and Cons of Standard ICs and ASICs

In comparison to ASICs, the advantages of standard devices can be summed up in one phrase –– ease-of-use. For standard ICs the cost structures are easily identified and the IC manufacturer can supply the standard IC user with fairly specific availability and reliability information. Moreover, in most cases, if the standard IC user does not like the way a vendor is treating him, it takes little effort to patronize other companies that make identical parts and that will better serve the user’s needs.

The major problem with standard ICs that helped begin the move to using ASIC devices was that standard parts were not optimized for each individual system’s specifications. The most important “pro” for ASIC devices has always been the “efficiency of the ASIC for optimizing system performance.”

INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-1 ASIC Cost Effectiveness

The major negatives of using ASICs have almost always dealt with cost. The obvious costs are the typically higher ASIC unit costs and NREs (non-recurring engineering costs). But there are other “costs” involved with using ASICs that are not so readily apparent to the potential ASIC user.

By definition, the decision to use ASICs instead of standard ICs will carry increased risks. These risks can lead to high costs incurred by the ASIC user. For example, if the ASIC design fails to work properly in the system, a new design (and possibly another NRE charge) will have to be created. Besides a cash outlay, the ASIC user will need to devote expensive in-house engineering and management resources to fix the problem.

Testing can also create some significant costs to the ASIC user. In some cases NRE charges do not include test program development. Moreover, with advanced ASICs averaging 95 percent to 99 percent fault coverage, problem-susceptible ASICs that make it into systems may increase field service and warranty costs.

Problems occurring at the vendor’s manufacturing facility could lead to long delays for a user to receive its ASICs, and thus lead to delays in shipping the system itself. The costs to a small company of not shipping its systems on-time could be catastrophic.

For the most part, IC vendors and users have worked hard to minimize the total “costs” of using ASICs. The growth of the ASIC industry is one indication that for most IC users the risks and associated costs of using ASICs are well worth the effort.

While it is true that each IC customer will have its own specific system requirements, some basic criteria can and should be explored by the ASIC user. This section will analyze the significant trade-offs and essential considerations necessary in choosing from among PLD, gate array, and standard cell approaches.

THE DESIGN CYCLE

As was previously mentioned, one of the primary distinguishing attributes of a gate array or standard cell approach is the cooperation that must exist between the vendor and user. In every cell- based design there are three major steps: design (including designing for test), layout and verification, and manufacturing.

As shown in Figure 5-2, the user typically handles most of the design work, while the layout and verification responsibilities are usually shared. Actual manufacturing of the device is, of course, handled entirely by the vendor (except in the case of PLDs where the user will sometimes program the devices).

5-2 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Cost Effectiveness

MAJOR ACTIVITY WITHIN DIVISION OF PHASES EACH PHASE RESPONSIBILITIES

Design Pre-design start Vendor/Customer Design review Cell selection Customer Schematic Customer capture Simulation Customer (functional) Layout and Simulation (timing) Vendor/Customer verification Pre-layout design Vendor/Customer review Test vector Vendor/Customer generation Auto-layout Vendor Post-layout Vendor/Customer simulation Prototype Post-layout Vendor/Customer manufacturing approval Mask generation Vendor Wafer fab Vendor Assembly/test Vendor Prototype Customer approval

Source: Intel/ICE, "ASIC 1997" 14033

Figure 5-2. Typical Design Cycle

It should be noted that the above description assumes that the user has at least a medium level of ASIC sophistication. Typically a user with little design experience will require more “hand hold- ing” by the vendor or may choose to use a third-party design house (a list of third-party design houses is given in the Appendix). Figure 5-3 shows a typical ASIC schedule when using a third- party design house and foundry.

Both of these approaches are effective but result in a more costly ASIC device. It behooves a large system house (or heavy user of ASICs) to perform internally as much of the design work as possible.

Not only are systems companies performing more of the design work of ASICs in-house, they are also becoming much more productive. Figures 5-4 and 5-5 show Silicon Graphics’ increasing productivity from using advanced CAD tools and the increasing ASIC design productivity as mea- sured in gates designed over a period (day or month) of time. As will be discussed further in Section 6, much of this increase is due to better CAD tools. However, it should be noted that some of the productivity gain is attributed to the increasing experience of ASIC designers within the system company.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-3 ASIC Cost Effectiveness

Week 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Technology Assessment Process, Device, Design Rules Simulation Develop Porting Methods Define Porting Algorithms Negotiate Rule Deviations Write Post Processing DRC, ERC, Verification Files Verification Prototyping Identify Prototype Design Post Process, Ship E-Tape Sign Off Maskmaking/Silicon Test/Assembly/Char'N E-Test/Sort Evaluation Assembly/Final Test

Design House Foundry Source: Integrated System Design/ICE, "ASIC 1997" 20100

Figure 5-3. Typical Design House/Foundry ASIC Schedule

NUMBER TOTAL PRODUCTIVITY OF CHIPS GATE COUNT

PROJECT A 56 - 66 3 18,000 Gates per person/day PROJECT B 75 1 30,000 Gates per person/day PROJECT C 26 1 2,000 Gates per person/day SCHEMATIC ENTRY PROJECT A 130 - 170 2 120,000 Gates per person/day PROJECT B 110 - 180 2 105,000 Gates per person/day SYNTHESIS PROJECT C 68 - 120 5 305,000 Gates per person/day

Source: Silicon Graphics/ICE, "ASIC 1997" 17661

Figure 5-4. Increasing ASIC Design Productivity With Design Synthesis

Although great strides have been made in ASIC software design tools, the improvements have not been able to keep pace with the increases in gate density (Figure 5-6). Figure 5-7 shows how far design productivity has lagged IC density increases since 1981. As will be discussed in Section 6, CAD tools are going to be a key issue in producing high-density sub-0.35µm ASICs.

5-4 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Cost Effectiveness

3,000 3,000

2,500

2,000

1,500 1,500

Gates/Person/Month 1,000 750

500 500

150

0 Early 1980's Mid 1980'sLate 1980's Early 1990's Mid 1990's

Source: ICE, "ASIC 1997" 17667B

Figure 5-5. Increasing Design Productivity

10M

Memory Density MPU Density (Bits) (Transistors) 1M

ASIC Density (Usable Gates) 100K

10K 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 Year

Source: ICE, "ASIC 1997" 21019

Figure 5-6. IC Density Increases

INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-5 ASIC Cost Effectiveness

Memory Density (Bits) 250x ASICs (Usable Gates) 100x MPUs (Transistors) 75x Design Productivity* 20x

*(Gates/Person/Month)

Source: ICE, "ASIC 1997" 21020

Figure 5-7. 1981-1996 IC Industry Improvements

Among the most critical areas for the ultimate success of an ASIC program are the simulation and verification steps. As was shown in Figure 5-2, most of the steps are a combined effort of the ASIC manufacturer and customer. As CAD tools become more sophisticated, some ASIC vendors are allowing the user to do all of the simulation and design-rule verification, when using the ASIC vendors’ software programs.

NRE COST TRENDS

The costs that are passed on to the user by the vendor (or third-party design house) are known as NREs or non-recurring engineering expenses. NREs usually cover everything from circuit design through prototype approval. The other major cost passed on to the user is the component charge, which is the cost of manufacturing the gate array or standard cell device.

Since the early 1980’s, the ASIC vendor’s revenue split between component charges and NREs has dramatically shifted. Revenue data from LSI Logic (the leading U.S.-based ASIC house) shows how rapidly the NRE portion has shrunk (Figure 5-8). The increasing capability of the system companies’ in-house design resources as well as the increasing number of ASIC designs moving into volume production are driving this evolution.

Figure 5-9 shows that since 1987 and until 1995, LSI Logic’s design and technology service revenue stayed at about $100 million per year. With standard cell NRE’s higher than those for gate arrays and LSI Logic’s quickly growing standard cell business, one would expect LSI’s NRE revenues to surge. However, the number of standard cell designs performed is usually less than that for gate arrays, leading to the declining design revenue for LSI Logic in 1995.

5-6 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Cost Effectiveness

100

80 49% 53% 70 63%

60 74% 83% 83% 85% 85% 87% 50 89% 94%

Percentage 40

51% 47% 20 37% 26% 10 17% 17% 15% 15% 13% 11% 6% 0 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 Year = Components = Design and Technology Services

Source: ICE, "ASIC 1997" 12873K

Figure 5-8. LSI Logic’s Changing Revenue Make-Up (1985-1995)

110 105 105

100 97 98 98 99 93 94 91 90

80 76 71 70

Millions of Dollars 40

0 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 Year Source: ICE "ASIC 1997" 15437F

Figure 5-9. LSI Logic’s Design and Technology Service Revenues (1985-1995)

INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-7 ASIC Cost Effectiveness

Although the percentage of LSI Logic’s total sales from ASICs rose in 1995, the NRE portion of its ASIC sales continued declining (Figure 5-10). Throughout the 1990’s, ICE expects the NRE percentage of total ASIC sales to continue to decline for LSI Logic as well as for the other ASIC suppliers.

Standard Cell MPU 11% MPU And Standard Cell 15% And MPR MPR 8% 11%

1992 1993 $617M $719M

ASIC* ASIC* 92% 89%

Gate Array Gate Array 81% 74%

Standard Cell MPU MPU 28% And Standard Cell And MPR 45% MPR 9% 7%

1994 1995 $902M $1,268M

ASIC* ASIC* 91% 93% Gate Array Gate Array 48% 63%

* NRE % OF ASIC 1992 = 19% 1993 = 15% 1994 = 12% 1995 = 6%

Source: ICE, "ASIC 1997" 19135B

Figure 5-10. LSI Logic’s Sales by Product Type

The major factors in setting NRE costs are the type of technology used, the number of competitors in the market, and the complexity level (number of gates or macrocells). In general, the higher the gate count the higher the NRE. This is especially true for technologies like ECL and CMOS.

5-8 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Cost Effectiveness

Below 10,000 usable gates, CMOS Technology Usable Gates NRE/Gate ($) gate array NREs tend to reside in GaAs ≤10K 4.00 - 10.00 the $10,000-$20,000 range. At the >10K 1.00 - 2.00 20,000-100,000 gate and greater den- BiCMOS All 1.50 - 3.00 CMOS ≤3K 6.00 sity levels, CMOS gate array NREs >3K - ≤10K 1.55 - 3.00 are approximately $0.75-$1.00 per >10k - ≤20K 1.50 gate. Beyond 150,000 gates, NREs >20K - ≤150K 0.75 - 1.00 >150K 0.30 - 0.50 come down to about 30-50¢ per ECL ≤2K 25.00 gate. Embedded functions like >2K - ≤10K 5.00 - 10.00 MCUs, MPUs, and blocks of high- >10K 1.00 - 2.00 speed SRAM can sometimes Source: ICE, "ASIC 1997" 18550C increase the NREs by up to 50 per- Figure 5-11. Typical 1996 Gate Array NRE Charges cent. Thus, a user should expect to pay an NRE of at least $75,000- $100,000 for a CMOS array with NRE RANGE 100,000 usable gates. For BiCMOS ASIC TYPE ($K) devices, $1.50-$3.00 per gate is a PLD* 2 - 75 typical range for NRE charges CMOS GATE ARRAY 9 - 450 (Figure 5-11). BiCMOS GATE ARRAY 20 - 250 GaAs GATE ARRAY 30 - 200 Compared to low-end gate arrays, ECL GATE ARRAY 10 - 200 the NRE charges for advanced CMOS STANDARD CELL 15 - 450 BIPOLAR STANDARD CELL 50 - 200 CMOS gate arrays and CMOS stan- GaAs STANDARD CELL 40 - 200 dard cell devices have remained FULL CUSTOM 100 - 350+ fairly high due to the complexities *One-time charge for software and of the technologies and the fewer programming equipment number of vendors (Figure 5-12). Source: ICE, "ASIC 1997" 14035G

Figure 5-12. Ranges of Non-Recurring One thing that should be remem- Engineering Charges (1996) bered about ASIC NREs is that they are almost always negotiable. If an ASIC manufacturer needs to better utilize its fab or the ASIC customer’s future business prospects look promising, the ASIC NRE charge to the customer may be lowered or even waived. In 1993, 1994, and most of 1995, the overall IC industry (and certain segments of the ASIC market) was booming. With demand outstripping the supply for advanced ICs, ASIC NRE quotes became less negotiable than in the late 1980’s and early 1990’s.

As less and less of the ASIC producers total revenue is realized from NRE, ASIC manufacturing efficiency is at the same level of importance as in standard IC processing. However, the ASIC fab is destined to be less efficient than a high volume memory facility, as the infrastructure needed for the ASIC fab to handle many mask sets, part types, and even processes is very complex and costly.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-9 ASIC Cost Effectiveness

An ASIC manufacturer must now operate IC facilities that are competitive in process technology and utilize a high percentage of available capacity. Anything less than this is going to make prof- itability a very difficult result for the ASIC vendor to attain.

PLD OVERVIEW

Up to this point very little has been said about programmable logic devices (PLDs), including FPGAs. This omission has been intentional as these devices fall somewhere in between a standard IC and a gate array or standard cell device. PLDs are purchased much like standard ICs and are available off-the-shelf. However, the PLD user is typically fully responsible for the logic design and programming of the finished device.

PLDs resemble gate arrays and standard cells in that a part is made unique by (or for) each individual user and can correctly be called an Application Specific Integrated Circuit. Moreover, NRE expense is incurred by the user. This cost covers the one-time purchase of programming software and a programming station. This cost can be significant.

Silicon Graphics, Inc. presented a TOTAL PROJECT COSTS case study that showed the advan- One PAL, GAL and PROM (300 mil) station $48,000 tages and cost elements (Figure 5- One EPROM (600 mil) station $20,000 13) of performing PLD program- ESD accessories $1,000 ming in-house. Silicon Graphics stated that the costs for the in-house General accessories $1,000 PLD programming facility were Equipment expenditures $70,000 recouped within the first three quar- One full-time engineer for 6 months + ters of operation. 25% overhead Engineering resources (NRE) $35,000 The traditional TTL-based fuse-pro- Total $105,000 grammable PLD, originally market- ANNUAL OPERATIONAL COSTS ed by Signetics and MMI, has been replaced by CMOS PLDs. In gener- Full service equipment contracts $4,000 al, these devices have surpassed the One full-time and one half-time operator at $10/hr + 25% overhead $38,000 capabilities of the bipolar PLDs by offering lower power requirements, One 1/3 time technician support at $17/hr + 25% overhead $14,000 enhanced functionality, and higher Total $56,000 gate densities. PLDs with up to

Source: Silicon Graphics/ASIC Technology & News/ 17675 twenty thousand usable gates are ICE, "ASIC 1997" now a viable option for the low-end Figure 5-13. Silicon Graphics’ In-House gate array user. PLD Programming Costs

5-10 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Cost Effectiveness

PLDs VERSUS GATE ARRAYS

The previous sections have general information and rule-of-thumb type data. This section will look at a specific comparison of 2Q96 plastic-packaged PLD and gate array costs. For this study, a CMOS 0.7 micron 60-90MHz gate array with 10,000 usable gates was compared to a 0.5 micron (three-layer metal) field-programmable gate array (FPGA) with a similar gate count that supports system performance of up to 50MHz. Higher performance PLDs are available but can cost twice as much or more per gate.

Cost can be divided into two categories, fixed and variable, that when added together give the total cost (Figure 5-14). Gate arrays have significantly higher fixed costs than PLDs, which tends to make PLDs more cost effective at low volume levels.

Total Cost = Fixed Cost + (Variable Cost)(Units)

Source: ICE, ASIC 1997" 14054

Figure 5-14. Cost Formula

The breakdown of fixed costs for the gate array and PLD is shown in Figure 5-15. An explanation of the various terms is given below.

COST SEGMENT GATE ARRAY ($) NRE 20,000 SIMULATION 5,000 TIME TO DESIGN FOR TESTABILITY (2 man weeks) 4,000 DESIGN ITERATIONS* 11,250 TEST PROGRAM (4 man weeks)** 8,000 TOTAL 48,250 PLD COST SEGMENT ($)

SIMULATION (1 man week) 2,000 SOFTWARE AND PROGRAMMER*** 1,200 TOTAL 3,200 *Design iterations = 1/2 (NRE) + 1/4 (simulation) **1 man week = $2,000 *** $1,200 = $60,000 total software and hardware cost ÷ 5-year life ÷ 10 designs/year Source: ICE, "ASIC 1997" 14041E

Figure 5-15. Calculation of Fixed Costs of 10,000 Usable-Gate Device

INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-11 ASIC Cost Effectiveness

Gate Array Terms

NRE - Includes on-line vendor interface, design verification, mask charges, prototype samples, and a nominal simulation (pre- and post-layout) time.

Simulation - Additional simulation costs cover use of the vendor’s computer (typically a mainframe).

Time to Design - This covers extra design time.

Testability - To insure the device can be tested. Estimated engineering time is two weeks for a 10,000 usable gate array. One man-week is assumed to cost $2,000.

Design Iterations - This cost covers modifying the design, device prototyping, and initial customer evaluation. Cost is calculated by taking 1/2 of the total NRE plus 1/4 of the simulation time (charge). This cost assumes the ASIC customer wants to change the design. Vendor-caused design iterations are rare and the customer is usually not charged when they occur. Currently, design iterations for gate array and standard cell designs are needed much less frequently than in the mid to late 1980’s.

Test Program Development - The engineering time necessary to create test vectors, estimated at four weeks for a 10,000 usable-gate array. Once again, one man-week is assumed to cost $2,000.

PLD Terms

Simulation - PLDs do not need the extensive simulations that gate arrays require. However, high- density PLDs should be simulated. This model assumes 1 week for a 10,000 usable gate PLD with one man-week costing $2,000.

Software and Programmer - These are the programming tools and system that users purchase to program PLDs. The tools cost $60,000 with an estimated life (usefulness) of five years. Assuming there are 10 designs per year, the software cost per device is only $1,200.

Variable Costs

Variable costs are those that fluctuate in direct proportion to changes in output. The variable portion of the cost to the user is calculated by taking the product of three values: price-per-gate, total gates, and units (Figure 5-16). As shown, the 1996 price-per-gate for the PLD device is only four times the price of a similar density CMOS gate array. In 1993, the PLD was 15 times the cost of a similar density CMOS gate array.

5-12 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Cost Effectiveness

Total Cost = Fixed Cost + (Cents/Gate)(Usable Gates)(Units) • 10K Usable Gate Array Total Cost = $48,250 + (0.06¢)(10,000)(Units) • 10K Usable Gate PLD Total Cost = $3,200 + (0.24¢)(10,000)(Units) Source: ICE, "ASIC 1997" 14047G

Figure 5-16. 1996 Total Cost Formulas for Gate Array and PLD Devices

Using the total cost formulas (Figure 5-16), the breakeven point for the gate array and PLD can be derived. At the 10,000 usable gate level, the PLD solution is more cost effective at unit volumes below 2,502 in 1996 (Figure 5-17). This figure was only 414 in 1991 for comparable 5,000 gate devices (Figure 5-18).

140

120

100

80 10K-Gate 75,200 1996 Gate Array 60 66,250

49,450 1996 40 Breakeven 10K-Gate Units 20 1996 2,502 Total Cost (Thousands of Dollars) PLD 8,000 0 0 200 400 600 800 1,000 1,200 1,400 1,600 1,800 2,000 2,200 2,400 2,600 2,800 3,000 Project Units Source: ICE, "ASIC 1997" 16723E

Figure 5-17. 1996 10,000 Usable Gate Total Cost

As shown, it does not take a large number of units for the gate array approach to amortize its large fixed cost to the point where it becomes more cost effective than the PLD. The $24 PLD unit price versus the $6.00 gate array device price assures a fairly low-volume crossover point given almost any reasonable gate array NRE charge. However, as was shown in Figure 5-18, the breakeven crossover point has become more favorable for PLDs with each passing year.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-13 ASIC Cost Effectiveness

3,000 2,800 2,600 2,502 2,400 2,200 2,000 1,800 1,600 1,386 1,400

Unit Volume 1,200 1,000 966

800 660 600 494 414 400 200 0 1991 1992 1993 1994 1995 1996 Year Source: ICE, "ASIC 1997" 21022

Figure 5-18. PLD Versus Gate Array Total Cost Breakeven Unit Volumes (1991-1996)

Because the NRE charge is such a small part of the total cost make-up of an FPGA, the total unit price of the 1996 10,000 usable gate device decreases only 37 percent when going from using 200 units to using 3,000 units. However, because such a large portion of the gate array total cost is NRE, the amortization of the NRE causes the 1996 10,000 usable gate array total unit price to decrease about 91 percent when going from using 200 units to 3,000 units.

Figure 5-19 shows that whether at 200 or 3,000 units, a very high percentage of the gate array’s cost is due to fixed (i.e., NRE) costs. When the IC industry was slumping (1989-1991) and heavi- ly discounted NRE charges were the norm, the choice to use a gate array was very clear from the beginning. However, now that NRE charges have firmed, the PLD choice looks more attractive, especially at low unit volumes.

As shown, 96 percent of the cost of using PLDs at 3,000 units is from variable costs (i.e., the unit price). This is the reason it is so critical for the PLD producer to reduce device costs by using advanced processes (0.6µm or less) and interconnect (3-layers of metal or more) schemes, both of which result in reduced die sizes and lower unit costs.

5-14 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Cost Effectiveness

2% 100

90 27%

60% 70

96% 50 98% Percent

40 73%

20 40%

4% 0 Gate Array PLD Gate Array PLD 200 Units 3,000 Units = Fixed Cost

= Variable Cost Source: ICE, "ASIC 1997" 20101A

Figure 5-19. 1996 10K-Gate PLD Versus Gate Array Cost Make-Up

Since 1985, Xilinx has lowered its FPGA price per gate by at least 30 percent per year*. Assuming this trend continues, the 10,000 usable gate FPGA would cost about $4.03 in 2001. However, at $4.03, the crossover point between the FPGA and gate array is over 500,000 total units. This figure is more than 225 times the unit crossover point of 1996.

If the FPGA and gate array price trends continue as mentioned in the previous paragraph, the relative FPGA/gate array price ratio by the end of the decade would be much less than 2:1 (Figure 5-20). Given the time-to-market benefits of FPGAs, and less than a 2x price difference, it would be safe to assume that FPGAs would serve the vast majority of low gate count (≤40,000 gates) needs at that time.

As was discussed in the ASIC Technology Trends section, PLDs will continue to increase in density to compete with “low-end” gate arrays. The current definition of low-end for the gate array market are devices with less than 20,000 gates and speeds of less than 40MHz.

* From 1991-1996 the average annual decline was 37 percent.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-15 ASIC Cost Effectiveness

10 8 6

1 1995 Actual 0.8 0.6 MOS PLD Price Per Gate 33X 0.4 Trend 1996 Actual 15X 12X 0.2 6X

Cents Per Usable Gate 4X 0.1 0.08 3X 2X 0.06 CMOS Gate Array 1.5X 0.04 Price Per Gate Trend

0.02

1990 1991 1992 1993 1994 1995 19961997 1998 1999 2000 2001 Year Source: ICE, "ASIC 1997" 18551E

Figure 5-20. Relative Price Per Gate for MOS PLDs Versus Low Gate Count Gate Arrays

ICE estimates that about 20 percent of the total dollar volume of the CMOS gate array market in 1996 would be defined as “low-end”. Thus, advanced PLD producers are attempting to use their 3-layer metal ≤0.6µm PLDs to target the $1.2 billion low-end business of the CMOS gate array supplier.

It is interesting to note that in most cases the CMOS gate array suppler is not fighting the PLDs attack on the low-end market. Most CMOS gate array suppliers are concentrating on the high- density, high-performance, and high unit volume segment of the gate array market. With business booming from 1992 through 1995, gate array vendors were very “selective” of the contracts they took for gate array devices—oftentimes turning down business in the process! As of mid- 1996, a few vendors had changed their tune with regard to the gate array business.

5-16 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Cost Effectiveness

What this now means as far as the trend lines shown in Figure 5-20 is that the low-end CMOS gate array price per gate may stay relatively flat in the future. With little competitive pressure, the low- end CMOS gate array price per gate could even increase in the late 1990’s. Low gate-count arrays could even be at a higher price per gate than PLDs after the year 2000!

Figures 5-21 and 5-22 show how steeply MOS PLD prices are dropping in 1996. In the case of Xilinx, it has also stated its aggressive PLD pricing plans for the second half of 1997.

48 x 45

42 = Early 1996 Price 39 x = Late 1996 Price 36 = 2H97 Price 33 30 27 x

Dollars 24 21

18 x 15 12 x 9 6 x 3 0 02 46 810 1214 1618 20 Thousands of Gates Source: Xilinx/ICE, "ASIC 1997" 21023

Figure 5-21. Xilinx’s FPGA Price Reductions

While the 30 percent or greater decline in the PLD price per gate may be difficult to sustain into the late 1990’s, there is little doubt that PLDs will become more competitive in price compared to low-end gate arrays. This is one reason that ICE is bullish about the future of the PLD/FPGA business (discussed in Section 4).

There is no doubt that when comparing specific unit costs of gate arrays (even including NREs) and PLDs in 1996, gate array devices look favorable at all but the lowest volume levels. Why then has there been a surge in the PLD market over the past few years? The answer is the increasing importance of the “time to market” factor. For example, in today’s high-end disk-drive market, lifecycles of six-months to a year are fairly common.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-17 ASIC Cost Effectiveness

8 16,000 Gates 7 EPF81500

6 12,000 Gates EPF81188 5 50% Average 4 Annual Reduction

Normalized Price/Gate 3 59% Average Annual Reduction 2,500 Gates 25% Average 2 EPF8282 Annual Reduction 1

0 1Q94 2Q94 3Q94 4Q94 1Q95 2Q95 3Q95 4Q95 1Q96

Source: Altera/ICE, "ASIC 1997" 21024

Figure 5-22. Altera’s FLEX 8000 Selling Prices

50 Time to market costs refer to lost margins incurred by the delay of the 40 introduction of the system product into the marketplace. According to 30 a McKinsey and Company study, one-third of the potential profit dol- 20 lars are lost when the system is six months late to market (Figure 5-23). Loss in Total Profit (%) 10 Thus, the off-the-shelf aspect of

0 using PLDs instead of gate arrays 50% Product Ship Product becomes very attractive to conserva- Development Cost 9% Six Months Cost Overrun Too High Late tive systems companies* and those * In a 20% growth rate market, with 12% annual with very short market windows price erosion and a five-year total product life. Source: McKinsey & Co./ICE, "ASIC 1997" 16725 (the number of these systems houses is rapidly increasing). However, Figure 5-23. Impact of Three Factors on Profit Hewlett-Packard offers an interesting philosophy on time-to-market by saying, “Time to market is a very high priority, but is not at the expense of technological inno- vation. There are times when we say we may not be the first with this, but we will be the best.”

* And also, conservative design engineers. The up-front financial risk (i.e., NRE) of using PLDs is much less than that of gate arrays.

5-18 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Cost Effectiveness

A simple model that illustrates the concept of the importance of avoiding delays into the market is shown in Figure 5-24. The model was created by Logic Automation. It assumes that the market peak is in the middle of the total lifecycle timeframe, the revenue stream from a delayed entry parallels the on-time entry, and both the delayed and on-time market peaks are at the same point in time.

Maximum Available Revenue (R)

Market Fall

Market Rise

Maximum Revenue From Delayed

On-Time Entry Entry Revenues

Delayed Entry

Delay (D) Time W W

Product Life = 2W

Target Product Lost Revenue ($M) Due to Delay of: Revenue ($M) Lifetime 1 Month 2 Months 3 Months 300 36 Months 25 48 71 300 18 Months 48 93 133 200 36 Months 16 32 47 200 18 Months 32 62 89 50 36 Months 4 8 19 50 18 Months 8 15 22

Source: Logic Automation/SIBS/ICE, "ASIC 1997" 17677A

Figure 5-24. Delayed Market Entry Model

The percent of potential revenue lost by a delayed entry is expressed as ([D (3W-D)/2W2] [100]). Thus, a product that is three months late in a market that will last 24 months would lose 34 percent of its possible potential market revenue ([3(3x12-3)/(2x122)]x100). Some lost revenue dollar examples are also given in Figure 5-24. Although one can argue the assumptions of the model, the conclusion that time to market is of critical importance to most companies is irrefutable.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-19 ASIC Cost Effectiveness

As is probably obvious by now, the choice between gate arrays and PLDs is getting more complex. Figure 5-25 summarizes some of the trade-offs of using PLDs versus gate arrays. In the near future, it appears that PLDs must be content to primarily service low unit volume, low density (compared to gate arrays), medium-performance designs, and/or those systems with short market windows. However, as has already been discussed, this will be a significant marketplace. Moreover, in the long run, PLDs may dominate the less than 40,000 gate marketplace based upon attractive price per gate costs!

No NRE Second Sourcing* Lower Volume Higher Density Possible Redesign Higher Volume In-System Reprogrammability Megacells** Fast Turnaround/Time-to-Market Higher Performance PLD ARRAY

*Second sourcing is becoming less common for high-end PLDs. **Some families of PLDs have begun to offer MCU, peripheral functions, as well as SRAM or ROM capability. Source: ICE, "ASIC 1997" 15441F

Figure 5-25. PLD and Array Trade-Offs

There are a few companies (e.g., Orbit Semiconductor) that have developed programs to quickly convert a PLD design into a gate array when the unit volume of the PLD device rises. In these cases the user can have the best of both worlds –– quick time to market with the PLD and low cost volume production of the gate array if system volume shipments take off. This is especially true for high density PLD devices where unit costs are extremely high*. Obviously time-to-market will be the primary selling point for these high-density PLDs/FPGAs.

Some of the PLD companies (e.g., Xilinx) are offering hard-wired versions (mask programmable) of their PLDs for about a $15,000 design conversion cost. About eight percent of Xilinx’s PLD sales in 1995 were for mask programmable devices (i.e., hardwire sales). Altera will also convert up to 40 EPLDs into one mask programmed device for a $20,000-$60,000 charge.

* In 2Q96 Altera announced availability of a 100,000 gate PLD that sells for $995 each in 100 piece lots.

5-20 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Cost Effectiveness

STANDARD CELLS VERSUS GATE ARRAYS

Similar to the on-going debate of when to use PLDs versus gate arrays, standard cell-based ASICs and gate arrays are oftentimes compared to each other and compete for many of the same appli- cations. A good analysis on the topic of cells versus arrays, and the basis for this sub-section, is by R. Walker, J. Rau, and R. Brossart of LSI Logic.

In this analysis, LSI’s double-layer metal LMA9000 series gate array family was compared to its LCBV15 cell-based ASICs (both of which had 0.9 micron effective channel lengths). Although LSI has updated these ASIC families with much more advanced array- and cell-based ASIC technologies, the basic trade-offs between cells and arrays presented hereafter still hold true in today’s marketplace.

Given the same gate-limited design implemented in comparable cell and array technologies, cell- based designs will always yield a smaller die size. Three main reasons for this situation include:

1. Because of the ability to optimize transistor size and gate usage, random logic in cell-based designs requires about 15 percent less die area than in arrays. 2. ASIC memory (e.g., RAM or ROM) is implemented much more efficiently in cell-based designs as compared to array-based designs (not including embedded megacells). 3. With gate array masterslices typically coming in 30 percent increments in density (Figure 5- 26), the odds are that an array-based design will result in some wasted die area as compared to standard cell designs.

Part # Raw Gates Usable Gates I/O (µPD659xx) (K) (K)

26 190 114 388

27 250 150 444

28 318 191 500

29 377 226 540

30 462 277 596

31 630 378 692

33 806 483 772

35 1,076 646 892

37 1,545 927 1,060

39 1,990 1,194 1,204

Source: NEC/ICE, "ASIC 1997" 21025

Figure 5-26. NEC’s 0.35µm Gate Arrays (CMOS Family, 3-Layer Metal)

INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-21 ASIC Cost Effectiveness

The next few examples of cell versus array figures were compiled by LSI Logic using actual pricing data. It should be noted that in all of the models NRE costs were not included as a factor. One of the key points that is critical in these analyses is the lower manufacturing cost of gate array wafers as compared to standard cell wafers.

Since gate array wafers are standard products up until the last few layers, they can be produced and inventoried in large volumes thus taking full advantage of a high volume production learning curve. In comparison, every mask layer of a standard cell wafer is customized and a customer may require only a few wafers at any one time. Moreover, every new set of standard cell wafers essentially starts nearer the beginning of a production learning curve.

The result of the manufacturing differences between cell and array wafers is that early in the production cycle, the array-based devices will typically cost less to produce than any specific cell- based device. This is in spite of the cell-based ASICs’ typically smaller die size and does not include or consider the lower NRE costs associated with array-based designs.

Figure 5-27 shows a 15,000 gate logic design implemented in array- and cell-based technologies. As shown, it takes 25,000 units before the smaller size of the cell technology die has enough of an effect on manufacturing cost to offset the cheaper array wafer (and thus die) production costs. At only 15,000 logic gate array densities, however, PLDs are now a competing ASIC alternative.

6 Cell Based

3 Array Based Relative Cost 2

0 1,000 2,000 5,000 10,000 20,000 50,000 100,000 250,000 Annual Production Quantity *84-pin plastic DIP Source: LSI Logic/ICE, "ASIC 1997" 15444

Figure 5-27. 15K Gate Random Logic Example*

5-22 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Cost Effectiveness

Figure 5-28 shows what happens when a logic design is mismatched to the array masterslice. In this example, only 37 percent (13K) of the logic gates were used (out of a possible 35K gates) as opposed to the typical 45 percent usage for double-layer metal arrays. As shown, the crossover point moves rapidly down to 10,000 units as the highly efficient cell-based die size competes very well with this inefficient large gate array. The use of triple-layer metal has helped boost the usable gate percentage into the 60-70 percent range*. Of course the triple-layer metal arrays add complexity and cost to the manufacturing process.

5 Cell Based

Array Based 3

Relative Cost 2

0 1,000 2,000 5,000 10,000 20,000 50,000 100,000 250,000 Annual Production Quantity Source: LSI Logic/ICE, "ASIC 1997" 15445

Figure 5-28. 13K Gate Random Logic Cell Array Example

The cell-based devices are very competitive with array technology when implementing memory. Figure 5-29 shows how the crossover point gets down to only 5,000 units for a 4,500 gate design with 4K of SRAM.

It should be remembered that in all of the previous examples, the amortization of NRE charges was not included. If NRE costs were included, the more expensive charges associated with cell- based ASICs would put the crossover points at slightly higher unit volume levels.

As was stated in the gate array versus PLD sub-section, the decision to use one ASIC method as opposed to another is multi-faceted. The same situation is very true when looking at using cells or arrays. The decision ultimately must be based on each application’s requirements.

Figure 5-30 shows some of the basic trade-offs between cell- and array-based ASICs. NEC states that about one-third of its cell-based customers desire analog functions on-chip. When implementing analog circuitry the cell-based design will almost always win versus the gate array.

* At the 1996 CICC Conference, Hitachi described a 1.8 million total gate gate array with five layers of metal that was able to offer 1.0 million usable gates (≈55 percent).

INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-23 ASIC Cost Effectiveness

5 Cell Based

4 Array 3 Based

Relative Cost 2

0 1,000 2,000 5,000 10,000 20,000 50,000 100,000 250,000

Annual Production Quantity *40-pin DIP Source: LSI Logic/ICE, "ASIC 1997" 15446A

Figure 5-29. 4,500 Gates Plus 4K Single-Port SRAM Example*

Analog Special I/O Lower NRE Higher Volume Pad-Limited Smaller Die Size Limited Time Select Megacells Lower Volume Package Flexibility Possible Redesign CELL ARRAY

Source: LSI Logic/ICE, "ASIC 1997" 15447A

Figure 5-30. Standard Cell Versus Gate Array Trade-Offs

One point that was not touched upon in the previous models was the packaging flexibility associated with cell-based designs. Because cell-based technology allows both smaller die size and the flexibility to make a longer and narrower die than arrays, the cell-based device can sometimes be housed in a less expensive or more readily available package type.

5-24 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Cost Effectiveness

Whether it is cells versus arrays or arrays versus PLDs, it is imperative that potential ASIC users (or the manufacturers they trust) be aware of their technology options and intimately knowl- edgeable about their designs (and the systems in which their ASICs will be implemented).

OTHER ASIC COST CONSIDERATIONS

Price Per Gate

In the ASIC industry there is always a lot of discussion concerning price per gate. As has already been covered, the importance of price-per-gate figures is sometimes overestimated by the customer when choosing an ASIC methodology. However, when ASIC vendors, especially gate array suppliers, begin vying for a potential customer’s attention, price-per-gate figures are often the main topic of discussion.

Figure 5-31 shows a survey of some published ECL, BiCMOS, GaAs, and CMOS price-per-usable- gate figures. As shown, there is usually a wide range of prices, even for similar density devices.

For the CMOS gate arrays, the lower pricing points (0.02-0.04 cent per gate) in the band are typically 100,000 piece prices. The higher pricing points (0.06 cent per gate) are for low-density CMOS arrays with unit volume shipments of 1K to 10K.

In 4Q95, Vitesse introduced its GLX Family of GaAs gate arrays (Figure 5-32). These devices were priced at 0.1¢/gate in unit volumes of 20,000. In 1990, Vitesse’s family of GaAs arrays was priced at 1.0¢/gate or 10x the 1995-1996 price!

Because many users are demanding increased I/O capabilities from their ASICs (as many as two I/O pins for each 100 usable gates), some companies have begun pricing gate array families by pin. Hitachi achieves a fairly low cost but high I/O design by using staggered bonding pads (shown in Section 6). Thus, by using staggered bonding pads and/or reducing the pitch between the pads, the die size can oftentimes be shrunk (especially in the frequently encountered “pad-limited” designs) and subsequently the die cost can be reduced (Figure 5-33).

One formula that does hold true to form is that the customer must pay for performance. As shown, the price per gate escalates as one moves from the lower performance CMOS arrays to the high-speed ECL arrays (with a 100 to 1 price per gate ratio not uncommon).

According to ICE’s survey, the price per gate for BiCMOS versus CMOS gate arrays is from three to six times greater. Unisys, a large user of ASICs, showed a comparison (Figure 5-34) it had made when examining BiCMOS ASIC offerings. While the cost/performance ratio of the high-end BiCMOS versus CMOS ASICs does not look attractive, more than likely the high-end BiCMOS

INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-25 ASIC Cost Effectiveness

devices are competing against ECL and GaAs rather than CMOS. The cost/performance ratio for high-end BiCMOS versus ECL or GaAs puts the high-end BiCMOS technology in a more favorable competitive position.

5GHz GaAs 10.0 High-Speed ECL Arrays (1 - 2GHz) 5.0

ECL Gate Arrays High-Performance GaAs (3GHz) 1.0

0.5 BiCMOS and GaAs Gate Arrays Cents/Gate (1GHz)

0.1 (700MHz) 0.05

CMOS Gate Arrays 0.01 15 10 50 100 500 1,000 Usable Gates (Thousands) Notes: • GaAs arrays in unit volumes of 20K. Key • ECL arrays packaged in ceramic, and unit volumes of 1K. = ECL • CMOS and BiCMOS arrays packaged in plastic QFP, feature = GaAs size 0.35µ - 0.8µ, typical loaded gate delays 125ps - 300ps, = BiCMOS and unit volumes 5K to 10K. = CMOS = CMOS 100K+ Unit Volumes Source: ICE, "ASIC 1997" 16720E

Figure 5-31. 1995-1996 Gate Array Price-Per-Gate

In general, the price-per-gate figures for standard cell devices average about the same as gate arrays. Although standard cell die sizes are typically smaller than similar density gate arrays, the more complex functions incorporated with standard cells (e.g. ,analog, MCUs, etc.) ultimately lead to fairly close price-per-gate figures. This, of course, does not include the amortization of the higher NRE charged for the standard cell parts. Because of the increasing use of analog, MPU, MCU, etc., functions on standard cell and gate array ASICs, direct price-per-gate comparisons are becoming more difficult and less applicable.

5-26 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Cost Effectiveness

0.3 FX

1GHz Performance 0.2

SLX VIPER 700MHz Performance GLX 0.1 Cost (Cents/Gate)

0.5µ CMOS

0 00.5 1.0 1.5 3.0 REL Speed/Power Product Source: Vitesse/ICE, "ASIC 1997" 21026

Figure 5-32. Vitesse GaAs ASIC Products

Die Pad Pitch (mils) 5.5 5.0 4.4 4.1 3.6 700 $4.00

600 $3.50

$3.00 500

$2.50 400 $2.00 300 $1.50 $900/Wafer Cost Die Cost Assumes

Good Die per 6" Wafer 200 $1.00

100 $0.50

0 $0.00 245 x 245 225 x 225 200 x 200 190 x 190 175 x 175 Die Size (mils) Good Die/Wafer Die Cost Defect Density = 2d/cm2 Defect Density = 2d/cm2

Source: ASAT Inc./ASIC & EDA/ICE, "ASIC 1997" 18555

Figure 5-33. Projected Die Cost Reduction for Shrunk Pad Limited ICs

INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-27 ASIC Cost Effectiveness

4 CMOS

Low-end BiCMOS

3 High-end BiCMOS

2 Ratio

0 Chip Cost Performance Cost/Performance Source: Unisys/ICE, "ASIC 1997" 17678

Figure 5-34. CMOS Versus BiCMOS ASIC Comparison

Time Considerations

The old phrase “time is money” is directly applicable to the ASIC industry. As mentioned earlier in this section, one of the primary benefits of using PLDs is off-the-shelf availability. As is exem- plified by the sharply increasing PLD market, this benefit is worth the relatively high PLD unit price to many ASIC users.

Figure 5-35 shows the typical ASIC (not including PLDs) prototype and production leadtimes. As shown, the typical time from a signed-off gate array design to the first available production quantities is nine weeks. For standard cells another five weeks is usually added.

Earlier in this section an example that showed Silicon Graphic’s experience with in-house PLD programming was given. Significantly, the company was able to reduce its PLD programming time to one to two days versus two weeks when using outside PLD programming services.

As manufacturers have gotten better at producing ASICs, factory cycle times have improved (Figure 5-36). Moreover, ASIC manufacturers have also implemented specialized programs (e.g., wafer banking) in an attempt to further speed up delivery times to customers.

One of the more unique programs to speed up delivery of ASIC prototypes is offered by Chip Express (Santa Clara, CA). The company uses a laser-based trimmer to make up to 6,000 cuts per second with 0.2 micron tolerance to customize gate arrays having from 2,000 to 100,000 usable gates. A 40,000 usable gate device requires about 15 million cuts and can be customized in about two hours.

5-28 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Cost Effectiveness

Prototypes Gate Array 2.0

Linear Array 6.0

Standard Cell 6.0

Production

Gate Array 7.0

Linear Array 8.0

Standard Cell 8.0

0246810 Weeks Source: ICE, "ASIC 1997" 17681D

Figure 5-35. Typical 1996 ASIC Leadtimes

120

100

60 Days

0 1989 1990 1991 1992 1993 1994 1995 Year Source: LSI Logic/ICE, "ASIC 1997" 17683D

Figure 5-36. Factory Cycle Time (Customer Order-to-Ship)

INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-29 ASIC Cost Effectiveness

The average fee for two 20K gate prototype chips delivered in one week is about $12,500. Specialized one-day turnaround is also available at about double this price. Chip Express can deliver production volumes (50-1,000 pieces) of its gate arrays in two weeks using photomask technology (there is a one time $18K charge). Because of the special design of the base wafer, one photomask customizes two layers of metal.

For very high volumes (e.g., tens of thousands) of parts, Chip Express began offering (in 1995) what it calls its HARD (High Area Reduction Die) array. The HARD arrays are produced at IC foundries (e.g., Seiko Epson and Tower Semiconductor) using normal gate array photomask technology. As shown in Figure 5-37, the HARD array option now gives Chip Express prototype to production capability.

LPGA - Laser-cut single die Micro-Fab Quick Laser® System Prototypes Quantities from 2-10 pcs Delivery 1-5 days

Mini-Fab One Mask® Technology Initial Single-step wafer-level fab Production Quantities from 10 to 5000+ pcs Delivery 1-2 weeks

HARD ArrayTM -compact die Mega-Fab High-volume production Volume Production Low unit cost Delivery 6-8 weeks

Source: Chip Express/ICE, "ASIC 1997" 20103

Figure 5-37. Chip Express’ Prototype to Production Programs

With the increasing customer demand for faster turnaround times we now have PLD vendors competing with gate array vendors as well as a few specialty gate array vendors attempting to match PLD availability characteristics. As always, the customer must weigh the benefit of fast turnaround versus its inevitable and sometimes significant price premium.

Packaging Trends

New sea-of-gates arrays are offering 1.9M total gates with up to 1.3M usable gates. One area that is under extreme pressure to meet the challenge of a 1.3M usable-gate device is the packaging industry. As shown in Figure 5-38, ASICs with 100K-150K usable gates require packages with 300-

5-30 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Cost Effectiveness

500 pins. Even some 12,000 usable-gate devices are specifying packages with more than 200 pins. Figure 5-39 shows the numerous package types LSI Logic offers and the pin-count ranges of these packages.

500

150K Gates 450 480 Pins 1 100K Gates 416 Pins 1 112K Gates 400 409 Pins

350 70K Gates 100K Gates 320 Pins 1 344 Pins 40K Gates 300 280 Pins 90K Gates 50K Gates 304 Pins 250 288 Pins 1

Package Pins 200

150

100

0 0 25 50 75 100 125 150 Usable Gates (Thousands) 1 TAB QFPs; a 560K gate, 652-pin TAB QFP is also available. IBM's 1.3M usable gate ASIC can be housed in ball-grid packages with over 1,000 pins. Source: ICE, "ASIC 1997" 16719B

Figure 5-38. Pin Count Versus Usable Gates

Figure 5-40 shows some of the most commonly used plastic and ceramic packages and their 1996 costs. It should be noted that all ceramic package types are hermetic, whereas plastic packages are non-hermetic (which is why military systems nearly always use ceramic packages).

For the high lead count ceramic packages, $0.08 per pin is typical. In some cases the package will cost more than the ASIC die! For the extremely high pin count devices (i.e., greater than 300 pins), TAB (tape automated bonding) or flip-chip bonding methods are displacing the typical wire- bonding techniques.

The packaging cost figures shown are only for the raw material. Typically, an additional $0.07- 0.10 per package can be added for labor and overhead associated with the packaging operation. North American and European companies’ IC packaging is usually performed in areas such as the Philippines or Malaysia rather than in North America or Europe* where labor rates are much higher (Figure 5-41). However, for quick turnaround, low-volume, or high ASP ASIC needs, local assembly is still sometimes a good alternative.

* Currently, much of the Japanese IC packaging needs are still being met with local facilities.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-31 ASIC Cost Effectiveness

800 Surface Mount Thru-hole 750 720 700 = Hermetic

600 = Non-Hermetic 527 503 500

400 383

340

Pin Count 304 304 313 300 313

240

200 176

160 169

100 84

80 64 64 68 44 44 0 28 PLCC TQFP PQFP COT PBGA TBGA CLDCC CPGA PPGA MQUAD E-PBGA Key: PLCC = Plastic Leaded Chip Carrier COT = Chip on Tape CLDCC = Ceramic Leaded Chip Carrier TQFP = Thin Quad Flatpack PBGA = Plastic Ball Grid Array CPGA = Ceramic Pin Grid Array PQFP = Plastic Quad Flatpack TBGA = Tape Ball Grid Array PPGA = Plastic Pin Grid Array MQUAD = Metal Quad Package E-PBGA = Enhanced PBGA

Source: LSI Logic/ICE, "ASIC 1997" 19138

Figure 5-39. Package Families for LSI Logic ASICs

In the case of a standard plastic metric quad flatpacks (MQFPs) for volume production, a copper heat spreader will average about $0.05-0.06 assembled into the IC package and a heat slug or lid about $0.07 each. The total thermal solution is therefore $0.13-0.14 per MQFP. This system works effectively for heat dissipation in a range of 2 to 3.5 watts/meter/k. Beyond these limits, the IC junction temperature becomes a reliability concern which could effect the long term IC package reliability. These copper heat spreaders and heat slugs or lids are stamped from copper plates and therefore represent the most competitive solution for lower heat devices in volume purchases of MQFP packages.

The issue of thermal management for higher watts/meter/k IC devices provide more difficult thermal challenges, which often eliminate the use of conventional copper heat spreaders and copper lids. Ceramic heat spreader and lids, thermally enhanced epoxies, and many other solutions are used in combinations to achieve more effective thermal management solutions for these IC package types. IC thermal management will continue to become a more significant challenge to overall IC package costs, as the gate counts per device and IC junction temperatures dramatically increase.

5-32 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Cost Effectiveness

Average IC Plastic Ceramic Lead Market Most Frequent Package Pin Counts Packages Packages Price ($)

P-DIP .008 16 18 20 24 28 32 40 48 64 C-DIP .021 16 18 22 24 28 32 40 48 CERDIP .024 16 18 20 22 24 28 32 40 42 SOJ .0085 20 24 SOP .0095 44 PLCC .0095 18 22 20 28 32 44 52 68 84 100 TSOP .01 20 24 26 32 34 40 44 48 50 54 62 (I&II) LCC .055 18 20 28 32 44 68 MQFP*/ .0097/ 36 80 100 132 164 TQFP .0099 44 84 128 184 196 48 100 144 240 232 52 120 160 296 244 64 208 304 68 256 376 PGA .02 10 x 10 11 x 11 13 x 13 15 x 15 16 x 16 17 x 17 18 x 18 20 x 20 40 x 40 (68) (68) (114, (145, (175) (168, (179, (272- (272- 121, 181) 207, 299) 375) 400+) 132) 209) PBGA .024 119 144 169 208 225 256 304 313 352 CBGA .065 customized configurations from 100 to 700+ positions CQFP .028 68 164 196 CPGA .087 68 88 132 168 208 240- 372 * Metric Quad Flatpack Source: Emissarius, Ltd./ICE, "Mid-Term 1996" 20104A

Figure 5-40. Base IC Package Price for Single-Chip Package Solutions Calculated from Volume Purchases for 1996 (Excluding IC Die, Heat Spreader/Lids, Test and Burn-in Cost)

Philippines $2.00/hr (50% Base/50% Benefits)

Korea $5.00/hr (50% Base/50% Benefits)

USA $11.00/hr (80% Base/20% Benefits)

Source: Integrated Packaging Assembly Corporation/ICE, "ASIC 1997" 21027

Figure 5-41. Typical Labor Cost Comparisons

Test Concerns

As ASIC devices have routinely begun to incorporate tens of thousands of usable gates, the testability issue has come to the forefront of ASIC user concerns (Figure 5-42). Most ASIC producers believe that ASIC users “should” be very concerned with testability when gate counts exceed 25K.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-33 ASIC Cost Effectiveness

Response Percentage 0 5 10 15 20 25

Test 23%

Tools 20%

Time to 13% Market

Simulation 13%

Performance 8%

Price 7%

System 6% Level

Analog 4%

Standards 3%

Support 2%

Source: Based on a survey by ASIC Technology & News/ICE, "ASIC 1997" 16730

Figure 5-42. Critical Issues for System Designers

Test vector generation typically consumes about 40 percent of an ASIC’s design time (Figure 5-43). This is especially true for high-density ASICs. Figure 5-44 shows the typical development costs of a mixed-signal ASIC. As shown, almost one-third of the development cost was directly attributed to test engineering. Thus, considering the large amount of time and money spent addressing ASIC test, it is easy to see why it is such a hot topic.

When manufacturing an IC wafer, defects can occur that make a transistor or piece of interconnect metal incomplete. When this happens, the logic function that the designer of the chip intended will not work properly. It’s the job of the production test program of the manufacturer to test all connection points in the circuit (nodes) and make sure they switch when they’re supposed to.

An IC with several thousand transistors will have several thousand nodes that will switch between one and zero in the course of operation. If one of the nodes is frozen at either of the logic levels, it’s called a “stuck at” node, or a “fault.” This defect must be caught by the production test program. As the IC becomes more complex (more transistors), it becomes more difficult to test all nodes and catch all the “faults.” Hence, the phrase “fault coverage.”

5-34 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Cost Effectiveness

Test Vector Generation Functional 40% Simulation 25%

Prototype Test 10% Vendor Interface 10%

Specification Schematic 5% Capture 10% Source: ASIC Technology & News/ICE, "ASIC 1997" 16734

Figure 5-43. Design Time by Task

Direct Labor 6%

Test Administrative Engineering 16.8% 31%

Customer Materials Engineering 25.7% 20.5%

Source: Harris/ICE, "ASIC 1997" 17685

Figure 5-44. Mixed-Signal ASIC Development Cost Breakdown

It is estimated that more than 60 percent of the ASIC market requires better than 95 percent fault coverage with 50 percent of the market requiring 99 percent fault coverage.

Figure 5-45 shows how important high fault coverage is, especially for high-density ASICs. As shown, if you have only 95 percent fault coverage for a 100K gate array, about 80 defects per 1,000 parts will get through test undetected (not a very comforting thought for the ASIC user).

Currently, ASIC customers using gate arrays of less than 100,000 gate densities are still more inter- ested in keeping the unit costs low by avoiding the use of on-chip test structures. Figure 4-46 shows some of the “costs” (i.e., overhead) of various testing options. Beyond the 100,000 gate level, the “choice” of not using some type or types of on-chip test becomes much more risky in terms of the users’ time and money.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-35 ASIC Cost Effectiveness

1,000

100K Gates

100 12.5K Gates

3.1K Gates 10

1 Defects Per 1,000 Parts

0.1

0.01 70 75 80 85 90 95 100 Fault Coverage Source: Raytheon/ICE, "ASIC 1997" 17686

Figure 5-45. Defect Rate Versus Fault Coverage

• Full Internal Scan • 12% to 15% of total area

• Boundary Scan • I/O cells: 20 gates/pad • TAP controller: 300 gates

• BIST • RAMs: 250 to 470 gates up to 16K • ROMs: 300 to 1,060 gates up to 128K • LFSRs: 12 to 20 gates/pattern bit

• ScanBIST • 2% above full scan

• Embedded Core Isolation • Four gates isolated cell I/O

• Combined Methodologies • 7+% of total area

Source: Compass Design Automation/ 21028 ICE, "ASIC 1997"

Figure 5-46. Test Architecture Overhead

5-36 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Cost Effectiveness

Figure 5-47 shows IBM’s “Premium Grade” ASIC reliability program and the surcharge (+15 percent) for this service. It is interesting to note the 4x increase in failure rates predicted for devices with more than 1.2 million gates.

Premium Grade Commercial Grade

Market High Reliability Low Price

Average Fail Rate 10 FITs 100 FITs

Early Fail Rate 25 FITs 250 FITs

Cost +15% Standard

AFR = End-of-life Average Failure Rate FITs. EFR = Early life (0-1 yr) Failure Rate in FITs. AFR/EFR = Failure Rates for product with more than 1.2M gates increase by 4X. Source: IBM/ICE, "ASIC 1997" 21184

Figure 5-47. IBM’s CMOS 5X ASIC Reliability Testing Program

MANUFACTURING COST EXAMPLES

Figure 5-48 looks at an analysis of five CMOS gate arrays. The analysis examines the arrays by usable gate densities assuming 40 percent of the total gates for 2-layer metal, 70 percent of the total gates for 3-layer metal arrays, and 75 percent of 4-layer metal arrays are usable. The manufacturer in this model is assumed to be running its ASIC facility at 70 percent of capacity.

The defect density figures used in the gate array cost models are based on total fatal defects assumed to be randomly distributed. With all of the varied circuitry (e.g., SRAM, I/O, logic gates, etc.) on advanced ASICs, yield models that account for the different susceptibility to fatal defects have been developed.

One such model was described by Motorola at the 1994 Custom Integrated Circuits Conference. This model empirically derived “sensitivity” levels to describe how sensitive physical areas of the chip are to defects.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-37 ASIC Cost Effectiveness

Usable Gates* Cost Factors 10,000 30,000 60,000 125,000 250,000

Technology (CMOS) 0.8µm, 2-layer metal 0.7µm, 2-layer metal 0.5µm, 3-layer metal 0.5µm, 3-layer metal 0.35µm, 4-layer metal Complexity 14 mask levels 16 mask levels 20 mask levels 20 mask levels 24 mask levels Wafer size 150mm 150mm 150mm 150mm 200mm Tested wafer cost $400 $700 $825 $825 $1,750 Die size (sq. mils) 52K 124K 100K 180K 150K Total dice available 440 180 210 112 260 Probe yield** 92% 82% 70% 53% 45% Number of good dice 405 148 147 59 117 Cost per good die $0.99 $4.74 $5.61 $13.90 $14.96 Packaging cost (plastic)*** $2.00 $2.47 $5.47 $6.54 $26.40 Assembly yield 98% 97% 96% 96% 96% Yielded assembly cost $3.05 $7.44 $11.54 $21.29 $43.08 Final test cost $0.50 $0.75 $1.25 $2.00 $2.00 Final test yield 95% 90% 85% 85% 82% Factory cost $3.74 $9.10 $15.05 $27.40 $54.98 Gross margin 38% 41% 46% 47% 47% Selling price (5,000) $6.03 $15.42 $27.87 $51.70 $103.73 Cents per usable gate 0.060 0.051 0.046 0.041 0.041

*Assumes 40% usable for 2-layer metal, 70% for 3-layer metal, 75% for 4-layer metal. ** 0.35d/cm2 for 0.8µm and 0.7µm, 0.6d/cm2 for 0.5µm, 0.8d/cm2 for 0.35µm. *** 250K usable gate device housed in a ceramic BGA. Source: ICE, "ASIC 1997" 17688E

Figure 5-48. CMOS Gate Array Price Analysis (1996)

Defect sensitivity using an ASIC example is shown below.

I/O: 0.25 CMOS Logic Gates: 0.50 SRAM : 0.80

Thus, 25 percent of the I/O area, 50 percent of the logic area, and 80 percent of the SRAM area would be “fatal” to a defect. As would be expected, the “non-critical” feature sizes of the I/O as well as liberally spaced circuitry, only marginally expose the I/O area to fatal defects. However, tightly packed SRAM cells are highly susceptible to fatal defects with the logic gate figure falling somewhere between I/O and SRAM.

Overall, as ASICs begin to further incorporate large blocks of MPUs, memory, and other functions, formulas that account for area defect sensitvity will become more useful for estimating probe yield.

5-38 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Cost Effectiveness

As shown in Figure 5-48, the ASIC manufacturer’s gross margin improves as gate density increases. This is the key reason that many gate array vendors are concentrating on high-density devices. As was discussed earlier, PLD vendors are targeting the low-end gate array market that many ASIC vendors are now de-emphasizing.

As shown in Figure 5-49, high-density gate arrays are among the largest devices produced in the IC industry. With only 112 total dice available for a 0.5-micron 125,000 usable gate array on a 150mm wafer, the high-density gate array will be a driving factor pushing the industry toward using 200mm wafers. Notice how large the die size is for the 0.8µm and 0.7µm 2-layer metal PLDs compared to gate arrays of similar density*. No wonder the relative cost was so high for the PLDs. However, as was shown earlier, new architectures, sub-0.6µm feature sizes, and a move to 3-layer, and eventually 4-layer, metal is helping reduce die sizes and close the gate array/PLD pricing gap.

10M

0.35µm CMOS Gate Array Family

0.5µ CMOS 0.7µ CMOS Gate Array Family Gate Array Family

100K

µ Available Gates 1.0 CMOS Gate Array Family

0.5µm * * 0.6µm 10K * * 8K Gate 0.7µ Antifuse FPGA 15K gate SRAM-based 4K Gate 3-layer metal 0.8µ EPLD FPGAs 0 0 100 200 300 400 500 Die Size, sq. mils (1,000's) Source: ICE, "ASIC 1997" 14008H

Figure 5-49. Die Size Comparison

* Typically about 50 percent of a 2-layer metal PLD’s available gates are usable.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 5-39 ASIC Cost Effectiveness

An important element in the gate array cost models, especially for the low-density devices, is packaging cost (Figure 5-50). Packaging cost as a percent of the total cost make-up goes from 55 percent to only 25 percent in the 10,000 and 125,000 gate devices, respectively. However, to illus- trate the importance of packaging costs, notice that the packaging/assembly cost segment jumps to 50 perceent for the 250K gate array. This is due to using a ceramic package instead of plastic.

100

90 27% 27% 37% 80 52% 51% 70

50 50% 55% 38% 40 Cost (Percent) 25% 28% 30

25% 10 20% 24% 23% 18%

0 10K 30K 60K 125K 250K 0.8µ, 0.7µ, 0.5µ, 0.5µ, 0.35µ, 2-Layer Metal 2-Layer Metal 3-Layer Metal 3-Layer Metal 4-Layer Metal

Usable Gates

Die Packaging/Assembly Final Test

Source: ICE, "ASIC 1997" 17689D

Figure 5-50. CMOS Gate Array Factory Cost Make-Up (1996)

It is interesting to note that a key element of Vitesse’s low-cost GaAs ASIC program (GLX and Viper) is the use of a low-cost plastic package. As was shown previously, Vitesse has been able to reduce its GaAs gate array prices enough to compete with BiCMOS arrays.

5-40 INTEGRATED CIRCUIT ENGINEERING CORPORATION