Programable Logic Devices

In the 1970s programmable logic circuits called programmable logic device (PLD) was introduced. They are based on a structure with an AND- OR array that makes it easy to implement SOP expression

William Sandqvist [email protected] PLD structure

x 1 x 2 x n

Input buffers and inverters

x 1 x 1 x n x n

AND plane OR plane Pk

f 1 f m William Sandqvist [email protected] Programmable Logic Array (PLA) x1 x2 x3

Both AND and OR arrays are OR P1 plane programmable

AND plane f f William Sandqvist [email protected] Programmable Array Logic (PAL) x1 x2 x3

Only the AND array is programmable P1

f1 P2

f2 P4

AND plane

William Sandqvist [email protected] Register output In the earlier PLD circuits there were • combinatorial outputs • register outputs (output with a flip-flop) For each circuit there were a fixed number of combinational and register outputs To increase flexibility the macrocell where you could choose if an output would be a combinatorial or a register output was introduced.

William Sandqvist [email protected] Macrocels ia a PLD Select Enable

f 1 Flip-flop

D Q With a programmable multiplexer one can Clock select the type of output

To AND plane

William Sandqvist [email protected] PAL

William Sandqvist [email protected] Programing of PLDs

William Sandqvist [email protected] Complex PLDs (CPLD)

PLD were quite small (PALCE 22V10 had 10 flip-flops) For bigger programmable circuits a structure consisting of several PLD-like block was developed.

William Sandqvist [email protected] CPLD (MAX)

William Sandqvist [email protected] CPLD structure

I/O block

PAL-like PAL-like block block I/O block block I/O

Interconnection wires

I/O block

PAL-like PAL-like block block I/O block block I/O

William Sandqvist [email protected] Programing with JTAG

Modern CPLDs (and FPGAs) can be programmed by downloading programming information via a cable

Download will usually use a standard port: JTAG-port

William Sandqvist [email protected] JTAG programing You can program the chips when they are soldered to the circuit board - from inside the programmer you (a) CPLD in a Quad Flat Pack (QFP) package can select which chip you want to program with the To computer JTAG connector.

Pri nted ci rcui t board

(b) JTAG programming William Sandqvist [email protected] FPGA chips CPLD:s are based on the AND-OR array, and it becomes difficult to make really large circuits

FPGA (Field Programmable Gate Array) circuits using a different concept based on logical blocks

William Sandqvist [email protected] FPGA-structure

William Sandqvist [email protected] LUT-LookUp-Table

Programmable 0/1 A LUT with n 1 cells inputs can realize all combinational 0/1 0 functions with n 1 inputs. f The usual size in 0/1 0 1 an FPGA is n=4

0/1 0

x2 x1 Two-input LUT

William Sandqvist [email protected] Ex. LUT for XOR-gate

0 1 xxf21 1 0 110 1 011 f 0 1 1 101 000 0 0 x2 x1 Two-input LUT

William Sandqvist [email protected] Logic block in FPGA A logic block of an FPGA consists of a LUT, a flip- flop, and a mux to select register output.

Select

Out Flip-flop In 1 In 2 LUT D Q In 3 Clock

William Sandqvist [email protected] Interconnexion matrix in FPGA

x 3 f

• Blue cross: connection is x programmed 1

x 1 0 x 2 0 • Black cross: 0 1 f 1 f 2 x x 0 x 0 connection is not 2 2 1 3 0 programmed

f 1 0 1 f 1 f 2 1

William Sandqvist [email protected] DE2 University Board

Cyclone II EP2C35 FPGA – Datorteknik- course

William Sandqvist [email protected] Cyclone II logic element

William Sandqvist [email protected] Cyclone II Family

(3) Total Number of 18x18 Multipliers DE2

William Sandqvist [email protected] Stratix III Family

DE3 Board

William Sandqvist [email protected] Multiple processors on an FPGA

• Nios II is a so-called 'soft- processor' (32-bit) which can be implemented on an Nios II Altera FPGA • Today's FPGAs are so large that multiple Nios II processors can fit on a single FPGA chip

Very powerful multiprocessor systems can be created on an FPGA!

William Sandqvist [email protected] ASIC • An ASIC (Application Specific Integrated Circuit) is a circuit that is madi in a semiconductor factory • In a full custom integrated circuit you in principle tailors the whole circuit • In an ASIC have certain work steps already been made to reduce design time and cost

William Sandqvist [email protected] ASIC, gate array In an Gate Array the gates (or transistors) are allready on the silicon.

William Sandqvist [email protected] ASIC, gate array

f 1

One only creates x 1 links between inputs, gates, and outputs x 2

x 3

William Sandqvist [email protected] Comparison ASIC, FPGA

Initial Cost Cost per part Performance Fabrication Time

FPGA Low High Low Short

Gate Array (ASIC) Standard Cell High Low High Long (ASIC)

William Sandqvist [email protected] Design Trade-Offs

Design Time Full Custom

Standard Cell

Gate Array

Programmable Logic Microprocessor

Performance

William Sandqvist [email protected] William Sandqvist [email protected] Sekvenskretsar med VHDL

State

NEXT STATE OUTPUT DECODER STATE REGISTER DECODER Input- Output- signals signals

Clk

Moore-machine

William Sandqvist [email protected] Model a State Machine in VHDL

• In a Moore-machine we have three blocks – Next-state-decoder – Output-decoder – State-register • These blocks execute in parallel

William Sandqvist [email protected] Quickie Question … which logic gate corresponds to the following VHDL code

William Sandqvist [email protected] Processes in VHDL

• An architecture in VHDL can consist of several processes • Processes are executed in parallel • A process is written as a sequential program

William Sandqvist [email protected] Moore-machine processes

• For a Moore-machine, we can create three processes – Next-state-decoder – Output-decoder – State-register

William Sandqvist [email protected] Internal signals

• Moore-machine contains internal signals – Next state – Present state • Theese signals are declared in the architecture-description

William Sandqvist [email protected] The vending machine in VHDL We use bottle vending machine (system control) from last lecture as a concrete VHDL example

COIN COIN_PRESENT DROP DROP BOTTLE RECEIVER GT_1_EURO DROP_READY

EQ_1_EURO SYSTEM CONTROL LT_1_EURO

DEC_ACC RETURN_10_CENT ACCUMU- COIN RETURN LATOR CLR_ACC CHANGER_READY

William Sandqvist [email protected] Vending machine entity ENTITY Vending_Machine IS COIN_PRESENT DROP PORT ( GT_1_EURO DROP_READY -- Inputs coin_present : IN std_logic; EQ_1_EURO SYSTEM CONTROL gt_1_euro : IN std_logic; LT_1_EURO eq_1_euro : IN std_logic; lt_1_euro : IN std_logic; DEC_ACC RETURN_10_CENT drop_ready : IN std_logic; CLR_ACC CHANGER_READY changer_ready : IN std_logic; Reset_n reset_n : IN std_logic; clk : IN std_logic; Clk -- Outputs dec_acc : OUT std_logic; clr_acc : OUT std_logic; Clk and Reset (active low) is drop : OUT std_logic; also needed! return_10_cent : OUT std_logic); END Vending_Machine;

William Sandqvist [email protected] Vending machine architecture

• The architecture describes the function of the vending machine • We define – internal signals for present and next state – three processes for next-state- decoder, output-decoder and state- register

William Sandqvist [email protected] State diagram

(a) Wait for coin input (b) Register the coin (c) Coin is registered (3 cases)

(d) Drop bottle (e) Reset sum (f) Return 10 Cent (g) Decrement sum with 10 Cent

William Sandqvist [email protected] Internal signals • We need to create a data type for the internal signal • Since we describe the states we use an enumeration type with values a,b,c,d,e,f,g • We declare a variable for the current state (current_state) and one for next state (next_state)

ARCHITECTURE Moore_FSM OF Vending_Machine IS TYPE state_type IS (a, b, c, d, e, f, g); SIGNAL current_state, next_state : state_type; BEGIN -- Moore_FSM …

William Sandqvist [email protected] We want to keep our "clever” state encoding

• If we do not specify the encoding state then the synthesis tool chooses the coding. • We can force it to a specific encoding with attributes (NOTE Attributes are dependent on synthesis tool and thus not portable!)

ARCHITECTURE Moore_FSM OF Vending_Machine IS TYPE state_type IS (a, b, c, d, e, f, g); -- We can use state encoding according to BV 8.4.6 -- to enforce a particular encoding (for Quartus) ATTRIBUTE enum_encoding : string; ATTRIBUTE enum_encoding OF state_type : TYPE IS "000 001 011 110 111 100 101"; SIGNAL current_state, next_state : state_type; BEGIN -- Moore_FSM … William Sandqvist [email protected] Block schematic DA A COIN_PRESENT D LT_I_EURO Clk DROP EQ_I_EURO RETURN_I0_CENT GT_I_EURO DB B DROP_READY Next State D Output Decoder Clk Decoder CHANGER_READY CLR_ACC

DEC_ACC A DC C B D

C Clk

• Signals A,B,C describes present state

• Signals DA, DB, DC describes next state William Sandqvist [email protected] Quickie Question … which statemachine corresponds to the VHDL code

William Sandqvist [email protected] Quickie Question … which statemachine corresponds to the VHDL code

William Sandqvist [email protected] Next-State-Decoder

• Next-State-Decoder describes as a process • Sensitivity list contains all input signals that 'activates' the process

William Sandqvist [email protected] Next-State-Decoder

• Usually the sensitivity list contains all the inputs to the process

NEXTSTATE : PROCESS (current_state, coin_present, gt_1_euro, eq_1_euro, lt_1_euro, drop_ready, changer_ready) –- Sensitivity List BEGIN -- PROCESS NEXT_STATE …

William Sandqvist [email protected] Next-State-Decoder • We now use a CASE statement to describe for each state conditions for the transition from a state to the next state … CASE current_state IS WHEN a => IF coin_present = '1' THEN next_state <= b; ELSE next_state <= a; END IF; WHEN b => IF coin_present = '0' THEN next_state <= c; ELSE next_state <= b; END IF;

William Sandqvist [email protected] Next-State-Decoder • We can simplify the description, by specifying a default value for the next state … next_state <= current_state; CASE current_state IS WHEN a => IF coin_present = '1' THEN next_state <= b; END IF; WHEN b => IF coin_present = '0' THEN next_state <= c; END IF; … It is important that we specify all options for the next_state signal. Otherwise, we implicitly gets an expression next_state <= next_state which will genarate a latch!

William Sandqvist [email protected] Next-State-Decoder • We end the CASE statement with a WHEN OTHERS statement. Here we specify that we should go to a certain state (a) if we end up in a unspecified state

… WHEN g => next_state <= c; WHEN OTHERS => next_state <= a; END CASE; END PROCESS NEXTSTATE;

William Sandqvist [email protected] Output-decoder

• Output-decoder is described as a own process • Sensitivity list contains only the state as outputs only depend on the state

William Sandqvist [email protected] Output-decoder

OUTPUT : PROCESS (current_state) BEGIN -- PROCESS OUTPUT drop <= '0'; clr_acc <= '0'; dec_acc <= '0'; return_10_cent <= '0'; CASE current_state IS WHEN d => drop <= '1'; WHEN e => clr_acc <= '1'; WHEN f => return_10_cent <= '1'; WHEN g => dec_acc <= '1'; WHEN OTHERS => NULL; END CASE; END PROCESS OUTPUT;

William Sandqvist [email protected] State register • The State register is modeled as a synchronous process with asynchronous reset (active low)

CLOCK : PROCESS (clk, reset_n) BEGIN -- PROCESS CLOCK IF reset_n = '0' THEN -- asynchronous reset (active low) current_state <= a; ELSIF clk'event AND clk = '1' THEN -- rising clock edge current_state <= next_state; END IF; END PROCESS CLOCK;

William Sandqvist [email protected] Mealy-machine? • A Mealy machine can be modeled in the same way as the Moore machine • The difference is that output-decoder is also dependent on the input signals • Process modeling outputs also need to have the inputs in the sensitivity list!

William Sandqvist [email protected] More about VHDL • The sample code for bottle vending machine available on the course website • Look at the study material of "VHDL synthesis" on the course website • Both Brown/Vranesic- and the Hemert-book includes code samples

William Sandqvist [email protected] William Sandqvist [email protected] Laboratory - codelock

• Task: to write VHDL code for a code lock that opens with the code "the last four digits of your Social Security number”. • Hint: a VHDL "template" for a simplified code lock that opens with the code "number one".

William Sandqvist [email protected] Code lock – classic example! Moore – ”Gedanken Experiments” on Sequential Machines 1956

Code lock 0-1-0 That example is listed in Moore's classic essay from 1956.

William Sandqvist [email protected] Template-program

Power On/Off

Templat-program for a simplified code lock that opens for the code "1", a little bit too easy it seems ...!

William Sandqvist [email protected] Open the lock with your Social! • Now it's time to rewrite the VHDL code to open the lock for the last four digits of your social security number!

(If you are preparing code for your Social Security number, then two in a lab group contribute with one half each of the code in the lab). William Sandqvist [email protected] William Sandqvist [email protected]