LT5521 Very High Linearity Active Mixer

FEATURES DESCRIPTIO U ■ Wideband Output Frequency Range to 3.7GHz The LT®5521 is a very high linearity mixer optimized for ■ +24.2dBm IIP3 at 1.95GHz RF Output low distortion and low LO leakage applications. The chip ■ Low LO Leakage: –42dBm includes a high speed LO buffer with single-ended input ■ Integrated LO Buffer: Low LO Drive Level and a double-balanced active mixer. The LT5521 requires ■ Single-Ended LO Drive only –5dBm LO input power to achieve excellent distor- ■ Wide Single Supply Range: 3.15V to 5.25V tion and noise performance, while reducing external drive ■ Double-Balanced Active Mixer circuit requirements. The LO buffer is internally 50Ω ■ Shutdown Function matched for wideband operation.

■ 16-Lead (4mm × 4mm) QFN Package

With a 250MHz input, a 1.7GHz LO and a 1.95GHz output U frequency, the mixer has a typical IIP3 of +24.2dBm, APPLICATIO S –0.5dB conversion gain and a 12.5dB noise figure. ■ Cellular, W-CDMA, PHS and UMTS Infrastructure The LT5521 offers exceptional LO-RF isolation, greatly ■ Cable Downlink Infrastructure reducing the need for output filtering to meet LO suppres- ■ Wireless Infrastructure sion requirements. ■ Fixed Wireless Access Equipment The device is designed to work over a supply voltage range ■ High Linearity Mixer Applications from 3.15V to 5.25V. , LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATIO U

Fundamental, 3rd Order LO INPUT Intermodulation Distortion –5dBm vs Input Power 6.8pF 20 LO GND 0 Ω BPF 1nF 110 4:1 82pF PFUND IN+ OUT+ 2.7nH IF –20 INPUT 1:1 6.8pF BPF 10pF – – IN OUT RF –40 PA 2.7nH OUTPUT IM3 1nF 110Ω 82pF –60 BIAS 1nF fIF = 250MHz OUTPUT POWER (dBm) fLO = 1.7GHz EN VCC VCC VCC –80 f = 1.95GHz 5V DC RF PLO = –5dBm TA = 25°C 1µF –100 –14–12 –10 –8 –6 –4 –2 0 2 4 6 5521 TA01 PIN (dBm)

5521 TA02

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ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATIONU (Note 1)

Power Supply Voltage ...... 5.5V TOP VIEW ORDER PART Enable Voltage ...... –0.2V to VCC + 0.2V NUMBER GND LO GND GND LO Input Power ...... +10dBm 16 15 14 13 LT5521EUF LO Input DC Voltage ...... 0V to 1.5V GND 1 12 OUT+ IF Input Power ...... +10dBm IN+ 2 11 GND 17 Difference Voltage Across Output Pins ...... ±1.5V IN– 3 10 GND – Maximum Pin 2 or Pin 3 Current ...... 34mA GND 4 9 OUT 5 6 7 8 UF PART Operating Ambient Temperature Range .. – 40°C to 85°C CC CC CC

EN MARKING V V Storage Temperature Range ...... –65°C to 125°C V UF PACKAGE Maximum Junction Temperature ...... 125°C 16-LEAD (4mm × 4mm) PLASTIC QFN 5521

TJMAX = 125°C, θJA = 37°C/W EXPOSED PAD (PIN 17) IS GND MUST BE SOLDERED TO PCB

Consult LTC Marketing for parts specified with wider operating temperature ranges.

DC ELECTRICAL CHARACTERISTICS VCC = 5V, EN = 2.9V, TA = 25°C unless otherwise noted. Test circuit shown in Figure 1. (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS Supply Voltage 3.15 5.25 V Supply Current 82 98 mA Shutdown Current EN = 0.2V 20 100 µA Enable (EN) Low = Off, High = On Enable Mode EN = High 2.9 V Disable Mode EN = Low 0.2 V Enable Current EN = 5V 137 µA Shutdown Enable Current EN = 0.2V 0.1 µA Turn-On Time (Note 3) 200 ns Turn-Off Time (Note 4) 200 ns LO Voltage (Pin 15) Internally Biased 0.96 V

Input Voltage (Pins 2, 3) VCC = 5V, Internally Biased 2.20 V VCC = 3.3V, Internally Biased 0.46 V

AC ELECTRICAL CHARACTERISTICS VCC = 5V, EN = 2.9V, TA = 25°C unless otherwise noted. Test circuit shown in Figure 1. (Note 2) PARAMETER CONDITIONS MIN TYP MAX UNITS LO Frequency Range 10 to 4000 MHz Input Frequency Range 10 to 3000 MHz Output Frequency Range 10 to 3700 MHz LO Input Power –5 1 dBm

LO Return Loss ZO = 50Ω, fLO = 1700MHz 12 dB Output Return Loss Requires Matching 12 dB Input Return Loss (Pins 2, 3) Requires Matching 15 dB

5521f 2 LT5521

AC ELECTRICAL CHARACTERISTICS VCC = 5V, EN = 2.9V, fIF = 250MHz, PIF = –7dBm, fLO = 1700MHz, PLO = –5dBm, fRF = 1950MHz, TA = 25°C. Test circuit shown in Figure 1. PARAMETER CONDITIONS MIN TYP MAX UNITS Conversion Gain –0.5 dB Conversion Gain Variation vs Temperature –0.009 dB/°C Input P1dB +10 dBm Single-Side Band Noise Figure 12.5 dB

IIP3 Two Tones, ∆fIF = 5MHz, PIF = –7dBm/Tone +24.2 dBm

IIP2 (Note 6) Two Tones, ∆fIF = 5MHz, PIF = –7dBm/Tone, +49 dBm fLO + fIF1 + fIF2 LO-RF Leakage –42 dBm LO-IF Leakage –40 dBm

VCC = 5V, EN = 2.9V, fIF = 44MHz, PIF = –7dBm, fLO = 1001MHz, PLO = –5dBm, fRF = 1045MHz, TA = 25°C. PARAMETER CONDITIONS MIN TYP MAX UNITS Conversion Gain –0.5 dB Conversion Gain Variation vs Temperature –0.012 dB/°C Input P1dB +10 dBm Single-Side Band Noise Figure 12.8 dB

IIP3 Two Tones, ∆fIF = 5MHz, PIF = –7dBm/Tone +24.5 dBm

IIP2 (Note 6) Two Tones, ∆fIF = 5MHz, PIF = –7dBm/Tone, +49 dBm fLO + fIF1 + fIF2 LO-RF Leakage –38 dBm LO-IF Leakage –59 dBm

VCC = 3.3V, EN = 2.9V, fIF = 250MHz, PIF = –7dBm, fLO = 1700MHz, PLO = –5dBm, fRF = 1950MHz, TA = 25°C. (Note 5) PARAMETER CONDITIONS MIN TYP MAX UNITS Conversion Gain –0.5 dB Conversion Gain Variation vs Temperature –0.013 dB/°C Input P1dB +11 dBm Single-Side Band Noise Figure 13.5 dB

IIP3 Two Tones, ∆fIF = 5MHz, PIF = –7dBm/Tone +25.8 dBm

IIP2 (Note 6) Two Tones, ∆fIF = 5MHz, PIF = –7dBm/Tone, +50 dBm fLO + fIF1 + fIF2 LO-RF Leakage –36 dBm LO-IF Leakage –60 dBm

Note 1: Absolute Maximum Ratings are those values beyond which the life Note 4: Interval from the falling edge of the Enable signal to a 20dB drop of a device may be impaired. in the RF output power. Note 2: Specifications over the –40°C to 85°C temperature range are Note 5: R1 = R7 = 22.6Ω, Z1 = Z7 = 100nH. assured by design, characterization and correlation with statistical process Note 6: Second harmonic distortion measured at fLO + fIF1 + fIF2. controls. Note 3: Interval from the rising edge of the Enable input to the time when the RF output is within 1dB of its steady-state output.

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TYPICAL DC PERFOR AW CE CHARACTERISTICS Test circuit shown in Figure 1.

Supply Current vs Supply Voltage Supply Current vs Supply Voltage (5V Application) (3.3V Application) 100 110

95 100 85°C ° 90 85 C 90 85 25°C 25°C 80 (mA) (mA) 80 CC CC I I ° 75 –40 C 70 –40°C 70 60 65

60 50 4.7 4.8 4.95.0 5.1 5.2 5.3 3.1 3.2 3.3 3.4 3.5

VCC (V) VCC (V)

5521 G01 5521 G02 U

TYPICAL AC PERFOR AW CE CHARACTERISTICS fLO = 1700MHz, fIF = 250MHz, fRF = 1950MHz, PLO = –5dBm, VCC = 5V, EN = 2.9V, TA = 25°C, unless otherwise noted. Test circuit shown in Figure 1 is tuned for 1.95GHz output frequency and VCC = 5V.

Fundamental, 2nd and 3rd Order Intermodulation Distortion Conversion Gain and IIP3 vs Input Power Conversion Gain vs Input Power vs RF Frequency 20 1.0 10 25 85°C 25°C P ° FUND –40 C 8 24 0 –40°C 0.5 IIP3

IM3 0 6 23 –20 25°C IIP3 (dBm) –0.5 4 22 ° (dB) 85 C

–40 (dB) C C ° °

85 C G 25 C IM2 G –1.0 2 21 –40°C –60 GC –1.5 0 20 OUTPUT POWER (dBm) IM2 –80 –2.0 –2 19 IM3 –100 –2.5 –4 18 –14–12 –10 –8 –6 –4 –2 0 2 4 6 –25 –20–15–10 –5 05 10 15 1750 1850 19502050 2150 PIN (dBm) PIN (dBm) RFOUT (MHz)

5521 G03 5521 G04 5521 G05

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TYPICAL AC PERFOR A CE CHARACTERISTICS fLO = 1700MHz, fIF = 250MHz, fRF = 1950MHz, PLO = –5dBm, VCC = 5V, EN = 2.9V, TA = 25°C, unless otherwise noted. Test circuit shown in Figure 1 is tuned for 1.95GHz output frequency and VCC = 5V. Conversion Gain, IIP3 and Noise Conversion Gain and IIP3 LO-RF Leakage vs LO Frequency Figure vs Supply Voltage vs LO Power –36 10 30 10 25

IIP3 IIP3 (dBm) AND NOISE FIGURE (dB) –38 8 25 8 24 IIP3 –40°C ° 6 23 –40 6 85 C 20

25°C IIP3 (dBm) ° 85°C –40 C 4 22 85°C

–42 (dB) 4 15 NF (dB) C C 25°C G G 2 21 –40°C

LEAKAGE (dBm) –44 25°C 2 10 GC 0 20 GC –46 0 5 –2 19

–48 –2 0 –4 18 1500 15501600 1650 1700 1750 1800 1850 1900 4.6 4.74.8 4.9 5.0 5.1 5.2 5.3 5.4 –25 –20 –15 –10–5 0 510 LO FREQUENCY (MHz) VCC (V) LO POWER (dBm)

5521 G06 5521 G07 5521 G08

LO-RF Leakage vs LO Power LO-RF Leakage vs Supply Voltage Noise Figure vs LO Power –32 –34 20 19 –34 –36 –36 18 –38 17 –38 –40°C –40 –40°C 16 –40 85°C –42 85°C 15 –42 85°C 25°C –44 14 –44 25°C NOISE FIGURE (dB) LO LEAKAGE (dBm) LO LEAKAGE (dBm) 13 25°C –46 –40°C –46 12 –48 –48 11 –50 –50 10 –25 –20 –15 –10–5 05 10 4.7 4.8 4.95.0 5.1 5.2 5.3 –20 –15 –10 –5 0 5 LO POWER (dBm) VCC (V) LO POWER (dBm)

5521 G09 5521 G10 5521 G11

Low Side LO (LS) and High Side Low Side LO (LS) and High Side LO (HS) Comparison: Conversion LO (HS) Comparison: Noise Figure Gain and IIP3 vs RF Frequency vs RF Frequency 10 26 13.5 LS: R1 = R7 = 110Ω LS 13.3 HS: R1 = R7 = 121Ω 8 IIP3 24 f = 250MHz 13.1 IF HS 6 22 12.9

LS: R1 = R7 = 110Ω IIP3 (dBm) 12.7 4 HS: R1 = R7 = 121Ω 20 f = 250MHz (dB) IF 12.5 HS C

G 2 18 12.3 LS NOISE FIGURE (dB) 12.1 0 GC LS 16 HS 11.9 –2 14 11.7 –4 12 11.5 1750 1850 19502050 2150 1700 17501800 1850 1900 1950 2000 2050 2100 RFOUT (MHz) RFOUT (MHz)

5521 G13 5521 G14

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TYPICAL AC PERFOR A CE CHARACTERISTICS fLO = 1001MHz, fIF = 44MHz, fRF = 1045MHz, PLO = –5dBm, VCC = 5V, EN = 2.9V, TA = 25°C, unless otherwise noted. Test circuit shown in Figure 1 is tuned for 1.045GHz output frequency.

Fundamental, 2nd and 3rd Order Intermodulation Distortion Conversion Gain and IIP3 vs Input Power Conversion Gain vs Input Power vs RF Frequency, Fixed IF 20 1.0 10 25

0 PFUND 0.5 –40°C 8 24 IM3 IIP3 –20 0 6 23 25°C 85°C IIP3 (dBm) –40 –0.5 4 25°C 22 IM2 ° (dB) –40 C (dB) C C

G ° –60 IM2 –1.0 85 C G 2 21

GC –80 –1.5 0 20 OUTPUT POWER (dBm) IM3 85°C –100 –2.0 –2 19 25°C –40°C –120 –2.5 –4 18 –14 –12 –10 –8 –6 –4 –20 2 4 6 –25 –20–15–10 –5 05 10 15 920 970 1020 10701120 1170 INPUT POWER (dBm) PIN (dBm) RFOUT (MHz)

5521 G15 5521 G16 5521 G17

Conversion Gain, IIP3 and Noise Conversion Gain and IIP3 LO-RF Leakage vs LO Frequency Figure vs Supply Voltage vs LO Power –32 10 26 10 25

–33 IIP3 IIP3 (dBm) AND NOISE FIGURE (dB) IIP3 8 22 8 24 –34 85°C 6 23 –35 6 25°C 18

–40°C –40°C IIP3 (dBm) –36 85°C NF 4 22 25°C (dB) –37 4 14 (dB) C C –40°C G 25°C G 2 21 –38 G LEAKAGE (dBm) 2 10 C –39 0 20 GC –40 0 6 85°C –2 19 –41 –42 –2 2 –4 18 850 900 950 1000 1050 1100 1150 4.6 4.74.8 4.9 5.0 5.1 5.2 5.3 5.4 –25 –20 –15 –10–5 0 510 LO FREQUENCY (MHz) VCC (V) LO POWER (dBm)

5521 G18 5521 G19 5521 G20

LO-RF Leakage vs LO Power LO-RF Leakage vs Supply Voltage –30 –30

–32 –32

–34 –34 ° ° –40 C –36 –40 C –36 ° 25°C 25 C –38 ° –38 85 C LO LEAKAGE (dBm) LO LEAKAGE (dBm) ° 85 C –40

–40 –42

–42 –44 –25 –20 –15 –10–5 0 5 10 4.6 4.74.84.9 5.0 5.15.2 5.3 5.4 LO POWER (dBm) VCC (V)

5521 G21 5521 G22 5521f 6

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Low Side LO (LS) and High Side Low Side LO (LS) and High Side LO (HS) Comparison: Conversion LO (HS) Comparison: Noise Figure Noise Figure vs LO Power Gain and IIP3 vs RF Frequency vs RF Frequency 20 4 25 14.0 fIF = 44MHz fIF = 44MHz 19 LS 3 24 13.5 18 IIP3 HS 17 2 23 13.0 16 IIP3 (dBm) 85°C HS 15 (dB) 1 22 12.5 25°C C 14 G LS 12.0

NOISE FIGURE (dB) 0 21 13 G LS NOISE FIGURE (dB) –40°C C 12 HS –1 20 11.5 11

10 –2 19 11.0 –20 –15 –10 –5 0 5 940 990 1040 1090 1140 945 985 1025 1065 1105 1145 LO POWER (dBm) RFOUT (MHz) RFOUT (MHz)

5521 G23 5521 G34 5521 G24 fLO = 1.7GHz, fIF = 250MHz, fRF = 1.95GHz, PLO = –5dBm, VCC = 3.3V, EN = 2.9V, TA = 25°C, unless otherwise noted. Test circuit shown in Figure 1 is tuned for 1.95GHz output frequency and VCC = 3.3V.

Conversion Gain and IIP3 POUT, IM3 and IM2 vs Input Power Conversion Gain vs Input Power vs RF Frequency 20 0.5 10 27 –40°C 8 25 0 POUT 0 IIP3 IM3 6 23 –20 –0.5 25°C IIP3 (dBm) 4 85°C 21 ° (dB) –40 (dB) –1.0 25 C C C

G ° IM2 G 85°C 2 –40 C 19

–60 –1.5 GC 0 17

OUTPUT POWER (dBm) IM2 ° –80 85 C –2.0 –2 15 25°C IM3 –40°C –100 –2.5 –4 13 –14 –12 –10 –8 –6 –4 –20 2 4 6 –20 –15 –10 –5 0105 1750 180018501900 1950 20002050 2100 2150 PIN (dBm) PIN (dBm) RFOUT (MHz)

5521 G25 5521 G26 5521 G27

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TYPICAL AC PERFOR A CE CHARACTERISTICS fLO = 1.7GHz, fIF = 250MHz, fRF = 1.95GHz, PLO = –5dBm, VCC = 3.3V, EN = 2.9V, TA = 25°C, unless otherwise noted. Test circuit shown in Figure 1 is tuned for 1.95GHz output frequency and VCC = 3.3V. Conversion Gain, IIP3 and Noise Conversion Gain and IIP3 LO-RF Leakage vs LO Frequency Figure vs Supply Voltage vs LO Power –32 10 27 85°C

25°C 8 24 IIP3 (dBm) AND NOISE FIGURE (dB) –33 8 25 –40°C IIP3 IIP3 –34 6 20 6 23 85°C –35 25°C IIP3 (dBm) NF 4 ° –40°C 85 C 21 4 16 ° (dB) –36 (dB) 25 C C C ° G G 2 –40 C 19 –37 2 12 LEAKAGE (dBm) GC 0 17 –38 GC 0 8 –2 15 –39

–40 –2 4 –4 13 1500 1550 1600 1650 1700 1750 1800 1850 1900 3.10 3.153.20 3.25 3.30 3.35 3.40 3.45 3.50 –25 –20–15–10 –5 0 5 10 LO FREQUENCY (MHz) VCC (V) LO POWER (dBm)

5521 G28 5521 G31 5521 G29

LO-RF Leakage vs LO Power Noise Figure vs LO Power LO Leakage vs Supply Voltage –30 22 –20 –23 –32 20 85°C –26 –34 –29 18 85°C –32 25°C –36 –40°C 16 –35 ° ° –40 C –38 85 C –38 ° 25 C 14 NOISE FIGURE (dB) ° LO LEAKAGE (dBm) LO LEAKAGE (dBm) –40 25 C –41

° –44 –42 12 –40 C –47

–44 10 –50 –25 –20 –15 –10–5 0 5 10 –20 –15 –10 –5 0 5 3.0 3.1 3.2 3.3 3.4 3.5 3.6

LO POWER (dBm) LO POWER (dBm) VCC (V)

5521 G30 5521 G32 5521 G33 UU

PI U FU CTIO S

GND (Pins 1, 4, 10, 11, 13, 14, 16): Ground. These pins VCC (Pins 6, 7, 8): Power Supply Pins. Total current draw are internally connected to the Exposed Pad for improved for these three pins is 40mA. isolation. They should be connected to RF ground on the OUT+, OUT– (Pins 12, 9): RF Output Pins. These pins must printed circuit board, and are not intended to replace the have a DC connection to the supply voltage (see Applica- primary grounding through the backside of the package. tions Information). These pins draw 20mA each. External IN+, IN– (Pins 2, 3): Differential Input Pins. Each pin matching is required. requires a resistive DC path to ground. See Applications LO (Pin 15): Local Oscillator Input. This input is internally Information for choosing the resistor value. External match- DC biased to 0.96V. Input signal must be AC coupled. ing is required. Exposed Pad (Pin 17): Circuit Ground Return for the EN (Pin 5): Enable Input Pin. The enable voltage should be Entire IC. For best performance, this pin must be soldered at least 2.9V to turn the chip on and less than 0.2V to turn to the printed circuit board. the chip off. 5521f 8 LT5521

BLOCK DIAGRA W

17 16 15 14 13 EXPOSED GND LO GND GND PAD

GND OUT+ 1 12

IN+ GND 2 11

IN– GND 3 10

GND OUT– 4 9

BIAS

EN VCC VCC VCC 5 6 7 8 5521 BD

TEST CIRCUITS C1 RF 0.017" εr = 4.4 LOIN GND 50Ω 0.062" DC 0.017" Z1 GND OPT 16 15 14 13 GND L0 GND GND T2 C3 C2 R1 L1 1 12 RF Z3 GND OUT+ OUT IFIN T1 50Ω Ω 2 LT5521 11 50 IN+ GND C4 Z14 C13 3 10 IN– EXPOSED GND C12 4 PAD (17) 9 L2 GND OUT– C6 R7 EN VCC VCC VCC Z7 5 678 OPT R8 VCC C11

5521 F01 EN

Figure 1. Demonstration Board Schematic

Table 1. Demonstration Board Bill of Materials1, 2

fIF = 250MHz, fRF = 1.95GHz fIF = 44MHz, fRF = 1.045GHz fIF = 250MHz, fRF = 1.95GHz REF fLO = 1.7GHz, VCC = 5V fLO = 1.001GHz, VCC = 5V fLO = 1.7GHz, VCC = 3.3V R1, R7 110Ω, 1% 110Ω, 1% 22.6Ω, 1% Z14 10pF 120nH 10pF Z3 0Ω 150pF 0Ω L1, L2 2.7nH 10nH 2.7nH T1 M/A-COM MABACT00103 M/A-COM MABACT00103 M/A-COM MABACT00103 T2 M/A-COM ETC1.6-4-2-3 M/A-COM ETC1.6-4-2-3 M/A-COM ETC1.6-4-2-3 C1, C13 6.8pF 27pF 6.8pF C3 82pF 3.9pF 82pF C12 82pF 1nF 82pF C2, C4, C6 1nF 1nF 1nF C11 1µF 1µF 1µF Z1, Z7 0Ω 0Ω 100nH THIS COMPONENT CAN BE REPLACED BY PCB TRACE ON FINAL APPLICATION R8 10k 10k 10k Note 1: Tabulated values are used for characterization measurements. Note 2: Components shown on the schematic are included for consistency with the demo board. If no value is shown for the component, the site is unpopulated. Note 3: T1 also M/A-COM ETC1-1-13 and Sprague Goodman GLSW4M202. These alternative transformers have been measured and have similar performance. 5521f 9

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APPLICATIO S I FOR ATIOWU

The LT5521 is a high linearity double-balanced active 0 mixer. The chip consists of a double-balanced mixer core, –5 a high performance LO buffer and associated bias and enable circuitry. The chip is designed to operate with a –10 supply voltage ranging from 3.15V to 5.25V. –15 Table 2. Port Impedance –20 FREQUENCY DIFFERENTIAL DIFFERENTIAL SINGLE-ENDED –25

(MHz) INPUT OUTPUT LO IF RETURN LOSS (dB) –30 50 19.8 + j0.7 282.2 – j8.4 49.9 + j0.1 –35 100 20.1 + j2.0 282.3 – j20.8 49.8 + j0.3 –40 300 18.2 + j5.3 262.3 – j55.1 49.2 + j0.9 100 150 200250 300 350 400 600 15.2 + j16.8 231.4 – j67.0 47.7 + j2.0 FREQUENCY (MHz) 5521 F03 1000 14.5 + j28.1 215.0 – j124.5 45.3 + j2.8 Figure 3. IF Input Return Loss 1500 20.5 + j42.3 109.5 – j158.0 43.3 + j2.8 2000 48.2 + j26.8 52.9 – j92.1 43.0 + j3.3 For input frequencies above 100MHz, a broadband im- 2300 18.2 + j29.4 61.6 – j74.2 43.4 + j4.6 pedance matching tranformer with a 1:1 impedance ratio 3200 22.4 + j125.1 14.2 – j27.5 44.6 + j14.0 is recommended. Table 3 provides the component values 3500 27.9 – j4.4 42.4 + j17.9 necessary to match various IF frequencies using the M/A- 4000 42.8 – j16.0 38.6 + j22.8 COM CT0010 transformer (T1, Figure 1). Table 3. Component Values for Input Matching Using the Signal Input Interface M/A-COM CT0010 Figure 2 shows the signal inputs of the LT5521. The signal IF C2 Z14 Z3 input pins are connected to the common emitter nodes of 44MHz 1000pF 120nH 150pF the mixer quad differential pairs. The real part of the 95MHz 820pF 33pF 27nH differential IN+/IN– impedance is 20Ω. The mixer core 120MHz 1000pF 27pF 18nH current is set by external resistors R1 and R7. Setting their 150MHz 330pF 22pF 10nH values at 110Ω, the nominal DC voltage at the inputs is 170MHz 330pF 18pF 6.8nH 250MHz 82pF 10pF 0Ω 2.2V with VCC = 5V. Figure 3 shows the input return loss for a matched input at 250MHz. 300MHz 15pF 3.9pF 0Ω 435MHz 8.2pF 0.5pF 0Ω 520MHz 6.8pF Unused 0Ω Z1 OPT

LT5521 Below 100MHz, the Mini-Circuits TCM2-1T or the Pulse C2 R1 Z3 + IFIN IN CX2045 are better choices for a wider input match. This 50Ω T1 2 1:1 C13 configuration is shown in Figure 4. The series 1nF capaci- tors maintain differential symmetry while providing DC Z14 VCC isolation between the inputs. This helps to improve LO IN– 3 suppression. C6 R7 1nF Shunt capacitor C13 (Figure 2) is an optional capacitor

5521 F02 Z7 across the input pins that significantly improves LO sup- OPT pression. Although this capacitor is optional, it is important to regulate LO suppression, mitigating part-to-part Figure 2. Signal Input with External Matching variation. This capacitor should be optimized depending 5521f 10

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APPLICATIO S I FOR ATIOWU Operation at Reduced Supply Voltage LT5521 C2 1nF R1 IF IN+ IN T1 External resistors R1 and R7 (Figure 2) set the current 50Ω 2 2:1 through the mixer core. For best distortion performance, these resistors should be chosen to maintain a total of C13 VCC 1nF 40mA through the mixer core (20mA per side). At 5V IN– Ω 3 supply, R1 and R7 should be 110 . Table 5 shows R7 recommended values for R1 and R7 at various supply

5521 F04 voltages. Caution: Using values below the recommended resistance can adversely affect operation or damage the Figure 4. Low Frequency Signal Input part. Table 5. Minimum External Resistor Values vs Supply Voltage on the IF input frequency and the LO frequency. Smaller V (V) R1, R7 (Ω) C13 values have reduced impact on the LO output sup- CC 5 110 pression; larger values will degrade the conversion gain. 4.5 82.5 A single-ended 50Ω source can also be matched to the 4 54.9 differential signal inputs of the LT5521 without an input 3.5 38.3 transformer. Figure 5 shows an example topology for a 3.3 23.2 discrete balun, and Table 4 lists component values for several frequencies. The discrete input match is intrinsi- Excessive mismatch between the external resistors R1 cally narrowband. LO suppression to the output is de- and R7 will degrade performance, particularly LO sup- graded and noise figure degrades by 4dB for input pression. Resistors with 1% mismatch are recommended frequencies greater than 200MHz. Noise figure degrada- for optimum performance. tion is worse at lower input frequencies. Figure 2 shows RF chokes in series with R1 and R7. These inductors are optional. In general, the chokes improve the conversion gain and noise figure by 2dB at 3.3V (i.e., at the R1 C16 110Ω LT5521 minimum values of R1 and R7). The DC resistance varia- L4 C2 tion of the RF chokes must be considered in the 1% source IN+ 82pF 2 resistance mismatch suggested for maintaining LO sup- IFIN 50Ω C13 C14 IN– pression performance. 3 Figure 6 indicates the typical performance of the LT5521 R7 L3 Ω as the external source resistance (R1, R7) is varied while 110 5521 F05 keeping the supply current constant. Figure 6 data was 1nF taken without the benefit of input chokes, and shows the gradual gain degradation for smaller values of the input Figure 5. Alternative Transformerless Input Circuit resistors R1 and R7. Figure 7 shows the typical behavior Using Low Cost Discrete Components when the supply voltage is fixed and the core current is varied by adjusting values of the external resistors R1 and Table 4. Component Values for Discrete Bridge Balun Signal R7. Decreasing the core current decreases the power Input Matching consumption and improves noise figure but degrades IF (MHz) C14, C16 (pF) L3, L4 (nH) distortion performance. Figure␣ 8 demonstrates the im- 220 22 22 pact of the RF chokes in series with the source resistance 250 18 18 at 3.3V. There is a 2dB improvement in conversion gain 640 4.7 4.7 and noise figure and a corresponding decrease in IIP3.

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APPLICATIO S I FOR ATIOWU 3.5 30 The user can tailor the biasing of the LT5521 to meet

IIP3 IIP3 (dBm) AND NOISE FIGURE (dB) individual system requirements. It is recommended to 2.5 25 TA = 25°C choose a source resistance as large as possible to mini- f = 250MHz 1.5 IF 20 fLO = 1.7GHz mize sensitivity to power supply variation. fRF = 1.95GHz 0.5 15 NF Output Interface

–0.5 10 A DC connection to VCC must be provided on the PCB to the CONVERSION GAIN (dB) GC output pins. These pins will draw approximately 20mA –1.5 5 each from the power supply. On-chip, there is a nominal –2.5 0 300Ω differential resistance between the output pins. 0 20 40 6080 100 120 140 R1 AND R7 (Ω) Figure 9 shows a typical matching circuit using an external 5521 F06 balun to provide differential to single-ended conversion.

Figure 6. IIP3, GC and Noise Figure vs External Resistance, LO suppression and 2xLO suppression are influenced by Constant Core Current (Variable Supply Voltage) the symmetry of the external output matching circuitry.

1.8 30 PCB design must maintain the trace layout symmetry of TA = 25°C fIF = 250MHz IIP3 (dBm) AND NOISE FIGURE (dB) the output pins as much as possible to minimize these 1.2 fLO = 1.7GHz 25 signals. fRF = 1.95GHz IIP3 VCC = 4V 0.6 20 The M/A-COM ETC1.6-4-2-3 4:1 transformer (T2, Fig- ure␣ 9) is suitable for applications with output frequencies 0 15 between 500MHz and 2700MHz. Output matching at vari- NF –0.6 10 ous frequencies is achieved by adding inductors in series

CONVERSION GAIN (dB) with the output (L1, L2) and DC blocking capacitor C3, as –1.2 GC 5 shown in Figure 9. Table 6 specifies center frequency and

–1.8 0 bandwidth of the output match for different matching 15 20 25 30 35 40 45 CORE CURRENT (mA) configurations. Figure 10 shows the typical output return

5521 F07 loss vs frequency for 1GHz and 2GHz applications. Capaci- tor C12 provides a solid AC ground at the RF output Figure 7. IIP3, GC and Noise Figure vs Core Current, Constant Supply Voltage frequency.

9 30 IIP3 IIP3 (dBm) AND NOISE FIGURE (dB) LT5521 7 25 RFC + L1 ° OUT TA = 25 C fRF = 1.95GHz 12 T2 5 fIF = 250MHz VCC = 3.3V 20 4:1 C3 fLO = 1.7GHz NF OUT 3 15 RFC 300Ω V VCC CC 1 10

CONVERSION GAIN (dB) GC RFC –1 5 – L2 OUT C12 9 –3 0 5521 F09 25 30 35 40 45 50 55 CORE CURRENT (mA)

5521 F08 Figure 8. Comparison of 3.3V Performance With Figure 9. Simplified Output Circuit and Without Input RF Choke with External Matching Components

5521f 12

LT5521 UU

APPLICATIO S I FOR ATIOWU Table 6. Matching Values Using M/A-COM ETC1.6-4-2-3 Johanson Technology supplies the 3700BL15B100S hy- Output Transformer brid balun for use between 3.4GHz and 4GHz. With addi- ∆ fOUT L1, L2 C3 C12 f (10dB RL) tional matching, this transformer can be used for 2.4GHz 0nH 82pF 82pF 450MHz applications between 3.3GHz and 3.7GHz. Example LT5521 2.2GHz 1nH 82pF 82pF 430MHz performance is shown in Figure 11. 2.0GHz 2.7nH 82pF 82pF 400MHz 1.7GHz 4.7nH 82pF 82pF 400MHz 10 22

LS IIP3 (dBm) AND NOISE FIGURE (dB) 1.3GHz 10nH 82pF 82pF 400MHz 8 20 HS 1.0GHz 10nH 3.9pF 1nF 500MHz IIP3 6 18 TA = 25°C 5 f = 300MHz 4 IF 16 HS NF 0 1GHz 2 14 2GHz LS –5 0 12 CONVERSION GAIN (dB) –10 GC –2 LS 10

–15 HS –4 8 3.2 3.3 3.4 3.53.6 3.7 3.8 RETURN LOSS (dB) –20 FREQUENCY (GHz)

5521 F11 –25 Figure 11. LT5521 Performance for an Application Tuned to –30 3.5GHz with Low Side (LS) and High Side (HS) LO Injection 0.7 1.2 1.7 2.2 FREQUENCY (GHz)

5521 F10 LO Interface Figure 10. Output Return Loss vs Frequency The LO input pin is internally matched to 50Ω. It has an internal DC bias of 960mV. External AC coupling is re- For applications with LO and output frequencies below quired. Figure 12 shows a simplified schematic of the LO 1GHz, the M/A-COM MABAES0054 is recommended for input. Overdriving the LO input will dramatically reduce the output component T2. This transformer maintains the performance of the mixer. The LO input power should better low frequency output symmetry. Table 7 lists com- not exceed +1dBm for normal operation. Select C1 (Figure ponents necessary for a 750MHz output match using the 12) only large enough to achieve the desired LO input M/A-COM MABAES0054. return loss. This reduces external low frequency signal Table 7. Matching Values Using M/A-COM MABAES0054 amplification through the LO buffer. Output Transformer For applications with LO frequency in the range of 2.1GHz fOUT L1, L2 C3 C12 ∆f (10dB RL) to 2.4GHz, the LT5521 achieves improved distortion and 750MHz 33nH 82pF 1nF 500MHz

Hybrid baluns provide a low cost alternative for differen- LT5521 tial to single-ended conversion. The critical performance parameters of conversion gain, IIP3, noise figure and LO VCC 60Ω suppression are largely unaffected by these transform- C1 8Ω ers. However, their limited bandwidth and reduced sym- LO IN 15 metry outside the frequency of operation degrades the 50Ω suppression of higher order LO harmonics, particularly 60Ω 2xLO. Murata LBD21 series hybrid balun transformers, for example, can be used for output frequencies as low as 5521 F12 840MHz and as high as 2.4GHz. Figure 12. Simplified LO Input Circuit 5521f 13

LT5521 UU

APPLICATIO S I FOR ATIOWU 0 0Ω resistor. If the shutdown function is not required, then –5 the EN pin should be wired directly to the VCC power supply on the PCB. –10 C1 = 6.8pF –15 Supply Decoupling –20 C1 = 2.7pF The power supply decoupling shown in the schematic of RETURN LOSS (dB) –25 Figure 1 is recommended to minimize spurious signal –30 coupling into the output through the power supply.

–35 0 50010001500 2000 25003000 3500 4000 ACPR Performance FREQUENCY (MHz) 5521 F13 Because of its high linearity and low noise, the LT5521 offers Figure 13. LO Port Return Loss outstanding ACPR performance in a variety of applications. For example, Figures 15 and 16 show ACPR and Alternate noise performance with slightly reduced current through Channel measurements for single channel and 4-channel the mixer core. Accordingly, in a 5V application operating 64 DPCH W-CDMA signals at 1.95GHz output frequency. within this LO frequency range, the recommended source Ω –30 –130 resistor value (R1 and R7) is increased to 121 . TA = 25°C fRF = 1.95GHz –40 –135 fIF = 70MHz

Enable Interface fLO = 1.88GHz NOISE FLOOR (dBm/Hz) –50 –140 Figure 14 shows a simplified schematic of the EN pin –60 –145 interface. The voltage necessary to turn on the LT5521 is ACPR –70 –150 2.9V. To disable the chip, the enable voltage must be below ACPR 0.2V. If the EN pin is not connected, the chip is disabled. –80 –155

It is not recommended, however, that any pins be left –90 –160 30MHz OFFSET NOISE floating for normal operation. –100 –165 –40 –30 –20 –100 10 It is important that the voltage at the EN pin never exceed OUTPUT CHANNEL POWER (dBm) VCC, the power supply voltage, by more than 0.2V. If this 5521 F15 should occur, the supply current could be sourced through Figure 15. Single Channel W-CDMA ACPR the EN pin ESD protection diodes, potentially damaging and 30MHz Offset Noise Performance the IC. The resistor R8 (Figure 1) in series with the EN pin on the demo board is populated with a 10kΩ resistor to –50 –135 protect the EN pin to avoid inadvertant damage to the IC. –55 –140 For timing measurements, this resistor is replaced with a NOISE FLOOR (dBm/Hz) –60 –145 ACPR LT5521 –65 –150 TA = 25°C f = 1.95GHz AltCPR –70 RF –155 fIF = 70MHz ACPR AND AltCPR (dB) fLO = 1.88GHz –75 –160 VCC 30MHz OFFSET NOISE –80 –165 –40 –35 –30 –25 –20 –15 OUTPUT CHANNEL POWER, EACH CHANNEL (dBm)

1635 G24 EN 5 5521 F14 Figure 16. 4-Channel W-CDMA ACPR, AltCPR and 30MHz Offset Noise Floor Figure 14. Enable Input Circuit 5521f 14

LT5521 UU

APPLICATIO S I FOR ATIOWU

Figure 17. Top View of Demo Board

PACKAGE DESCRIPTIO U

UF Package 16-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1692)

BOTTOM VIEW—EXPOSED PAD ± 4.00 ± 0.10 0.75 0.05 R = 0.115 0.55 ± 0.20 TYP (4 SIDES) 15 16 0.72 ±0.05 PIN 1 TOP MARK (NOTE 6) 1

2 4.35 ± 0.05 2.15 ± 0.05 2.15 ± 0.10 (4 SIDES) (4-SIDES) 2.90 ± 0.05

PACKAGE OUTLINE (UF) QFN 1103 ± 0.30 ±0.05 0.200 REF 0.30 0.05 0.65 BSC 0.00 – 0.05 0.65 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

5521f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LT5521

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5521f Linear Technology Corporation LT/TP 0604 1K • PRINTED IN THE USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 16 ● ● (408) 432-1900 FAX: (408) 434-0507 www.linear.com  LINEAR TECHNOLOGY CORPORATION 2004