Low-Noise, High-Voltage, Current-Feedback Op Amplifiers

THS3110 THS3111 www.ti.com...... SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009 LOW-NOISE, HIGH-VOLTAGE, CURRENT-FEEDBACK OPERATIONAL AMPLIFIERS Check for Samples: THS3110 THS3111

1FEATURES DESCRIPTION

23• Low Noise The THS3110 and THS3111 are low-noise, – 2-pA/√Hz Noninverting Current Noise high-voltage, current-feedback amplifiers designed to – 10-pA/√Hz Inverting Current Noise operate over a wide supply range of ±5 V to ±15 V for today's high performance applications. – 3-nV/√Hz Voltage Noise • High Output Current Drive: 260 mA The THS3110 features a power-down pin (PD) that puts the amplifier in low-power standby mode, and • High Slew Rate: 1300 V/μs lowers the quiescent current from 4.8 mA to 270 μA. – (R = 100 Ω, V = 8 V ) L O PP These amplifiers provide well-regulated ac • Wide Bandwidth: 90 MHz (G = 2, RL = 100 Ω) performance characteristics. The unity-gain • Wide Supply Range: ±5 V to ±15 V bandwidth of 100 MHz allows for good distortion • Power-Down Feature: (THS3110 Only) characteristics below 10 MHz. Coupled with a high 1300-V/μs slew rate, the THS3110 and THS3111 amplifiers allow for high output voltage swings at high APPLICATIONS frequencies. • Video Distribution The THS3110 and THS3111 are offered in the • Power FET Driver SOIC-8 (D) and the MSOP-8 (DGN) packages with • Pin Driver PowerPAD™. • Capacitive Load Driver space space

DIFFERENTIAL GAIN DIFFERENTIAL PHASE vs vs NUMBER OF LOADS NUMBER OF LOADS 0.3 0.4 Gain = 2, Gain = 2, VIDEO DISTRIBUTION AMPLIFIER APPLICATION Ω RF = 1 kΩ, RF = 1 k , 0.35 V = ±15 V, Ω Ω 0.25 VS = ±15 V, S 1 k 1 k 40 IRE − NTSC and PAL, 40 IRE − NTSC and PAL, Worst Case ±100 IRE Ramp Worst Case ±100 IRE Ramp 0.3 Ω 5 15 V 75- Transmission Line 0.2 VO(1) 0.25 PAL − PAL V + 0.15 0.2 I 75 Ω NTSC −15 V 75 Ω NTSC 0.15 n Lines 0.1 75 Ω Differential Gain − % 0.1 Differential Phase − 75 Ω VO(n) 0.05 0.05

0 0 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 75 Ω Number of 150 Ω Loads Number of 150 Ω Loads

1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 2003–2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. THS3110 THS3111

SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009...... www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

TOPVIEW D,DGN TOPVIEW D,DGN

THS3110 THS3111

REF 1 8 PD NC 1 8 NC VIN− 2 7 VS+ VIN − 2 7 VS+ VIN+ 3 6 VOUT VIN + 3 6 VOUT VS− 4 5 NC VS− 4 5 NC

NC=NoInternalConnection NC =NoInternalConnection

NOTE:Thedevicewiththepower-downoptiondefaultstotheONstateifnosignalisappliedtothePDpin.Additionally,theREFpin - functionalrangeisfromVS- to(V S+ 4V).

AVAILABLE OPTIONS(1) PACKAGED DEVICE TA PLASTIC SMALL OUTLINE SOIC (D) PLASTIC MSOP (DGN) (2) SYMBOL THS3110CD THS3110CDGN 0°C to +70°C BJB THS3110CDR THS3110CDGNR THS3110ID THS3110IDGN –40°C to +85°C BIR THS3110IDR THS3110IDGNR THS3111CD THS3111CDGN 0°C to +70°C BJA THS3111CDR THS3111CDGNR THS3111ID THS3111IDGN –40°C to +85°C BIS THS3111IDR THS3111IDGNR

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. (2) The PowerPAD is electrically isolated from all other pins.

DISSIPATION RATINGS TABLE POWER RATING T = +125°C PACKAGE θJC (°C/W) θJA (°C/W) J TA = +25°C TA = +85°C D-8(1) 38.3 95 1.05 W 421 mW DGN-8(2) 4.7 58.4 1.71 W 685 mW

(1) These data were taken using the JEDEC standard low-K test PCB. For the JEDEC proposed high-K test PCB, the θJA is 95°C/W with power rating at TA = +25°C of 1.05 W. (2) These data were taken using 2 oz. trace and copper pad that is soldered directly to a 3 inch × 3 inch (76,2 mm × 76,2 mm) PCB. For further information, refer to the Application Information section of this data sheet.

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RECOMMENDED OPERATING CONDITIONS MIN NOM MAX UNIT Dual supply ±5 ±15 Supply voltage V Single supply 10 30 Commercial 0 +70 Operating free-air temperature, TA Industrial –40 +85 °C Operating junction temperature, continuous operating temperature, TJ –40 +125

Normal storage temperature, TSTG –40 +85

ABSOLUTE MAXIMUM RATINGS(1) Over operating free-air temperature, unless otherwise noted. UNIT

Supply voltage, VS– to VS+ 33 V

Input voltage, VI ± VS

Differential input voltage, VID ± 4 V (2) Output current, IO 300 mA Continuous power dissipation See Dissipation Ratings Table (3) Maximum junction temperature, TJ +150°C (4) Maximum junction temperature, continuous operation, long term reliability, TJ +125°C Commercial 0°C to +70°C Operating free-air temperature, TA Industrial –40°C to +85°C

Storage temperature, Tstg –65°C to +125°C ESD ratings: HBM 900 CDM 1500 MM 200

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The THS3110 and THS3111 may incorporate a PowerPAD on the underside of the chip. This feature acts as a heatsink and must be connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the PowerPAD™ thermally-enhanced package. (3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process. (4) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device.

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ELECTRICAL CHARACTERISTICS

VS = ±15 V, RF = 1 k Ω,RL = 100 Ω, and G = 2, unless otherwise noted. TYP OVER TEMPERATURE MIN/TYP/ PARAMETER TEST CONDITIONS 0°C to –40°C to UNIT +25°C +25°C MAX +70°C +85°C AC PERFORMANCE

G = 1, RF = 1.5 kΩ, VO = 200 mVPP 100

G = 2, RF = 1 kΩ, VO = 200 mVPP 90 Small-signal bandwidth, –3 dB G = 5, RF = 806 Ω, VO = 200 mVPP 87 MHz TYP G = 10, RF = 604 Ω, VO = 200 mVPP 66

0.1-dB bandwidth flatness G = 2, RF = 1.15 kΩ, VO = 200 mVPP 45

Large-signal bandwidth G = 5, RF = 806 Ω , VO = 4 VPP 95

G = 1, VO = 4-V step, RF = 1.5 kΩ 800 Slew rate (25% to 75% level) V/μs TYP G = 2, VO = 8-V step, RF = 1 kΩ 1300 Recommended maximum SR for Slew rate 900 V/μs MAX repetitive signals(1)

Rise and fall time G = –5, VO = 10-V step, RF = 806 Ω 8 ns TYP

Settling time to 0.1% G = –2, VO = 2 VPP step 27 ns TYP Settling time to 0.01% G = –2, VO = 2 VPP step 250 Harmonic distortion

RL = 100 Ω 52 2nd harmonic distortion G = 2, R = 1 kΩ, RL = 1 kΩ 53 F dBc TYP V = 2 V , O PP RL = 100 Ω 48 3rd harmonic distortion f = 10 MHz RL = 1 kΩ 68 Input voltage noise f > 20 kHz 3 nV/√Hz TYP Noninverting input current noise f > 20 kHz 2 pA/√Hz TYP Inverting input current noise f > 20 kHz 10 pA/√Hz TYP NTSC 0.011% Differential gain G = 2, PAL 0.013% RL = 150 Ω, TYP R = 1 kΩ NTSC 0.029° Differential phase F PAL 0.033° DC PERFORMANCE

Transimpedance VO = ±3.75 V, gain = 1 1 0.75 0.5 0.5 MΩ MIN Input offset voltage 3 10 12 12 mV MAX VCM = 0 V Average offset voltage drift ±10 ±10 μV/°C TYP Noninverting input bias current 1 4 6 6 μA MAX VCM = 0 V Average bias current drift ±10 ±10 nA/°C TYP Inverting input bias current 1.5 15 20 20 μA MAX VCM = 0 V Average bias current drift ±10 ±10 nA/°C TYP Input offset current 2.5 15 20 20 μA MAX VCM = 0 V Average offset current drift ±30 ±30 nA/°C TYP INPUT CHARACTERISTICS Input common-mode voltage range ±13.3 ±13 ±12.5 ±12.5 V MIN

Common-mode rejection ratio VCM = ±12.5 V 68 62 60 60 dB MIN Noninverting input resistance 41 MΩ TYP Noninverting input capacitance 0.4 pF TYP OUTPUT CHARACTERISTICS

RL = 1 kΩ ±13.5 ±13 ±12.5 ±12.5 Output voltage swing V MIN RL = 100 Ω ±13.4 ±12.5 ±12 ±12

Output current (sourcing) RL = 25 Ω 260 200 175 175 mA MIN

Output current (sinking) RL = 25 Ω 260 200 175 175 mA MIN Output impedance f = 1 MHz, closed loop 0.15 Ω TYP

(1) For more information, see the Application Information section of this data sheet.

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ELECTRICAL CHARACTERISTICS (continued)

VS = ±15 V, RF = 1 k Ω,RL = 100 Ω, and G = 2, unless otherwise noted. TYP OVER TEMPERATURE MIN/TYP/ PARAMETER TEST CONDITIONS 0°C to –40°C to UNIT +25°C +25°C MAX +70°C +85°C POWER SUPPLY Specified operating voltage ±15 ±16 ±16 ±16 V MAX Maximum quiescent current 4.8 6.5 7.5 7.5 mA MAX Minimum quiescent current 4.8 3.8 2.5 2.5 mA MIN

Power-supply rejection (+PSRR) VS+ = 15.5 V to 14.5 V, VS– = 15 V 75 65 60 60 dB MIN

Power-supply rejection (–PSRR) VS+ = 15 V, VS– = –15.5 V to –14.5 V 69 60 55 55 dB MIN POWER-DOWN CHARACTERISTICS (THS3110 Only)

VS+– 4 V MAX REF voltage range (2) VS– V MIN PD ≤ Enable V MIN REF+ 0.8 Power-down voltage level(2) PD ≥ REF Disable V MAX + 2 Power-down quiescent current PD ≥ REF + 2 V 270 450 500 500 μA MAX

VPD = 0 V, REF = 0 V, 11 PD pin bias current μA TYP VPD = 3.3 V, REF = 0 V 11 Turn-on time delay 90% of final value 4 μs TYP Turn-off time delay 10% of final value 6 Input impedance 3.4 || 1.7 kΩ || pF TYP

(2) For detailed information on the behavior of the power-down circuit, see the Saving Power with Power-Down Functionality and Power-Down Reference Pin Operation sections in the Application Information section of this data sheet.

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ELECTRICAL CHARACTERISTICS

VS = ±5 V, RF = 1.15 Ω, RL = 100 Ω, and G = 2, unless otherwise noted. TYP OVER TEMPERATURE MIN/TYP/ PARAMETER TEST CONDITIONS 0°C to –40°C to UNIT +25°C +25°C MAX +70°C +85°C AC PERFORMANCE

G = 1, RF = 1.5 kΩ, VO = 200 mVPP 85

G = 2, RF = 1.15 kΩ, VO = 200 mVPP 78 Small-signal bandwidth, –3 dB G = 5, RF = 806 Ω, VO = 200 mVPP 80 MHz TYP G = 10, RF = 604 Ω, VO = 200 mVPP 60

0.1-dB bandwidth flatness G = 2, RF = 1.15 kΩ, VO = 200 mVPP 15

Large-signal bandwidth G = 5, RF = 806 Ω, VO = 4 VPP 80

G = 1, VO = 4-V step, RF = 1.5 kΩ 640 Slew rate (25% to 75% level) V/μs TYP G = 2, VO = 4-V step, RF = 1 kΩ 700 Recommended maximum SR for Slew rate 900 V/μs MAX repetitive signals(1)

Rise and fall time G = –5, VO = 5-V step, RF = 806 Ω 7 ns TYP

Settling time to 0.1% G = –2, VO = 2 VPP step 20 ns TYP Settling time to 0.01% G = –2, VO = 2 VPP step 200 Harmonic distortion

RL = 100 Ω 55 2nd harmonic distortion G = 2, R = 1 kΩ, RL = 1 kΩ 56 F dBc TYP V = 2 V , O PP RL = 100 Ω 45 3rd harmonic distortion f = 10 MHz RL = 1 kΩ 62 Input voltage noise f > 20 kHz 3 nV/√Hz TYP Noninverting input current noise f > 20 kHz 2 pA/√Hz TYP Inverting input current noise f > 20 kHz 10 pA/√Hz TYP NTSC 0.011% Differential gain G = 2, PAL 0.015% RL = 150 Ω, TYP R = 1 kΩ NTSC 0.020° Differential phase F PAL 0.033° DC PERFORMANCE

Transimpedance VO = ±1.25 V, gain = 1 1 0.75 0.5 0.5 MΩ MIN Input offset voltage 6 10 12 12 mV MAX VCM = 0 V Average offset voltage drift ±10 ±10 μV/°C TYP Noninverting input bias current 1 4 6 6 μA MAX VCM = 0 V Average bias current drift ±10 ±10 nA/°C TYP Inverting input bias current 1 8 10 10 μA MAX VCM = 0 V Average bias current drift ±10 ±10 nA/°C TYP Input offset current 1 6 8 8 μA MAX VCM = 0 V Average offset current drift ±20 ±20 nA/°C TYP INPUT CHARACTERISTICS Input common-mode voltage range ±3.2 ±2.9 ±2.8 ±2.8 V MIN

Common-mode rejection ratio VCM = ±2.5 V 65 62 58 58 dB MIN Noninverting input resistance 35 MΩ TYP Noninverting input capacitance 0.5 pF TYP OUTPUT CHARACTERISTICS

RL = 1 kΩ ±4 ±3.8 ±3.6 ±3.6 Output voltage swing V MIN RL = 100 Ω ±3.8 ±3.7 ±3.5 ±3.5

Output current (sourcing) RL = 10 Ω 220 150 125 125 mA MIN

Output current (sinking) RL = 10 Ω 220 150 125 125 mA MIN Output impedance f = 1 MHz, closed loop 0.15 Ω TYP

(1) For more information, see the Application Information section of this data sheet.

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ELECTRICAL CHARACTERISTICS (continued)

VS = ±5 V, RF = 1.15 Ω, RL = 100 Ω, and G = 2, unless otherwise noted. TYP OVER TEMPERATURE MIN/TYP/ PARAMETER TEST CONDITIONS 0°C to –40°C to UNIT +25°C +25°C MAX +70°C +85°C POWER SUPPLY Specified operating voltage ±5 ±4.5 ±4.5 ±4.5 V MIN Maximum quiescent current 4 6 7 7 mA MAX Minimum quiescent current 4 3.2 2 2 mA MIN

Power-supply rejection (+PSRR) VS+ = 5.5 V to 4.5 V, VS– = 5 V 71 62 57 57 dB MIN

Power-supply rejection (–PSRR) VS+ = 5 V, VS– = –5.5 V to –4.5 V 66 57 52 52 dB MIN POWER-DOWN CHARACTERISTICS (THS3110 Only)

VS+ –4 V MAX REF voltage range(2) VS– V MIN PD ≤ REF Enable V MIN + 0.8 Power-down voltage level(2) PD ≥ REF Disable V MAX + 2 Power-down quiescent current PD ≥ REF + 2 V 200 450 500 500 μA MAX

(2) For detailed information on the behavior of the power-down circuit, see the Power-Down and Power-down Reference sections in the Application Information section of this data sheet.

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TYPICAL CHARACTERISTICS

TABLE OF GRAPHS

FIGURE ±15-V Graphs Noninverting small-signal gain frequency response 1, 2 Inverting small-signal gain frequency response 3 0.1-dB flatness 4 Noninverting large-signal gain frequency response 5 Inverting large-signal gain frequency response 6 Frequency response capacitive load 7

Recommended RISO vs Capacitive load 8 2nd harmonic distortion vs Frequency 9 3rd harmonic distortion vs Frequency 10 Harmonic distortion vs Output voltage swing 11, 12 Slew rate vs Output voltage step 13, 14, 15, 16 Noise vs Frequency 17 Settling time 18, 19 Quiescent current vs Supply voltage 20 Output voltage vs Load resistance 21 Input bias and offset current vs Case temperature 22 Input offset voltage vs Case temperature 23 Transimpedance vs Frequency 24 Rejection ratio vs Frequency 25 Noninverting small-signal transient response 26 Inverting large signal transient response 27 Overdrive recovery time 28 Differential gain vs Number of loads 29 Differential phase vs Number of loads 30 Closed loop output impedance vs Frequency 31 Power-down quiescent current vs Supply voltage 32 Turn-on and turn-off time delay 33 ±5-V Graphs Noninverting small-signal gain frequency response 34 Inverting small-signal gain frequency response 35 0.1-dB flatness 36 Noninverting large-signal gain frequency response 37 Inverting large-signal gain frequency response 38 Slew rate vs Output voltage step 39, 40, 41, 42 2nd harmonic distortion vs Frequency 43 3rd harmonic distortion vs Frequency 44 Harmonic distortion vs Output voltage swing 45, 46 Noninverting small-signal transient response 47 Inverting small-signal transient response 48 Overdrive recovery time 49 Rejection ratio vs Frequency 50

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TYPICAL CHARACTERISTICS (±15 V) space NONINVERTING SMALL-SIGNAL NONINVERTING SMALL-SIGNAL INVERTING SMALL-SIGNAL FREQUENCY RESPONSE FREQUENCY RESPONSE FREQUENCY RESPONSE 9 24 24 Ω RL = 100 Ω, RF = 649 Ω 22 22 G = -10, RF = 649 8 G = 10, RF = 604 Ω V = 0.2 V , 20 20 O PP VS = ±15 V 7 18 18 Ω 16 G = 5, R = 806 Ω 16 G = -5, RF = 909 6 F 14 14 R = 100 Ω, 5 Ω 12 L 12 RF = 1.15 k VO = 0.2 VPP, 10 VS = ±15 V 10 4 8 Ω RF = 1.5 kΩ G = 2, RF = 1.15 kΩ 8 G = -2, RF = 1.1 k 3 6 6

Gain = 2, 4 Inverting Gain - dB 4 Noninverting Gain - dB 2 R = 100 Ω, L Noninverting Gain - dB 2 G = 1, R = 1.5 kΩ 2 G = -1, RF = 1 kΩ V = 0.2 V , F O PP 0 0 1 V = ±15 V S -2 -2 0 -4 -4 1 M 10 M 100 M 1 G 100 k 1 M 10 M 100 M 1 G 1 M 10 M 100 M 1 G f - Frequency - Hz f - Frequency - Hz f - Frequency - Hz Figure 1. Figure 2. Figure 3.

NONINVERTING LARGE-SIGNAL INVERTING LARGE-SIGNAL 0.1-dB FLATNESS FREQUENCY RESPONSE FREQUENCY RESPONSE 6.4 16 16 R = 100 Ω, G = 5, R = 806 Ω L Gain = 2, F 14 V = 2 V , 6.3 14 O PP Ω Ω ± RF = 1.15 k , 12 G = -5, RF = 806 VS = 15 V R = 100 Ω, 6.2 L 12 VO = 0.2 VPP, 10 V = ±15 V 6.1 S 10 8

6 8 6 G = 2, RF = 1 kΩ 4 5.9 6 Inverting Gain - dB 2 Ω Noninverting Gain - dB G =-1, RF = 1 k 5.8 4 Noninverting Gain - dB 0 RL = 100 Ω, 5.7 2 VO = 4 VPP, -2 VS = ±15 V 5.6 0 -4 1 M 10 M 100 M 1 G 100 k 1 M 10 M 100 M 1 M 10 M 100 M 1 G f - Frequency - Hz f - Frequency - Hz f - Frequency - Hz Figure 4. Figure 5. Figure 6.

RECOMMENDED RISO 2nd HARMONIC DISTORTION FREQUENCY RESPONSE vs vs CAPACITIVE LOAD CAPACITIVE LOAD FREQUENCY

16 60 -30 R(ISO) = 54.9 Ω, CL = 22 pF Gain = 5, G = 5, RF = 806 Ω 14 RL = 100 Ω, 50 -40 VS = ±15 V 12 Gain = 5, Ω RL = 100 Ω - -50 10 40 V = ±15 V G = 2, RF = 1 kΩ S ISO 8 -60 30 R(ISO) = 54.9 Ω ` 6 CL = 10 pF -70 Ω 4 20 G = -2, RF = 1 k Signal Gain - dB R(ISO) = 39.2 Ω -80 RL = 1 kΩ, CL = 47 pF 2 Recommended R 10 VO = 2 VPP,

Ω 2nd Harmonic Destortion - dBc -90 R(ISO) = 28 RL = 100 Ω, 0 C = 100 pF L VS = ±15 V -2 0 -100 10 M 100 M 200 M 10 100 100 k 1 M 10 M 100 M Capacitive Load - MHz CL - Capacitive Load - pF f - Frequency - Hz Figure 7. Figure 8. Figure 9.

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TYPICAL CHARACTERISTICS (±15 V) (continued) space 3rd HARMONIC DISTORTION HARMONIC DISTORTION HARMONIC DISTORTION vs vs vs FREQUENCY OUTPUT VOLTAGE SWING OUTPUT VOLTAGE SWING

-30 -70 -40 V = 2 V , O PP HD3 RL = 100 Ω, -40 -45 VS = ±15 V -75 HD3

-50 G = 5, R = 806 Ω F -80 -50

-60 HD2 G = 2, -85 -55 HD2 RF = 1 kΩ -70 -90 Gain = 2, -60 Gain = 2, -80 Ω RF = 1 kΩ, RF = 1 k , G = -2, Ω Harmonic Distortion - dBc RL = 100 , Harmonic Distortion - dBc RL = 100 Ω, RF = 1 kΩ -95 -65 2nd Harmonic Destortion - dBc -90 f= 1 MHz f = 8 MHz Ω RL = 1 k , VS = ±15 V VS = ±15 V -100 -100 -70 100 k 1 M 10 M 100 M 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10 f - Frequency - Hz VO - Output Voltage Swing - VPP VO - Output Voltage Swing - VPP

Figure 10. Figure 11. Figure 12.

SLEW RATE SLEW RATE SLEW RATE vs vs vs OUTPUT VOLTAGE STEP OUTPUT VOLTAGE STEP OUTPUT VOLTAGE STEP 1000 1400 1400 Gain = 1 Gain = 2 Gain = 1 Fall RL = 100 Ω R =100 Ω Fall 1200 RL = 1 kΩ 1200 L R = 1.5 kΩ Fall Ω 800 F R = 1.5 kΩ RF =1 k s s F s ± µ µ ± µ VS = 15 V V = 15 V 1000 VS = ±15 V 1000 S Rise Rise 600 800 800 Rise

600 600 400 SR - Slew Rate V/ SR - Slew Rate V/

SR - Slew Rate V/ 400 400 200 200 200

0 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 1 2 3 4 5 6 7 8 9 10

VO - Output Voltage -VPP VO - Output Voltage -VPP VO - Output Voltage -VPP Figure 13. Figure 14. Figure 15.

SLEW RATE NOISE vs vs OUTPUT VOLTAGE STEP FREQUENCY SETTLING TIME 1600 100 1.5 Gain = 2 Fall Rising Edge 1400 R =1 kΩ

L Hz

Hz 1 R =1 kΩ

s F

µ 1200 V = ±15 V S nV/ Rise pA/ 0.5 In- 1000 Gain = -2 Ω oltage - V RL = 100 800 10 0 RF = 1.1 kΩ Vn VS = ±15 V 600 oltage Noise - -0.5 - Output V - V - Current Noise SR - Slew Rate V/ n O 400 n I V

V Falling Edge In+ -1 200

0 1 -1.5 0 1 2 3 4 5 6 7 8 9 10 10 100 1 k 10 k 100 k 0 2 4 6 8 10 12 14 16 18 f - Frequency - Hz VO - Output Voltage -VPP t - Time - ns Figure 16. Figure 17. Figure 18.

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TYPICAL CHARACTERISTICS (±15 V) (continued) space QUIESCENT CURRENT OUTPUT VOLTAGE vs vs SETTLING TIME SUPPLY VOLTAGE LOAD RESISTANCE 3 6 16 14 2.5 TA = 85 °C Rising Edge 12 5 2 10 ° 1.5 TA = 25 C 8 6 1 4 TA = -40 °C 4 0.5 Gain = -2 2 VS = ±15 V oltage - V Ω oltage - V 0 RL = 100 3 0 TA = -40° to 85°C R = 1.1 kΩ -0.5 F -2 VS = ±15 V -4 -1 2 - Output V - Output V -6 - Quiescent Current mA O O -1.5 -8 Q V V I -2 1 -10 Falling Edge -12 -2.5 -14 -3 0 -16 0 2 4 6 8 10 12 14 16 18 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 10 100 1000

t - Time - ns VS - Supply Voltage - ± V RL - Load Resistance - Ω Figure 19. Figure 20. Figure 21.

INPUT BIAS AND OFFSET CURRENT INPUT OFFSET VOLTAGE TRANSIMPEDANCE vs vs vs CASE TEMPERATURE CASE TEMPERATURE FREQUENCY 3.5 4 110 VS = ±15 V 100 3.5 3 VS =± 15Vand ± 5V A 90 A µ

µ 3 I 80 2.5 IB- -

2.5 VS = ±5 V 70

2 oltage - mV 60 2 1.5 IOS 50 1.5 40 ± 1 VS = 15 V 1 30 - Input Offset Current - Input Bias Current - Input Offset V

TransimpedanceGain dB IB I 20

I IB+ OS OS I 0.5 0.5 V 10 0 0 0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 -40-30-20 -10 0 10 20 30 40 50 60 70 80 90 0.1 1 10 100 1000 ° TC - Case Temperature - °C TC - Case Temperature - C Frequency- MHz Figure 22. Figure 23. Figure 24.

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TYPICAL CHARACTERISTICS (±15 V) (continued) space REJECTION RATIO vs NONINVERTING SMALL-SIGNAL INVERTING LARGE-SIGNAL FREQUENCY TRANSIENT RESPONSE TRANSIENT RESPONSE

70 0.2 6 ± Gain = -5, VS = 15 V 5 0.15 RL = 100 Ω, 60 CMRR Output 4 RF = 909 Ω, 0.1 3 V = ±15 V 50 S 2 0.05 PSRR+ 1

oltage - V Input

40 oltage - V Input 0 0 30 -1 -0.05 - Output V

- Output V -2 PSRR- Gain = 2, O 20 O Rejection Ratio - dB V -0.1 RL = 100 Ω, V -3 RF = 1 kΩ, -4 10 Output -0.15 V = ±15 V S -5 0 -0.2 -6 100 k 1 M 10 M 100 M 0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80 f - Frequency - Hz t - Time - ns t - Time - ns Figure 25. Figure 26. Figure 27.

DIFFERENTIAL GAIN DIFFERENTIAL PHASE vs vs OVERDRIVE RECOVERY TIME NUMBER OF LOADS NUMBER OF LOADS

20 5 0.3 0.4 Gain = 4, Gain = 2, Gain = 2, 15 Ω R = 1 kΩ, RF = 1 kΩ, RL = 100 , F 0.35 ± Ω 0.25 V = ±15 V, VS = 15 V, RF = 681 , S 40 IRE - NTSC and PAL, 10 ± 40 IRE - NTSC and PAL, VS = 15 V 2.5 0.3 Worst Case ±100 IRE Ramp Worst Case ±100 IRE Ramp 5 5 0.2 0.25 oltage - V oltage - V PAL PAL 0 0 0.15 0.2 -5 NTSC - Input V

- Output V 0.15 I NTSC

V 0.1 O -10 -2.5 V Differential Gain - % 0.1 Differential Phase - -15 0.05 0.05 -20 -5 0 0.2 0.4 0.6 0.8 1 0 0 t - Time - µs 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 Number of 150 Ω Loads Number of 150 Ω Loads Figure 28. Figure 29. Figure 30.

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TYPICAL CHARACTERISTICS (±15 V) (continued) space CLOSED-LOOP OUTPUT POWER-DOWN QUIESCENT IMPEDANCE CURRENT vs vs TURN-ON AND TURN-OFF FREQUENCY SUPPLY VOLTAGE TIME DELAY 100 350 1.5 Ω Gain = 2,

A 1 Ω RF = 1 k , µ 300 0.5 Output Voltage RF = 100 Ω, TA = 85°C 10 ± VS = 15 V 250 0 −0.5 Powerdown Pulse 6 200 ° 5 TA = -40 C oltage Level − V 1 4 150 T = 25°C A 3 PowerDown Pulse − V 100 − Output V Gain = 5, 2 O

0.1 V VI = 0.1 Vdc 1 Ω 50 RL = 100 - Closed-Loop Output Impedance 0 Powerdown Quiescent Current - VS = ±15 V and ±5 V O −1 Z 0.01 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 100 k 1 M 10 M 100 M 1 G 3 5 7 9 11 13 15 t − Time − ms f - Frequency - Hz VS - Supply Voltage - ±V Figure 31. Figure 32. Figure 33.

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TYPICAL CHARACTERISTICS (±5 V) space NONINVERTING SMALL-SIGNAL INVERTING SMALL-SIGNAL FREQUENCY RESPONSE FREQUENCY RESPONSE 0.1-dB FLATNESS 24 24 6.4 R = 100 Ω, R = 100 Ω, 22 Ω L 22 G = -10, R = 649 Ω L Gain = 2, G = 10, RF = 604 F VO = 0.2 VPP, VO = 0.2 VPP, ± 6.3 R = 1.15 kΩ, 20 ± 20 VS = 5 V F VS = 5 V Ω 18 18 RL = 100 , 6.2 V = 0.2 V , 16 G = 5, R = 806 Ω 16 Ω O PP F G = -5, RF = 909 V = ±5 V 14 14 S 6.1 12 12 10 10 6 8 G = 2, R = 1.15 kΩ 8 F G = -2, RF = 1.1 kΩ 6 6 5.9

Inverting Gain - dB 4

4 Noninverting Gain - dB

Noninverting Gain − dB 5.8 2 2 Ω G = 1, RF = 1.5 kΩ G = -1, RF = 1 k 0 0 5.7 −2 -2 −4 -4 5.6 1 M 10 M 100 M 1 G 1 M 10 M 100 M 1 G 100 k 1 M 10 M 100 M f − Frequency − Hz f - Frequency - Hz f - Frequency - Hz Figure 34. Figure 35. Figure 36.

SLEW RATE NONINVERTING LARGE-SIGNAL INVERTING LARGE-SIGNAL vs FREQUENCY RESPONSE FREQUENCY RESPONSE OUTPUT VOLTAGE STEP 16 16 800 G = -5, R = 909 Ω G = 5, RF = 806 Ω F Gain = 1 14 Fall 14 700 RL = 100 Ω Ω 12 RF = 1.5 k

s ± 12 600 VS = 5 V 10 µ Rise 10 8 VO = 2 VPP, 500 RL = 100 Ω, 8 6 VS = ±5 V 400 Ω G = 2, RF = 1.15 k 4 6 300 Inverting Gain - dB 2 Ω SR - Slew Rate V/ 4 G =-12, RF = 1 k

Noninverting Gain - dB 200 VO = 4 VPP, 0 RL = 100 Ω, 2 -2 100 VS = ±5 V 0 -4 0 1 M 10 M 100 M 1 G 1 10 M 100 M 1 G 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

f - Frequency - Hz f - Frequency - Hz VO - Output Voltage -VPP Figure 37. Figure 38. Figure 39.

SLEW RATE SLEW RATE SLEW RATE vs vs vs OUTPUT VOLTAGE STEP OUTPUT VOLTAGE STEP OUTPUT VOLTAGE STEP 800 800 800 Rise Gain = 1 Gain = 2 Fall Gain = 2 R = 100 Ω R = 1 kΩ 700 RL = 1 kΩ Rise 700 L 700 L R = 1 kΩ R = 1 kΩ RF = 1.5 kΩ F Rise F

s ± s ± ± s VS = 5 V VS = 5 V µ 600 V = 5 V µ 600 Fall S Fall µ 600

500 500 500

400 400 400

300 300 300 SR - Slew Rate V/ SR - Slew Rate V/ 200 SR - Slew Rate V/ 200 200

100 100 100

0 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 1 2 3 4 5 6 0 1 2 3 4 5 6

VO - Output Voltage -VPP VO - Output Voltage -VPP VO - Output Voltage -VPP Figure 40. Figure 41. Figure 42.

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TYPICAL CHARACTERISTICS (±5 V) (continued) space 2nd HARMONIC DISTORTION 3rd HARMONIC DISTORTION HARMONIC DISTORTION vs vs vs FREQUENCY FREQUENCY OUTPUT VOLTAGE SWING

-30 -30 -65 VO = 2 VPP, Ω G = 5, RF = 681 RL = 100 Ω, -40 -40 -70 VS = ±5 V HD3 G = 2, R = 681 Ω -50 F -50 -75 G = 5, Ω -60 -60 RF = 681 -80 HD2 -70 -70 -85 G = 2, G = -2, RF = 1 kΩ R = 681 Ω Gain = 2, RL = 1 kΩ, F -80 -80 -90 RF = 1.15 kΩ RL = 100 Ω,

V = 2 V , Harmonic Distortion - dBc O PP f= 1 MHz Ω 2nd Harmonic Destortion - dBc -90 R = 100 Ω, 2nd Harmonic Destortion - dBc -90 G = -2, RF = 1 k -95 L VS = ±5 V VS = ±5 V RL = 1 kΩ, -100 -100 -100 100 k 1 M 10 M 100 M 100 k 1 M 10 M 100 M 0 1 2 3 4 5 6 7 f - Frequency - Hz f - Frequency - Hz VO - Output Voltage Swing - VPP Figure 43. Figure 44. Figure 45.

HARMONIC DISTORTION vs NONINVERTING SMALL-SIGNAL INVERTING LARGE-SIGNAL OUTPUT VOLTAGE SWING TRANSIENT RESPONSE TRANSIENT RESPONSE -40 0.2 3 2.5 Gain = -5, 0.15 R = 100 Ω, HD3 Output 2 L -50 RF = 909 Ω, 0.1 1.5 V = ±5 V Input S 1 HD2 0.05 -60 0.5 oltage - V oltage - V Input 0 0 -70 -0.5 -0.05 -1 - Output V Gain = 2, - Output V Gain = 2

Ω O R = 1 k O Ω F -0.1 R = 100 V V -1.5 Ω L Harmonic Distortion - dBc -80 RL = 100 , Ω RF = 1.15 k -2 Output f= 8 MHz -0.15 VS = ±5 V VS = ±5 V -2.5 -90 -0.2 -3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80 VO - Output Voltage Swing - VPP t - Time - ns t - Time - ns Figure 46. Figure 47. Figure 48.

REJECTION RATIO vs OVERDRIVE RECOVERY TIME FREQUENCY 5 1.25 70 Gain = 4, VS = ±5 V 4 Ω 1 RL = 100 , 60 Ω 3 RF = 909 , 0.75 CMRR VS = ±5 V 2 0.5 50

1 0.25 PSRR+ 40 oltage - V

0 0 oltage - V 30 -1 -0.25 - Output V -2 - Input V

-0.5 I 20 Rejection Ratio - dB O V V -3 -0.75 10 PSRR- -4 -1

-5 -1.25 0 0 0.2 0.4 0.6 0.8 1 100 k 1 M 10 M 100 M t - Time - µs f - Frequency - Hz Figure 49. Figure 50.

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APPLICATION INFORMATION

MAXIMUM SLEW RATE FOR REPETITIVE 15 V SIGNALS +VS The THS3110 and THS3111 are recommended for + µ µ high slew rate pulsed applications where the internal 50 Ω Source 0.1 F 6.8 F nodes of the amplifier have time to stabilize between + pulses. It is recommended to have at least 20-ns VI 49.9 Ω THS3110 delay between pulses. 49.9 Ω _ 50 Ω LOAD The THS3110 and THS3111 are not recommended RF for applications with repetitive signals (sine, square, 1 kΩ sawtooth, or other) that exceed 900 V/μs. Using the 1 kΩ RG part in these applications results in excessive current 0.1 µF 6.8 µF draw from the power supply and possible device + damage. -VS For applications with high slew rate, repetitive signals, -15 V the THS3091 and THS3095 (single), or THS3092 and THS3096 (dual) are recommended. Figure 51. Wideband, Noninverting Gain Configuration WIDEBAND, NONINVERTING OPERATION The THS3110 and THS3111 are unity-gain stable, Current-feedback amplifiers are highly dependent on 100-MHz, current-feedback operational amplifiers, the feedback resistor RF for maximum performance designed to operate from a ±5-V to ±15-V power and stability. Table 1 shows the optimal gain setting supply. resistors RF and RG at different gains to give maximum bandwidth with minimal peaking in the Figure 51 shows the THS3111 in a noninverting gain frequency response. Higher bandwidths can be of 2-V/V configuration typically used to generate the achieved, at the expense of added peaking in the performance curves. Most of the curves were frequency response, by using even lower values for characterized using signal sources with 50-Ω source RF. Conversely, increasing RF decreases the impedance, and with measurement equipment bandwidth, but stability is improved. presenting a 50-Ω load impedance.

Table 1. Recommended Resistor Values for Optimum Frequency Response

THS3110 AND THS3111 RF AND RG VALUES FOR MINIMAL PEAKING WITH RL = 100 Ω

GAIN (V/V) SUPPLY VOLTAGE (V) RG (Ω) RF (Ω) ±15 — 1.5 k 1 ±5 — 1.5 k ±15 1 k 1 k 2 ±5 1.15 k 1.15 k ±15 200 806 5 ±5 200 806 ±15 66.5 604 10 ±5 66.5 604 ±15 1 k 1 k –1 ±5 1 k 1 k –2 ±15 and ±5 549 1.1 k –5 ±15 and ±5 182 909 –10 ±15 and ±5 64.9 649

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WIDEBAND, INVERTING OPERATION +VS Figure 52 shows the THS3111 in a typical inverting 50 Ω Source gain configuration where the input and output + 49.9 Ω impedances and signal gain from Figure 51 are VI 49.9 Ω THS3110 retained in an inverting circuit configuration. RT _ 50 Ω LOAD

15 V +V +VS S RF 2 1 kΩ + RG Ω 0.1 µF 6.8 µF 1 k

+ +VS 49.9 Ω 2 THS3110 RF _ 50 Ω LOAD 1.1 kΩ 50 Ω Source V R S G RF 50 Ω Source RG _ VI 549 Ω 1.1 kΩ V 49.9 Ω I 549 Ω RM µ µ THS3110 0.1 F 6.8 F 56.2 Ω RT 56.2 Ω + Ω + 50 LOAD +VS +VS -V 2 2 -15 V S Figure 53. DC-Coupled, Single-Supply Operation Figure 52. Wideband, Inverting Gain Configuration Video Distribution SINGLE-SUPPLY OPERATION The wide bandwidth, high slew rate, and high output drive current of the THS3110 and THS3111 match The THS3110 and THS3111 have the capability to the demands for video distribution for delivering video operate from a single-supply voltage ranging from signals down multiple cables. To ensure high signal 10 V to 30 V. When operating from a single power quality with minimal degradation of performance, a supply, biasing the input and output at mid-supply 0.1-dB gain flatness should be at least 7x the allows for the maximum output voltage swing. The passband frequency to minimize group delay circuits shown in Figure 53 shows inverting and variations from the amplifier. A high slew rate noninverting amplifiers configured for single supply minimizes distortion of the video signal, and supports operations. component video and RGB video signals that require fast transition times and fast settling times for high signal quality.

1 kΩ 1 kΩ

15 V 75-Ω Transmission Line V Ω O(1) - 75 VI + -15 V 75 Ω n Lines 75 Ω 75 Ω VO(n)

75 Ω

Figure 54. Video Distribution Amplifier Application

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Driving Capacitive Loads frequency load independence of the amplifier while Applications such as FET drivers and line drivers can isolating the phase shift caused by the capacitance at be highly capacitive and cause stability problems for high frequency. Use a ferrite chip with similar high-speed amplifiers. impedance to RISO, 20 Ω to 50 Ω, at 100 MHz and low impedance at dc. Figure 55 through Figure 61 show recommended methods for driving capacitive loads. The basic idea 806 Ω is to use a resistor or ferrite chip to isolate the phase shift at high frequency caused by the capacitive load VS from the amplifier feedback path. See Figure 55 for 200 Ω Ferrite Bead recommended resistor values versus capacitive load. _ + 100 Ω LOAD 60 µ Gain = 5, -VS 1 F Ω RL = 100 , Ω 50 ± 49.9 VS = 15 V VS Ω - 40 ISO

30 Figure 57. Ferrite Bead to Isolate Capacitive Load 20 Recommended R 10 Figure 58 shows another method used to maintain the low frequency load independence of the amplifier 0 while isolating the phase shift caused by the 10 100 capacitance at high frequency. At low frequency, CL - Capacitive Load - pF feedback is mainly from the load side of RISO. At high frequency, the feedback is mainly via the 27-pF Figure 55. Recommended RISO vs Capacitive capacitor. The resistor RIN in series with the negative Load input is used to stabilize the amplifier and should be equal to the recommended value of RF at unity gain. Replacing R with a ferrite of similar impedance at Placing a small series resistor, RISO, between the IN amplifier output and the capacitive load, as shown in about 100 MHz as shown in Figure 59 gives similar Figure 56, is an easy way of isolating the load results with reduced dc offset and low frequency capacitance. noise. (See the Additional Reference Material section for expanding the usability of current-feedback 806 Ω amplifiers.)

VS RF Ω 200 100 Ω LOAD _ 5.11 Ω 806 Ω 27 pF

+ RISO RIN µ V -VS 1 F S RG 750 Ω 100 Ω LOAD 49.9 Ω _ 5.11 Ω VS 200 Ω + µ -VS 1 F 49.9 Ω VS Figure 56. Resistor to Isolate Capacitive Load

Using a ferrite chip in place of RISO, as shown in Figure 57, is another approach of isolating the output Figure 58. Feedback Technique with Input of the amplifier. The ferrite impedance characteristic Resistor for Capacitive Load versus frequency is useful to maintain the low

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R Figure 61 shows a push-pull FET driver circuit typical F of ultrasound applications with isolation resistors to 806 Ω isolate the gate capacitance from the amplifier. 27 pF

FIN VS VS VS R FB G 100 Ω LOAD + 5.11 Ω _ 5.11 Ω 200 Ω _ + µ -V -VS 1 F S 49.9 Ω VS 301 Ω

66.5 Ω 301 Ω

Figure 59. Feedback Technique with Input Ferrite V Bead for Capacitive Load S _ 5.11 Ω Figure 60 shows how to use two amplifiers in parallel + to double the output drive current to larger capacitive -V -V loads. This technique is used when more output S S current is needed to charge and discharge the load faster like when driving large FET transistors. Figure 61. PowerFET Drive Circuit

Ω 806 SAVING POWER WITH POWER-DOWN

VS FUNCTIONALITY AND SETTING 200 Ω THRESHOLD LEVELS WITH THE _ 5.11 Ω REFERENCE PIN + 24.9 Ω The THS3110 features a power-down pin (PD) which -VS lowers the quiescent current from 4.8 mA down to 806 Ω 270 μA, ideal for reducing system power.

VS The power-down pin of the amplifier defaults to the VS 1 nF 200 Ω REF pin voltage in the absence of an applied voltage, _ Ω 5.11 putting the amplifier in the normal on mode of + operation. To turn off the amplifier in an effort to 24.9 Ω -VS conserve power, the power-down pin can be driven towards the positive rail. The threshold voltages for Figure 60. Parallel Amplifiers for Higher Output power-on and power-down are relative to the supply Drive rails and are given in the specification tables. Below the Enable Threshold Voltage, the device is on. Above the Disable Threshold Voltage, the device is off. Behavior in between these threshold voltages is not specified. Note that this power-down functionality is just that; the amplifier consumes less power in power-down mode. The power-down mode is not intended to provide a high-impedance output. In other words, the power-down functionality is not intended to allow use as a 3-state bus driver. When in power-down mode, the impedance looking back into the output of the amplifier is dominated by the feedback and gain setting resistors, but the output impedance of the device itself varies depending on the voltage applied to the outputs.

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Figure 62 shows the total system output impedance POWER-DOWN REFERENCE PIN which includes the amplifier output impedance in OPERATION parallel with the feedback plus gain resistors, which In addition to the power-down pin, the THS3110 cumulate to 1870 Ω. Figure 51 shows this circuit configuration for reference. features a reference pin (REF) which allows the user to control the enable or disable power-down voltage levels applied to the PD pin. In most split-supply 2000 applications, the reference pin is connected to Ω 1800 ground. In either case, the user needs to be aware of 1600 voltage-level thresholds that apply to the power-down 1400 pin. The tables below show examples and illustrate 1200 the relationship between the reference voltage and 1000 the power-down thresholds. In the table, the threshold 800 levels are derived by the following equations: 600 PD ≤ REF + 0.8 V for enable 400 Gain = 2 PD ≥ REF + 2.0 V for disable Ω Powerdown Output Impedance - RF = 1 k 200 ± ± VS = 15 V and 5 V where the usable range at the REF pin is 0 100 k 1 M 10 M 100 M 1 G VS– ≤ VREF ≤ (VS+ – 4 V). f - Frequency - Hz The recommended mode of operation is to tie the REF pin to midrail, thus setting the enable/disable Figure 62. Power-Down Output Impedance vs thresholds to V + 0.8 V and V + 2 V Frequency midrail midrail respectively.

As with most current feedback amplifiers, the internal POWER-DOWN THRESHOLD VOLTAGE LEVELS architecture places some limitations on the system SUPPLY REFERENCE PIN ENABLE DISABLE when in power-down mode. Most notably is the fact VOLTAGE (V) VOLTAGE (V) LEVEL (V) LEVEL (V) that the amplifier actually turns ON if there is a ±0.7 V ±15, ±5 0.0 0.8 2.0 or greater difference between the two input nodes ±15 2.0 2.8 4 (V+ and V–) of the amplifier. If this difference exceeds ±0.7 V, the output of the amplifier creates an ±15 –2.0 –1.2 0 output voltage equal to approximately [(V+ – V–) – ±5 1.0 1.8 3 0.7 V] × Gain. Also, if a voltage is applied to the ±5 –1.0 –0.2 1 output while in power-down mode, the V– node +30 15 15.8 17 voltage is equal to V × R /(R + R ). For low O(applied) G F G +10 5.0 5.8 7 gain configurations and a large applied voltage at the output, the amplifier may actually turn ON due to the Note that if the REF pin is left unterminated, it floats aforementioned behavior. to the positive rail and falls outside of the The time delays associated with turning the device on recommended operating range given above (VS– ≤ and off are specified as the time it takes for the VREF ≤ VS+ – 4 V). As a result, it no longer serves as amplifier to reach either 10% or 90% of the final a reliable reference for the PD pin and the output voltage. The time delays are in the order of enable/disable thresholds given above no longer microseconds because the amplifier moves in and out apply. If the PD pin is also left unterminated, it also of the linear mode of operation in these transitions. floats to the positive rail and the device is disabled. If balanced, split supplies are used (±VS) and the REF and PD pins are grounded, the device is enabled.

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PRINTED-CIRCUIT BOARD LAYOUT • Connections to other wideband devices on the TECHNIQUES FOR OPTIMAL board may be made with short direct traces or PERFORMANCE through onboard transmission lines. For short connections, consider the trace and the input to Achieving optimum performance with a the next device as a lumped capacitive load. high-frequency amplifier, such as the THS3110 and Relatively wide traces [0.05 inch (1,3 mm) to 0.1 THS3111, requires careful attention to board layout inch (2,54 mm)] should be used, preferably with parasitic and external component types. ground and power planes opened up around Recommendations that optimize performance include: them. Estimate the total capacitive load and • Minimize parasitic capacitance to any ac ground determine if isolation resistors on the outputs are for all of the signal I/O pins. Parasitic capacitance necessary. Low parasitic capacitive loads (< 4 pF) on the output and input pins can cause instability. may not need an RS since the THS3110 and To reduce unwanted capacitance, a window THS3111 are nominally compensated to operate around the signal I/O pins should be opened in all with a 2-pF parasitic load. Higher parasitic of the ground and power planes around those capacitive loads without an RS are allowed as the pins. Otherwise, ground and power planes should signal gain increases (increasing the unloaded be unbroken elsewhere on the board. phase margin). If a long trace is required, and the • Minimize the distance [< 0.25 inch (6,35 mm)] 6-dB signal loss intrinsic to a doubly-terminated from the power-supply pins to high frequency transmission line is acceptable, implement a 0.1-μF and 100-pF decoupling capacitors. At the matched impedance transmission line using device pins, the ground and power plane layout microstrip or stripline techniques (consult an ECL should not be in close proximity to the signal I/O design handbook for microstrip and stripline layout pins. Avoid narrow power and ground traces to techniques). A 50-Ω environment is not necessary minimize inductance between the pins and the onboard, and in fact, a higher impedance decoupling capacitors. The power-supply environment improves distortion as shown in the connections should always be decoupled with distortion versus load plots. With a characteristic these capacitors. Larger (6.8 μF or more) board trace impedance based on board material tantalum decoupling capacitors, effective at lower and trace dimensions, a matching series resistor frequency, should also be used on the main into the trace from the output of the supply pins. These may be placed somewhat THS3110/THS3111 is used as well as a farther from the device and may be shared among terminating shunt resistor at the input of the several devices in the same area of the PC board. destination device. Remember also that the • Careful selection and placement of external terminating impedance is the parallel combination components preserve the high-frequency of the shunt resistor and the input impedance of performance of the THS3110 and THS3111. the destination device: this total effective Resistors should be a very low reactance type. impedance should be set to match the trace Surface-mount resistors work best and allow a impedance. If the 6-dB attenuation of a tighter overall layout. Again, keep their leads and doubly-terminated transmission line is PC board trace length as short as possible. Never unacceptable, a long trace can be use wirewound-type resistors in a high-frequency series-terminated at the source end only. Treat application. Because the output pin and inverting the trace as a capacitive load in this case. This input pins are the most sensitive to parasitic does not preserve signal integrity as well as a capacitance, always position the feedback and doubly-terminated line. If the input impedance of series output resistors, if any, as close as possible the destination device is low, there is some signal to the inverting input pins and output pins. Other attenuation due to the voltage divider formed by network components, such as input termination the series output into the terminating impedance. resistors, should be placed close to the • Socketing a high-speed part like the THS3110 and gain-setting resistors. Even with a low parasitic THS3111 is not recommended. The additional capacitance shunting the external resistors, lead length and pin-to-pin capacitance introduced excessively high resistor values can create by the socket can create an extremely significant time constants that can degrade troublesome parasitic network which can make it performance. Good axial metal-film or almost impossible to achieve a smooth, stable surface-mount resistors have approximately 0.2 frequency response. Best results are obtained by pF in shunt with the resistor. For resistor values soldering the THS3110/THS3111 parts directly greater than 2.0 kΩ, this parasitic capacitance can onto the board. add a pole and/or a zero that can affect circuit operation. Keep resistor values as low as possible, consistent with load driving considerations.

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PowerPAD DESIGN CONSIDERATIONS PowerPAD LAYOUT CONSIDERATIONS The THS3110 and THS3111 are available in a 1. PCB with a top side etch pattern as shown in thermally-enhanced PowerPAD family of packages. Figure 64. There should be etch for the leads as These packages are constructed using a downset well as etch for the thermal pad. leadframe upon which the die is mounted (see Figure 63a and Figure 63b). This arrangement results 0.205 in the lead frame being exposed as a thermal pad on (5,21) the underside of the package (see Figure 63c). 0.060 (1,52) 0.017 Because this thermal pad has direct thermal contact (0,432) with the die, excellent thermal performance can be 0.013 achieved by providing a good thermal path away from (0,33) the thermal pad. Note that devices such as the 0.094 0.075 THS311x have no electrical connection between the (2,39) PowerPAD and the die. (1,91) 0.025 0.030 (0,64) The PowerPAD package allows for both assembly (0,76) and thermal management in one manufacturing operation. During the surface-mount solder operation 0.010 0.040 (0,254) (1,01) 0.035 (when the leads are being soldered), the thermal pad vias (0,89) can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat Dimensions are in inches (mm). dissipating device. Figure 64. DGN PowerPAD PCB Etch and Via Pattern The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of 2. Place five holes in the area of the thermal pad. surface mount with the, heretofore, awkward These holes should be 0.01 inch (0,254 mm) in mechanical methods of heatsinking. diameter. Keep them small so that solder wicking through the holes is not a problem during reflow.

DIE 3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad Side View (a) Thermal area. This helps dissipate the heat generated by Pad the THS3110/THS3111 IC. These additional vias DIE may be larger than the 0.01-inch (0,254 mm) End View (b) diameter vias directly under the thermal pad. Bottom View (c) They can be larger because they are not in the thermal pad area to be soldered so that wicking Figure 63. Views of Thermal Enhanced Package is not a problem. 4. Connect all holes to the internal ground plane. Although there are many ways to properly heatsink Note that the PowerPAD is electrically isolated the PowerPAD package, the following steps illustrate from the silicon and all leads. Connecting the the recommended approach. PowerPAD to any potential voltage such as VS–, space is acceptable as there is no electrical connection to the silicon. space 5. When connecting these holes to the ground space plane, do not use the typical web or spoke via connection methodology. Web connections have space a high thermal resistance connection that is space useful for slowing the heat transfer during soldering operations. This makes the soldering of space vias that have plane connections easier. In this space application, however, low thermal resistance is desired for the most efficient heat transfer. space Therefore, the holes under the THS3110/THS3111 PowerPAD package should space make their connection to the internal ground space plane with a complete connection around the

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entire circumference of the plated-through hole. Maximum power dissipation levels are depicted in 6. The top-side solder mask should leave the Figure 65 for the available packages. The data for the terminals of the package and the thermal pad PowerPAD packages assume a board layout that area with its five holes exposed. The bottom-side follows the PowerPAD layout guidelines referenced solder mask should cover the five holes of the above and detailed in the PowerPAD application note thermal pad area. This prevents solder from (literature number SLMA002). Figure 65 also being pulled away from the thermal pad area illustrates the effect of not soldering the PowerPAD to during the reflow process. a PCB. The thermal impedance increases substantially which may cause serious heat and 7. Apply solder paste to the exposed thermal pad performance issues. Be sure to always solder the area and all of the IC terminals. PowerPAD to the PCB for optimum performance. 8. With these preparatory steps in place, the IC is simply placed in position and run through the T =125° C solder reflow operation as any standard J surface-mount component. This results in a part that is properly installed.

POWER DISSIPATION AND THERMAL CONSIDERATIONS The THS3110 and THS3111 incorporate automatic thermal shutoff protection. This protection circuitry shuts down the amplifier if the junction temperature exceeds approximately +160°C. When the junction temperature reduces to approximately +140°C, the amplifier turns on again. But, for maximum -- ° performance and reliability, the designer must take TA Free-AirTemperature C care to ensure that the design does not exceed a junction temperature of +125°C. Between +125°C Results are with no airflow and PCB size = 3 in × 3 in (7,62 mm × and +150°C, damage does not occur, but the 7,62 mm); θJA = 58.4°C/W for MSOP-8 with PowerPAD (DGN); θJA performance of the amplifier begins to degrade and = 95°C/W for SOIC-8 High-K Test PCB (D); θJA = 158°C/W for long term reliability suffers. The thermal MSOP-8 with PowerPAD, without solder. characteristics of the device are dictated by the Figure 65. Maximum Power Distribution package and the PC board. Maximum power vs Ambient Temperature dissipation for a given package can be calculated using the following formula. When determining whether or not the device satisfies TT- P = Max A the maximum power dissipation requirement, it is DMax q JA (1) important to not only consider quiescent power dissipation, but also dynamic power dissipation. Often Where: times, this is difficult to quantify because the signal • PDMax is the maximum power dissipation in the pattern is inconsistent, but an estimate of the RMS amplifier (W) power dissipation can provide visibility into a possible • TMax is the absolute maximum junction problem. temperature (°C)

• TA is the ambient temperature (°C) DESIGN TOOLS

• θJA = θJC + θCA Evaluation Fixtures, Spice Models, and • θJC is the thermal coefficient from the silicon junctions to the case (°C/W) Application Support

• θCA is the thermal coefficient from the case to Texas Instruments is committed to providing its ambient air (°C/W) customers with the highest quality of applications For systems where heat dissipation is more critical, support. To support this goal an evaluation board has the THS3110 and THS3111 are offered in an been developed for the THS3110 and THS3111 MSOP-8 with PowerPAD package offering even operational amplifiers. The board is easy to use, better thermal performance. The thermal coefficient allowing for straightforward evaluation of the device. for the PowerPAD packages are substantially The evaluation board can be ordered through the improved over the traditional SOIC. Texas Instruments web site, www.ti.com, or through your local Texas Instruments sales representative.

SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009...... www.ti.com

Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF-amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the THS3111 is available through the Texas Instruments web site (www.ti.com). The product information center (PIC) is also available for design assistance and detailed product information. These models do a good job of predicting small-signal ac and transient performance under a wide variety of operating conditions. They are not intended to model the distortion characteristics of the amplifier, nor do they attempt to distinguish between the package types in their small-signal ac performance. Detailed information about what is and is not modeled is contained in the model file itself.

J2 GND TP2 J1 J7 VS+ VS−

FB1 FB2 VS+ VS−

+ C4 Figure 67. THS3110 EVM Board Layout C5 C3 C1 C2 C6 + (Top Layer)

PD J7 NOTE: The Edge number for the THS3111 is R5 Z1 6445587. R6 R4 0

TP1 Vs+ R8B 7 R3 J5 2 _ 8 R8A 6 Vin− J6 3 + 1 Vout R1 4 R7A R7B Z2

Vs −

J4 Vin+ REF R2 J8

Figure 66. THS3110 EVM Circuit Configuration

Figure 68. THS3110 EVM Board Layout (Bottom Layer)

24 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated Product Folder Link(s): THS3110 THS3111 THS3110 THS3111 www.ti.com...... SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009

Table 2. Bill of Materials

THS3110DGN and THS3111DGN EVM REFERENCE PCB MANUFACTURER'S ITEM DESCRIPTION SMD SIZE DESIGNATOR QTY PART NUMBER (1) 1 Bead, ferrite, 3 A, 80 Ω 1206 FB1, FB2 2 (Steward) HI1206N800R-00 Capacitor 6.8 μF, tantalum, 2 D C1, C2 2 (AVX) TAJD685K035R 35 V, 10% 3 Open 0805 R5, Z1 2 Capacitor 0.1 μF, ceramic, X7R, 50 4 0805 C3, C4 2 (AVX) 08055C104KAT2A V Capacitor 100 pF, ceramic, NPO, 5 0805 C5, C6 2 (AVX) 08051A101JAT2A 100 V 6 Resistor, 0 Ω, 1/8 W, 1% 0805 R6(2) 1 (Phycomp) 9C08052A0R00JLHFT 7 Resistor, 750 Ω, 1/8 W, 1% 0805 R3, R4 2 (Phycomp) 9C08052A7500FKHFT 8 Open 1206 R7A, Z2 2 9 Resistor, 49.9 Ω, 1/4 W, 1% 1206 R2, R8A 2 (Phycomp) 9C12063A49R9FKRFT 10 Resistor, 53.6 Ω, 1/4 W, 1% 1206 R1 1 (Phycomp) 9C12063A53R6FKRFT 11 Open 2512 R7B, R8B 2 Header, 0.1" (2,54 mm) CTRS, 12 3 Pos. JP1(2) 1 (Sullins) PZC36SAAN 0.025" (6,35 mm) SQ pins 13 Shunts JP1(2) 1 (Sullins) SSC02SYAN Jack, banana receptance, 14 J1, J2, J3 3 (SPC) 813 0.25" (6,35 mm) dia. hole 15 Test point, red J7(2), J8(2), TP1 3 (Keystone) 5000 16 Test point, black TP2 1 (Keystone) 5001 17 Connector, SMA PCB jack J4, J5, J6 3 (Amphenol) 901-144-8RFX Standoff, 4-40 hex, 18 4 (Keystone) 1808 0.625" (15,875 mm) length Screw, Phillips, 4-40, 19 4 SHR-0440-016-SN 0.250" (6,35 mm) 20 IC, THS3110 U1 1 (TI) THS3110DGN 21 Board, printed-circuit (THS3110) 1 (TI) EDGE # 6445586 22 IC, THS3111 U1 1 (TI) THS3111DGN 23 Board, printed-circuit (THS3111) 1 (TI) EDGE # 6445587

(1) Manufacturer part numbers are used for test purposes only. (2) Applies to the THS3110DGN EVM only.

ADDITIONAL REFERENCE MATERIAL • PowerPAD Made Easy, application brief (SLMA004) • PowerPAD Thermally-Enhanced Package, technical brief (SLMA002) • Voltage Feedback vs Current Feedback Amplifiers, (SLVA051) • Current Feedback Analysis and Compensation (SLOA021) • Current Feedback Amplifiers: Review, Stability, and Application (SBOA081) • Effect of Parasitic Capacitance in Op Amp Circuits (SLOA013) • Expanding the Usability of Current-Feedback Amplifiers, by Randy Stephens, 3Q 2003 Analog Applications Journal www.ti.com/sc/analogapps).

SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009...... www.ti.com

REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (May 2008) to Revision E ...... Page

• Changed Power-Down Characteristics, Power-down quiescent current test conditions of VS = ±15 V Electrical Characteristics ...... 5

• Changed Power-Down Characteristics, PD pin bias current parameter of VS = ±15 V Electrical Characteristics ...... 5

• Changed Power-Down Characteristics, Power-down quiescent current test conditions of VS = ±5 V Electrical Characteristics ...... 7

• Changed Power-Down Characteristics, PD pin bias current parameter of VS = ±5 V Electrical Characteristics ...... 7 • Added caption title to Figure 56 ...... 18 • Added caption title to Figure 57 ...... 18 • Added caption title to Figure 58 ...... 18 • Added caption title to Figure 59 ...... 19 • Added caption title to Figure 60 ...... 19 • Changed the first sentence of the second paragraph of Saving Power with Power-Down Functionality section ...... 19

Changes from Revision C (February, 2007) to Revision D ...... Page

• Changed VS = ±15 V Transimpedance specifications from 1.5 MΩ (typ) to 1 MΩ (typ); 1 MΩ (at +25°C) to 0.75 MΩ; 0.7 MΩ (over temperature) to 0.5 MΩ ...... 4

• Changed VS = ±15 V Input offset voltage specifications from 1.5 mV (typ) to 3 mV (typ); 6 mV (at +25°C) to 10 mV; 8 mV (over temperature) to 12 mV ...... 4

• Changed VS = ±15 V +PSRR specifications from 83 dB to 75 dB (typ); from 75 dB to 65 dB (at +25°C); from 70 dB (over temperature) to 60 dB ...... 5

• Changed VS = ±15 V –PSRR specifications from 78 dB to 69 dB (typ); from 70 dB to 60 dB (at +25°C); from 66 dB (over temperature) to 55 dB ...... 5

• Changed VS = ±5 V Transimpedance specifications from 1.6 MΩ (typ) to 1 MΩ (typ); 1 MΩ (at +25°C) to 0.75 MΩ; 0.7 MΩ (over temperature) to 0.5 MΩ ...... 6

• Changed VS = ±5 V Input offset voltage specifications from 3 mV (typ) to 6 mV (typ); 6 mV (at +25°C) to 10 mV; 8 mV (over temperature) to 12 mV ...... 6

• Changed VS = ±5 V +PSRR specifications from 80 dB to 71 dB (typ); from 72 dB to 62 dB (at +25°C); from 67 dB (over temperature) to 57 dB ...... 7

• Changed VS = ±5 V –PSRR specifications from 75 dB to 66 dB (typ); from 67 dB to 57 dB (at +25°C); from 62 dB (over temperature) to 52 dB ...... 7 • Corrected Typical Characteristic figure numbering errors from previous version ...... 9 • Updated ±15 V Transimpedance vs Frequency characteristic graph ...... 11

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples (1) Drawing Qty (2) Ball material (3) (4/5) (6) THS3110ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3110I

THS3110IDGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 BIR

THS3110IDGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 BIR

THS3110IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3110I

THS3110IDRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3110I

THS3111CD ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 3111C

THS3111CDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 3111C

THS3111ID ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3111I

THS3111IDG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3111I

THS3111IDGN ACTIVE HVSSOP DGN 8 80 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 BIS

THS3111IDGNR ACTIVE HVSSOP DGN 8 2500 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 BIS

THS3111IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 3111I

(1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement.

Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 13-Aug-2021

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jul-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) THS3110IDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS3110IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 THS3111IDGNR HVSSOP DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS3111IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION

www.ti.com 17-Jul-2020

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS3110IDGNR HVSSOP DGN 8 2500 364.0 364.0 27.0 THS3110IDR SOIC D 8 2500 350.0 350.0 43.0 THS3111IDGNR HVSSOP DGN 8 2500 364.0 364.0 27.0 THS3111IDR SOIC D 8 2500 350.0 350.0 43.0

Pack Materials-Page 2 GENERIC PACKAGE VIEW DGN 8 PowerPAD VSSOP - 1.1 mm max height 3 x 3, 0.65 mm pitch SMALL OUTLINE PACKAGE

This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details.

4225482/A

www.ti.com PACKAGE OUTLINE

TM DGN0008D PowerPAD VSSOP - 1.1 mm max height SCALE 4.000 SMALL OUTLINE PACKAGE

C 5.05 A TYP 4.75 0.1 C PIN 1 INDEX AREA SEATING PLANE 6X 0.65 8 1

2X 3.1 1.95 2.9 NOTE 3

5 0.38 8X 0.25 3.1 B 0.13 CAB 2.9 NOTE 4

0.23 0.13

SEE DETAIL A

EXPOSED THERMAL PAD

4 5

0.25 GAGE PLANE 1.89 1.63 9 1.1 MAX

8 1 0.7 0.15 0 -8 0.4 0.05

A 20 1.57 DETAIL A TYPICAL 1.28

4225481/A 11/2019 PowerPAD is a trademark of Texas Instruments. NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-187.

www.ti.com EXAMPLE BOARD LAYOUT

TM DGN0008D PowerPAD VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE

(2) NOTE 9 METAL COVERED BY SOLDER MASK (1.57) SYMM SOLDER MASK DEFINED PAD 8X (1.4) (R0.05) TYP

8 8X (0.45) 1

(3) 9 SYMM NOTE 9

(1.89)

6X (0.65) (1.22) 5 4

( 0.2) TYP VIA (0.55) SEE DETAILS

(4.4) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X

SOLDER MASK SOLDER MASK METAL METAL UNDER OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER15.000 MASK DETAILS

4225481/A 11/2019 NOTES: (continued)

6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement.

www.ti.com EXAMPLE STENCIL DESIGN

TM DGN0008D PowerPAD VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE

(1.57) BASED ON 0.125 THICK STENCIL SYMM

8X (1.4) (R0.05) TYP

8 8X (0.45) 1

(1.89) SYMM BASED ON 0.125 THICK STENCIL 6X (0.65)

4 5

METAL COVERED SEE TABLE FOR BY SOLDER MASK DIFFERENT OPENINGS (4.4) FOR OTHER STENCIL THICKNESSES

SOLDER PASTE EXAMPLE EXPOSED PAD 9: 100% PRINTED SOLDER COVERAGE BY AREA SCALE: 15X

STENCIL SOLDER STENCIL THICKNESS OPENING 0.1 1.76 X 2.11 0.125 1.57 X 1.89 (SHOWN) 0.15 1.43 X 1.73 0.175 1.33 X 1.60

4225481/A 11/2019 NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. Board assembly site may have different recommendations for stencil design.

www.ti.com PACKAGE OUTLINE

TM PowerPAD VSSOP - 1.1 mm max height DGN0008G SCALE 4.000 SMALL OUTLINE PACKAGE

C 5.05 A TYP 4.75 0.1 C PIN 1 INDEX AREA SEATING PLANE 6X 0.65 8 1

2X 3.1 1.95 2.9 NOTE 3

5 0.38 8X 0.25 3.1 B 0.13 CAB 2.9 NOTE 4

0.23 0.13

SEE DETAIL A

EXPOSED THERMAL PAD

4 5

0.25 GAGE PLANE 2.15 1.95 9 1.1 MAX

8 1 0.7 0.15 0 -8 0.4 0.05

A 20 1.846 DETAIL A TYPICAL 1.646

4225480/A 11/2019 PowerPAD is a trademark of Texas Instruments. NOTES:

www.ti.com EXAMPLE BOARD LAYOUT

TM DGN0008G PowerPAD VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE

(2) NOTE 9 METAL COVERED BY SOLDER MASK (1.846) SYMM SOLDER MASK DEFINED PAD 8X (1.4) (R0.05) TYP

8 8X (0.45) 1

(3) 9 SYMM NOTE 9

(2.15) 6X (0.65) (1.22) 5 4

( 0.2) TYP VIA (0.55) SEE DETAILS

(4.4) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X

SOLDER MASK SOLDER MASK METAL METAL UNDER OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK DEFINED DEFINED (PREFERRED) SOLDER15.000 MASK DETAILS

4225480/A 11/2019 NOTES: (continued)

www.ti.com EXAMPLE STENCIL DESIGN

TM DGN0008G PowerPAD VSSOP - 1.1 mm max height SMALL OUTLINE PACKAGE

(1.846) BASED ON 0.125 THICK STENCIL SYMM

8X (1.4) (R0.05) TYP

8 8X (0.45) 1

(2.15) SYMM BASED ON 0.125 THICK STENCIL

6X (0.65)

4 5

METAL COVERED SEE TABLE FOR BY SOLDER MASK DIFFERENT OPENINGS (4.4) FOR OTHER STENCIL THICKNESSES

SOLDER PASTE EXAMPLE EXPOSED PAD 9: 100% PRINTED SOLDER COVERAGE BY AREA SCALE: 15X

STENCIL SOLDER STENCIL THICKNESS OPENING 0.1 2.06 X 2.40 0.125 1.846 X 2.15 (SHOWN) 0.15 1.69 X 1.96 0.175 1.56 X 1.82

4225480/A 11/2019 NOTES: (continued)

www.ti.com PACKAGE OUTLINE D0008A SOIC - 1.75 mm max height SCALE 2.800 SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE .228-.244 TYP [5.80-6.19] .004 [0.1] C A PIN 1 ID AREA 6X .050 [1.27] 8 1

.189-.197 2X [4.81-5.00] .150 NOTE 3 [3.81]

4X (0 -15 )

4 5 8X .012-.020 [0.31-0.51] B .150-.157 .069 MAX [3.81-3.98] .010 [0.25] CAB [1.75] NOTE 4

.005-.010 TYP [0.13-0.25]

4X (0 -15 )

SEE DETAIL A .010 [0.25]

.004-.010 0 - 8 [0.11-0.25] .016-.050 [0.41-1.27] DETAIL A (.041) TYPICAL [1.04]

4214825/C 02/2019 NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed .006 [0.15] per side. 4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA.

www.ti.com EXAMPLE BOARD LAYOUT D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 ) [1.55] SYMM SEE DETAILS 1 8

8X (.024) [0.6] SYMM

(R.002 ) TYP [0.05] 5 4 6X (.050 ) [1.27] (.213) [5.4]

LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:8X

SOLDER MASK SOLDER MASK METAL UNDER METAL OPENING OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL .0028 MAX .0028 MIN [0.07] [0.07] ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com EXAMPLE STENCIL DESIGN D0008A SOIC - 1.75 mm max height SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 ) [1.55] SYMM

1 8

8X (.024) [0.6] SYMM

(R.002 ) TYP 5 [0.05] 4 6X (.050 ) [1.27] (.213) [5.4]

SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design.

www.ti.com IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE