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Motorola Mpc107 Pci Bridge/Integrated Memory Controller MPC107FACT/D Fact Sheet MOTOROLA MPC107 PCI BRIDGE/INTEGRATED MEMORY CONTROLLER The MPC107 PCI Bridge/Integrated Memory Controller provides a bridge between the Peripheral Component Interconnect, (PCI) bus and PowerPC 603e™, PowerPC 740™, PowerPC 750™ or MPC7400 microprocessors. PCI support allows system designers to design systems quickly using peripherals already designed for PCI and the other standard interfaces available in the personal computer hardware environment. The MPC107 provides many of the other necessities for embedded applications including a high-performance memory controller and dual processor support, 2-channel flexible DMA controller, an interrupt controller, an I2O-ready message unit, an inter-integrated circuit controller (I2C), and low skew clock drivers. The MPC107 contains an Embedded Programmable Interrupt Controller (EPIC) featuring five hardware interrupts (IRQ’s) as well as sixteen serial interrupts along with four timers. The MPC107 uses an advanced, 2.5-volt HiP3 process technology and is fully compatible with TTL devices. Integrated Memory Controller The memory interface controls processor and PCI interactions to main memory. It supports a variety of programmable timing supporting DRAM (FPM, EDO), SDRAM, and ROM/Flash ROM configurations, up to speeds of 100 MHz. PCI Bus Support The MPC107 PCI interface is designed to connect the processor and memory buses to the PCI local bus without the need for "glue" logic at speeds up to 66 MHz. The MPC107 acts as either a master or slave device on the PCI MPC107 Block Diagram bus and contains a PCI bus arbitration unit 60x Bus which reduces the need for an equivalent Memory Data external unit thus reducing the total system Data Path ECC / Parity complexity and cost. Unit PIU I2O Multiprocessor and Local Memory Bus Slave Support Add / Cntl CCU MCU The MPC107 supports a programmable DMA interface to PowerPC microprocessors 2 Mem Clocks I C DLL operating at bus frequencies up to 100 I2C MHz. The MPC107 processor interface PCIU IRQs Clock In allows for a variety of system configura- EPIC PLL tions by providing support for a second PCI Clocks processor and a local bus slave. ATU Arbiter FO Buffer Timers PCI Bus REQ / GNT OSC Continued on back. MPC107 Major Features Memory Interface Other Embedded Features ■ High-bandwidth (32/64-bit) data bus up to ■ Two-channel integrated DMA controller 100 MHz ♦ Supports direct or chaining modes ■ Programmable timing supporting either ♦ Scatter gather DRAM (FPM, EDO) or SDRAM ♦ Interrupt on completed segment, chain, and error ■ Supports 1 to 8 banks - 4MBit, 16MBit, ♦ 64MBit, 128MBit, and/or 256MBit Local to local memory ♦ PCI to PCI memory DRAMs or SDRAMs ♦ PCI to local memory ■ 1 Gbyte of RAM space, 144 Mbytes of ♦ Local to PCI memory ROM space ■ Message Unit ■ 8-, 32-, or 64-bit ROM/Flash ROM ♦ Intelligent Input/Output (I O) Message ■ 2 PortX: 8-, 32-, or 64-bit general-purpose Controller I/O port uses ROM controller interface ♦ Two door-bell registers with address strobe ♦ Inbound and outbound messaging registers ■ Supports parity, read-modify-write, or ■ Inter-Integrated Circuit (I2C) Controller error-correcting code (ECC) ♦ Full master/slave support Processor Interface ■ Embedded programmable interrupt controller (EPIC) ■ Processor bus frequency up to 100 MHz ♦ Five hardware interrupts (IRQs) or 16 serial ■ 64-bit or 32-bit data bus and 32-bit interupts address bus ♦ Four programmable timers ■ SMP support for a second processor ■ Integrated PCI bus and SDRAM clock ■ Full memory coherency supported, generation integrated arbiter and slave peripheral ■ Programmable memory and PCI bus drivers support ■ Debug Features ■ Supports PowerPC 603e, PowerPC 740, ♦ Watchpoint monitor PowerPC 750 and MPC7400 processors ♦ Memory attribute and PCI attribute signals ♦ PCI Interface JTAG/COP – Common On-board Processor for in-circuit hardware debugging ■ Compliant with PCI specification, ♦ IEEE 1149.1-compliant, JTAG boundary- revision 2.1 scan interface ■ 32-Bit PCI interface operates up to 66 MHz ■ 503-pin ball grid array (BGA) package ■ 5.0-volt compatible ■ Read and write buffers to improve PCI Power Management performance ■ Four levels of power reduction–doze, nap, ■ Selectable big or little endian operation sleep, and suspend ■ PCI interface can be configured as host or ■ Fully static, internal logic states preserved agent, allowing multiple MPC107 chips on during all power modes same PCI bus ■ Arbiter supports up to five other PCI devices ■ Parity support For additional information: call 1-800-845-6686 or your local Motorola sales representative or visit http://motorola.com/PowerPC/ ©1999 Motorola, Inc. All rights reserved. Printed in the U.S.A. Motorola and the are registered trademarks of Motorola, Inc. PowerPC, the PowerPC logo, PowerPC Architecture, PowerPC 603e, PowerPC 740 and PowerPC 750 are trademarks of International Business Machines Corporation and used under license therefrom. This document contains informa- tion on a new product under development. Specifications and information herein are subject to change without notice. 1ATX45601-0 Printed in USA 10/99 Hibbert LITRISC.
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