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Keystone Architecture DDR3 Memory Controller

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Keystone Architecture DDR3 Memory Controller Keystone Architecture DDR3 Memory Controller User's Guide Literature Number: SPRUGV8E November 2010–Revised January 2015 Contents Preface....................................................................................................................................... 11 1 Introduction ....................................................................................................................... 13 1.1 Purpose of the Peripheral ................................................................................................. 14 1.2 Features ..................................................................................................................... 14 1.3 Industry Standard(s) Compliance Statement ........................................................................... 14 2 Peripheral Architecture ....................................................................................................... 16 2.1 Clock Interface.............................................................................................................. 17 2.2 SDRAM Memory Map ..................................................................................................... 17 2.3 Signal Descriptions......................................................................................................... 17 2.4 Protocol Descriptions ...................................................................................................... 18 2.4.1 Mode Register Set (MRS or EMRS) ............................................................................ 19 2.4.2 Refresh Mode...................................................................................................... 20 2.4.3 Activation ........................................................................................................... 20 2.4.4 Deactivation ........................................................................................................ 20 2.4.5 READ Command .................................................................................................. 20 2.4.6 Write (WR) Command ............................................................................................ 21 2.5 Address Mapping........................................................................................................... 22 2.6 DDR3 Memory Controller Interface ...................................................................................... 27 2.6.1 Arbitration .......................................................................................................... 28 2.6.2 Command Starvation ............................................................................................. 29 2.6.3 Possible Race Condition ......................................................................................... 29 2.6.4 Class of Service ................................................................................................... 29 2.7 Refresh Scheduling ........................................................................................................ 30 2.8 Self-Refresh Mode ......................................................................................................... 30 2.8.1 Extended Temperature Range .................................................................................. 31 2.9 Reset Considerations ...................................................................................................... 31 2.10 Turnaround Time ........................................................................................................... 32 2.11 DDR3 SDRAM Memory Initialization .................................................................................... 32 2.11.1 DDR3 Initialization Sequence .................................................................................. 34 2.12 Dual Rank Support......................................................................................................... 34 2.13 Leveling...................................................................................................................... 34 2.13.1 Full Leveling (Auto Leveling)................................................................................... 34 2.13.2 Incremental Leveling............................................................................................. 35 2.13.2.1 Ramp Incremental Leveling................................................................................ 36 2.13.3 Impact On Bandwidth............................................................................................ 36 2.13.4 Programming Full Leveling ..................................................................................... 36 2.13.4.1 Leveling Timeout ............................................................................................ 37 2.13.4.2 Read Data Eye Training Errata For Full Leveling ...................................................... 37 2.13.5 Programming Incremental Leveling............................................................................ 38 2.13.5.1 Standalone Incremental Leveling ......................................................................... 38 2.13.6 Programming Ratio Forced Leveling .......................................................................... 38 2.13.7 Using Invert Clock Out........................................................................................... 38 2.14 Interrupt Support ........................................................................................................... 39 2.15 EDMA Event Support ...................................................................................................... 39 2.16 Emulation Considerations ................................................................................................. 39 2 Contents SPRUGV8E–November 2010–Revised January 2015 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated www.ti.com 2.17 ECC .......................................................................................................................... 39 2.18 Power Management........................................................................................................ 40 2.18.1 SDRAM Self-Refresh Mode..................................................................................... 40 2.18.2 SDRAM Power-Down Mode .................................................................................... 40 2.19 Performance Monitoring ................................................................................................... 40 3 Using the DDR3 Memory Controller ...................................................................................... 43 3.1 Connecting the DDR3 Memory Controller to DDR3 SDRAM......................................................... 44 3.2 Configuring DDR3 Memory Controller Registers to Meet DDR3 SDRAM Specifications......................... 48 3.2.1 Programming the SDRAM Configuration Register (SDCFG)................................................ 48 3.2.2 Programming the SDRAM Refresh Control Register (SDRFC) ............................................. 48 3.2.3 Configuring SDRAM Timing Registers (SDTIM1, SDTIM2, SDTIM3, SDTIM4) .......................... 49 3.2.4 Configuring Leveling Registers .................................................................................. 50 3.2.5 Configuring Read Latency ....................................................................................... 50 4 DDR3 Memory Controller Registers ...................................................................................... 52 4.1 Module ID and Revision Register (MIDR)............................................................................... 55 4.2 DDR3 Memory Controller Status Register (STATUS)................................................................. 56 4.3 SDRAM Configuration Register (SDCFG) .............................................................................. 57 4.4 SDRAM Refresh Control Register (SDRFC)............................................................................ 59 4.5 SDRAM Timing 1 (SDTIM1) Register ................................................................................... 60 4.6 SDRAM Timing 2 (SDTIM2) Register ................................................................................... 61 4.7 SDRAM Timing 3 (SDTIM3) Register ................................................................................... 62 4.8 Power Management Control Register (PMCTL) ....................................................................... 63 4.9 VBUSM Configuration Register (VBUSM_CONFIG) .................................................................. 65 4.10 Performance Counter 1 Register (PERF_CNT_1) ..................................................................... 66 4.11 Performance Counter 2 Register (PERF_CNT_2) ..................................................................... 67 4.12 Performance Counter Config Register (PERF_CNT_CFG) .......................................................... 68 4.13 Performance Counter Master Region Select Register (PERF_CNT_SEL) ......................................... 69 4.14 Performance Counter Time Register (PERF_CNT_TIM) ............................................................. 70 4.15 Interrupt Raw Status Register (IRQSTATUS_RAW_SYS) ........................................................... 71 4.16 Interrupt Status Register (IRQSTATUS_ SYS)......................................................................... 72 4.17
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